Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.58 100.00 100.00 99.76 99.49 100.00


Total tests in report: 903
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
47.70 47.70 36.58 36.58 29.51 29.51 51.51 51.51 100.00 100.00 27.53 27.53 79.55 79.55 9.22 9.22 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3410379127
82.84 35.15 94.71 58.13 75.63 46.12 56.03 4.52 100.00 0.00 96.47 68.94 93.94 14.39 63.14 53.92 /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2331053276
95.27 12.42 99.07 4.36 92.90 17.27 94.97 38.94 100.00 0.00 97.65 1.18 94.95 1.01 87.35 24.21 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.265310307
96.68 1.42 99.07 0.00 96.72 3.83 97.24 2.26 100.00 0.00 99.06 1.41 95.71 0.76 89.00 1.65 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3369866592
97.24 0.56 99.07 0.00 96.72 0.00 97.24 0.00 100.00 0.00 99.29 0.24 95.96 0.25 92.43 3.44 /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.3265318668
97.75 0.50 99.07 0.00 96.72 0.00 98.74 1.51 100.00 0.00 99.29 0.00 97.98 2.02 92.43 0.00 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4154151026
98.08 0.33 99.07 0.00 96.72 0.00 98.99 0.25 100.00 0.00 99.29 0.00 97.98 0.00 94.50 2.06 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1902971146
98.41 0.33 99.53 0.47 97.81 1.09 98.99 0.00 100.00 0.00 99.76 0.47 97.98 0.00 94.77 0.28 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1409943318
98.66 0.26 99.53 0.00 97.81 0.00 98.99 0.00 100.00 0.00 99.76 0.00 97.98 0.00 96.56 1.79 /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.1850777433
98.84 0.18 99.53 0.00 98.03 0.22 99.50 0.50 100.00 0.00 99.76 0.00 98.23 0.25 96.84 0.28 /workspace/coverage/default/2.hmac_sec_cm.76310381
98.97 0.13 99.53 0.00 98.03 0.00 100.00 0.50 100.00 0.00 99.76 0.00 98.23 0.00 97.25 0.41 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3556231613
99.10 0.13 99.53 0.00 98.25 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 97.94 0.69 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.1986930310
99.18 0.08 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 98.49 0.55 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3000142269
99.24 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 98.90 0.41 /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.2829949988
99.28 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 99.17 0.28 /workspace/coverage/default/11.hmac_stress_all.3370760326
99.32 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.25 99.17 0.00 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2823618714
99.35 0.03 99.53 0.00 98.47 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.00 /workspace/coverage/default/14.hmac_alert_test.1607610429
99.37 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.743022537
99.39 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3855875629
99.41 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3427523736
99.43 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.153437909
99.45 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1098122492
99.46 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 100.00 0.14 /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.1911534639
99.48 0.02 99.53 0.00 98.58 0.11 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 100.00 0.00 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1167356419


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.208246007
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.157356555
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4057464404
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.2473845267
/workspace/coverage/cover_reg_top/0.hmac_intr_test.2267459488
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1526976434
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.735382574
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4158800070
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3799530932
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3439706370
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3412972221
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.991155898
/workspace/coverage/cover_reg_top/1.hmac_intr_test.4184969140
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3990005389
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.1320595859
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1475078440
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.3659679913
/workspace/coverage/cover_reg_top/10.hmac_intr_test.2172255461
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3574889635
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.2033450040
/workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2998970792
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3678299232
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.119240929
/workspace/coverage/cover_reg_top/11.hmac_intr_test.927926122
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2937978966
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.4276747806
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1864572971
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1836799556
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.1845055243
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1818410005
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.3273111702
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1750407316
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.2055702897
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1113265507
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.1027893180
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.298149689
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4107671510
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.3729971707
/workspace/coverage/cover_reg_top/14.hmac_intr_test.1417853433
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1258604192
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.2623316524
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.922487381
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1454577074
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.1342487871
/workspace/coverage/cover_reg_top/15.hmac_intr_test.2523528835
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3362479955
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.1523903460
/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1365182932
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3664728482
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.1680505011
/workspace/coverage/cover_reg_top/16.hmac_intr_test.2078995072
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1713651212
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.245721169
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2628424113
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4088005774
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.3290063427
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063323626
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.2243375697
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2552291063
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1395663076
/workspace/coverage/cover_reg_top/18.hmac_intr_test.474350045
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3112157955
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.2731183758
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.79891262
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2135408958
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.2822159311
/workspace/coverage/cover_reg_top/19.hmac_intr_test.2022952276
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1718654866
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.3505363726
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.296463536
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4035749978
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2006937497
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3565993806
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3087363707
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.3022242292
/workspace/coverage/cover_reg_top/2.hmac_intr_test.898477112
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1147057200
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.3738014008
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.363741440
/workspace/coverage/cover_reg_top/20.hmac_intr_test.2862783841
/workspace/coverage/cover_reg_top/21.hmac_intr_test.2246657705
/workspace/coverage/cover_reg_top/22.hmac_intr_test.468286969
/workspace/coverage/cover_reg_top/23.hmac_intr_test.3230744717
/workspace/coverage/cover_reg_top/24.hmac_intr_test.589283330
/workspace/coverage/cover_reg_top/25.hmac_intr_test.1859831972
/workspace/coverage/cover_reg_top/26.hmac_intr_test.2575568600
/workspace/coverage/cover_reg_top/27.hmac_intr_test.1340500005
/workspace/coverage/cover_reg_top/28.hmac_intr_test.846428360
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2049979363
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.386608612
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2828640155
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.642083222
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.1391863287
/workspace/coverage/cover_reg_top/3.hmac_intr_test.2002662844
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2837452162
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.1620309497
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1698969858
/workspace/coverage/cover_reg_top/30.hmac_intr_test.4220904810
/workspace/coverage/cover_reg_top/31.hmac_intr_test.221543410
/workspace/coverage/cover_reg_top/32.hmac_intr_test.3128288606
/workspace/coverage/cover_reg_top/33.hmac_intr_test.1658080696
/workspace/coverage/cover_reg_top/34.hmac_intr_test.2526202228
/workspace/coverage/cover_reg_top/35.hmac_intr_test.185833592
/workspace/coverage/cover_reg_top/36.hmac_intr_test.1594665368
/workspace/coverage/cover_reg_top/37.hmac_intr_test.1792221028
/workspace/coverage/cover_reg_top/38.hmac_intr_test.211089771
/workspace/coverage/cover_reg_top/39.hmac_intr_test.4104045244
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.936161311
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3299462642
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.500616789
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3634501894
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.3391028633
/workspace/coverage/cover_reg_top/4.hmac_intr_test.257391761
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3214006050
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4132003426
/workspace/coverage/cover_reg_top/40.hmac_intr_test.3356437708
/workspace/coverage/cover_reg_top/41.hmac_intr_test.2677412099
/workspace/coverage/cover_reg_top/42.hmac_intr_test.2315611434
/workspace/coverage/cover_reg_top/44.hmac_intr_test.927125687
/workspace/coverage/cover_reg_top/45.hmac_intr_test.3227766419
/workspace/coverage/cover_reg_top/46.hmac_intr_test.120963140
/workspace/coverage/cover_reg_top/47.hmac_intr_test.2271945371
/workspace/coverage/cover_reg_top/48.hmac_intr_test.2429283961
/workspace/coverage/cover_reg_top/49.hmac_intr_test.435776555
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.9514442
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.883313006
/workspace/coverage/cover_reg_top/5.hmac_intr_test.503689907
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.423544417
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.1687168523
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.110187008
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.426780714
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.3811853261
/workspace/coverage/cover_reg_top/6.hmac_intr_test.4181313213
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3355333564
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.2604487281
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.67266987
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3625555912
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2423490869
/workspace/coverage/cover_reg_top/7.hmac_intr_test.2893699268
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1957691983
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.4134574542
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4051102290
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1310143137
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.1622651979
/workspace/coverage/cover_reg_top/8.hmac_intr_test.3882123877
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1561486469
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.822514451
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3161367339
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.1221191545
/workspace/coverage/cover_reg_top/9.hmac_intr_test.1496745943
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.616069011
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.3818452904
/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2169078803
/workspace/coverage/default/0.hmac_alert_test.3287016406
/workspace/coverage/default/0.hmac_back_pressure.3408115901
/workspace/coverage/default/0.hmac_burst_wr.597589030
/workspace/coverage/default/0.hmac_datapath_stress.3073459332
/workspace/coverage/default/0.hmac_error.181343192
/workspace/coverage/default/0.hmac_long_msg.3836769018
/workspace/coverage/default/0.hmac_sec_cm.1614550381
/workspace/coverage/default/0.hmac_smoke.2067752435
/workspace/coverage/default/0.hmac_stress_all.3134391896
/workspace/coverage/default/0.hmac_test_hmac_vectors.1184293358
/workspace/coverage/default/0.hmac_test_sha_vectors.2652605088
/workspace/coverage/default/0.hmac_wipe_secret.121669768
/workspace/coverage/default/1.hmac_alert_test.2050684565
/workspace/coverage/default/1.hmac_back_pressure.1355481897
/workspace/coverage/default/1.hmac_burst_wr.4053326481
/workspace/coverage/default/1.hmac_datapath_stress.2435086521
/workspace/coverage/default/1.hmac_error.102923272
/workspace/coverage/default/1.hmac_long_msg.775819676
/workspace/coverage/default/1.hmac_sec_cm.837789712
/workspace/coverage/default/1.hmac_smoke.2344184653
/workspace/coverage/default/1.hmac_stress_all.2399989388
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3323836818
/workspace/coverage/default/1.hmac_test_hmac_vectors.2875587432
/workspace/coverage/default/1.hmac_test_sha_vectors.2321889964
/workspace/coverage/default/1.hmac_wipe_secret.2993101743
/workspace/coverage/default/10.hmac_alert_test.2919872690
/workspace/coverage/default/10.hmac_back_pressure.1379753172
/workspace/coverage/default/10.hmac_burst_wr.1638683967
/workspace/coverage/default/10.hmac_datapath_stress.425047729
/workspace/coverage/default/10.hmac_error.3040004155
/workspace/coverage/default/10.hmac_long_msg.978883646
/workspace/coverage/default/10.hmac_smoke.1944867619
/workspace/coverage/default/10.hmac_stress_all.1413032937
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2657421600
/workspace/coverage/default/10.hmac_test_hmac_vectors.2714297496
/workspace/coverage/default/10.hmac_test_sha_vectors.2406887158
/workspace/coverage/default/10.hmac_wipe_secret.1462806777
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3723442546
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2293883814
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.621954392
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2064342766
/workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3961987964
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.3203744447
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1111919040
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1579337550
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.2421123981
/workspace/coverage/default/11.hmac_alert_test.3340002670
/workspace/coverage/default/11.hmac_back_pressure.397141844
/workspace/coverage/default/11.hmac_burst_wr.1395762864
/workspace/coverage/default/11.hmac_datapath_stress.3556426895
/workspace/coverage/default/11.hmac_error.367018376
/workspace/coverage/default/11.hmac_long_msg.2298442260
/workspace/coverage/default/11.hmac_smoke.169153016
/workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2093827453
/workspace/coverage/default/11.hmac_test_hmac_vectors.1574382604
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/workspace/coverage/default/8.hmac_alert_test.2309125096
/workspace/coverage/default/8.hmac_back_pressure.2433135328
/workspace/coverage/default/8.hmac_burst_wr.3468936998
/workspace/coverage/default/8.hmac_datapath_stress.1470610397
/workspace/coverage/default/8.hmac_error.2765079571
/workspace/coverage/default/8.hmac_long_msg.3073096124
/workspace/coverage/default/8.hmac_smoke.1256680839
/workspace/coverage/default/8.hmac_stress_all.3689116172
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2038315949
/workspace/coverage/default/8.hmac_test_hmac_vectors.2418369993
/workspace/coverage/default/8.hmac_test_sha_vectors.3454448641
/workspace/coverage/default/8.hmac_wipe_secret.2720766618
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.959159964
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3645196869
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.3123891062
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.4073623246
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2687239839
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.73826063
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2230392193
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.800938915
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.1742231629
/workspace/coverage/default/9.hmac_alert_test.2295394657
/workspace/coverage/default/9.hmac_back_pressure.33882948
/workspace/coverage/default/9.hmac_burst_wr.438364849
/workspace/coverage/default/9.hmac_datapath_stress.2609615918
/workspace/coverage/default/9.hmac_error.4129176326
/workspace/coverage/default/9.hmac_long_msg.2264374065
/workspace/coverage/default/9.hmac_smoke.1038820873
/workspace/coverage/default/9.hmac_stress_all.3250776451
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2693202583
/workspace/coverage/default/9.hmac_test_hmac_vectors.3848232703
/workspace/coverage/default/9.hmac_test_sha_vectors.359638098
/workspace/coverage/default/9.hmac_wipe_secret.1998972251
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1712699398
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.2025065073
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1431997215
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.3954492410
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.4159843296
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.4167037959
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.535428790
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.3260765931
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.512556282




Total test records in report: 903
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T12 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3410379127 Dec 20 12:26:25 PM PST 23 Dec 20 12:27:00 PM PST 23 13092158 ps
T13 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.245721169 Dec 20 12:26:14 PM PST 23 Dec 20 12:26:45 PM PST 23 60036623 ps
T14 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3161367339 Dec 20 12:26:01 PM PST 23 Dec 20 12:26:24 PM PST 23 48540010 ps
T15 /workspace/coverage/cover_reg_top/5.hmac_intr_test.503689907 Dec 20 12:25:22 PM PST 23 Dec 20 12:25:46 PM PST 23 38509686 ps
T16 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1221191545 Dec 20 12:25:41 PM PST 23 Dec 20 12:26:12 PM PST 23 24465005 ps
T17 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3565993806 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 35829149 ps
T18 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.265310307 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:18 PM PST 23 155879717 ps
T19 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4181313213 Dec 20 12:26:08 PM PST 23 Dec 20 12:26:35 PM PST 23 135167959 ps
T20 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3799530932 Dec 20 12:26:47 PM PST 23 Dec 20 12:27:20 PM PST 23 116348391 ps
T21 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1864572971 Dec 20 12:26:10 PM PST 23 Dec 20 12:26:38 PM PST 23 45638283 ps
T23 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1845055243 Dec 20 12:26:03 PM PST 23 Dec 20 12:26:26 PM PST 23 19239981 ps
T64 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.386608612 Dec 20 12:25:32 PM PST 23 Dec 20 12:26:01 PM PST 23 56467150 ps
T22 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3369866592 Dec 20 12:26:14 PM PST 23 Dec 20 12:26:46 PM PST 23 64853216 ps
T47 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2523528835 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:30 PM PST 23 107039915 ps
T48 /workspace/coverage/cover_reg_top/38.hmac_intr_test.211089771 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:30 PM PST 23 15312817 ps
T71 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1957691983 Dec 20 12:26:21 PM PST 23 Dec 20 12:26:55 PM PST 23 59504814 ps
T72 /workspace/coverage/cover_reg_top/22.hmac_intr_test.468286969 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:28 PM PST 23 15705474 ps
T24 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.426780714 Dec 20 12:25:56 PM PST 23 Dec 20 12:26:20 PM PST 23 86364702 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.157356555 Dec 20 12:25:20 PM PST 23 Dec 20 12:25:42 PM PST 23 45205305 ps
T73 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4154151026 Dec 20 12:25:57 PM PST 23 Dec 20 12:26:21 PM PST 23 19908530 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1391863287 Dec 20 12:25:37 PM PST 23 Dec 20 12:26:06 PM PST 23 35165462 ps
T101 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2893699268 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:31 PM PST 23 10757040 ps
T98 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1340500005 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 164094162 ps
T25 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1750407316 Dec 20 12:26:07 PM PST 23 Dec 20 12:26:35 PM PST 23 104473747 ps
T94 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1622651979 Dec 20 12:25:47 PM PST 23 Dec 20 12:26:14 PM PST 23 41133766 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1902971146 Dec 20 12:26:24 PM PST 23 Dec 20 12:26:58 PM PST 23 45197181 ps
T74 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2055702897 Dec 20 12:26:08 PM PST 23 Dec 20 12:26:35 PM PST 23 19526840 ps
T75 /workspace/coverage/cover_reg_top/28.hmac_intr_test.846428360 Dec 20 12:26:10 PM PST 23 Dec 20 12:26:38 PM PST 23 23226599 ps
T76 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3439706370 Dec 20 12:25:23 PM PST 23 Dec 20 12:25:49 PM PST 23 50418107 ps
T63 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.298149689 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:51 PM PST 23 129968361 ps
T26 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3678299232 Dec 20 12:26:14 PM PST 23 Dec 20 12:26:46 PM PST 23 40283136 ps
T100 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2677412099 Dec 20 12:25:56 PM PST 23 Dec 20 12:26:20 PM PST 23 41465120 ps
T27 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1409943318 Dec 20 12:25:59 PM PST 23 Dec 20 12:27:29 PM PST 23 21466375960 ps
T95 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2423490869 Dec 20 12:25:26 PM PST 23 Dec 20 12:25:52 PM PST 23 85804931 ps
T134 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3729971707 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 44189612 ps
T96 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1113265507 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:32 PM PST 23 250301820 ps
T79 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3112157955 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:30 PM PST 23 64107923 ps
T70 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3556231613 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:18 PM PST 23 162812454 ps
T28 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1395663076 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:36 PM PST 23 115398080 ps
T29 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2135408958 Dec 20 12:26:13 PM PST 23 Dec 20 12:26:43 PM PST 23 68286155 ps
T135 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1417853433 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 58712095 ps
T136 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4104045244 Dec 20 12:26:20 PM PST 23 Dec 20 12:27:00 PM PST 23 32926214 ps
T30 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1836799556 Dec 20 12:26:46 PM PST 23 Dec 20 12:27:18 PM PST 23 52210444 ps
T137 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3412972221 Dec 20 12:25:36 PM PST 23 Dec 20 12:26:06 PM PST 23 79391742 ps
T138 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1475078440 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:13 PM PST 23 108087771 ps
T139 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4057464404 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:17 PM PST 23 53228989 ps
T66 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3505363726 Dec 20 12:26:25 PM PST 23 Dec 20 12:27:01 PM PST 23 188216179 ps
T140 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4088005774 Dec 20 12:26:16 PM PST 23 Dec 20 12:26:49 PM PST 23 107895356 ps
T80 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1680505011 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 38373287 ps
T81 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1713651212 Dec 20 12:26:41 PM PST 23 Dec 20 12:27:14 PM PST 23 29617398 ps
T78 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4132003426 Dec 20 12:25:35 PM PST 23 Dec 20 12:26:06 PM PST 23 924542365 ps
T65 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1687168523 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:18 PM PST 23 102400063 ps
T68 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3273111702 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:37 PM PST 23 88437960 ps
T82 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2473845267 Dec 20 12:26:37 PM PST 23 Dec 20 12:27:11 PM PST 23 20343566 ps
T141 /workspace/coverage/cover_reg_top/31.hmac_intr_test.221543410 Dec 20 12:26:34 PM PST 23 Dec 20 12:27:08 PM PST 23 14591629 ps
T142 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2429283961 Dec 20 12:26:18 PM PST 23 Dec 20 12:26:52 PM PST 23 21439628 ps
T143 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3855875629 Dec 20 12:26:37 PM PST 23 Dec 20 12:27:11 PM PST 23 53189135 ps
T83 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2822159311 Dec 20 12:26:25 PM PST 23 Dec 20 12:27:00 PM PST 23 93529899 ps
T144 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2006937497 Dec 20 12:25:47 PM PST 23 Dec 20 12:26:17 PM PST 23 347103170 ps
T145 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2049979363 Dec 20 12:26:53 PM PST 23 Dec 20 12:27:33 PM PST 23 30555105 ps
T146 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3000142269 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:24 PM PST 23 16908190 ps
T147 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2862783841 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:36 PM PST 23 32610519 ps
T77 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1523903460 Dec 20 12:25:53 PM PST 23 Dec 20 12:26:19 PM PST 23 63355690 ps
T69 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2243375697 Dec 20 12:26:04 PM PST 23 Dec 20 12:26:28 PM PST 23 105382543 ps
T148 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2022952276 Dec 20 12:26:18 PM PST 23 Dec 20 12:26:51 PM PST 23 38684104 ps
T149 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1658080696 Dec 20 12:26:16 PM PST 23 Dec 20 12:26:49 PM PST 23 14068864 ps
T150 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2172255461 Dec 20 12:26:08 PM PST 23 Dec 20 12:26:34 PM PST 23 49570130 ps
T151 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2731183758 Dec 20 12:26:07 PM PST 23 Dec 20 12:26:35 PM PST 23 32073744 ps
T152 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1526976434 Dec 20 12:25:31 PM PST 23 Dec 20 12:26:00 PM PST 23 174309625 ps
T153 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3882123877 Dec 20 12:25:57 PM PST 23 Dec 20 12:26:21 PM PST 23 16154477 ps
T154 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1859831972 Dec 20 12:26:15 PM PST 23 Dec 20 12:26:46 PM PST 23 12790199 ps
T155 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1594665368 Dec 20 12:26:36 PM PST 23 Dec 20 12:27:10 PM PST 23 186489060 ps
T156 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2033450040 Dec 20 12:26:11 PM PST 23 Dec 20 12:26:45 PM PST 23 411651125 ps
T157 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2271945371 Dec 20 12:26:04 PM PST 23 Dec 20 12:26:27 PM PST 23 72728081 ps
T103 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2169078803 Dec 20 12:27:05 PM PST 23 Dec 20 12:27:36 PM PST 23 670428605 ps
T158 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2575568600 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:22 PM PST 23 50248679 ps
T159 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.616069011 Dec 20 12:25:35 PM PST 23 Dec 20 12:26:05 PM PST 23 30185936 ps
T160 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063323626 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:36 PM PST 23 45652802 ps
T161 /workspace/coverage/cover_reg_top/35.hmac_intr_test.185833592 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:22 PM PST 23 51304103 ps
T162 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3227766419 Dec 20 12:25:57 PM PST 23 Dec 20 12:26:21 PM PST 23 21152128 ps
T163 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3391028633 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:12 PM PST 23 72472355 ps
T86 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3299462642 Dec 20 12:25:30 PM PST 23 Dec 20 12:26:01 PM PST 23 348370814 ps
T164 /workspace/coverage/cover_reg_top/46.hmac_intr_test.120963140 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:31 PM PST 23 31770690 ps
T165 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2078995072 Dec 20 12:26:12 PM PST 23 Dec 20 12:26:41 PM PST 23 23638443 ps
T166 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3738014008 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:25 PM PST 23 609677352 ps
T84 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.883313006 Dec 20 12:27:31 PM PST 23 Dec 20 12:28:09 PM PST 23 135877524 ps
T167 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4134574542 Dec 20 12:25:42 PM PST 23 Dec 20 12:26:13 PM PST 23 312988067 ps
T168 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2246657705 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:36 PM PST 23 34816110 ps
T102 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2998970792 Dec 20 12:26:10 PM PST 23 Dec 20 12:26:39 PM PST 23 181113709 ps
T169 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3625555912 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:25 PM PST 23 123062151 ps
T170 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2315611434 Dec 20 12:25:58 PM PST 23 Dec 20 12:26:21 PM PST 23 22085049 ps
T67 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1167356419 Dec 20 12:25:34 PM PST 23 Dec 20 12:26:06 PM PST 23 645777947 ps
T171 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.119240929 Dec 20 12:25:52 PM PST 23 Dec 20 12:26:17 PM PST 23 66535369 ps
T172 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1258604192 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:24 PM PST 23 327327763 ps
T173 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.642083222 Dec 20 12:25:36 PM PST 23 Dec 20 12:26:06 PM PST 23 13717956 ps
T174 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.822514451 Dec 20 12:25:27 PM PST 23 Dec 20 12:25:56 PM PST 23 250076748 ps
T175 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3574889635 Dec 20 12:26:27 PM PST 23 Dec 20 12:27:02 PM PST 23 249649636 ps
T176 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3230744717 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:24 PM PST 23 48763299 ps
T85 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4158800070 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:12 PM PST 23 97016164 ps
T177 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1561486469 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:51 PM PST 23 66641450 ps
T105 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4051102290 Dec 20 12:26:54 PM PST 23 Dec 20 12:27:25 PM PST 23 101671540 ps
T104 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.296463536 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:25 PM PST 23 1548945399 ps
T178 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1718654866 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:28 PM PST 23 51585582 ps
T1 /workspace/coverage/default/45.hmac_long_msg.3320810025 Dec 20 12:46:33 PM PST 23 Dec 20 12:47:53 PM PST 23 3299291772 ps
T2 /workspace/coverage/default/14.hmac_test_sha_vectors.2402076134 Dec 20 12:42:09 PM PST 23 Dec 20 12:49:54 PM PST 23 26289771007 ps
T3 /workspace/coverage/default/8.hmac_stress_all.3689116172 Dec 20 12:42:08 PM PST 23 Dec 20 01:04:46 PM PST 23 220853324681 ps
T4 /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2956279807 Dec 20 12:47:01 PM PST 23 Dec 20 01:11:17 PM PST 23 101060160906 ps
T9 /workspace/coverage/default/16.hmac_test_sha_vectors.4283186500 Dec 20 12:46:48 PM PST 23 Dec 20 12:52:49 PM PST 23 15076399862 ps
T5 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.1986930310 Dec 20 12:46:32 PM PST 23 Dec 20 01:56:01 PM PST 23 97447955325 ps
T6 /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.2860753963 Dec 20 12:46:39 PM PST 23 Dec 20 01:18:21 PM PST 23 403723728876 ps
T10 /workspace/coverage/default/13.hmac_wipe_secret.1600082551 Dec 20 12:42:11 PM PST 23 Dec 20 12:43:48 PM PST 23 2843936996 ps
T7 /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2331053276 Dec 20 12:47:21 PM PST 23 Dec 20 01:02:30 PM PST 23 75853223594 ps
T11 /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.192481544 Dec 20 12:46:20 PM PST 23 Dec 20 12:58:37 PM PST 23 218179630917 ps
T38 /workspace/coverage/default/28.hmac_burst_wr.1968691096 Dec 20 12:47:25 PM PST 23 Dec 20 12:48:39 PM PST 23 718740491 ps
T39 /workspace/coverage/default/28.hmac_test_sha_vectors.1602085940 Dec 20 12:47:05 PM PST 23 Dec 20 12:54:00 PM PST 23 25498727099 ps
T40 /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.367660386 Dec 20 12:47:04 PM PST 23 Dec 20 01:33:30 PM PST 23 156149453315 ps
T41 /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2064342766 Dec 20 12:47:23 PM PST 23 Dec 20 12:55:29 PM PST 23 27337595781 ps
T42 /workspace/coverage/default/4.hmac_test_sha_vectors.1506266137 Dec 20 12:41:53 PM PST 23 Dec 20 12:49:39 PM PST 23 8370614794 ps
T179 /workspace/coverage/default/22.hmac_long_msg.753012584 Dec 20 12:47:20 PM PST 23 Dec 20 12:49:06 PM PST 23 13344411370 ps
T91 /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.316625361 Dec 20 12:42:00 PM PST 23 Dec 20 01:14:19 PM PST 23 428571994066 ps
T8 /workspace/coverage/default/2.hmac_datapath_stress.537613000 Dec 20 12:42:05 PM PST 23 Dec 20 12:44:56 PM PST 23 9057561179 ps
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