Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20217351

1

T1

5408

T2

37341

T3

90928

auto[1]

10008561

1

T1

3464

T3

29651

T4

43653

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9818342

1

T1

2633

T3

21960

T4

44635

auto[1]

20407570

1

T1

6239

T2

37341

T3

98619

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17793419

1

T1

2916

T2

37341

T3

89278

auto[1]

12432493

1

T1

5956

T3

31301

T4

59227

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16760911	1			T1	7649		T2	34930		T3	114487
fifo_depth[1]	1528575	1			T1	559		T2	1444		T3	3694
fifo_depth[2]	1389602	1			T1	364		T2	638		T3	1532
fifo_depth[3]	1185544	1			T1	194		T2	238		T3	430
fifo_depth[4]	1156824	1			T1	81		T2	69		T3	296
fifo_depth[5]	983645	1			T1	18		T2	16		T3	77
fifo_depth[6]	1020781	1			T1	6		T2	5		T3	50
fifo_depth[7]	868248	1			T1	1		T2	1		T3	10
fifo_depth[8]	1033249	1			T3	3		T4	1		T9	822
fifo_depth[9]	600888	1			T9	590		T5	7119		T6	102
fifo_depth[10]	612320	1			T9	359		T5	5396		T6	43
fifo_depth[11]	368592	1			T9	189		T5	3267		T6	8
fifo_depth[12]	635877	1			T9	95		T5	3027		T6	9
fifo_depth[13]	276816	1			T9	45		T5	1519		T7	1829
fifo_depth[14]	458870	1			T9	20		T5	1451		T7	3921
fifo_depth[15]	254413	1			T9	6		T5	919		T7	1676
fifo_depth[16]	1090757	1			T9	2		T5	2909		T7	9155

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13465001

1

T1

1223

T2

2411

T3

6092

auto[1]

16760911

1

T1

7649

T2

34930

T3

114487

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29135155

1

T1

8872

T2

37341

T3

120579

auto[1]

1090757

1

T9

2

T5

2909

T7

9155

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1000897

1

T1

284

T3

252

T4

701

auto[0]

auto[0]

auto[0]

auto[1]

991511

1

T3

384

T4

356

T5

1774

auto[0]

auto[0]

auto[1]

auto[0]

3668587

1

T1

51

T2

2411

T3

2560

auto[0]

auto[0]

auto[1]

auto[1]

1064138

1

T1

54

T3

248

T4

595

auto[0]

auto[1]

auto[0]

auto[0]

1630192

1

T1

33

T3

604

T4

1179

auto[0]

auto[1]

auto[0]

auto[1]

1730475

1

T1

42

T3

542

T4

1182

auto[0]

auto[1]

auto[1]

auto[0]

1650817

1

T1

381

T3

428

T4

990

auto[0]

auto[1]

auto[1]

auto[1]

1728384

1

T1

378

T3

1074

T4

1138

auto[1]

auto[0]

auto[0]

auto[0]

850849

1

T1

1796

T3

2597

T4

8045

auto[1]

auto[0]

auto[0]

auto[1]

821922

1

T3

6113

T4

4755

T5

2051

auto[1]

auto[0]

auto[1]

auto[0]

8569173

1

T1

335

T2

34930

T3

75044

auto[1]

auto[0]

auto[1]

auto[1]

826342

1

T1

396

T3

2080

T4

7433

auto[1]

auto[1]

auto[0]

auto[0]

1386368

1

T1

218

T3

5174

T4

14328

auto[1]

auto[1]

auto[0]

auto[1]

1406128

1

T1

260

T3

6294

T4

14089

auto[1]

auto[1]

auto[1]

auto[0]

1460468

1

T1

2310

T3

4269

T4

12216

auto[1]

auto[1]

auto[1]

auto[1]

1439661

1

T1

2334

T3

12916

T4

14105

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1718487

1

T1

2080

T3

2849

T4

8746

auto[0]

auto[0]

auto[0]

auto[1]

1694356

1

T3

6497

T4

5111

T5

3824

auto[0]

auto[0]

auto[1]

auto[0]

12099059

1

T1

386

T2

37341

T3

77604

auto[0]

auto[0]

auto[1]

auto[1]

1760182

1

T1

450

T3

2328

T4

8028

auto[0]

auto[1]

auto[0]

auto[0]

2884410

1

T1

251

T3

5778

T4

15507

auto[0]

auto[1]

auto[0]

auto[1]

2990925

1

T1

302

T3

6836

T4

15271

auto[0]

auto[1]

auto[1]

auto[0]

2968377

1

T1

2691

T3

4697

T4

13206

auto[0]

auto[1]

auto[1]

auto[1]

3019359

1

T1

2712

T3

13990

T4

15243

auto[1]

auto[0]

auto[0]

auto[0]

133259

1

T5

71

T7

1035

T31

1142

auto[1]

auto[0]

auto[0]

auto[1]

119077

1

T5

1

T7

749

T31

1354

auto[1]

auto[0]

auto[1]

auto[0]

138701

1

T9

2

T5

486

T7

643

auto[1]

auto[0]

auto[1]

auto[1]

130298

1

T5

555

T7

2140

T31

227

auto[1]

auto[1]

auto[0]

auto[0]

132150

1

T5

138

T7

816

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

145678

1

T5

807

T7

1268

T31

443

auto[1]

auto[1]

auto[1]

auto[0]

142908

1

T5

259

T7

616

T31

358

auto[1]

auto[1]

auto[1]

auto[1]

148686

1

T5

592

T7

1888

T31

866

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	850849	1			T1	1796		T3	2597		T4	8045
fifo_depth[0]	auto[0]	auto[0]	auto[1]	821922	1			T3	6113		T4	4755		T5	2051
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8569173	1			T1	335		T2	34930		T3	75044
fifo_depth[0]	auto[0]	auto[1]	auto[1]	826342	1			T1	396		T3	2080		T4	7433
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1386368	1			T1	218		T3	5174		T4	14328
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1406128	1			T1	260		T3	6294		T4	14089
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1460468	1			T1	2310		T3	4269		T4	12216
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1439661	1			T1	2334		T3	12916		T4	14105
fifo_depth[1]	auto[0]	auto[0]	auto[0]	78587	1			T1	132		T3	137		T4	382
fifo_depth[1]	auto[0]	auto[0]	auto[1]	77571	1			T3	208		T4	196		T5	256
fifo_depth[1]	auto[0]	auto[1]	auto[0]	651471	1			T1	29		T2	1444		T3	1834
fifo_depth[1]	auto[0]	auto[1]	auto[1]	77096	1			T1	32		T3	80		T4	380
fifo_depth[1]	auto[1]	auto[0]	auto[0]	157760	1			T1	18		T3	249		T4	730
fifo_depth[1]	auto[1]	auto[0]	auto[1]	160899	1			T1	11		T3	315		T4	666
fifo_depth[1]	auto[1]	auto[1]	auto[0]	162209	1			T1	170		T3	209		T4	585
fifo_depth[1]	auto[1]	auto[1]	auto[1]	162982	1			T1	167		T3	662		T4	670
fifo_depth[2]	auto[0]	auto[0]	auto[0]	74042	1			T1	78		T3	66		T4	215
fifo_depth[2]	auto[0]	auto[0]	auto[1]	73514	1			T3	111		T4	90		T5	228
fifo_depth[2]	auto[0]	auto[1]	auto[0]	567825	1			T1	13		T2	638		T3	528
fifo_depth[2]	auto[0]	auto[1]	auto[1]	73067	1			T1	14		T3	91		T4	154
fifo_depth[2]	auto[1]	auto[0]	auto[0]	146789	1			T1	7		T3	179		T4	313
fifo_depth[2]	auto[1]	auto[0]	auto[1]	151028	1			T1	21		T3	152		T4	319
fifo_depth[2]	auto[1]	auto[1]	auto[0]	150987	1			T1	124		T3	128		T4	284
fifo_depth[2]	auto[1]	auto[1]	auto[1]	152350	1			T1	107		T3	277		T4	331
fifo_depth[3]	auto[0]	auto[0]	auto[0]	63614	1			T1	52		T3	26		T4	55
fifo_depth[3]	auto[0]	auto[0]	auto[1]	64873	1			T3	24		T4	33		T5	229
fifo_depth[3]	auto[0]	auto[1]	auto[0]	456412	1			T1	5		T2	238		T3	129
fifo_depth[3]	auto[0]	auto[1]	auto[1]	63821	1			T1	6		T3	19		T4	44
fifo_depth[3]	auto[1]	auto[0]	auto[0]	131071	1			T1	6		T3	68		T4	79
fifo_depth[3]	auto[1]	auto[0]	auto[1]	135649	1			T1	7		T3	46		T4	117
fifo_depth[3]	auto[1]	auto[1]	auto[0]	133706	1			T1	53		T3	35		T4	79
fifo_depth[3]	auto[1]	auto[1]	auto[1]	136398	1			T1	65		T3	83		T4	101
fifo_depth[4]	auto[0]	auto[0]	auto[0]	75074	1			T1	13		T3	12		T4	39
fifo_depth[4]	auto[0]	auto[0]	auto[1]	74889	1			T3	29		T4	31		T5	187
fifo_depth[4]	auto[0]	auto[1]	auto[0]	361282	1			T1	4		T2	69		T3	55
fifo_depth[4]	auto[0]	auto[1]	auto[1]	78184	1			T1	2		T3	41		T4	14
fifo_depth[4]	auto[1]	auto[0]	auto[0]	139720	1			T1	2		T3	62		T4	44
fifo_depth[4]	auto[1]	auto[0]	auto[1]	145324	1			T1	2		T3	21		T4	54
fifo_depth[4]	auto[1]	auto[1]	auto[0]	139129	1			T1	27		T3	41		T4	33
fifo_depth[4]	auto[1]	auto[1]	auto[1]	143222	1			T1	31		T3	35		T4	31
fifo_depth[5]	auto[0]	auto[0]	auto[0]	60439	1			T1	5		T3	6		T4	8
fifo_depth[5]	auto[0]	auto[0]	auto[1]	61116	1			T3	3		T4	4		T5	160
fifo_depth[5]	auto[0]	auto[1]	auto[0]	296582	1			T2	16		T3	8		T4	9
fifo_depth[5]	auto[0]	auto[1]	auto[1]	60981	1			T3	6		T4	3		T5	206
fifo_depth[5]	auto[1]	auto[0]	auto[0]	123973	1			T3	27		T4	9		T5	1676
fifo_depth[5]	auto[1]	auto[0]	auto[1]	128202	1			T1	1		T3	8		T4	17
fifo_depth[5]	auto[1]	auto[1]	auto[0]	124288	1			T1	6		T3	10		T4	4
fifo_depth[5]	auto[1]	auto[1]	auto[1]	128064	1			T1	6		T3	9		T4	4
fifo_depth[6]	auto[0]	auto[0]	auto[0]	69819	1			T1	3		T3	5		T4	2
fifo_depth[6]	auto[0]	auto[0]	auto[1]	70438	1			T3	6		T4	1		T5	163
fifo_depth[6]	auto[0]	auto[1]	auto[0]	270626	1			T2	5		T3	6		T4	4
fifo_depth[6]	auto[0]	auto[1]	auto[1]	73428	1			T3	9		T5	210		T6	108
fifo_depth[6]	auto[1]	auto[0]	auto[0]	131955	1			T3	15		T4	1		T5	1583
fifo_depth[6]	auto[1]	auto[0]	auto[1]	138132	1			T4	7		T5	2453		T6	115
fifo_depth[6]	auto[1]	auto[1]	auto[0]	130064	1			T1	1		T3	5		T4	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	136319	1			T1	2		T3	4		T4	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	58054	1			T1	1		T5	435		T6	25
fifo_depth[7]	auto[0]	auto[0]	auto[1]	58372	1			T5	154		T6	47		T7	457
fifo_depth[7]	auto[0]	auto[1]	auto[0]	218475	1			T2	1		T9	1179		T5	3496
fifo_depth[7]	auto[0]	auto[1]	auto[1]	59715	1			T3	2		T5	170		T6	35
fifo_depth[7]	auto[1]	auto[0]	auto[0]	116606	1			T3	4		T4	3		T5	1496
fifo_depth[7]	auto[1]	auto[0]	auto[1]	120577	1			T4	2		T5	2238		T6	57
fifo_depth[7]	auto[1]	auto[1]	auto[0]	116515	1			T4	1		T5	1680		T6	30
fifo_depth[7]	auto[1]	auto[1]	auto[1]	119934	1			T3	4		T5	1789		T6	24
fifo_depth[8]	auto[0]	auto[0]	auto[0]	82803	1			T5	317		T6	96		T7	938
fifo_depth[8]	auto[0]	auto[0]	auto[1]	90563	1			T3	3		T4	1		T5	134
fifo_depth[8]	auto[0]	auto[1]	auto[0]	205178	1			T9	822		T5	2662		T6	119
fifo_depth[8]	auto[0]	auto[1]	auto[1]	95621	1			T5	180		T6	45		T7	747
fifo_depth[8]	auto[1]	auto[0]	auto[0]	131286	1			T5	1423		T6	62		T7	1123
fifo_depth[8]	auto[1]	auto[0]	auto[1]	147208	1			T5	2324		T6	59		T7	1151
fifo_depth[8]	auto[1]	auto[1]	auto[0]	139004	1			T5	1594		T6	61		T7	825
fifo_depth[8]	auto[1]	auto[1]	auto[1]	141586	1			T5	1805		T6	63		T7	812
fifo_depth[9]	auto[0]	auto[0]	auto[0]	44677	1			T5	249		T6	8		T7	233
fifo_depth[9]	auto[0]	auto[0]	auto[1]	43965	1			T5	109		T6	18		T7	347
fifo_depth[9]	auto[0]	auto[1]	auto[0]	122289	1			T9	590		T5	1692		T6	8
fifo_depth[9]	auto[0]	auto[1]	auto[1]	46781	1			T5	142		T6	11		T7	455
fifo_depth[9]	auto[1]	auto[0]	auto[0]	84373	1			T5	946		T6	7		T7	756
fifo_depth[9]	auto[1]	auto[0]	auto[1]	86982	1			T5	1544		T6	14		T7	982
fifo_depth[9]	auto[1]	auto[1]	auto[0]	84888	1			T5	1103		T6	18		T7	542
fifo_depth[9]	auto[1]	auto[1]	auto[1]	86933	1			T5	1334		T6	18		T7	548
fifo_depth[10]	auto[0]	auto[0]	auto[0]	53060	1			T5	254		T6	3		T7	498
fifo_depth[10]	auto[0]	auto[0]	auto[1]	53932	1			T5	77		T6	1		T7	468
fifo_depth[10]	auto[0]	auto[1]	auto[0]	105253	1			T9	359		T5	1103		T6	4
fifo_depth[10]	auto[0]	auto[1]	auto[1]	62434	1			T5	151		T6	8		T7	525
fifo_depth[10]	auto[1]	auto[0]	auto[0]	80709	1			T5	602		T6	8		T7	736
fifo_depth[10]	auto[1]	auto[0]	auto[1]	89699	1			T5	1024		T6	8		T7	868
fifo_depth[10]	auto[1]	auto[1]	auto[0]	79899	1			T5	1010		T6	8		T7	576
fifo_depth[10]	auto[1]	auto[1]	auto[1]	87334	1			T5	1175		T6	3		T7	503
fifo_depth[11]	auto[0]	auto[0]	auto[0]	31807	1			T5	168		T7	130		T31	330
fifo_depth[11]	auto[0]	auto[0]	auto[1]	31215	1			T5	43		T6	1		T7	219
fifo_depth[11]	auto[0]	auto[1]	auto[0]	61611	1			T9	189		T5	569		T6	2
fifo_depth[11]	auto[0]	auto[1]	auto[1]	36770	1			T5	104		T7	450		T31	108
fifo_depth[11]	auto[1]	auto[0]	auto[0]	49583	1			T5	349		T6	2		T7	499
fifo_depth[11]	auto[1]	auto[0]	auto[1]	53202	1			T5	657		T6	1		T7	541
fifo_depth[11]	auto[1]	auto[1]	auto[0]	49856	1			T5	644		T6	1		T7	335
fifo_depth[11]	auto[1]	auto[1]	auto[1]	54548	1			T5	733		T6	1		T7	329
fifo_depth[12]	auto[0]	auto[0]	auto[0]	68129	1			T5	161		T7	851		T91	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	68691	1			T5	21		T7	567		T31	663
fifo_depth[12]	auto[0]	auto[1]	auto[0]	85869	1			T9	95		T5	383		T6	2
fifo_depth[12]	auto[0]	auto[1]	auto[1]	80600	1			T5	184		T6	1		T7	550
fifo_depth[12]	auto[1]	auto[0]	auto[0]	77376	1			T5	394		T6	3		T7	463
fifo_depth[12]	auto[1]	auto[0]	auto[1]	90858	1			T5	633		T6	3		T7	1619
fifo_depth[12]	auto[1]	auto[1]	auto[0]	76890	1			T5	678		T7	613		T8	21
fifo_depth[12]	auto[1]	auto[1]	auto[1]	87464	1			T5	573		T7	519		T8	72
fifo_depth[13]	auto[0]	auto[0]	auto[0]	28108	1			T5	123		T7	78		T31	221
fifo_depth[13]	auto[0]	auto[0]	auto[1]	28115	1			T5	9		T7	182		T31	219
fifo_depth[13]	auto[0]	auto[1]	auto[0]	38443	1			T9	45		T5	163		T7	139
fifo_depth[13]	auto[0]	auto[1]	auto[1]	34042	1			T5	167		T7	344		T31	66
fifo_depth[13]	auto[1]	auto[0]	auto[0]	34212	1			T5	105		T7	320		T91	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	38023	1			T5	220		T7	329		T8	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	34544	1			T5	336		T7	219		T8	8
fifo_depth[13]	auto[1]	auto[1]	auto[1]	41329	1			T5	396		T7	218		T91	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	52781	1			T5	80		T7	463		T31	209
fifo_depth[14]	auto[0]	auto[0]	auto[1]	48652	1			T5	3		T7	278		T31	471
fifo_depth[14]	auto[0]	auto[1]	auto[0]	57053	1			T9	20		T5	128		T7	184
fifo_depth[14]	auto[0]	auto[1]	auto[1]	59221	1			T5	147		T7	374		T31	269
fifo_depth[14]	auto[1]	auto[0]	auto[0]	59735	1			T5	50		T7	512		T8	10
fifo_depth[14]	auto[1]	auto[0]	auto[1]	64492	1			T5	140		T7	1153		T31	499
fifo_depth[14]	auto[1]	auto[1]	auto[0]	53268	1			T5	427		T7	437		T8	2
fifo_depth[14]	auto[1]	auto[1]	auto[1]	63668	1			T5	476		T7	520		T8	14
fifo_depth[15]	auto[0]	auto[0]	auto[0]	26644	1			T5	87		T7	117		T31	176
fifo_depth[15]	auto[0]	auto[0]	auto[1]	26528	1			T7	128		T31	174		T33	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	31517	1			T9	6		T5	44		T7	69
fifo_depth[15]	auto[0]	auto[1]	auto[1]	32079	1			T5	147		T7	298		T31	28
fifo_depth[15]	auto[1]	auto[0]	auto[0]	32894	1			T5	28		T7	386		T8	5
fifo_depth[15]	auto[1]	auto[0]	auto[1]	34522	1			T5	105		T7	240		T31	342
fifo_depth[15]	auto[1]	auto[1]	auto[0]	32662	1			T5	163		T7	134		T8	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	37567	1			T5	345		T7	304		T8	5
fifo_depth[16]	auto[0]	auto[0]	auto[0]	133259	1			T5	71		T7	1035		T31	1142
fifo_depth[16]	auto[0]	auto[0]	auto[1]	119077	1			T5	1		T7	749		T31	1354
fifo_depth[16]	auto[0]	auto[1]	auto[0]	138701	1			T9	2		T5	486		T7	643
fifo_depth[16]	auto[0]	auto[1]	auto[1]	130298	1			T5	555		T7	2140		T31	227
fifo_depth[16]	auto[1]	auto[0]	auto[0]	132150	1			T5	138		T7	816		T8	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	145678	1			T5	807		T7	1268		T31	443
fifo_depth[16]	auto[1]	auto[1]	auto[0]	142908	1			T5	259		T7	616		T31	358
fifo_depth[16]	auto[1]	auto[1]	auto[1]	148686	1			T5	592		T7	1888		T31	866