Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	40878834	1			T12	5		T13	1		T15	5
all_pins[1]	40878834	1			T12	5		T13	1		T15	5
all_pins[2]	40878834	1			T12	5		T13	1		T15	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88743266	1			T12	13		T13	3		T15	15
values[0x1]	33893236	1			T12	2		T19	8		T47	6
transitions[0x0=>0x1]	29839429	1			T12	2		T19	5		T47	4
transitions[0x1=>0x0]	29839450	1			T12	2		T19	6		T47	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	40703446	1			T12	5		T13	1		T15	5
all_pins[0]	values[0x1]	175388	1			T19	1		T47	1		T48	3
all_pins[0]	transitions[0x0=>0x1]	175138	1			T48	2		T98	2		T99	3
all_pins[0]	transitions[0x1=>0x0]	15803672	1			T12	2		T19	1		T48	2
all_pins[1]	values[0x0]	22964887	1			T12	5		T13	1		T15	5
all_pins[1]	values[0x1]	17913947	1			T19	6		T47	4		T48	5
all_pins[1]	transitions[0x0=>0x1]	17777122	1			T19	5		T47	4		T48	2
all_pins[1]	transitions[0x1=>0x0]	38563	1			T47	1		T98	2		T99	4
all_pins[2]	values[0x0]	25074933	1			T12	3		T13	1		T15	5
all_pins[2]	values[0x1]	15803901	1			T12	2		T19	1		T47	1
all_pins[2]	transitions[0x0=>0x1]	11887169	1			T12	2		T48	2		T99	3
all_pins[2]	transitions[0x1=>0x0]	13997215	1			T19	5		T47	3		T48	4