Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4382 1 T12 4 T15 4 T19 10
all_values[1] 4382 1 T12 4 T15 4 T19 10
all_values[2] 4382 1 T12 4 T15 4 T19 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6304 1 T12 6 T15 8 T19 18
auto[1] 6842 1 T12 6 T15 4 T19 12


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4922 1 T12 5 T15 4 T19 12
auto[1] 8224 1 T12 7 T15 8 T19 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7478 1 T12 6 T15 8 T19 16
auto[1] 5668 1 T12 6 T15 4 T19 14


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 749 1 T19 2 T47 2 T48 1
all_values[0] auto[0] auto[0] auto[1] 431 1 T15 2 T47 1 T100 2
all_values[0] auto[0] auto[1] auto[0] 885 1 T12 2 T19 3 T47 2
all_values[0] auto[0] auto[1] auto[1] 449 1 T48 1 T98 1 T99 2
all_values[0] auto[1] auto[0] auto[1] 910 1 T12 2 T15 2 T19 5
all_values[0] auto[1] auto[1] auto[1] 958 1 T47 2 T48 1 T101 1
all_values[1] auto[0] auto[0] auto[0] 805 1 T12 2 T19 1 T72 1
all_values[1] auto[0] auto[0] auto[1] 422 1 T15 1 T48 1 T72 1
all_values[1] auto[0] auto[1] auto[0] 836 1 T15 2 T19 1 T47 2
all_values[1] auto[0] auto[1] auto[1] 413 1 T19 3 T47 1 T48 3
all_values[1] auto[1] auto[0] auto[1] 869 1 T15 1 T19 2 T47 1
all_values[1] auto[1] auto[1] auto[1] 1037 1 T12 2 T19 3 T47 3
all_values[2] auto[0] auto[0] auto[0] 801 1 T12 1 T19 3 T47 4
all_values[2] auto[0] auto[0] auto[1] 431 1 T15 1 T19 1 T101 1
all_values[2] auto[0] auto[1] auto[0] 846 1 T15 2 T19 2 T98 3
all_values[2] auto[0] auto[1] auto[1] 410 1 T12 1 T48 3 T99 3
all_values[2] auto[1] auto[0] auto[1] 886 1 T12 1 T15 1 T19 4
all_values[2] auto[1] auto[1] auto[1] 1008 1 T12 1 T47 2 T48 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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