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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.58 100.00 100.00 99.76 99.49 100.00


Total test records in report: 903
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T761 /workspace/coverage/default/42.hmac_wipe_secret.1463215952 Dec 20 12:46:23 PM PST 23 Dec 20 12:47:10 PM PST 23 952903249 ps
T762 /workspace/coverage/default/37.hmac_test_sha_vectors.327375162 Dec 20 12:46:33 PM PST 23 Dec 20 12:55:14 PM PST 23 48495574519 ps
T763 /workspace/coverage/default/18.hmac_test_sha_vectors.1781776349 Dec 20 12:47:27 PM PST 23 Dec 20 12:54:30 PM PST 23 7557740830 ps
T764 /workspace/coverage/default/32.hmac_test_sha_vectors.2030994039 Dec 20 12:47:40 PM PST 23 Dec 20 12:56:02 PM PST 23 160858981344 ps
T765 /workspace/coverage/default/49.hmac_burst_wr.1435931211 Dec 20 12:47:21 PM PST 23 Dec 20 12:48:56 PM PST 23 24349174912 ps
T766 /workspace/coverage/default/39.hmac_test_hmac_vectors.245810447 Dec 20 12:46:32 PM PST 23 Dec 20 12:46:56 PM PST 23 770900150 ps
T767 /workspace/coverage/default/6.hmac_error.3915804311 Dec 20 12:41:57 PM PST 23 Dec 20 12:44:56 PM PST 23 2540165777 ps
T768 /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.4060939230 Dec 20 12:46:24 PM PST 23 Dec 20 01:15:56 PM PST 23 138122258360 ps
T769 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.1553440525 Dec 20 12:46:23 PM PST 23 Dec 20 12:52:09 PM PST 23 35706419025 ps
T770 /workspace/coverage/default/8.hmac_test_sha_vectors.3454448641 Dec 20 12:42:14 PM PST 23 Dec 20 12:50:17 PM PST 23 114218707320 ps
T771 /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.1811744294 Dec 20 12:46:45 PM PST 23 Dec 20 01:02:11 PM PST 23 53123421911 ps
T772 /workspace/coverage/default/46.hmac_smoke.276661677 Dec 20 12:46:41 PM PST 23 Dec 20 12:47:18 PM PST 23 781593653 ps
T773 /workspace/coverage/default/40.hmac_test_hmac_vectors.2440747978 Dec 20 12:46:33 PM PST 23 Dec 20 12:46:59 PM PST 23 52936092 ps
T774 /workspace/coverage/default/3.hmac_wipe_secret.3394816747 Dec 20 12:42:07 PM PST 23 Dec 20 12:43:57 PM PST 23 4936724244 ps
T775 /workspace/coverage/default/26.hmac_burst_wr.2352207353 Dec 20 12:47:39 PM PST 23 Dec 20 12:49:52 PM PST 23 5296579443 ps
T776 /workspace/coverage/default/6.hmac_datapath_stress.2077735002 Dec 20 12:41:57 PM PST 23 Dec 20 12:44:15 PM PST 23 3119202209 ps
T777 /workspace/coverage/default/19.hmac_test_hmac_vectors.1632197756 Dec 20 12:47:24 PM PST 23 Dec 20 12:48:31 PM PST 23 51046018 ps
T778 /workspace/coverage/default/36.hmac_alert_test.2214182571 Dec 20 12:46:33 PM PST 23 Dec 20 12:46:57 PM PST 23 64930647 ps
T779 /workspace/coverage/default/3.hmac_error.1469126007 Dec 20 12:42:09 PM PST 23 Dec 20 12:46:27 PM PST 23 18304017093 ps
T780 /workspace/coverage/default/5.hmac_test_hmac_vectors.525031361 Dec 20 12:41:55 PM PST 23 Dec 20 12:42:56 PM PST 23 54422521 ps
T781 /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3677035928 Dec 20 12:46:23 PM PST 23 Dec 20 01:04:01 PM PST 23 518168561983 ps
T782 /workspace/coverage/default/29.hmac_smoke.4230592849 Dec 20 12:46:55 PM PST 23 Dec 20 12:47:38 PM PST 23 220543879 ps
T783 /workspace/coverage/default/9.hmac_back_pressure.33882948 Dec 20 12:42:12 PM PST 23 Dec 20 12:43:31 PM PST 23 649243258 ps
T784 /workspace/coverage/default/8.hmac_alert_test.2309125096 Dec 20 12:42:13 PM PST 23 Dec 20 12:43:13 PM PST 23 23535202 ps
T785 /workspace/coverage/default/43.hmac_test_sha_vectors.299193622 Dec 20 12:46:29 PM PST 23 Dec 20 12:52:30 PM PST 23 9341472045 ps
T786 /workspace/coverage/default/35.hmac_long_msg.407151692 Dec 20 12:46:22 PM PST 23 Dec 20 12:46:50 PM PST 23 2014370950 ps
T787 /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1062114372 Dec 20 12:46:20 PM PST 23 Dec 20 01:11:48 PM PST 23 345527712721 ps
T788 /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3640081257 Dec 20 12:46:42 PM PST 23 Dec 20 12:58:19 PM PST 23 15803333654 ps
T789 /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.1768521743 Dec 20 12:46:22 PM PST 23 Dec 20 01:01:08 PM PST 23 255493918930 ps
T790 /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.3764827759 Dec 20 12:46:22 PM PST 23 Dec 20 12:52:13 PM PST 23 94519398004 ps
T791 /workspace/coverage/default/31.hmac_error.357527045 Dec 20 12:47:20 PM PST 23 Dec 20 12:49:09 PM PST 23 1098527195 ps
T792 /workspace/coverage/default/13.hmac_test_hmac_vectors.2656002316 Dec 20 12:42:15 PM PST 23 Dec 20 12:43:13 PM PST 23 164022982 ps
T793 /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3645196869 Dec 20 12:47:07 PM PST 23 Dec 20 12:59:24 PM PST 23 76868309409 ps
T794 /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.1242508194 Dec 20 12:46:22 PM PST 23 Dec 20 01:08:47 PM PST 23 123040425040 ps
T795 /workspace/coverage/default/19.hmac_long_msg.3795673173 Dec 20 12:46:58 PM PST 23 Dec 20 12:48:06 PM PST 23 2292929424 ps
T796 /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2032232959 Dec 20 12:46:29 PM PST 23 Dec 20 12:56:26 PM PST 23 376588629824 ps
T797 /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.1309465558 Dec 20 12:46:36 PM PST 23 Dec 20 01:02:38 PM PST 23 333572852359 ps
T798 /workspace/coverage/default/29.hmac_long_msg.1602694914 Dec 20 12:46:55 PM PST 23 Dec 20 12:48:46 PM PST 23 1447330477 ps
T799 /workspace/coverage/default/15.hmac_stress_all.1450525914 Dec 20 12:46:50 PM PST 23 Dec 20 01:08:49 PM PST 23 111176374675 ps
T800 /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.1605403250 Dec 20 12:47:35 PM PST 23 Dec 20 01:42:28 PM PST 23 77024014124 ps
T801 /workspace/coverage/default/31.hmac_test_hmac_vectors.2438604084 Dec 20 12:47:15 PM PST 23 Dec 20 12:48:07 PM PST 23 187364380 ps
T802 /workspace/coverage/default/33.hmac_alert_test.2633077837 Dec 20 12:46:20 PM PST 23 Dec 20 12:46:30 PM PST 23 161604536 ps
T130 /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1098122492 Dec 20 12:47:10 PM PST 23 Dec 20 01:37:23 PM PST 23 98264391551 ps
T803 /workspace/coverage/default/43.hmac_datapath_stress.2643321147 Dec 20 12:46:37 PM PST 23 Dec 20 12:47:27 PM PST 23 396295672 ps
T804 /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.2388876135 Dec 20 12:46:38 PM PST 23 Dec 20 12:51:28 PM PST 23 37812583231 ps
T805 /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.3168625476 Dec 20 12:46:39 PM PST 23 Dec 20 01:04:56 PM PST 23 405718116298 ps
T806 /workspace/coverage/default/18.hmac_alert_test.3810411837 Dec 20 12:47:18 PM PST 23 Dec 20 12:48:14 PM PST 23 40714025 ps
T807 /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1390349582 Dec 20 12:46:52 PM PST 23 Dec 20 01:22:48 PM PST 23 331931473948 ps
T808 /workspace/coverage/default/35.hmac_wipe_secret.1175479556 Dec 20 12:46:33 PM PST 23 Dec 20 12:47:53 PM PST 23 2801926616 ps
T809 /workspace/coverage/default/36.hmac_wipe_secret.3361298108 Dec 20 12:46:29 PM PST 23 Dec 20 12:47:25 PM PST 23 3146179479 ps
T810 /workspace/coverage/default/26.hmac_test_sha_vectors.4156037089 Dec 20 12:46:56 PM PST 23 Dec 20 12:53:15 PM PST 23 7471542692 ps
T811 /workspace/coverage/default/12.hmac_wipe_secret.475756994 Dec 20 12:42:19 PM PST 23 Dec 20 12:44:03 PM PST 23 8270177789 ps
T53 /workspace/coverage/default/0.hmac_sec_cm.1614550381 Dec 20 12:41:52 PM PST 23 Dec 20 12:42:54 PM PST 23 838553233 ps
T812 /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3396828232 Dec 20 12:46:23 PM PST 23 Dec 20 01:00:16 PM PST 23 285227375464 ps
T813 /workspace/coverage/default/41.hmac_stress_all.2947410832 Dec 20 12:46:36 PM PST 23 Dec 20 12:47:38 PM PST 23 2361941066 ps
T814 /workspace/coverage/default/39.hmac_datapath_stress.2339594385 Dec 20 12:46:39 PM PST 23 Dec 20 12:49:19 PM PST 23 2634938878 ps
T815 /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.955167765 Dec 20 12:46:17 PM PST 23 Dec 20 12:51:22 PM PST 23 81665734399 ps
T816 /workspace/coverage/default/14.hmac_burst_wr.375054813 Dec 20 12:42:11 PM PST 23 Dec 20 12:43:29 PM PST 23 1116102273 ps
T817 /workspace/coverage/default/35.hmac_datapath_stress.1339165842 Dec 20 12:46:25 PM PST 23 Dec 20 12:46:34 PM PST 23 66919409 ps
T818 /workspace/coverage/default/4.hmac_test_hmac_vectors.1450824730 Dec 20 12:41:52 PM PST 23 Dec 20 12:42:54 PM PST 23 59499669 ps
T819 /workspace/coverage/default/26.hmac_stress_all.3425486074 Dec 20 12:47:08 PM PST 23 Dec 20 12:58:27 PM PST 23 149479497421 ps
T820 /workspace/coverage/default/26.hmac_datapath_stress.502748050 Dec 20 12:47:20 PM PST 23 Dec 20 12:49:10 PM PST 23 1942332292 ps
T821 /workspace/coverage/default/36.hmac_test_hmac_vectors.2045360523 Dec 20 12:46:29 PM PST 23 Dec 20 12:46:49 PM PST 23 76353474 ps
T822 /workspace/coverage/default/26.hmac_alert_test.492861242 Dec 20 12:47:03 PM PST 23 Dec 20 12:47:46 PM PST 23 24882351 ps
T823 /workspace/coverage/default/45.hmac_test_sha_vectors.3097149514 Dec 20 12:46:40 PM PST 23 Dec 20 12:52:58 PM PST 23 74114938172 ps
T824 /workspace/coverage/default/26.hmac_back_pressure.700357750 Dec 20 12:47:08 PM PST 23 Dec 20 12:48:15 PM PST 23 1449167610 ps
T825 /workspace/coverage/default/27.hmac_burst_wr.704587002 Dec 20 12:47:22 PM PST 23 Dec 20 12:48:38 PM PST 23 460604770 ps
T826 /workspace/coverage/default/41.hmac_back_pressure.3434837818 Dec 20 12:46:39 PM PST 23 Dec 20 12:47:58 PM PST 23 3825965487 ps
T827 /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.726613323 Dec 20 12:42:01 PM PST 23 Dec 20 12:55:24 PM PST 23 47376634426 ps
T828 /workspace/coverage/default/43.hmac_wipe_secret.3921854858 Dec 20 12:46:27 PM PST 23 Dec 20 12:47:13 PM PST 23 2872376996 ps
T829 /workspace/coverage/default/36.hmac_smoke.1425393791 Dec 20 12:46:29 PM PST 23 Dec 20 12:46:51 PM PST 23 1305571288 ps
T830 /workspace/coverage/default/29.hmac_stress_all.37961633 Dec 20 12:47:08 PM PST 23 Dec 20 12:50:18 PM PST 23 124965583545 ps
T831 /workspace/coverage/default/23.hmac_back_pressure.3419350608 Dec 20 12:47:11 PM PST 23 Dec 20 12:48:53 PM PST 23 1542887017 ps
T832 /workspace/coverage/default/39.hmac_smoke.3716683187 Dec 20 12:46:36 PM PST 23 Dec 20 12:47:06 PM PST 23 991753284 ps
T833 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.153437909 Dec 20 12:46:17 PM PST 23 Dec 20 12:56:56 PM PST 23 359321966244 ps
T834 /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.3188253519 Dec 20 12:46:30 PM PST 23 Dec 20 01:12:11 PM PST 23 113945679492 ps
T835 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.3203744447 Dec 20 12:47:35 PM PST 23 Dec 20 01:47:58 PM PST 23 95565626630 ps
T836 /workspace/coverage/default/42.hmac_datapath_stress.1939676810 Dec 20 12:46:25 PM PST 23 Dec 20 12:47:37 PM PST 23 4555495724 ps
T837 /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.4188484013 Dec 20 12:46:25 PM PST 23 Dec 20 01:06:23 PM PST 23 140269801640 ps
T838 /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.3737322227 Dec 20 12:47:24 PM PST 23 Dec 20 12:58:20 PM PST 23 165770140000 ps
T839 /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.4159843296 Dec 20 12:47:17 PM PST 23 Dec 20 12:51:00 PM PST 23 38613993492 ps
T840 /workspace/coverage/default/44.hmac_wipe_secret.1229977317 Dec 20 12:46:33 PM PST 23 Dec 20 12:47:07 PM PST 23 1446246364 ps
T841 /workspace/coverage/default/13.hmac_datapath_stress.1911190949 Dec 20 12:42:18 PM PST 23 Dec 20 12:44:16 PM PST 23 1325342247 ps
T842 /workspace/coverage/default/13.hmac_test_sha_vectors.1957194959 Dec 20 12:42:10 PM PST 23 Dec 20 12:50:16 PM PST 23 74928314500 ps
T843 /workspace/coverage/default/0.hmac_test_sha_vectors.2652605088 Dec 20 12:42:00 PM PST 23 Dec 20 12:49:52 PM PST 23 27708262204 ps
T844 /workspace/coverage/default/43.hmac_stress_all.1127232986 Dec 20 12:46:31 PM PST 23 Dec 20 12:52:05 PM PST 23 31259445437 ps
T845 /workspace/coverage/default/28.hmac_long_msg.1122497017 Dec 20 12:47:17 PM PST 23 Dec 20 12:48:35 PM PST 23 8129348733 ps
T846 /workspace/coverage/default/42.hmac_alert_test.215878416 Dec 20 12:46:29 PM PST 23 Dec 20 12:46:46 PM PST 23 14037985 ps
T847 /workspace/coverage/default/44.hmac_burst_wr.3679272380 Dec 20 12:46:30 PM PST 23 Dec 20 12:47:07 PM PST 23 5371256113 ps
T848 /workspace/coverage/default/4.hmac_error.3804966158 Dec 20 12:41:53 PM PST 23 Dec 20 12:42:57 PM PST 23 1599096225 ps
T849 /workspace/coverage/default/8.hmac_burst_wr.3468936998 Dec 20 12:41:54 PM PST 23 Dec 20 12:43:54 PM PST 23 3571892231 ps
T87 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.208246007 Dec 20 12:27:35 PM PST 23 Dec 20 12:28:17 PM PST 23 7218858334 ps
T106 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.110187008 Dec 20 12:25:28 PM PST 23 Dec 20 12:25:55 PM PST 23 64781294 ps
T850 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1342487871 Dec 20 12:26:37 PM PST 23 Dec 20 12:27:10 PM PST 23 26309802 ps
T851 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3356437708 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:23 PM PST 23 11310747 ps
T852 /workspace/coverage/cover_reg_top/11.hmac_intr_test.927926122 Dec 20 12:25:42 PM PST 23 Dec 20 12:26:10 PM PST 23 40931830 ps
T853 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1147057200 Dec 20 12:25:39 PM PST 23 Dec 20 12:26:08 PM PST 23 32265393 ps
T854 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2267459488 Dec 20 12:25:26 PM PST 23 Dec 20 12:25:53 PM PST 23 23781912 ps
T855 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3087363707 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:26 PM PST 23 38482382 ps
T856 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2526202228 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:36 PM PST 23 85258415 ps
T857 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3811853261 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:11 PM PST 23 129707639 ps
T858 /workspace/coverage/cover_reg_top/24.hmac_intr_test.589283330 Dec 20 12:26:10 PM PST 23 Dec 20 12:26:37 PM PST 23 39495797 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.743022537 Dec 20 12:25:34 PM PST 23 Dec 20 12:26:06 PM PST 23 444021538 ps
T859 /workspace/coverage/cover_reg_top/2.hmac_intr_test.898477112 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:50 PM PST 23 20773361 ps
T860 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2937978966 Dec 20 12:25:57 PM PST 23 Dec 20 12:26:21 PM PST 23 84593819 ps
T861 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2828640155 Dec 20 12:25:51 PM PST 23 Dec 20 12:26:21 PM PST 23 272532649 ps
T862 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1310143137 Dec 20 12:26:12 PM PST 23 Dec 20 12:26:41 PM PST 23 19864071 ps
T863 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1792221028 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:22 PM PST 23 33763979 ps
T864 /workspace/coverage/cover_reg_top/44.hmac_intr_test.927125687 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:37 PM PST 23 24124351 ps
T865 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1496745943 Dec 20 12:25:29 PM PST 23 Dec 20 12:25:56 PM PST 23 12062232 ps
T866 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.500616789 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:29 PM PST 23 34132774 ps
T867 /workspace/coverage/cover_reg_top/4.hmac_intr_test.257391761 Dec 20 12:25:45 PM PST 23 Dec 20 12:26:13 PM PST 23 53198270 ps
T868 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3818452904 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:26 PM PST 23 174594595 ps
T869 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1698969858 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:24 PM PST 23 503967914 ps
T870 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3128288606 Dec 20 12:26:22 PM PST 23 Dec 20 12:26:56 PM PST 23 36981073 ps
T108 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2628424113 Dec 20 12:26:07 PM PST 23 Dec 20 12:26:34 PM PST 23 166965645 ps
T871 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4220904810 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:37 PM PST 23 13102028 ps
T872 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.363741440 Dec 20 12:26:24 PM PST 23 Dec 20 12:26:59 PM PST 23 150059859 ps
T873 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1454577074 Dec 20 12:26:12 PM PST 23 Dec 20 12:39:46 PM PST 23 59853244367 ps
T874 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3362479955 Dec 20 12:26:03 PM PST 23 Dec 20 12:26:26 PM PST 23 44179312 ps
T875 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4107671510 Dec 20 12:26:11 PM PST 23 Dec 20 12:26:39 PM PST 23 36706703 ps
T876 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3214006050 Dec 20 12:25:22 PM PST 23 Dec 20 12:25:47 PM PST 23 80867829 ps
T877 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1818410005 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:12 PM PST 23 242366827 ps
T878 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1027893180 Dec 20 12:25:36 PM PST 23 Dec 20 12:26:07 PM PST 23 160577363 ps
T879 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4276747806 Dec 20 12:26:26 PM PST 23 Dec 20 12:27:03 PM PST 23 166757142 ps
T880 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1320595859 Dec 20 12:26:32 PM PST 23 Dec 20 12:27:11 PM PST 23 60191708 ps
T881 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.67266987 Dec 20 12:25:20 PM PST 23 Dec 20 12:25:44 PM PST 23 114581157 ps
T882 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.423544417 Dec 20 12:25:31 PM PST 23 Dec 20 12:26:00 PM PST 23 60355626 ps
T883 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3990005389 Dec 20 12:25:24 PM PST 23 Dec 20 12:25:50 PM PST 23 600313401 ps
T884 /workspace/coverage/cover_reg_top/18.hmac_intr_test.474350045 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 14187564 ps
T885 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.9514442 Dec 20 12:27:36 PM PST 23 Dec 20 12:28:12 PM PST 23 17579820 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4035749978 Dec 20 12:26:26 PM PST 23 Dec 20 12:27:01 PM PST 23 93456240 ps
T886 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3290063427 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:22 PM PST 23 15570949 ps
T887 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3659679913 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:25 PM PST 23 16757658 ps
T888 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1365182932 Dec 20 12:26:07 PM PST 23 Dec 20 12:26:33 PM PST 23 41247143 ps
T889 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2604487281 Dec 20 12:26:26 PM PST 23 Dec 20 12:27:04 PM PST 23 242005381 ps
T890 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1620309497 Dec 20 12:25:40 PM PST 23 Dec 20 12:26:12 PM PST 23 174440088 ps
T891 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2623316524 Dec 20 12:25:55 PM PST 23 Dec 20 12:26:22 PM PST 23 436472535 ps
T892 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3664728482 Dec 20 12:25:47 PM PST 23 Dec 20 12:26:14 PM PST 23 22649952 ps
T89 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.991155898 Dec 20 12:26:04 PM PST 23 Dec 20 12:26:28 PM PST 23 23462242 ps
T893 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.936161311 Dec 20 12:25:51 PM PST 23 Dec 20 12:26:18 PM PST 23 54513912 ps
T894 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2837452162 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:11 PM PST 23 109984162 ps
T895 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3022242292 Dec 20 12:26:50 PM PST 23 Dec 20 12:27:20 PM PST 23 42619252 ps
T896 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2002662844 Dec 20 12:26:06 PM PST 23 Dec 20 12:26:31 PM PST 23 13994679 ps
T897 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4184969140 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:11 PM PST 23 20481148 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2823618714 Dec 20 12:26:53 PM PST 23 Dec 20 12:27:25 PM PST 23 189870602 ps
T898 /workspace/coverage/cover_reg_top/49.hmac_intr_test.435776555 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:30 PM PST 23 27059540 ps
T899 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.735382574 Dec 20 12:27:45 PM PST 23 Dec 20 12:28:23 PM PST 23 216393783 ps
T900 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.922487381 Dec 20 12:25:54 PM PST 23 Dec 20 12:26:20 PM PST 23 142414956 ps
T901 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.79891262 Dec 20 12:26:02 PM PST 23 Dec 20 12:26:27 PM PST 23 606427615 ps
T902 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3634501894 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:17 PM PST 23 19144824 ps
T903 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3355333564 Dec 20 12:27:32 PM PST 23 Dec 20 12:28:12 PM PST 23 282415141 ps
T109 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2552291063 Dec 20 12:26:01 PM PST 23 Dec 20 12:26:26 PM PST 23 110216230 ps

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3410379127
Short name T12
Test name
Test status
Simulation time 13092158 ps
CPU time 0.55 seconds
Started Dec 20 12:26:25 PM PST 23
Finished Dec 20 12:27:00 PM PST 23
Peak memory 183740 kb
Host smart-8ee5221d-b978-42ed-83ad-4c689b9fddeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410379127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3410379127
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2331053276
Short name T7
Test name
Test status
Simulation time 75853223594 ps
CPU time 843.39 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 01:02:30 PM PST 23
Peak memory 240744 kb
Host smart-866cba6a-cada-4ebf-8bc7-345a7b96caef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331053276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.2331053276
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.265310307
Short name T18
Test name
Test status
Simulation time 155879717 ps
CPU time 2.34 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 198404 kb
Host smart-366c0532-5f17-47bd-ad09-bf3536d90963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265310307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.265310307
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3369866592
Short name T22
Test name
Test status
Simulation time 64853216 ps
CPU time 1.67 seconds
Started Dec 20 12:26:14 PM PST 23
Finished Dec 20 12:26:46 PM PST 23
Peak memory 198604 kb
Host smart-5e7fad97-ec3d-426b-8538-248a20e30e21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369866592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3369866592
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.3265318668
Short name T92
Test name
Test status
Simulation time 413182533455 ps
CPU time 1460.55 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 01:11:16 PM PST 23
Peak memory 231764 kb
Host smart-51af2537-0473-4d99-8511-0ef56b488dab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265318668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.3265318668
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4154151026
Short name T73
Test name
Test status
Simulation time 19908530 ps
CPU time 0.65 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 194340 kb
Host smart-05ce5fe3-a78a-40bc-935d-3f0488e39e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154151026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4154151026
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1902971146
Short name T99
Test name
Test status
Simulation time 45197181 ps
CPU time 0.58 seconds
Started Dec 20 12:26:24 PM PST 23
Finished Dec 20 12:26:58 PM PST 23
Peak memory 183656 kb
Host smart-586da173-bed4-4d07-b560-6a9faa591c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902971146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1902971146
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1409943318
Short name T27
Test name
Test status
Simulation time 21466375960 ps
CPU time 66.74 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:27:29 PM PST 23
Peak memory 206804 kb
Host smart-ed3e4c1c-32ab-44f1-914c-cef74a30799d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409943318 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1409943318
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.1850777433
Short name T114
Test name
Test status
Simulation time 239333133029 ps
CPU time 2748.19 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 01:34:04 PM PST 23
Peak memory 257320 kb
Host smart-aa84896d-895d-456f-8ce6-04aa86c76fbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850777433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.1850777433
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.76310381
Short name T49
Test name
Test status
Simulation time 373021821 ps
CPU time 0.91 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:43:00 PM PST 23
Peak memory 218028 kb
Host smart-891da00c-d5d5-4021-8235-9e3c4dc4a922
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76310381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.76310381
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3556231613
Short name T70
Test name
Test status
Simulation time 162812454 ps
CPU time 2.4 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 198260 kb
Host smart-ea02eeaf-ace1-46a3-a173-7dd281f75e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556231613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3556231613
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.1986930310
Short name T5
Test name
Test status
Simulation time 97447955325 ps
CPU time 4145.06 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 01:56:01 PM PST 23
Peak memory 247912 kb
Host smart-50364c38-616b-4b63-8a1e-5bc00017736e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986930310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.1986930310
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3000142269
Short name T146
Test name
Test status
Simulation time 16908190 ps
CPU time 0.58 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 183756 kb
Host smart-f67f0fbc-7dac-45bb-b35e-fb05f95fc1e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000142269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3000142269
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.2829949988
Short name T128
Test name
Test status
Simulation time 2665584480727 ps
CPU time 5310.57 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 02:15:02 PM PST 23
Peak memory 264604 kb
Host smart-1d2a2057-8dd8-4fa7-adff-6ea1c07f6abe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829949988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.2829949988
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3370760326
Short name T132
Test name
Test status
Simulation time 39135349373 ps
CPU time 588.04 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:52:59 PM PST 23
Peak memory 206944 kb
Host smart-645cada0-8b11-40ce-a633-36350703cafd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370760326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3370760326
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2823618714
Short name T90
Test name
Test status
Simulation time 189870602 ps
CPU time 2.36 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:25 PM PST 23
Peak memory 192304 kb
Host smart-6fef4b22-755a-4cc2-85dd-5d30c113720c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823618714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2823618714
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1607610429
Short name T255
Test name
Test status
Simulation time 65938747 ps
CPU time 0.55 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:21 PM PST 23
Peak memory 193164 kb
Host smart-f857beac-3397-49f5-ac34-39068fd77d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607610429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1607610429
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.743022537
Short name T107
Test name
Test status
Simulation time 444021538 ps
CPU time 2.4 seconds
Started Dec 20 12:25:34 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 198300 kb
Host smart-df01d6a7-4345-4782-bc58-63cc9f94f64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743022537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.743022537
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3855875629
Short name T143
Test name
Test status
Simulation time 53189135 ps
CPU time 0.59 seconds
Started Dec 20 12:26:37 PM PST 23
Finished Dec 20 12:27:11 PM PST 23
Peak memory 183808 kb
Host smart-5460b833-5e43-4a5e-833e-bb0ec54cb2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855875629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3855875629
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3427523736
Short name T261
Test name
Test status
Simulation time 76782892463 ps
CPU time 1286.62 seconds
Started Dec 20 12:46:18 PM PST 23
Finished Dec 20 01:07:46 PM PST 23
Peak memory 239904 kb
Host smart-38461c84-4992-4b5d-a758-cd54351862e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427523736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.3427523736
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.153437909
Short name T833
Test name
Test status
Simulation time 359321966244 ps
CPU time 636.27 seconds
Started Dec 20 12:46:17 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 255568 kb
Host smart-2507abab-df54-472c-a803-1e87e5bc1d4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153437909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.153437909
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1098122492
Short name T130
Test name
Test status
Simulation time 98264391551 ps
CPU time 2964.58 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 01:37:23 PM PST 23
Peak memory 263080 kb
Host smart-d69d05dc-3f74-4a5a-8f20-67db7ee22964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098122492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.1098122492
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.1911534639
Short name T131
Test name
Test status
Simulation time 344600460481 ps
CPU time 3925.87 seconds
Started Dec 20 12:46:48 PM PST 23
Finished Dec 20 01:52:50 PM PST 23
Peak memory 280540 kb
Host smart-7345fe38-a0ce-46bd-99c5-6b1f6c961d94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911534639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.1911534639
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1167356419
Short name T67
Test name
Test status
Simulation time 645777947 ps
CPU time 2.46 seconds
Started Dec 20 12:25:34 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 198536 kb
Host smart-701c7361-66e9-4687-a9ef-b6ac3c86dd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167356419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1167356419
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.208246007
Short name T87
Test name
Test status
Simulation time 7218858334 ps
CPU time 6.8 seconds
Started Dec 20 12:27:35 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 192364 kb
Host smart-57e5aa27-d8e7-4e34-b30e-232b2e5c983c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208246007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.208246007
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.157356555
Short name T97
Test name
Test status
Simulation time 45205305 ps
CPU time 0.64 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 193436 kb
Host smart-a30ff0aa-a80a-4799-943e-fcc54108c366
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157356555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.157356555
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4057464404
Short name T139
Test name
Test status
Simulation time 53228989 ps
CPU time 0.89 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 198476 kb
Host smart-43320c4e-df18-45fc-b01f-ea4fea826e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057464404 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4057464404
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2473845267
Short name T82
Test name
Test status
Simulation time 20343566 ps
CPU time 0.68 seconds
Started Dec 20 12:26:37 PM PST 23
Finished Dec 20 12:27:11 PM PST 23
Peak memory 194556 kb
Host smart-9782c0ad-e2eb-4b67-a10b-9a2edb48c219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473845267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2473845267
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2267459488
Short name T854
Test name
Test status
Simulation time 23781912 ps
CPU time 0.56 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:53 PM PST 23
Peak memory 183692 kb
Host smart-230b08c1-01d6-4303-b76a-605af99dcb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267459488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2267459488
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1526976434
Short name T152
Test name
Test status
Simulation time 174309625 ps
CPU time 1.33 seconds
Started Dec 20 12:25:31 PM PST 23
Finished Dec 20 12:26:00 PM PST 23
Peak memory 192156 kb
Host smart-ebe19168-8c6e-4236-b620-cccbefe77577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526976434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1526976434
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.735382574
Short name T899
Test name
Test status
Simulation time 216393783 ps
CPU time 3.75 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:23 PM PST 23
Peak memory 198668 kb
Host smart-e66a1dfe-a304-481e-bb47-a0faccbce925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735382574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.735382574
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4158800070
Short name T85
Test name
Test status
Simulation time 97016164 ps
CPU time 1.78 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 192140 kb
Host smart-ec0431f4-da0a-4472-91f8-dfd2b75c20c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158800070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4158800070
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3799530932
Short name T20
Test name
Test status
Simulation time 116348391 ps
CPU time 2.95 seconds
Started Dec 20 12:26:47 PM PST 23
Finished Dec 20 12:27:20 PM PST 23
Peak memory 192216 kb
Host smart-226c7002-ca26-424f-a64c-29ba7409b289
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799530932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3799530932
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3439706370
Short name T76
Test name
Test status
Simulation time 50418107 ps
CPU time 0.6 seconds
Started Dec 20 12:25:23 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 193748 kb
Host smart-f47bf94d-0561-4e6b-b8aa-9d20fd955e4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439706370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3439706370
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3412972221
Short name T137
Test name
Test status
Simulation time 79391742 ps
CPU time 1.54 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 198656 kb
Host smart-458bd23d-4b16-4b7a-8aed-5917c5649bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412972221 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3412972221
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.991155898
Short name T89
Test name
Test status
Simulation time 23462242 ps
CPU time 0.7 seconds
Started Dec 20 12:26:04 PM PST 23
Finished Dec 20 12:26:28 PM PST 23
Peak memory 194376 kb
Host smart-ddb3b2ab-937e-45c0-827a-bab4a68b744a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991155898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.991155898
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4184969140
Short name T897
Test name
Test status
Simulation time 20481148 ps
CPU time 0.58 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:11 PM PST 23
Peak memory 183776 kb
Host smart-e82781b9-70ab-4f51-afb6-b5cfa48a856b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184969140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4184969140
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3990005389
Short name T883
Test name
Test status
Simulation time 600313401 ps
CPU time 1.3 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:50 PM PST 23
Peak memory 192280 kb
Host smart-365c8c92-ae9d-4099-83d5-30218860cc25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990005389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3990005389
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1320595859
Short name T880
Test name
Test status
Simulation time 60191708 ps
CPU time 3.3 seconds
Started Dec 20 12:26:32 PM PST 23
Finished Dec 20 12:27:11 PM PST 23
Peak memory 198504 kb
Host smart-04cc5d52-e7bb-44be-a138-b97be020a986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320595859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1320595859
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1475078440
Short name T138
Test name
Test status
Simulation time 108087771 ps
CPU time 2.25 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:13 PM PST 23
Peak memory 198672 kb
Host smart-67434a15-65ae-4892-8709-e090543aeaab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475078440 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1475078440
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3659679913
Short name T887
Test name
Test status
Simulation time 16757658 ps
CPU time 0.59 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 193892 kb
Host smart-ddc6f1b9-9942-4158-96cf-41914eff87cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659679913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3659679913
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2172255461
Short name T150
Test name
Test status
Simulation time 49570130 ps
CPU time 0.57 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:34 PM PST 23
Peak memory 183788 kb
Host smart-6e5c0567-2e66-4e7f-bec4-88d722a968f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172255461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2172255461
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3574889635
Short name T175
Test name
Test status
Simulation time 249649636 ps
CPU time 1.32 seconds
Started Dec 20 12:26:27 PM PST 23
Finished Dec 20 12:27:02 PM PST 23
Peak memory 192524 kb
Host smart-2c1d0a48-ffbf-4868-aec6-30b7c5258036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574889635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3574889635
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2033450040
Short name T156
Test name
Test status
Simulation time 411651125 ps
CPU time 1.27 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:45 PM PST 23
Peak memory 198740 kb
Host smart-f97a5d86-09b7-4661-bee7-71a01d8cd9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033450040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2033450040
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2998970792
Short name T102
Test name
Test status
Simulation time 181113709 ps
CPU time 2.54 seconds
Started Dec 20 12:26:10 PM PST 23
Finished Dec 20 12:26:39 PM PST 23
Peak memory 198352 kb
Host smart-8edcbf8a-ccfa-4367-b16e-c2507e9a2def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998970792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2998970792
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3678299232
Short name T26
Test name
Test status
Simulation time 40283136 ps
CPU time 1.73 seconds
Started Dec 20 12:26:14 PM PST 23
Finished Dec 20 12:26:46 PM PST 23
Peak memory 198576 kb
Host smart-443a6eab-8b32-400d-9b24-58e832b18546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678299232 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3678299232
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.119240929
Short name T171
Test name
Test status
Simulation time 66535369 ps
CPU time 0.69 seconds
Started Dec 20 12:25:52 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 194732 kb
Host smart-2c8b6701-9257-429d-a665-c85c4844d610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119240929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.119240929
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.927926122
Short name T852
Test name
Test status
Simulation time 40931830 ps
CPU time 0.58 seconds
Started Dec 20 12:25:42 PM PST 23
Finished Dec 20 12:26:10 PM PST 23
Peak memory 183820 kb
Host smart-61b62200-c673-450b-b25c-9abaf52ee01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927926122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.927926122
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2937978966
Short name T860
Test name
Test status
Simulation time 84593819 ps
CPU time 1.05 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 197068 kb
Host smart-01e827ba-8684-4d02-a475-c22e175e5b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937978966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2937978966
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4276747806
Short name T879
Test name
Test status
Simulation time 166757142 ps
CPU time 2.28 seconds
Started Dec 20 12:26:26 PM PST 23
Finished Dec 20 12:27:03 PM PST 23
Peak memory 198632 kb
Host smart-ba8292fb-1f32-476f-9622-7ef632a6adab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276747806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4276747806
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1864572971
Short name T21
Test name
Test status
Simulation time 45638283 ps
CPU time 1.13 seconds
Started Dec 20 12:26:10 PM PST 23
Finished Dec 20 12:26:38 PM PST 23
Peak memory 197740 kb
Host smart-47f13d04-445f-4919-90ca-5c888edfa16b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864572971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1864572971
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1836799556
Short name T30
Test name
Test status
Simulation time 52210444 ps
CPU time 1.54 seconds
Started Dec 20 12:26:46 PM PST 23
Finished Dec 20 12:27:18 PM PST 23
Peak memory 198624 kb
Host smart-a7434fcf-a372-4a3b-ae1a-227e8ded0055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836799556 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1836799556
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1845055243
Short name T23
Test name
Test status
Simulation time 19239981 ps
CPU time 0.67 seconds
Started Dec 20 12:26:03 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 194616 kb
Host smart-60a2c036-5ad1-44e9-8038-59cad8b2e653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845055243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1845055243
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1818410005
Short name T877
Test name
Test status
Simulation time 242366827 ps
CPU time 1.28 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 192212 kb
Host smart-f114e344-d2d1-46cd-9244-2bec9b853930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818410005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1818410005
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3273111702
Short name T68
Test name
Test status
Simulation time 88437960 ps
CPU time 1.35 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 198528 kb
Host smart-c76ae08b-274e-44cc-9448-63492222c9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273111702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3273111702
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1750407316
Short name T25
Test name
Test status
Simulation time 104473747 ps
CPU time 1.91 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 198628 kb
Host smart-3b17519e-61f3-4632-b202-d249987422b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750407316 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1750407316
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2055702897
Short name T74
Test name
Test status
Simulation time 19526840 ps
CPU time 0.65 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 194396 kb
Host smart-0dfd8866-fc74-4184-8b43-aa0c87104ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055702897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2055702897
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1113265507
Short name T96
Test name
Test status
Simulation time 250301820 ps
CPU time 1.03 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:32 PM PST 23
Peak memory 192172 kb
Host smart-8f2996b7-ee7e-41df-b455-dab906df604c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113265507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1113265507
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1027893180
Short name T878
Test name
Test status
Simulation time 160577363 ps
CPU time 1.73 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:07 PM PST 23
Peak memory 198588 kb
Host smart-88ee9323-5686-4fac-a3f1-39c2aeec12cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027893180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1027893180
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.298149689
Short name T63
Test name
Test status
Simulation time 129968361 ps
CPU time 1.25 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:51 PM PST 23
Peak memory 197900 kb
Host smart-2bb42023-48fd-487a-82d9-88295b5f26a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298149689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.298149689
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4107671510
Short name T875
Test name
Test status
Simulation time 36706703 ps
CPU time 1.92 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:39 PM PST 23
Peak memory 198688 kb
Host smart-e25c6a22-4eac-4ed3-9800-483d7995a8f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107671510 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4107671510
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3729971707
Short name T134
Test name
Test status
Simulation time 44189612 ps
CPU time 0.66 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 194348 kb
Host smart-b630185d-a60e-4699-9a3e-e61b309bfed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729971707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3729971707
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1417853433
Short name T135
Test name
Test status
Simulation time 58712095 ps
CPU time 0.56 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 183788 kb
Host smart-066f33ff-6e1f-469d-9e6e-8dc0ef39ab83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417853433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1417853433
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1258604192
Short name T172
Test name
Test status
Simulation time 327327763 ps
CPU time 1.39 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 197032 kb
Host smart-15d21f0f-4138-4fa4-8512-3e89696d139c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258604192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1258604192
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2623316524
Short name T891
Test name
Test status
Simulation time 436472535 ps
CPU time 3.6 seconds
Started Dec 20 12:25:55 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 198688 kb
Host smart-934d2dfa-09a6-46be-8173-4d6df0ff2438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623316524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2623316524
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.922487381
Short name T900
Test name
Test status
Simulation time 142414956 ps
CPU time 1.15 seconds
Started Dec 20 12:25:54 PM PST 23
Finished Dec 20 12:26:20 PM PST 23
Peak memory 198036 kb
Host smart-4087658b-1f06-4b1c-902d-5164f39f07b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922487381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.922487381
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1454577074
Short name T873
Test name
Test status
Simulation time 59853244367 ps
CPU time 785.35 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:39:46 PM PST 23
Peak memory 208324 kb
Host smart-d91f8a2b-9157-48d6-96fc-86cbb282df8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454577074 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1454577074
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1342487871
Short name T850
Test name
Test status
Simulation time 26309802 ps
CPU time 0.76 seconds
Started Dec 20 12:26:37 PM PST 23
Finished Dec 20 12:27:10 PM PST 23
Peak memory 194476 kb
Host smart-35a803de-6088-461e-af6e-27c5810fb9f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342487871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1342487871
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2523528835
Short name T47
Test name
Test status
Simulation time 107039915 ps
CPU time 0.57 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 183760 kb
Host smart-1a942e35-597c-4a1b-9dcd-27573c85f013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523528835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2523528835
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3362479955
Short name T874
Test name
Test status
Simulation time 44179312 ps
CPU time 0.77 seconds
Started Dec 20 12:26:03 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 195404 kb
Host smart-4237c1a9-beb3-4f34-9b76-eedcbf9c26e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362479955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3362479955
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1523903460
Short name T77
Test name
Test status
Simulation time 63355690 ps
CPU time 1.51 seconds
Started Dec 20 12:25:53 PM PST 23
Finished Dec 20 12:26:19 PM PST 23
Peak memory 198700 kb
Host smart-a2846281-2e81-4321-bb10-f43672f7c5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523903460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1523903460
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1365182932
Short name T888
Test name
Test status
Simulation time 41247143 ps
CPU time 1.12 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:33 PM PST 23
Peak memory 197888 kb
Host smart-6acdf9f3-bc8c-440f-9e60-e873c35f313f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365182932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1365182932
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3664728482
Short name T892
Test name
Test status
Simulation time 22649952 ps
CPU time 1.24 seconds
Started Dec 20 12:25:47 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 198592 kb
Host smart-4c204cfb-24db-4e91-9805-2033397d6394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664728482 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3664728482
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1680505011
Short name T80
Test name
Test status
Simulation time 38373287 ps
CPU time 0.61 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 194368 kb
Host smart-e4f72d01-1555-48c1-978b-fdd98ba9ea1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680505011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1680505011
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2078995072
Short name T165
Test name
Test status
Simulation time 23638443 ps
CPU time 0.55 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:41 PM PST 23
Peak memory 183664 kb
Host smart-f7613786-5719-4adc-8bbc-a9d82bf45595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078995072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2078995072
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1713651212
Short name T81
Test name
Test status
Simulation time 29617398 ps
CPU time 0.85 seconds
Started Dec 20 12:26:41 PM PST 23
Finished Dec 20 12:27:14 PM PST 23
Peak memory 191936 kb
Host smart-f7c834af-ae22-45c2-be61-a0b9f85d6d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713651212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1713651212
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.245721169
Short name T13
Test name
Test status
Simulation time 60036623 ps
CPU time 1.61 seconds
Started Dec 20 12:26:14 PM PST 23
Finished Dec 20 12:26:45 PM PST 23
Peak memory 198660 kb
Host smart-d0a2d395-0bb3-4193-9efc-f24b75dcb19c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245721169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.245721169
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2628424113
Short name T108
Test name
Test status
Simulation time 166965645 ps
CPU time 2.52 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:34 PM PST 23
Peak memory 198344 kb
Host smart-700004bd-c5ab-41af-81b3-8b549864ca82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628424113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2628424113
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4088005774
Short name T140
Test name
Test status
Simulation time 107895356 ps
CPU time 2.1 seconds
Started Dec 20 12:26:16 PM PST 23
Finished Dec 20 12:26:49 PM PST 23
Peak memory 198576 kb
Host smart-dd3dcfc4-6f6e-4836-a017-7926bf9795f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088005774 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4088005774
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3290063427
Short name T886
Test name
Test status
Simulation time 15570949 ps
CPU time 0.6 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 193776 kb
Host smart-a4bc8e63-46c0-4dc5-9b70-643b295be528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290063427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3290063427
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063323626
Short name T160
Test name
Test status
Simulation time 45652802 ps
CPU time 1 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:36 PM PST 23
Peak memory 192156 kb
Host smart-50150a99-fc8d-44a3-bc61-0b2c7ccccded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063323626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1063323626
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2243375697
Short name T69
Test name
Test status
Simulation time 105382543 ps
CPU time 1.48 seconds
Started Dec 20 12:26:04 PM PST 23
Finished Dec 20 12:26:28 PM PST 23
Peak memory 198632 kb
Host smart-0df97203-e41d-4166-9e4e-d2ed2936f740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243375697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2243375697
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2552291063
Short name T109
Test name
Test status
Simulation time 110216230 ps
CPU time 1.79 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 198280 kb
Host smart-5c6fc257-b92f-4663-b8f2-53a48999ceb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552291063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2552291063
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1395663076
Short name T28
Test name
Test status
Simulation time 115398080 ps
CPU time 1.7 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:36 PM PST 23
Peak memory 198496 kb
Host smart-8ee89055-1c34-46e0-a311-2cded798cd89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395663076 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1395663076
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.474350045
Short name T884
Test name
Test status
Simulation time 14187564 ps
CPU time 0.57 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 183680 kb
Host smart-aae6ea32-f3f7-48b3-ad4e-b30e7976d7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474350045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.474350045
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3112157955
Short name T79
Test name
Test status
Simulation time 64107923 ps
CPU time 0.76 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 191920 kb
Host smart-953ee88c-45c3-4d44-9548-bfe6e4ae8929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112157955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3112157955
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2731183758
Short name T151
Test name
Test status
Simulation time 32073744 ps
CPU time 1.51 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 198588 kb
Host smart-8db3d11e-0d1c-4717-96f4-f7cc726e92ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731183758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2731183758
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.79891262
Short name T901
Test name
Test status
Simulation time 606427615 ps
CPU time 1.75 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:27 PM PST 23
Peak memory 198280 kb
Host smart-fadfcff8-d9d2-44ca-a696-3767e8e5df08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79891262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.79891262
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2135408958
Short name T29
Test name
Test status
Simulation time 68286155 ps
CPU time 1.28 seconds
Started Dec 20 12:26:13 PM PST 23
Finished Dec 20 12:26:43 PM PST 23
Peak memory 198508 kb
Host smart-62067424-7dab-45b3-90bc-d04e52b0f452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135408958 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2135408958
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2822159311
Short name T83
Test name
Test status
Simulation time 93529899 ps
CPU time 0.66 seconds
Started Dec 20 12:26:25 PM PST 23
Finished Dec 20 12:27:00 PM PST 23
Peak memory 194536 kb
Host smart-2ef73bd7-51bc-4664-b83f-8000725236e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822159311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2822159311
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2022952276
Short name T148
Test name
Test status
Simulation time 38684104 ps
CPU time 0.57 seconds
Started Dec 20 12:26:18 PM PST 23
Finished Dec 20 12:26:51 PM PST 23
Peak memory 183800 kb
Host smart-5b167146-7e11-4f54-a3da-b4a63f08ce72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022952276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2022952276
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1718654866
Short name T178
Test name
Test status
Simulation time 51585582 ps
CPU time 1.12 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:28 PM PST 23
Peak memory 192208 kb
Host smart-8a70f1f2-7a8b-4366-8443-742677e06b55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718654866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1718654866
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3505363726
Short name T66
Test name
Test status
Simulation time 188216179 ps
CPU time 2.61 seconds
Started Dec 20 12:26:25 PM PST 23
Finished Dec 20 12:27:01 PM PST 23
Peak memory 198660 kb
Host smart-a8e11986-855e-48f6-bf10-84a485fd35d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505363726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3505363726
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.296463536
Short name T104
Test name
Test status
Simulation time 1548945399 ps
CPU time 1.95 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 198184 kb
Host smart-31dc0408-1864-47ea-a816-6e23d8f3f06c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296463536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.296463536
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4035749978
Short name T88
Test name
Test status
Simulation time 93456240 ps
CPU time 1.12 seconds
Started Dec 20 12:26:26 PM PST 23
Finished Dec 20 12:27:01 PM PST 23
Peak memory 192192 kb
Host smart-2c6c2c55-024a-4868-acc3-0af1238833b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035749978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4035749978
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2006937497
Short name T144
Test name
Test status
Simulation time 347103170 ps
CPU time 3.71 seconds
Started Dec 20 12:25:47 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 192272 kb
Host smart-100bf847-b0b9-4c2b-b3d1-dcfe4ac81d67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006937497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2006937497
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3565993806
Short name T17
Test name
Test status
Simulation time 35829149 ps
CPU time 0.69 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 194480 kb
Host smart-637e3e1b-51ae-4616-8020-9ad7c5eec9a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565993806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3565993806
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3087363707
Short name T855
Test name
Test status
Simulation time 38482382 ps
CPU time 1.54 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 198540 kb
Host smart-6202e928-890e-400a-bd51-2a4bc22355d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087363707 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3087363707
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3022242292
Short name T895
Test name
Test status
Simulation time 42619252 ps
CPU time 0.68 seconds
Started Dec 20 12:26:50 PM PST 23
Finished Dec 20 12:27:20 PM PST 23
Peak memory 194612 kb
Host smart-58172fd6-2955-425d-95ec-2ee1af9b0300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022242292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3022242292
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.898477112
Short name T859
Test name
Test status
Simulation time 20773361 ps
CPU time 0.6 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:50 PM PST 23
Peak memory 183768 kb
Host smart-40f2fd4a-1077-45d3-9563-be91adbab0bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898477112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.898477112
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1147057200
Short name T853
Test name
Test status
Simulation time 32265393 ps
CPU time 0.87 seconds
Started Dec 20 12:25:39 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 191952 kb
Host smart-cf41bedd-d6be-40d8-9f67-815a3a08456e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147057200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1147057200
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3738014008
Short name T166
Test name
Test status
Simulation time 609677352 ps
CPU time 3.31 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 198684 kb
Host smart-7bf45f07-c9b5-40d5-894c-bcf70e68831c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738014008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3738014008
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.363741440
Short name T872
Test name
Test status
Simulation time 150059859 ps
CPU time 1.21 seconds
Started Dec 20 12:26:24 PM PST 23
Finished Dec 20 12:26:59 PM PST 23
Peak memory 197784 kb
Host smart-15817dc9-79c0-4d91-9390-fc6880391c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363741440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.363741440
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2862783841
Short name T147
Test name
Test status
Simulation time 32610519 ps
CPU time 0.62 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:36 PM PST 23
Peak memory 183676 kb
Host smart-62defa37-5ed0-4a0a-8ed0-85fa63448844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862783841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2862783841
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2246657705
Short name T168
Test name
Test status
Simulation time 34816110 ps
CPU time 0.56 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:36 PM PST 23
Peak memory 183596 kb
Host smart-a889e262-840f-4ece-a7a2-15f16126baa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246657705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2246657705
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.468286969
Short name T72
Test name
Test status
Simulation time 15705474 ps
CPU time 0.57 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:28 PM PST 23
Peak memory 183760 kb
Host smart-a79dcec0-8a06-45d7-8a8b-12497b6eb7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468286969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.468286969
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3230744717
Short name T176
Test name
Test status
Simulation time 48763299 ps
CPU time 0.57 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 183740 kb
Host smart-c5e7fd16-3061-4263-a90a-3cff4ef096c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230744717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3230744717
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.589283330
Short name T858
Test name
Test status
Simulation time 39495797 ps
CPU time 0.54 seconds
Started Dec 20 12:26:10 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 183744 kb
Host smart-1119d338-c0fb-447e-932e-24f79c1138fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589283330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.589283330
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1859831972
Short name T154
Test name
Test status
Simulation time 12790199 ps
CPU time 0.56 seconds
Started Dec 20 12:26:15 PM PST 23
Finished Dec 20 12:26:46 PM PST 23
Peak memory 183776 kb
Host smart-9a3e432a-e1f9-4ae6-83e7-eef230c63ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859831972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1859831972
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2575568600
Short name T158
Test name
Test status
Simulation time 50248679 ps
CPU time 0.56 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 183776 kb
Host smart-49826e81-8a38-44b0-b106-3038adbd8b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575568600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2575568600
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1340500005
Short name T98
Test name
Test status
Simulation time 164094162 ps
CPU time 0.59 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 183760 kb
Host smart-ab32d68e-ad8d-4e12-b5e0-f12c22eedaa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340500005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1340500005
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.846428360
Short name T75
Test name
Test status
Simulation time 23226599 ps
CPU time 0.56 seconds
Started Dec 20 12:26:10 PM PST 23
Finished Dec 20 12:26:38 PM PST 23
Peak memory 183672 kb
Host smart-f15ecd8c-2f84-4eba-90b5-d54bdcaf2838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846428360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.846428360
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2049979363
Short name T145
Test name
Test status
Simulation time 30555105 ps
CPU time 0.56 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:33 PM PST 23
Peak memory 183804 kb
Host smart-efd0776c-d994-4588-80ac-13d3019c7293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049979363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2049979363
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.386608612
Short name T64
Test name
Test status
Simulation time 56467150 ps
CPU time 1.17 seconds
Started Dec 20 12:25:32 PM PST 23
Finished Dec 20 12:26:01 PM PST 23
Peak memory 192220 kb
Host smart-4da0a602-8f2c-48c4-99d0-cb87ad182100
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386608612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.386608612
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2828640155
Short name T861
Test name
Test status
Simulation time 272532649 ps
CPU time 2.95 seconds
Started Dec 20 12:25:51 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 192208 kb
Host smart-ab05a493-467f-4285-9c53-e0104a94b35f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828640155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2828640155
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.642083222
Short name T173
Test name
Test status
Simulation time 13717956 ps
CPU time 0.65 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 193916 kb
Host smart-e82ed254-3816-4617-b2e7-b67720425e59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642083222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.642083222
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1391863287
Short name T93
Test name
Test status
Simulation time 35165462 ps
CPU time 0.75 seconds
Started Dec 20 12:25:37 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 194756 kb
Host smart-32f703f7-fa47-4fd2-9572-94afa2ad99cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391863287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1391863287
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2002662844
Short name T896
Test name
Test status
Simulation time 13994679 ps
CPU time 0.55 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 183704 kb
Host smart-6593cc3e-56eb-40a2-a52b-5ac6382a5f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002662844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2002662844
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2837452162
Short name T894
Test name
Test status
Simulation time 109984162 ps
CPU time 0.76 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:11 PM PST 23
Peak memory 195328 kb
Host smart-fdb9beab-3fd5-4476-a705-0b6b47198a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837452162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2837452162
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1620309497
Short name T890
Test name
Test status
Simulation time 174440088 ps
CPU time 3.69 seconds
Started Dec 20 12:25:40 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 198712 kb
Host smart-a9888fe2-84c7-49d2-a764-2f4a6a4ac06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620309497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1620309497
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1698969858
Short name T869
Test name
Test status
Simulation time 503967914 ps
CPU time 1.77 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 198416 kb
Host smart-34b82387-aaa5-4156-afbc-a088d21fc640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698969858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1698969858
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4220904810
Short name T871
Test name
Test status
Simulation time 13102028 ps
CPU time 0.63 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 183768 kb
Host smart-87b2a411-509e-4950-a01e-b30ae88823b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220904810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4220904810
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.221543410
Short name T141
Test name
Test status
Simulation time 14591629 ps
CPU time 0.53 seconds
Started Dec 20 12:26:34 PM PST 23
Finished Dec 20 12:27:08 PM PST 23
Peak memory 183608 kb
Host smart-05dde2ee-efc0-49cc-9022-712adad6eb33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221543410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.221543410
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3128288606
Short name T870
Test name
Test status
Simulation time 36981073 ps
CPU time 0.55 seconds
Started Dec 20 12:26:22 PM PST 23
Finished Dec 20 12:26:56 PM PST 23
Peak memory 183872 kb
Host smart-e8d4bdc1-a3bb-4666-bed5-31e4118e89d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128288606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3128288606
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1658080696
Short name T149
Test name
Test status
Simulation time 14068864 ps
CPU time 0.6 seconds
Started Dec 20 12:26:16 PM PST 23
Finished Dec 20 12:26:49 PM PST 23
Peak memory 183684 kb
Host smart-1bb5cc1f-af70-406c-bfdd-4f7497352c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658080696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1658080696
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2526202228
Short name T856
Test name
Test status
Simulation time 85258415 ps
CPU time 0.56 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:36 PM PST 23
Peak memory 183740 kb
Host smart-ef347a59-fc84-48da-82ba-3c40acb94c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526202228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2526202228
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.185833592
Short name T161
Test name
Test status
Simulation time 51304103 ps
CPU time 0.6 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 183752 kb
Host smart-f2736eb9-8db6-432c-87eb-b6ac473f8159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185833592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.185833592
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1594665368
Short name T155
Test name
Test status
Simulation time 186489060 ps
CPU time 0.55 seconds
Started Dec 20 12:26:36 PM PST 23
Finished Dec 20 12:27:10 PM PST 23
Peak memory 183784 kb
Host smart-7341ccc7-312d-48f6-95ab-d665c016d396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594665368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1594665368
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1792221028
Short name T863
Test name
Test status
Simulation time 33763979 ps
CPU time 0.59 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 183620 kb
Host smart-b7debcf3-f5f5-4797-914e-c4647938d232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792221028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1792221028
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.211089771
Short name T48
Test name
Test status
Simulation time 15312817 ps
CPU time 0.57 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 183760 kb
Host smart-2c4db2d7-5b11-47ed-8973-fa6505afebba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211089771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.211089771
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4104045244
Short name T136
Test name
Test status
Simulation time 32926214 ps
CPU time 0.57 seconds
Started Dec 20 12:26:20 PM PST 23
Finished Dec 20 12:27:00 PM PST 23
Peak memory 183784 kb
Host smart-81dd70d1-1641-4f9f-8ec0-b128c4768f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104045244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4104045244
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.936161311
Short name T893
Test name
Test status
Simulation time 54513912 ps
CPU time 1.24 seconds
Started Dec 20 12:25:51 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 184032 kb
Host smart-8a24a6d4-d7a8-45e0-a01b-31d0ec6af1d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936161311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.936161311
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3299462642
Short name T86
Test name
Test status
Simulation time 348370814 ps
CPU time 3.53 seconds
Started Dec 20 12:25:30 PM PST 23
Finished Dec 20 12:26:01 PM PST 23
Peak memory 192168 kb
Host smart-b1bc216e-d5bb-4514-86d8-3acfaa8d0215
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299462642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3299462642
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.500616789
Short name T866
Test name
Test status
Simulation time 34132774 ps
CPU time 0.65 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:29 PM PST 23
Peak memory 194144 kb
Host smart-0b35edee-00e9-47ae-b368-138bb0416ec0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500616789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.500616789
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3634501894
Short name T902
Test name
Test status
Simulation time 19144824 ps
CPU time 1.03 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 198372 kb
Host smart-76e52aa1-a503-4213-9c8d-876be177d56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634501894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3634501894
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3391028633
Short name T163
Test name
Test status
Simulation time 72472355 ps
CPU time 0.65 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 193736 kb
Host smart-b7372538-fef5-41dd-97b3-3ce8c1534337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391028633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3391028633
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.257391761
Short name T867
Test name
Test status
Simulation time 53198270 ps
CPU time 0.55 seconds
Started Dec 20 12:25:45 PM PST 23
Finished Dec 20 12:26:13 PM PST 23
Peak memory 183848 kb
Host smart-0c15a9ec-c4ed-453e-86b1-3d6e2c248b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257391761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.257391761
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3214006050
Short name T876
Test name
Test status
Simulation time 80867829 ps
CPU time 1.43 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 192172 kb
Host smart-e3fb5eac-901c-4d9f-b9d2-49414113094e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214006050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3214006050
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4132003426
Short name T78
Test name
Test status
Simulation time 924542365 ps
CPU time 1.82 seconds
Started Dec 20 12:25:35 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 198076 kb
Host smart-993e5eb2-efa5-4a6d-ad01-3ab93de70b39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132003426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4132003426
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3356437708
Short name T851
Test name
Test status
Simulation time 11310747 ps
CPU time 0.58 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:23 PM PST 23
Peak memory 183716 kb
Host smart-1c9f8e0d-4c9e-4369-bcdd-ec9716bbe89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356437708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3356437708
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2677412099
Short name T100
Test name
Test status
Simulation time 41465120 ps
CPU time 0.56 seconds
Started Dec 20 12:25:56 PM PST 23
Finished Dec 20 12:26:20 PM PST 23
Peak memory 183736 kb
Host smart-57c12437-6d0d-415f-aab2-1f5696d2ae12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677412099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2677412099
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2315611434
Short name T170
Test name
Test status
Simulation time 22085049 ps
CPU time 0.56 seconds
Started Dec 20 12:25:58 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 183812 kb
Host smart-1e07ff35-ff19-4219-92be-802cab98c1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315611434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2315611434
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.927125687
Short name T864
Test name
Test status
Simulation time 24124351 ps
CPU time 0.6 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 183692 kb
Host smart-e6cf97b5-8237-4e04-b9ac-5a62a3e95c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927125687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.927125687
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3227766419
Short name T162
Test name
Test status
Simulation time 21152128 ps
CPU time 0.58 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 183768 kb
Host smart-f8cac04c-2610-48fb-8e37-9b3918b5cfbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227766419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3227766419
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.120963140
Short name T164
Test name
Test status
Simulation time 31770690 ps
CPU time 0.56 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 183784 kb
Host smart-c90b048c-33d0-4a75-8003-7fa7834f4866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120963140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.120963140
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2271945371
Short name T157
Test name
Test status
Simulation time 72728081 ps
CPU time 0.57 seconds
Started Dec 20 12:26:04 PM PST 23
Finished Dec 20 12:26:27 PM PST 23
Peak memory 183828 kb
Host smart-0283d6c8-bab4-4ad8-a968-0bc4a42898dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271945371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2271945371
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2429283961
Short name T142
Test name
Test status
Simulation time 21439628 ps
CPU time 0.55 seconds
Started Dec 20 12:26:18 PM PST 23
Finished Dec 20 12:26:52 PM PST 23
Peak memory 183812 kb
Host smart-c1f6fe72-2f57-40e1-b9f4-1b96284f8715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429283961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2429283961
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.435776555
Short name T898
Test name
Test status
Simulation time 27059540 ps
CPU time 0.56 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 183744 kb
Host smart-e542caf3-ef4a-430f-818b-01da1c11bb8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435776555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.435776555
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.9514442
Short name T885
Test name
Test status
Simulation time 17579820 ps
CPU time 1.37 seconds
Started Dec 20 12:27:36 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 198584 kb
Host smart-9765d920-46f3-451e-890c-7707c44b8924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9514442 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.9514442
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.883313006
Short name T84
Test name
Test status
Simulation time 135877524 ps
CPU time 0.59 seconds
Started Dec 20 12:27:31 PM PST 23
Finished Dec 20 12:28:09 PM PST 23
Peak memory 194300 kb
Host smart-c0835807-21bd-4f81-a8f3-70bf4e4ea282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883313006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.883313006
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.503689907
Short name T15
Test name
Test status
Simulation time 38509686 ps
CPU time 0.54 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 183752 kb
Host smart-eb5f81c4-8a26-4c12-816e-c3192d26c1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503689907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.503689907
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.423544417
Short name T882
Test name
Test status
Simulation time 60355626 ps
CPU time 1.07 seconds
Started Dec 20 12:25:31 PM PST 23
Finished Dec 20 12:26:00 PM PST 23
Peak memory 196300 kb
Host smart-ef589543-8dc1-45e4-aba5-8c92fc2c948d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423544417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.423544417
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1687168523
Short name T65
Test name
Test status
Simulation time 102400063 ps
CPU time 1.46 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 198424 kb
Host smart-e8e25763-1c26-4d11-be92-beec6765f0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687168523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1687168523
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.110187008
Short name T106
Test name
Test status
Simulation time 64781294 ps
CPU time 1.16 seconds
Started Dec 20 12:25:28 PM PST 23
Finished Dec 20 12:25:55 PM PST 23
Peak memory 197892 kb
Host smart-20a99ec9-fdf0-4fac-97e1-8fe7115f5808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110187008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.110187008
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.426780714
Short name T24
Test name
Test status
Simulation time 86364702 ps
CPU time 1.02 seconds
Started Dec 20 12:25:56 PM PST 23
Finished Dec 20 12:26:20 PM PST 23
Peak memory 198440 kb
Host smart-4b82e9cc-2d20-4aa1-84a6-d0caeb1014e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426780714 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.426780714
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3811853261
Short name T857
Test name
Test status
Simulation time 129707639 ps
CPU time 0.69 seconds
Started Dec 20 12:25:43 PM PST 23
Finished Dec 20 12:26:11 PM PST 23
Peak memory 194520 kb
Host smart-6578202c-ef4f-4f75-b039-832ba38c7a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811853261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3811853261
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4181313213
Short name T19
Test name
Test status
Simulation time 135167959 ps
CPU time 0.6 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 183780 kb
Host smart-bfc5683a-25f5-40c3-b1f3-852a8345edbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181313213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4181313213
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3355333564
Short name T903
Test name
Test status
Simulation time 282415141 ps
CPU time 0.79 seconds
Started Dec 20 12:27:32 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 195832 kb
Host smart-0f02c439-3091-4f9d-8ef4-0ffb3f045b24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355333564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3355333564
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2604487281
Short name T889
Test name
Test status
Simulation time 242005381 ps
CPU time 4.03 seconds
Started Dec 20 12:26:26 PM PST 23
Finished Dec 20 12:27:04 PM PST 23
Peak memory 198684 kb
Host smart-d7a72ccb-bc99-4083-924a-a0657611e84d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604487281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2604487281
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.67266987
Short name T881
Test name
Test status
Simulation time 114581157 ps
CPU time 1.89 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:44 PM PST 23
Peak memory 198260 kb
Host smart-4895a4c1-0f6c-497c-a0a0-7f2d6071f1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67266987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.67266987
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3625555912
Short name T169
Test name
Test status
Simulation time 123062151 ps
CPU time 1.76 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 198528 kb
Host smart-c6816106-6607-4d32-a8c9-d094ebf30a36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625555912 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3625555912
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2423490869
Short name T95
Test name
Test status
Simulation time 85804931 ps
CPU time 0.71 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 194680 kb
Host smart-74d7c3c7-3deb-40f1-8ba0-965923fd8486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423490869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2423490869
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2893699268
Short name T101
Test name
Test status
Simulation time 10757040 ps
CPU time 0.57 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 183824 kb
Host smart-c802471b-a7fe-416b-b287-33f92fe4f5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893699268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2893699268
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1957691983
Short name T71
Test name
Test status
Simulation time 59504814 ps
CPU time 1.09 seconds
Started Dec 20 12:26:21 PM PST 23
Finished Dec 20 12:26:55 PM PST 23
Peak memory 196680 kb
Host smart-51f515d5-c996-4ee8-9f1f-3998a51446f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957691983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1957691983
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4134574542
Short name T167
Test name
Test status
Simulation time 312988067 ps
CPU time 3.04 seconds
Started Dec 20 12:25:42 PM PST 23
Finished Dec 20 12:26:13 PM PST 23
Peak memory 198608 kb
Host smart-903645e7-91d4-4b19-aae5-eb25f5fbcd13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134574542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4134574542
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4051102290
Short name T105
Test name
Test status
Simulation time 101671540 ps
CPU time 1.69 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:27:25 PM PST 23
Peak memory 198012 kb
Host smart-1d6af2b3-7e5e-47ba-ba63-4640fe6daafc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051102290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4051102290
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1310143137
Short name T862
Test name
Test status
Simulation time 19864071 ps
CPU time 0.8 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:41 PM PST 23
Peak memory 198396 kb
Host smart-cb089034-74fe-43eb-954b-98e31413e116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310143137 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1310143137
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1622651979
Short name T94
Test name
Test status
Simulation time 41133766 ps
CPU time 0.69 seconds
Started Dec 20 12:25:47 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 194472 kb
Host smart-7a81696b-936c-4dc5-8e38-f3f4d6f1371b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622651979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1622651979
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3882123877
Short name T153
Test name
Test status
Simulation time 16154477 ps
CPU time 0.59 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 183772 kb
Host smart-0c43604b-c3a5-4672-9705-74803db135e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882123877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3882123877
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1561486469
Short name T177
Test name
Test status
Simulation time 66641450 ps
CPU time 1.15 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:51 PM PST 23
Peak memory 192384 kb
Host smart-6759f62a-efb0-4c4a-8cfd-8a2f834f773b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561486469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1561486469
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.822514451
Short name T174
Test name
Test status
Simulation time 250076748 ps
CPU time 2.89 seconds
Started Dec 20 12:25:27 PM PST 23
Finished Dec 20 12:25:56 PM PST 23
Peak memory 198664 kb
Host smart-765eb59b-f3bd-4194-b7f0-7b533631d4cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822514451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.822514451
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3161367339
Short name T14
Test name
Test status
Simulation time 48540010 ps
CPU time 0.93 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 198320 kb
Host smart-f96a20c5-eb0a-48ac-86c4-4f101757b0d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161367339 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3161367339
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1221191545
Short name T16
Test name
Test status
Simulation time 24465005 ps
CPU time 0.69 seconds
Started Dec 20 12:25:41 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 194512 kb
Host smart-15da652a-4c9e-456b-a903-9cc75c9fd9a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221191545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1221191545
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1496745943
Short name T865
Test name
Test status
Simulation time 12062232 ps
CPU time 0.59 seconds
Started Dec 20 12:25:29 PM PST 23
Finished Dec 20 12:25:56 PM PST 23
Peak memory 183852 kb
Host smart-29009e94-432d-43cf-9dfd-21eb00350534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496745943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1496745943
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.616069011
Short name T159
Test name
Test status
Simulation time 30185936 ps
CPU time 0.75 seconds
Started Dec 20 12:25:35 PM PST 23
Finished Dec 20 12:26:05 PM PST 23
Peak memory 191972 kb
Host smart-8bc197a5-4210-4fc7-9da8-43f54cf53868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616069011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.616069011
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3818452904
Short name T868
Test name
Test status
Simulation time 174594595 ps
CPU time 3.24 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 198692 kb
Host smart-50c34c2d-9a1d-436d-8741-47a1d04893fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818452904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3818452904
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2169078803
Short name T103
Test name
Test status
Simulation time 670428605 ps
CPU time 2.43 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:27:36 PM PST 23
Peak memory 198400 kb
Host smart-d48ea0e4-280c-4e14-9ddc-99cf94dcbf80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169078803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2169078803
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3287016406
Short name T413
Test name
Test status
Simulation time 105972422 ps
CPU time 0.54 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 193072 kb
Host smart-5f088c64-41a5-476a-8cc5-47caa872dc2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287016406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3287016406
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3408115901
Short name T202
Test name
Test status
Simulation time 1335144649 ps
CPU time 21.08 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:59 PM PST 23
Peak memory 216332 kb
Host smart-eb9e3fc6-a961-42d9-91d9-4b54635a065d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408115901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3408115901
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.597589030
Short name T401
Test name
Test status
Simulation time 5914815860 ps
CPU time 21.98 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:43:19 PM PST 23
Peak memory 198812 kb
Host smart-c5ed7421-e6cd-4dae-961e-1467f0b206bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597589030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.597589030
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3073459332
Short name T192
Test name
Test status
Simulation time 9172545619 ps
CPU time 118.1 seconds
Started Dec 20 12:41:50 PM PST 23
Finished Dec 20 12:44:50 PM PST 23
Peak memory 198844 kb
Host smart-103b234c-e08b-44fe-af9a-8b08441cb937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073459332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3073459332
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.181343192
Short name T711
Test name
Test status
Simulation time 1104885958 ps
CPU time 17.84 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 198748 kb
Host smart-7ae86a3f-5e2d-467c-b906-05b12ba97d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181343192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.181343192
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3836769018
Short name T423
Test name
Test status
Simulation time 3590664808 ps
CPU time 58.61 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:43:47 PM PST 23
Peak memory 198840 kb
Host smart-9c571ac4-84f5-4c28-bf85-46d875675c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836769018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3836769018
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1614550381
Short name T53
Test name
Test status
Simulation time 838553233 ps
CPU time 0.98 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 217240 kb
Host smart-c0104aa5-5f00-4fb6-9a6f-ecfbbc6ef252
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614550381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1614550381
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2067752435
Short name T428
Test name
Test status
Simulation time 1294787590 ps
CPU time 2.34 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 198356 kb
Host smart-25def43d-dd3e-4d9b-9e56-dd359f2f5b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067752435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2067752435
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3134391896
Short name T449
Test name
Test status
Simulation time 1115199582 ps
CPU time 48.36 seconds
Started Dec 20 12:41:51 PM PST 23
Finished Dec 20 12:43:41 PM PST 23
Peak memory 198648 kb
Host smart-1346181e-b424-44e1-aa76-d38a7c108a36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134391896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3134391896
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1184293358
Short name T281
Test name
Test status
Simulation time 89540925 ps
CPU time 0.9 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 195752 kb
Host smart-412716d5-0b2c-4cbd-905d-e35fe7f6edc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184293358 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1184293358
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2652605088
Short name T843
Test name
Test status
Simulation time 27708262204 ps
CPU time 411.78 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:49:52 PM PST 23
Peak memory 198984 kb
Host smart-b7f88722-d0c6-4948-bde1-7fa3aab23bec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652605088 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.2652605088
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.121669768
Short name T561
Test name
Test status
Simulation time 4104913259 ps
CPU time 45.8 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:48 PM PST 23
Peak memory 198868 kb
Host smart-38a165ad-ecdc-4750-957a-e4e07e70547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121669768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.121669768
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2050684565
Short name T723
Test name
Test status
Simulation time 33095379 ps
CPU time 0.52 seconds
Started Dec 20 12:41:54 PM PST 23
Finished Dec 20 12:42:56 PM PST 23
Peak memory 193172 kb
Host smart-08df23ff-4139-405a-87ae-8add2dc07d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050684565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2050684565
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1355481897
Short name T451
Test name
Test status
Simulation time 650396786 ps
CPU time 4.58 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:43:00 PM PST 23
Peak memory 198784 kb
Host smart-a2f6c2b2-5fa6-4d80-855b-04e87bb8d2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355481897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1355481897
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.4053326481
Short name T474
Test name
Test status
Simulation time 4521103337 ps
CPU time 20.28 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:21 PM PST 23
Peak memory 198952 kb
Host smart-fbceff4d-10be-4aa2-821c-13fb352a662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053326481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4053326481
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2435086521
Short name T554
Test name
Test status
Simulation time 1397670095 ps
CPU time 68.32 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:44:04 PM PST 23
Peak memory 198620 kb
Host smart-930d83ad-4c07-4eaa-813c-abd19129d11e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435086521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2435086521
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.102923272
Short name T517
Test name
Test status
Simulation time 29005788986 ps
CPU time 80.11 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:44:16 PM PST 23
Peak memory 198932 kb
Host smart-4d75f41f-97d9-494e-8a90-d4b1d69495a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102923272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.102923272
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.775819676
Short name T458
Test name
Test status
Simulation time 1029425012 ps
CPU time 52.09 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:43:49 PM PST 23
Peak memory 198792 kb
Host smart-8b655a4c-ed47-4cf9-ac2c-6c7a89b09a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775819676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.775819676
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.837789712
Short name T52
Test name
Test status
Simulation time 127829802 ps
CPU time 0.95 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 215924 kb
Host smart-3b75f7d1-cd5f-4b84-be9f-75183ec92f6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837789712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.837789712
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2344184653
Short name T260
Test name
Test status
Simulation time 80897896 ps
CPU time 2.05 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:03 PM PST 23
Peak memory 198676 kb
Host smart-ae173706-0987-4231-a5b6-9b6c4e73f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344184653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2344184653
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2399989388
Short name T285
Test name
Test status
Simulation time 18303232862 ps
CPU time 441.98 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:50:22 PM PST 23
Peak memory 198824 kb
Host smart-80f6a207-8763-407b-9407-e5e75dc133a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399989388 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2399989388
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3323836818
Short name T538
Test name
Test status
Simulation time 600529084461 ps
CPU time 2747.81 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 01:28:49 PM PST 23
Peak memory 239800 kb
Host smart-21a6ddd3-5303-449b-9c8d-2ac4ccd58b6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323836818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3323836818
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2875587432
Short name T646
Test name
Test status
Simulation time 91508531 ps
CPU time 0.92 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 195752 kb
Host smart-bb42cd34-4b74-4fea-ae7b-abbfe46d61c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875587432 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2875587432
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2321889964
Short name T478
Test name
Test status
Simulation time 126496222474 ps
CPU time 369.02 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:49:07 PM PST 23
Peak memory 198900 kb
Host smart-8091302c-52a0-42be-acf6-0d94a4b610a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321889964 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.2321889964
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2993101743
Short name T529
Test name
Test status
Simulation time 1352450535 ps
CPU time 54.25 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 198728 kb
Host smart-fd745b59-8075-47a8-8430-f9c99be6f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993101743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2993101743
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2919872690
Short name T407
Test name
Test status
Simulation time 17073271 ps
CPU time 0.56 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 193264 kb
Host smart-aa3374f0-64ee-429d-8b2f-ff0bc7ceb246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919872690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2919872690
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1379753172
Short name T212
Test name
Test status
Simulation time 850523285 ps
CPU time 31.38 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:43:40 PM PST 23
Peak memory 231496 kb
Host smart-353c761a-c1f1-4d39-aafa-a333654f50d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379753172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1379753172
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1638683967
Short name T264
Test name
Test status
Simulation time 4239984583 ps
CPU time 36.28 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:43:49 PM PST 23
Peak memory 198944 kb
Host smart-13144e17-c74e-4e6a-aa48-a833acff2fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638683967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1638683967
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.425047729
Short name T689
Test name
Test status
Simulation time 176689783 ps
CPU time 9.18 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:43:19 PM PST 23
Peak memory 198784 kb
Host smart-480a8fd6-c328-45d2-8db9-8370e826f6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425047729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.425047729
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3040004155
Short name T213
Test name
Test status
Simulation time 12095999439 ps
CPU time 139.94 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:45:29 PM PST 23
Peak memory 198872 kb
Host smart-fce11ecd-5bad-4f8e-8a37-8ef7ac4c23e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040004155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3040004155
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.978883646
Short name T369
Test name
Test status
Simulation time 1389140200 ps
CPU time 16.69 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:24 PM PST 23
Peak memory 198704 kb
Host smart-c10e9bcc-827c-4c50-bb4d-4ae7604bb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978883646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.978883646
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1944867619
Short name T256
Test name
Test status
Simulation time 61726979 ps
CPU time 0.91 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 196788 kb
Host smart-172071f8-df2c-482f-a29c-335352f0926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944867619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1944867619
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1413032937
Short name T735
Test name
Test status
Simulation time 80130989197 ps
CPU time 1289.71 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 01:04:42 PM PST 23
Peak memory 207096 kb
Host smart-fa13c347-82f2-419d-9a07-db68c0aeec73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413032937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1413032937
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2657421600
Short name T742
Test name
Test status
Simulation time 177810475905 ps
CPU time 1653.72 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 01:10:44 PM PST 23
Peak memory 245628 kb
Host smart-64b92301-8552-41eb-99a1-1558fa380b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657421600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.2657421600
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2714297496
Short name T231
Test name
Test status
Simulation time 60235209 ps
CPU time 1.1 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:43:12 PM PST 23
Peak memory 197040 kb
Host smart-d954ad51-663d-40dd-a00f-f996b78fc845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714297496 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2714297496
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2406887158
Short name T377
Test name
Test status
Simulation time 93022200412 ps
CPU time 344.96 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:48:57 PM PST 23
Peak memory 198800 kb
Host smart-02a8fb5f-ddf3-4a88-baff-ffe4714d7eb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406887158 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.2406887158
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1462806777
Short name T502
Test name
Test status
Simulation time 21737509840 ps
CPU time 33.1 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:43:41 PM PST 23
Peak memory 198928 kb
Host smart-ae67cfd4-0ce8-4e33-9a26-ed7e448959ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462806777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1462806777
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3723442546
Short name T542
Test name
Test status
Simulation time 79520003222 ps
CPU time 1288.28 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 01:09:59 PM PST 23
Peak memory 239612 kb
Host smart-7e38371f-6562-457b-ab98-43ee8a226d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723442546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.3723442546
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2293883814
Short name T484
Test name
Test status
Simulation time 75967007460 ps
CPU time 897.5 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 01:03:38 PM PST 23
Peak memory 215112 kb
Host smart-e81918de-3a31-4c81-8552-b13f9b1f6098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293883814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.2293883814
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.621954392
Short name T724
Test name
Test status
Simulation time 58061685075 ps
CPU time 2680.68 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 01:34:48 PM PST 23
Peak memory 247772 kb
Host smart-f239297f-862d-4504-846f-d9ff69a46de9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621954392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.621954392
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2064342766
Short name T41
Test name
Test status
Simulation time 27337595781 ps
CPU time 419.82 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 215360 kb
Host smart-a60e43f3-5b0d-457d-9073-f440cb4b7580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064342766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.2064342766
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3961987964
Short name T193
Test name
Test status
Simulation time 87745582454 ps
CPU time 2778.5 seconds
Started Dec 20 12:47:30 PM PST 23
Finished Dec 20 01:35:05 PM PST 23
Peak memory 256112 kb
Host smart-02410eb6-131f-44b2-abc3-e1c973897d0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961987964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.3961987964
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.3203744447
Short name T835
Test name
Test status
Simulation time 95565626630 ps
CPU time 3542.8 seconds
Started Dec 20 12:47:35 PM PST 23
Finished Dec 20 01:47:58 PM PST 23
Peak memory 263556 kb
Host smart-4d525827-d122-412e-a980-def04e74b516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203744447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.3203744447
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1111919040
Short name T652
Test name
Test status
Simulation time 123683747178 ps
CPU time 1665.55 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 01:15:29 PM PST 23
Peak memory 214564 kb
Host smart-e7516228-7a03-41cd-be78-11c4fff6f36d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111919040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.1111919040
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1579337550
Short name T568
Test name
Test status
Simulation time 228443773780 ps
CPU time 1937.11 seconds
Started Dec 20 12:47:54 PM PST 23
Finished Dec 20 01:21:25 PM PST 23
Peak memory 263772 kb
Host smart-19d380ae-c9cd-4caa-a894-a051cec93684
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579337550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.1579337550
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.2421123981
Short name T584
Test name
Test status
Simulation time 220039249924 ps
CPU time 2455.71 seconds
Started Dec 20 12:48:58 PM PST 23
Finished Dec 20 01:30:56 PM PST 23
Peak memory 231368 kb
Host smart-5281e21a-63b8-4f44-881b-dca442675e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421123981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.2421123981
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3340002670
Short name T520
Test name
Test status
Simulation time 13385493 ps
CPU time 0.57 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 193220 kb
Host smart-e6546c91-3ef4-4e52-ac04-529ab4edfc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340002670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3340002670
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.397141844
Short name T436
Test name
Test status
Simulation time 533260672 ps
CPU time 18.95 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 220280 kb
Host smart-08822221-006a-4794-8d27-5a464e3378af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397141844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.397141844
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1395762864
Short name T525
Test name
Test status
Simulation time 4635272258 ps
CPU time 41.13 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 198828 kb
Host smart-a9d229da-7a31-4745-abac-4d904efcc4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395762864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1395762864
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3556426895
Short name T487
Test name
Test status
Simulation time 3405781563 ps
CPU time 81.91 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:44:32 PM PST 23
Peak memory 198852 kb
Host smart-690e204e-130a-4fb1-a6fa-6cd6274c6b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556426895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3556426895
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.367018376
Short name T206
Test name
Test status
Simulation time 1799063086 ps
CPU time 86.69 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:44:39 PM PST 23
Peak memory 198764 kb
Host smart-1e5a4aa7-194e-4e0b-8dbb-dfdb88113f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367018376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.367018376
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2298442260
Short name T524
Test name
Test status
Simulation time 2845626717 ps
CPU time 34.26 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:43:45 PM PST 23
Peak memory 198920 kb
Host smart-83436eeb-e4a1-41ca-a9bb-da773c887aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298442260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2298442260
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.169153016
Short name T526
Test name
Test status
Simulation time 332595283 ps
CPU time 3.75 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:14 PM PST 23
Peak memory 198772 kb
Host smart-610e0af4-ce69-4416-be09-018c1d0348b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169153016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.169153016
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2093827453
Short name T718
Test name
Test status
Simulation time 36384187126 ps
CPU time 496.93 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:51:28 PM PST 23
Peak memory 215028 kb
Host smart-8ab1ad35-691c-4482-ab95-4f9ace64166a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093827453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.2093827453
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1574382604
Short name T229
Test name
Test status
Simulation time 56501802 ps
CPU time 1.12 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:43:14 PM PST 23
Peak memory 197292 kb
Host smart-fe8eba82-d2ba-4048-8425-6ae02bd0d2fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574382604 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1574382604
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1086300430
Short name T657
Test name
Test status
Simulation time 26202129084 ps
CPU time 396.68 seconds
Started Dec 20 12:42:17 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 198888 kb
Host smart-0e009a2e-223a-44d8-b3b1-4efba50a645f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086300430 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.1086300430
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3315809859
Short name T590
Test name
Test status
Simulation time 16418894880 ps
CPU time 48.5 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:59 PM PST 23
Peak memory 198936 kb
Host smart-781e56c8-b547-4231-8393-f0c785c05abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315809859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3315809859
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2732687907
Short name T752
Test name
Test status
Simulation time 1073605998955 ps
CPU time 1272.42 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 01:09:02 PM PST 23
Peak memory 248116 kb
Host smart-7dc49092-5a70-459a-ab5c-ed161cb0f158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732687907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.2732687907
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1062114372
Short name T787
Test name
Test status
Simulation time 345527712721 ps
CPU time 1518.35 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 01:11:48 PM PST 23
Peak memory 245996 kb
Host smart-88ce2ece-2445-4a5f-8cbd-1d085c5c3f4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062114372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.1062114372
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.955167765
Short name T815
Test name
Test status
Simulation time 81665734399 ps
CPU time 303.24 seconds
Started Dec 20 12:46:17 PM PST 23
Finished Dec 20 12:51:22 PM PST 23
Peak memory 226612 kb
Host smart-a505128d-85bf-4d0f-8981-252a97ccd5c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955167765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.955167765
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.2920703768
Short name T269
Test name
Test status
Simulation time 72254938852 ps
CPU time 1336.62 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:09:22 PM PST 23
Peak memory 244140 kb
Host smart-201bb3ff-0c90-40b4-b46a-2f80cee04186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920703768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.2920703768
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1651418666
Short name T603
Test name
Test status
Simulation time 51880004665 ps
CPU time 1746.03 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 01:15:33 PM PST 23
Peak memory 231736 kb
Host smart-ad541254-5649-411b-983f-101f3cbf5f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651418666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.1651418666
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.3223563427
Short name T263
Test name
Test status
Simulation time 52854110369 ps
CPU time 1837.32 seconds
Started Dec 20 12:46:18 PM PST 23
Finished Dec 20 01:17:02 PM PST 23
Peak memory 239752 kb
Host smart-92dc5ed5-4f11-4bee-a250-646aa9a34f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223563427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.3223563427
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.2111380976
Short name T460
Test name
Test status
Simulation time 94972453822 ps
CPU time 857.81 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 01:00:44 PM PST 23
Peak memory 247460 kb
Host smart-b6fce97e-d6aa-4078-bc34-e7c7dd932fbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111380976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.2111380976
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.421788082
Short name T565
Test name
Test status
Simulation time 61181843632 ps
CPU time 958.74 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 01:02:55 PM PST 23
Peak memory 248140 kb
Host smart-01704103-c2da-48be-b010-d86f98403d53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421788082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.421788082
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.3929457589
Short name T744
Test name
Test status
Simulation time 123019804067 ps
CPU time 1821.38 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 01:16:55 PM PST 23
Peak memory 256404 kb
Host smart-fbba5838-8a0f-4215-8726-c73f7308c26c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929457589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.3929457589
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.621660051
Short name T585
Test name
Test status
Simulation time 38032067 ps
CPU time 0.55 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 193156 kb
Host smart-e1ec52c7-8c71-471b-b733-e4d9f56f1c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621660051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.621660051
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3960717303
Short name T32
Test name
Test status
Simulation time 1084853594 ps
CPU time 15.03 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 206964 kb
Host smart-6a0a659a-7cca-4545-9d34-9e6ff15a3587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3960717303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3960717303
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1815197230
Short name T670
Test name
Test status
Simulation time 908563389 ps
CPU time 15.91 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 198800 kb
Host smart-54f820ee-d82c-491e-b008-2b488a3a0710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815197230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1815197230
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2334323966
Short name T306
Test name
Test status
Simulation time 1180586688 ps
CPU time 59.3 seconds
Started Dec 20 12:42:23 PM PST 23
Finished Dec 20 12:44:15 PM PST 23
Peak memory 198776 kb
Host smart-774aa060-3e3c-4e21-a2c4-293b8b4b96bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334323966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2334323966
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3077126807
Short name T643
Test name
Test status
Simulation time 3127663639 ps
CPU time 69.49 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:44:22 PM PST 23
Peak memory 198908 kb
Host smart-b9953630-4e2a-4678-a659-4a7ce7ccff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077126807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3077126807
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4232069425
Short name T464
Test name
Test status
Simulation time 13523027878 ps
CPU time 40.14 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 198584 kb
Host smart-05193a6f-1d75-49ba-adcd-504bcfeb22d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232069425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4232069425
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.835390875
Short name T540
Test name
Test status
Simulation time 529785138 ps
CPU time 1.66 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:14 PM PST 23
Peak memory 198388 kb
Host smart-7f10aab2-2492-47fa-9dbb-0d563ccc565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835390875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.835390875
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1317688275
Short name T434
Test name
Test status
Simulation time 24440766199 ps
CPU time 1058.64 seconds
Started Dec 20 12:42:17 PM PST 23
Finished Dec 20 01:00:51 PM PST 23
Peak memory 214284 kb
Host smart-9836e6f9-6721-4741-ac0a-222e8c751d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317688275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1317688275
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.573124864
Short name T745
Test name
Test status
Simulation time 80144629646 ps
CPU time 721.27 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:55:15 PM PST 23
Peak memory 248132 kb
Host smart-85ffd022-615a-4afa-9b67-f650336004a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573124864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.573124864
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1984356743
Short name T691
Test name
Test status
Simulation time 57573340 ps
CPU time 1.01 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:43:12 PM PST 23
Peak memory 195916 kb
Host smart-4b592f24-af9e-4fc5-8bc7-d51861dbcdc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984356743 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1984356743
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1030649705
Short name T409
Test name
Test status
Simulation time 153054533857 ps
CPU time 381.98 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:49:35 PM PST 23
Peak memory 198884 kb
Host smart-d78ced78-2ed3-4d5d-a004-1377da8f26ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030649705 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.1030649705
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.475756994
Short name T811
Test name
Test status
Simulation time 8270177789 ps
CPU time 49.27 seconds
Started Dec 20 12:42:19 PM PST 23
Finished Dec 20 12:44:03 PM PST 23
Peak memory 198616 kb
Host smart-78cf39f6-28a2-46c0-a6e5-ca9ec02f0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475756994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.475756994
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.2388876135
Short name T804
Test name
Test status
Simulation time 37812583231 ps
CPU time 259.21 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:51:28 PM PST 23
Peak memory 215384 kb
Host smart-044143c1-f9aa-4ed5-9a6f-bd769e91cc51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388876135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.2388876135
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.3861680228
Short name T572
Test name
Test status
Simulation time 374307714143 ps
CPU time 3853.75 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 01:50:39 PM PST 23
Peak memory 262412 kb
Host smart-bf886b0e-dd17-45a7-a370-d2fd5bcee362
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861680228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.3861680228
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3368240388
Short name T544
Test name
Test status
Simulation time 151526956530 ps
CPU time 1023.95 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 01:03:37 PM PST 23
Peak memory 215360 kb
Host smart-4483b029-4417-43d5-a2a3-a0bddff46635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368240388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3368240388
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.3925916267
Short name T248
Test name
Test status
Simulation time 239706413670 ps
CPU time 1493.6 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 01:12:02 PM PST 23
Peak memory 257572 kb
Host smart-738e46e8-036e-482e-846b-a465647c60e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925916267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.3925916267
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.2165823528
Short name T359
Test name
Test status
Simulation time 858114252456 ps
CPU time 1691.61 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 01:14:45 PM PST 23
Peak memory 223500 kb
Host smart-891dafbe-4a5a-4b48-811d-1d39a3add4b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165823528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.2165823528
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.394141598
Short name T543
Test name
Test status
Simulation time 676285839465 ps
CPU time 921.15 seconds
Started Dec 20 12:46:21 PM PST 23
Finished Dec 20 01:01:54 PM PST 23
Peak memory 255804 kb
Host smart-2b5c17ea-097c-41bd-9a54-fb166579fbd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394141598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.394141598
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.1242508194
Short name T794
Test name
Test status
Simulation time 123040425040 ps
CPU time 1334.02 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 01:08:47 PM PST 23
Peak memory 240544 kb
Host smart-d130de01-695d-46ec-bbee-fcea9e90b0cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242508194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.1242508194
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.3294289623
Short name T214
Test name
Test status
Simulation time 23621042580 ps
CPU time 431.06 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 207152 kb
Host smart-bf789c01-2cfa-4ffe-9ef4-1fc2a719fe6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294289623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.3294289623
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1812802028
Short name T350
Test name
Test status
Simulation time 36486182 ps
CPU time 0.55 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 193116 kb
Host smart-f935b9d2-46f5-4a52-bdbd-db1c2a82a77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812802028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1812802028
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1380296444
Short name T645
Test name
Test status
Simulation time 2782119535 ps
CPU time 50.15 seconds
Started Dec 20 12:42:16 PM PST 23
Finished Dec 20 12:44:03 PM PST 23
Peak memory 229984 kb
Host smart-777e2dc7-1757-4a2b-a554-8cc55e91d66e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380296444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1380296444
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2801299370
Short name T254
Test name
Test status
Simulation time 533375173 ps
CPU time 22.16 seconds
Started Dec 20 12:42:16 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 198748 kb
Host smart-464339b8-0124-41be-94e5-97654e171372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801299370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2801299370
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1911190949
Short name T841
Test name
Test status
Simulation time 1325342247 ps
CPU time 63.07 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:44:16 PM PST 23
Peak memory 198776 kb
Host smart-9c2ea45e-e602-4c88-b8bc-16213b9e129e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911190949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1911190949
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2284450136
Short name T267
Test name
Test status
Simulation time 2242968098 ps
CPU time 101.08 seconds
Started Dec 20 12:42:07 PM PST 23
Finished Dec 20 12:44:48 PM PST 23
Peak memory 198704 kb
Host smart-26e550f7-9e05-4527-86e2-e3518c84c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284450136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2284450136
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2101108100
Short name T237
Test name
Test status
Simulation time 8072403691 ps
CPU time 23.34 seconds
Started Dec 20 12:42:17 PM PST 23
Finished Dec 20 12:43:36 PM PST 23
Peak memory 198900 kb
Host smart-305846d9-21ef-433b-b34d-e1a22cc2d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101108100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2101108100
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3033184718
Short name T739
Test name
Test status
Simulation time 164348320 ps
CPU time 2.53 seconds
Started Dec 20 12:42:17 PM PST 23
Finished Dec 20 12:43:15 PM PST 23
Peak memory 198512 kb
Host smart-a0ba37e1-f48f-404d-800e-362dd8cada67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033184718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3033184718
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.707753163
Short name T304
Test name
Test status
Simulation time 19913145570 ps
CPU time 169.39 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:45:59 PM PST 23
Peak memory 218380 kb
Host smart-d46771b1-b14f-4b85-9633-1d6f29da7761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707753163 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.707753163
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2257463187
Short name T633
Test name
Test status
Simulation time 419197621287 ps
CPU time 1978.22 seconds
Started Dec 20 12:42:07 PM PST 23
Finished Dec 20 01:16:05 PM PST 23
Peak memory 256284 kb
Host smart-ce44e7c7-8d33-4e47-be11-fb4dd5dd125d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257463187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2257463187
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2656002316
Short name T792
Test name
Test status
Simulation time 164022982 ps
CPU time 1.09 seconds
Started Dec 20 12:42:15 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 196952 kb
Host smart-7aafb1c6-d4a1-478f-a514-a28dfc904844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656002316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2656002316
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1957194959
Short name T842
Test name
Test status
Simulation time 74928314500 ps
CPU time 426.96 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 198640 kb
Host smart-6f80db47-c47b-4e5b-b28c-babca13e2784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957194959 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.1957194959
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1600082551
Short name T10
Test name
Test status
Simulation time 2843936996 ps
CPU time 37.7 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:43:48 PM PST 23
Peak memory 198848 kb
Host smart-c6327d28-d3ea-4925-ba87-80721fbf7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600082551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1600082551
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1610187546
Short name T408
Test name
Test status
Simulation time 858775716964 ps
CPU time 2942.99 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 01:35:32 PM PST 23
Peak memory 243484 kb
Host smart-eb30df2e-ad94-4b36-994d-e70b436f617e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610187546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1610187546
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.366265226
Short name T36
Test name
Test status
Simulation time 45126647685 ps
CPU time 999.49 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 01:03:13 PM PST 23
Peak memory 249140 kb
Host smart-721adc62-cf93-475b-a45f-631450eeee16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366265226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.366265226
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.137362159
Short name T120
Test name
Test status
Simulation time 106323351602 ps
CPU time 3848.1 seconds
Started Dec 20 12:46:21 PM PST 23
Finished Dec 20 01:50:41 PM PST 23
Peak memory 258256 kb
Host smart-c6e4f457-4b52-4fbd-8037-f8bcc3dd776d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137362159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.137362159
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.1351025492
Short name T677
Test name
Test status
Simulation time 1010160140309 ps
CPU time 7571.02 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 02:52:45 PM PST 23
Peak memory 295108 kb
Host smart-5ddac0b2-3d90-4e8a-b810-c2ec1371f199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351025492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.1351025492
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.199609492
Short name T501
Test name
Test status
Simulation time 72027654776 ps
CPU time 572.83 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 241528 kb
Host smart-244f5d1c-bb9f-4219-bdae-c9fa1d2faf26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199609492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.199609492
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.600840233
Short name T223
Test name
Test status
Simulation time 282771926419 ps
CPU time 1565.91 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 01:12:39 PM PST 23
Peak memory 224568 kb
Host smart-c0455bff-5de3-42e7-b12d-60e11f314c9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600840233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.600840233
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.4209291264
Short name T111
Test name
Test status
Simulation time 57845517608 ps
CPU time 431.6 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 234732 kb
Host smart-9378a5d6-c00f-4990-b2ae-8a44606bfeb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209291264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.4209291264
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.1768521743
Short name T789
Test name
Test status
Simulation time 255493918930 ps
CPU time 875.16 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 01:01:08 PM PST 23
Peak memory 244988 kb
Host smart-957190a4-3793-4682-b0ef-c20c73424573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768521743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.1768521743
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.3944655528
Short name T242
Test name
Test status
Simulation time 93163603007 ps
CPU time 548.42 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 209616 kb
Host smart-ae8e430b-210d-4005-b1a9-91581726bf63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944655528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.3944655528
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.3618946122
Short name T183
Test name
Test status
Simulation time 99490765098 ps
CPU time 441.92 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 247672 kb
Host smart-879be623-1f64-407d-83ed-021148452166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618946122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.3618946122
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.340906031
Short name T332
Test name
Test status
Simulation time 1657301439 ps
CPU time 46.75 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:43:58 PM PST 23
Peak memory 215132 kb
Host smart-5086c270-a042-4e21-b624-2015b599baa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340906031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.340906031
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.375054813
Short name T816
Test name
Test status
Simulation time 1116102273 ps
CPU time 19.6 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 198760 kb
Host smart-f72725db-3f16-48f1-ae93-9bfc3c5a1df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375054813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.375054813
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2667354973
Short name T366
Test name
Test status
Simulation time 1702180174 ps
CPU time 85.38 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:44:33 PM PST 23
Peak memory 198816 kb
Host smart-2a743fed-ccaf-4c5b-b061-6eab44feee0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667354973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2667354973
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.812453901
Short name T185
Test name
Test status
Simulation time 7510888625 ps
CPU time 25.24 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 198868 kb
Host smart-a1b768ff-6423-4b4f-9f8c-e5ee904346c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812453901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.812453901
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1431379311
Short name T198
Test name
Test status
Simulation time 902257648 ps
CPU time 30.19 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:38 PM PST 23
Peak memory 198648 kb
Host smart-f986b0a1-7a47-4019-85ea-515d7e08b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431379311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1431379311
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4080947130
Short name T476
Test name
Test status
Simulation time 790357900 ps
CPU time 3.08 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:43:15 PM PST 23
Peak memory 198060 kb
Host smart-c5862732-209f-4738-b61f-47755aac5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080947130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4080947130
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1512517687
Short name T607
Test name
Test status
Simulation time 27760612944 ps
CPU time 304.18 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:52:47 PM PST 23
Peak memory 198892 kb
Host smart-5d5d94fc-5435-4d44-b899-ee27b7ea9cc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512517687 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1512517687
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2273430061
Short name T619
Test name
Test status
Simulation time 135370688157 ps
CPU time 598.6 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:57:42 PM PST 23
Peak memory 228348 kb
Host smart-3e191dea-832f-4df7-ade4-c68ba8598d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273430061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2273430061
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3575005073
Short name T697
Test name
Test status
Simulation time 184455801 ps
CPU time 0.93 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 197292 kb
Host smart-44b80ce5-2a91-4b6f-994d-a1fe1fb525b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575005073 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3575005073
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2402076134
Short name T2
Test name
Test status
Simulation time 26289771007 ps
CPU time 406.37 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:49:54 PM PST 23
Peak memory 198860 kb
Host smart-916d5ea4-f94c-4074-91a3-5e72b8bb4da5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402076134 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.2402076134
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.666009640
Short name T290
Test name
Test status
Simulation time 9599370783 ps
CPU time 54.5 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:44:02 PM PST 23
Peak memory 198852 kb
Host smart-229db172-23dc-4777-b55d-6d868c3ab1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666009640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.666009640
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.2982521233
Short name T338
Test name
Test status
Simulation time 89679053587 ps
CPU time 1070.24 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 01:04:33 PM PST 23
Peak memory 235388 kb
Host smart-efa16022-6d4b-40c0-b429-2bb7800e39fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982521233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.2982521233
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.44837227
Short name T367
Test name
Test status
Simulation time 118551528973 ps
CPU time 1641.4 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 01:14:01 PM PST 23
Peak memory 248096 kb
Host smart-7f69d95b-2ec1-49bb-8397-935bac979353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44837227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.44837227
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.2125457614
Short name T371
Test name
Test status
Simulation time 66923012130 ps
CPU time 946.7 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:02:52 PM PST 23
Peak memory 244408 kb
Host smart-8bfa5d77-4cf3-4b16-84a2-81db1f206411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125457614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.2125457614
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.1404376896
Short name T268
Test name
Test status
Simulation time 184815798757 ps
CPU time 1165.36 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 01:06:22 PM PST 23
Peak memory 223248 kb
Host smart-bd3c3b86-ca13-4c12-9ef0-c9c0cec06fe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404376896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.1404376896
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3588194986
Short name T113
Test name
Test status
Simulation time 23559791632 ps
CPU time 420.5 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 215280 kb
Host smart-6309345e-f22b-46bc-bde7-0d76ddb2d47c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588194986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.3588194986
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.3359678603
Short name T555
Test name
Test status
Simulation time 75351526054 ps
CPU time 326.57 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 214704 kb
Host smart-d79d3727-9d10-49d7-9193-ef906559d9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359678603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.3359678603
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.331561345
Short name T466
Test name
Test status
Simulation time 65208596388 ps
CPU time 222.25 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 12:50:22 PM PST 23
Peak memory 214340 kb
Host smart-34f5abaa-037f-474d-8b31-c0a0a4612374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331561345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.331561345
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.1583515749
Short name T344
Test name
Test status
Simulation time 247338439448 ps
CPU time 2334.75 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 01:25:51 PM PST 23
Peak memory 252856 kb
Host smart-2dd41c3e-9b78-46ac-bcd1-e3d06f488ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583515749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.1583515749
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1427071038
Short name T522
Test name
Test status
Simulation time 66330127 ps
CPU time 0.56 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:48:01 PM PST 23
Peak memory 194168 kb
Host smart-70fb0afb-16a2-4d70-9461-70681804d8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427071038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1427071038
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3107685299
Short name T227
Test name
Test status
Simulation time 1440586494 ps
CPU time 39.28 seconds
Started Dec 20 12:46:59 PM PST 23
Finished Dec 20 12:48:19 PM PST 23
Peak memory 219212 kb
Host smart-3f88ef36-2ff7-4599-84cc-f2dd7129f0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107685299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3107685299
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2637930872
Short name T432
Test name
Test status
Simulation time 4384258250 ps
CPU time 39.34 seconds
Started Dec 20 12:46:49 PM PST 23
Finished Dec 20 12:48:05 PM PST 23
Peak memory 198888 kb
Host smart-5d9dd1ea-5a83-4ed6-8572-eabbbb6ecb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637930872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2637930872
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.66435428
Short name T203
Test name
Test status
Simulation time 8491356990 ps
CPU time 106.88 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:49:00 PM PST 23
Peak memory 198848 kb
Host smart-14d2df87-8f24-4532-bb51-df1523752617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66435428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.66435428
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.872813139
Short name T552
Test name
Test status
Simulation time 2931026427 ps
CPU time 11.34 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:47:54 PM PST 23
Peak memory 198928 kb
Host smart-d3d17f29-0f42-4788-9128-5b4e346af7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872813139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.872813139
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3322626637
Short name T575
Test name
Test status
Simulation time 17100989167 ps
CPU time 58.94 seconds
Started Dec 20 12:47:00 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 198912 kb
Host smart-64e44897-36f2-45b2-9644-0d5d4ab2dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322626637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3322626637
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4089843153
Short name T241
Test name
Test status
Simulation time 151913016 ps
CPU time 3.52 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:48:08 PM PST 23
Peak memory 198704 kb
Host smart-a15e4002-b106-4817-b278-474a0534a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089843153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4089843153
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1450525914
Short name T799
Test name
Test status
Simulation time 111176374675 ps
CPU time 1281.04 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 01:08:49 PM PST 23
Peak memory 214700 kb
Host smart-9c349373-ae68-45dd-b6f0-6b13a49f5ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450525914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1450525914
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2661683253
Short name T348
Test name
Test status
Simulation time 47369055692 ps
CPU time 2120.81 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 01:23:09 PM PST 23
Peak memory 212636 kb
Host smart-9f1e682c-9b9a-4017-83de-d35670d25f2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661683253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2661683253
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.741166261
Short name T662
Test name
Test status
Simulation time 1057163074 ps
CPU time 1.15 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 12:47:28 PM PST 23
Peak memory 196788 kb
Host smart-8bd269ae-14f0-46e0-821f-7ec664c67d73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741166261 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.741166261
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3820288156
Short name T580
Test name
Test status
Simulation time 12424852852 ps
CPU time 73.56 seconds
Started Dec 20 12:46:43 PM PST 23
Finished Dec 20 12:48:32 PM PST 23
Peak memory 198856 kb
Host smart-e9368c3b-a773-46da-8ce3-ce5a268b4fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820288156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3820288156
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.1044715467
Short name T709
Test name
Test status
Simulation time 125308481037 ps
CPU time 1428.52 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 01:10:27 PM PST 23
Peak memory 223616 kb
Host smart-1ddd2e06-4144-4467-9e03-812131f4fa5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044715467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.1044715467
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1811615805
Short name T34
Test name
Test status
Simulation time 148063967198 ps
CPU time 4512.63 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 02:02:13 PM PST 23
Peak memory 261280 kb
Host smart-d9eaa70e-ce1c-42ed-b0cd-d72c527f1b89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811615805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.1811615805
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.4230172020
Short name T246
Test name
Test status
Simulation time 32469094422 ps
CPU time 125.84 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:48:49 PM PST 23
Peak memory 207272 kb
Host smart-d212f8d4-2362-4424-bb13-8a079466973f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230172020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.4230172020
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.424394425
Short name T272
Test name
Test status
Simulation time 264925264204 ps
CPU time 1383.46 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 01:09:53 PM PST 23
Peak memory 231228 kb
Host smart-02c6e84a-0943-4fed-932a-63e907e17afd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424394425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.424394425
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1058793097
Short name T750
Test name
Test status
Simulation time 313485691932 ps
CPU time 2975.15 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 01:36:56 PM PST 23
Peak memory 244996 kb
Host smart-b77db82c-75c2-42fb-a971-c24b97933409
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058793097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1058793097
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2032232959
Short name T796
Test name
Test status
Simulation time 376588629824 ps
CPU time 578.99 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 230216 kb
Host smart-f5360501-b616-4bb8-a72e-6bb678dbbd33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032232959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.2032232959
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.356803839
Short name T758
Test name
Test status
Simulation time 283631264306 ps
CPU time 2796.57 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 01:33:50 PM PST 23
Peak memory 261376 kb
Host smart-5314b7cf-2c3f-45fd-8d4a-e006fdb8c0f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356803839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.356803839
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.4161086228
Short name T341
Test name
Test status
Simulation time 241908098846 ps
CPU time 897.72 seconds
Started Dec 20 12:46:42 PM PST 23
Finished Dec 20 01:02:14 PM PST 23
Peak memory 214660 kb
Host smart-a4e11519-d6df-4697-b261-6ccab9370524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161086228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.4161086228
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.237026392
Short name T545
Test name
Test status
Simulation time 242993781703 ps
CPU time 814.03 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 01:00:47 PM PST 23
Peak memory 231644 kb
Host smart-40a02aca-3a8c-4997-9b0f-97384f3d21a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237026392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.237026392
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.1309465558
Short name T797
Test name
Test status
Simulation time 333572852359 ps
CPU time 931.89 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:02:38 PM PST 23
Peak memory 248024 kb
Host smart-142addd3-b703-484c-b790-5ab7089a7709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309465558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.1309465558
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4089533765
Short name T700
Test name
Test status
Simulation time 37281200 ps
CPU time 0.55 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 12:47:35 PM PST 23
Peak memory 193176 kb
Host smart-75d79306-ee7c-4aa6-8e40-e66541a2f5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089533765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4089533765
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2449617523
Short name T238
Test name
Test status
Simulation time 199621547 ps
CPU time 6.54 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 207020 kb
Host smart-6e0e6c12-ccc7-483f-ac0d-e7cb50a2c986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449617523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2449617523
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1198933043
Short name T351
Test name
Test status
Simulation time 435875724 ps
CPU time 19.16 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:48:07 PM PST 23
Peak memory 198776 kb
Host smart-b1fc7913-5738-4215-8a87-f1a29c3dee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198933043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1198933043
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_error.2799882735
Short name T277
Test name
Test status
Simulation time 685505369 ps
CPU time 31.36 seconds
Started Dec 20 12:46:43 PM PST 23
Finished Dec 20 12:47:50 PM PST 23
Peak memory 198772 kb
Host smart-0587958d-12ac-42b4-a2bf-fe12f6d71a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799882735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2799882735
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3486707291
Short name T626
Test name
Test status
Simulation time 51323450552 ps
CPU time 45.24 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:48:54 PM PST 23
Peak memory 198912 kb
Host smart-91feeabb-7680-4005-9317-bb826be992c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486707291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3486707291
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4020192554
Short name T226
Test name
Test status
Simulation time 1417524792 ps
CPU time 2.94 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 12:47:48 PM PST 23
Peak memory 198744 kb
Host smart-4eab2042-1c30-490c-9367-8d33c12f124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020192554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4020192554
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2744034572
Short name T305
Test name
Test status
Simulation time 826027493426 ps
CPU time 1449.39 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 01:12:52 PM PST 23
Peak memory 207172 kb
Host smart-e6350478-22c4-4c3b-8903-17d24664d3e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744034572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2744034572
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.67856056
Short name T315
Test name
Test status
Simulation time 22992963220 ps
CPU time 404.31 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 214412 kb
Host smart-df1d309f-f61d-41f2-936b-c23306977992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67856056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.67856056
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1821504744
Short name T604
Test name
Test status
Simulation time 67513906 ps
CPU time 1.01 seconds
Started Dec 20 12:46:45 PM PST 23
Finished Dec 20 12:47:22 PM PST 23
Peak memory 197148 kb
Host smart-656dcc9a-7c98-4591-af4f-21595e1294ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821504744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1821504744
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.4283186500
Short name T9
Test name
Test status
Simulation time 15076399862 ps
CPU time 319.81 seconds
Started Dec 20 12:46:48 PM PST 23
Finished Dec 20 12:52:49 PM PST 23
Peak memory 198844 kb
Host smart-1ca82eec-653d-4121-9084-df91a80132d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283186500 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.4283186500
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2409157905
Short name T747
Test name
Test status
Simulation time 10655669241 ps
CPU time 64.46 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:49:24 PM PST 23
Peak memory 198880 kb
Host smart-f46c9d6c-2cb8-4de8-a7e5-6c3d26da3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409157905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2409157905
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.957155199
Short name T658
Test name
Test status
Simulation time 98989290155 ps
CPU time 436.26 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:54:25 PM PST 23
Peak memory 240912 kb
Host smart-7758f56c-0d29-4501-b824-77eb064a5dc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957155199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.957155199
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1416836373
Short name T442
Test name
Test status
Simulation time 76542576111 ps
CPU time 3274.39 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 01:41:30 PM PST 23
Peak memory 264580 kb
Host smart-3a9d5bed-6a84-468d-9ce3-92e53f66ef83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416836373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.1416836373
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.284448066
Short name T444
Test name
Test status
Simulation time 150352453802 ps
CPU time 4100.48 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:55:36 PM PST 23
Peak memory 280556 kb
Host smart-bb72e462-c7cd-4998-beea-a52aaee2a88f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284448066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.284448066
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.919099379
Short name T283
Test name
Test status
Simulation time 143962736196 ps
CPU time 921.52 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:02:26 PM PST 23
Peak memory 248036 kb
Host smart-d4fab1be-fbca-4d6b-9247-aa6e0dcd9a93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919099379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.919099379
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.4250152296
Short name T270
Test name
Test status
Simulation time 74604109360 ps
CPU time 1827.94 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 01:17:38 PM PST 23
Peak memory 241076 kb
Host smart-19c9b75e-524d-45b3-b056-254781c956d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250152296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.4250152296
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.2831637831
Short name T35
Test name
Test status
Simulation time 19715658613 ps
CPU time 943.13 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:02:54 PM PST 23
Peak memory 214328 kb
Host smart-f4f286b2-7f87-4bfc-8b33-8292fddfacfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831637831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.2831637831
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.441193320
Short name T125
Test name
Test status
Simulation time 232773936457 ps
CPU time 1459.47 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 01:11:18 PM PST 23
Peak memory 215396 kb
Host smart-88624168-8b34-4a6e-94ea-a12ac4a4dbbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441193320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.441193320
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.613811006
Short name T463
Test name
Test status
Simulation time 4361463500 ps
CPU time 182.72 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 215396 kb
Host smart-67b7ac27-4c31-4f26-8169-5c7362bafcd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613811006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.613811006
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.786228185
Short name T637
Test name
Test status
Simulation time 15957713179 ps
CPU time 399.82 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 231732 kb
Host smart-195c84e9-4428-467a-b65a-9ba7fcdf8680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786228185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.786228185
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.590840512
Short name T614
Test name
Test status
Simulation time 67344450846 ps
CPU time 2662.44 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 01:31:15 PM PST 23
Peak memory 263456 kb
Host smart-0fad9a28-8334-4aaf-8fb6-7f73f1219e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590840512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.590840512
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4204128632
Short name T505
Test name
Test status
Simulation time 16692052 ps
CPU time 0.56 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 193100 kb
Host smart-2ae55aae-3c1f-4544-b49f-d5bec5e09aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204128632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4204128632
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3043110724
Short name T701
Test name
Test status
Simulation time 643340646 ps
CPU time 23.75 seconds
Started Dec 20 12:46:47 PM PST 23
Finished Dec 20 12:47:47 PM PST 23
Peak memory 231492 kb
Host smart-f63d26a0-827a-4196-832c-86972aa1454b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043110724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3043110724
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1877449156
Short name T671
Test name
Test status
Simulation time 2069085436 ps
CPU time 7.16 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 12:47:39 PM PST 23
Peak memory 198732 kb
Host smart-824209a7-ef4f-4381-b462-e7d932e0b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877449156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1877449156
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3734731717
Short name T613
Test name
Test status
Simulation time 3420157335 ps
CPU time 45.81 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:43 PM PST 23
Peak memory 198912 kb
Host smart-9878019d-6102-4d93-a244-4f8f6dcc9e04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734731717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3734731717
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1740423114
Short name T661
Test name
Test status
Simulation time 1976740058 ps
CPU time 48.92 seconds
Started Dec 20 12:46:54 PM PST 23
Finished Dec 20 12:48:22 PM PST 23
Peak memory 198772 kb
Host smart-94bb0ace-e881-4e56-9b7d-c80bbcce61ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740423114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1740423114
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.65423981
Short name T278
Test name
Test status
Simulation time 432089248 ps
CPU time 7.58 seconds
Started Dec 20 12:47:00 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 198768 kb
Host smart-b75f6675-e2c0-40e2-bcb2-aeab2dfe5e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65423981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.65423981
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3831737121
Short name T672
Test name
Test status
Simulation time 654276888 ps
CPU time 3.85 seconds
Started Dec 20 12:46:55 PM PST 23
Finished Dec 20 12:47:40 PM PST 23
Peak memory 198824 kb
Host smart-f70d0020-0feb-40bc-a266-9ec1ca376a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831737121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3831737121
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1756855872
Short name T355
Test name
Test status
Simulation time 59118558762 ps
CPU time 693.38 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 12:59:01 PM PST 23
Peak memory 214596 kb
Host smart-6937ee05-864c-47be-8f0d-dc067f746b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756855872 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1756855872
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.2737127776
Short name T419
Test name
Test status
Simulation time 205202351120 ps
CPU time 1305.14 seconds
Started Dec 20 12:46:58 PM PST 23
Finished Dec 20 01:09:23 PM PST 23
Peak memory 244016 kb
Host smart-f983d1c9-fa55-4af8-930e-817359db9f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737127776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.2737127776
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3297128676
Short name T730
Test name
Test status
Simulation time 69442061 ps
CPU time 1.02 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 12:47:37 PM PST 23
Peak memory 196284 kb
Host smart-fd48f58b-7615-4578-9661-db98a9c9c586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297128676 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3297128676
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3840286831
Short name T760
Test name
Test status
Simulation time 44026485852 ps
CPU time 486.45 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 198912 kb
Host smart-3725ca25-868a-43eb-bd31-34c2706ecadd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840286831 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.3840286831
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3942474024
Short name T469
Test name
Test status
Simulation time 12338741839 ps
CPU time 72.69 seconds
Started Dec 20 12:47:00 PM PST 23
Finished Dec 20 12:48:54 PM PST 23
Peak memory 198868 kb
Host smart-fbb6c5a0-873a-4dfa-9fce-842dfb498610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942474024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3942474024
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3524683835
Short name T669
Test name
Test status
Simulation time 488839899463 ps
CPU time 4832.85 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 02:07:26 PM PST 23
Peak memory 275696 kb
Host smart-3b7aa377-753a-4307-9e63-cbdd1375cf4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524683835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3524683835
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.983919286
Short name T414
Test name
Test status
Simulation time 25283640927 ps
CPU time 953.97 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 01:02:44 PM PST 23
Peak memory 248056 kb
Host smart-e4884703-90e3-441e-ace2-557e840f10a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983919286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.983919286
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.2852645983
Short name T644
Test name
Test status
Simulation time 82809176877 ps
CPU time 2317.98 seconds
Started Dec 20 12:46:49 PM PST 23
Finished Dec 20 01:26:05 PM PST 23
Peak memory 261392 kb
Host smart-e86d8fb7-5f12-42e7-94f4-462c8be10f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852645983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.2852645983
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.490439978
Short name T347
Test name
Test status
Simulation time 26681484056 ps
CPU time 339.17 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:52:33 PM PST 23
Peak memory 214912 kb
Host smart-dd42a00b-55bf-45c1-a1a3-0b60c5ca6de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490439978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.490439978
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3514460933
Short name T596
Test name
Test status
Simulation time 69314805335 ps
CPU time 1188.48 seconds
Started Dec 20 12:46:18 PM PST 23
Finished Dec 20 01:06:09 PM PST 23
Peak memory 247476 kb
Host smart-b0200849-0649-4660-8796-6a06fb9987b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514460933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.3514460933
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.3966600143
Short name T546
Test name
Test status
Simulation time 291597700638 ps
CPU time 804.15 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 12:59:57 PM PST 23
Peak memory 231768 kb
Host smart-2c5bbc95-fb06-49ee-ba57-4db94ddef234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966600143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.3966600143
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.1012023300
Short name T737
Test name
Test status
Simulation time 45780603058 ps
CPU time 2110.35 seconds
Started Dec 20 12:45:39 PM PST 23
Finished Dec 20 01:20:50 PM PST 23
Peak memory 247104 kb
Host smart-d8460adc-e137-428d-a91d-b3a5636387c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012023300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.1012023300
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2758146487
Short name T399
Test name
Test status
Simulation time 14052262780 ps
CPU time 199.14 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:50:08 PM PST 23
Peak memory 199004 kb
Host smart-b639edd5-d906-42f7-9a90-b5c5b346168c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758146487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2758146487
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.2860753963
Short name T6
Test name
Test status
Simulation time 403723728876 ps
CPU time 1869.31 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:18:21 PM PST 23
Peak memory 257212 kb
Host smart-8c6b6674-12ce-41c4-b0f5-68b9052a0173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860753963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.2860753963
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3810411837
Short name T806
Test name
Test status
Simulation time 40714025 ps
CPU time 0.56 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:48:14 PM PST 23
Peak memory 193112 kb
Host smart-8651138c-f1f9-43da-8afb-69516ed19211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810411837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3810411837
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4180359581
Short name T470
Test name
Test status
Simulation time 3270082557 ps
CPU time 27.02 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:48:30 PM PST 23
Peak memory 219448 kb
Host smart-cd112ef0-4b9b-4963-8d36-219606afcc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180359581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4180359581
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2598865050
Short name T499
Test name
Test status
Simulation time 2185799755 ps
CPU time 29.82 seconds
Started Dec 20 12:47:47 PM PST 23
Finished Dec 20 12:49:43 PM PST 23
Peak memory 198796 kb
Host smart-330d4133-e9c4-4d2b-a375-26b0e5774a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598865050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2598865050
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3262780697
Short name T569
Test name
Test status
Simulation time 7387845925 ps
CPU time 70.21 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:49:22 PM PST 23
Peak memory 198824 kb
Host smart-11b4b67d-e515-4d42-9c41-626dbf58ce19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262780697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3262780697
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3605735604
Short name T683
Test name
Test status
Simulation time 4211136039 ps
CPU time 64.98 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:49:18 PM PST 23
Peak memory 198920 kb
Host smart-97bd571b-1e15-4080-b9d0-b91a62475d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605735604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3605735604
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.78276577
Short name T688
Test name
Test status
Simulation time 15163852352 ps
CPU time 44.87 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:48:33 PM PST 23
Peak memory 198904 kb
Host smart-519b4468-bbe5-4904-a97d-47c19ce7a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78276577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.78276577
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1907856315
Short name T197
Test name
Test status
Simulation time 112059023 ps
CPU time 0.97 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:47:57 PM PST 23
Peak memory 197264 kb
Host smart-ea61a377-7234-4dcd-8420-4befe5a1d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907856315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1907856315
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2899931921
Short name T207
Test name
Test status
Simulation time 99276094774 ps
CPU time 1082.43 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 01:06:11 PM PST 23
Peak memory 206900 kb
Host smart-afb65ef0-7511-49de-b3ce-9e1904e40047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899931921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2899931921
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.1004758541
Short name T218
Test name
Test status
Simulation time 104551799710 ps
CPU time 2418.36 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 01:28:56 PM PST 23
Peak memory 264520 kb
Host smart-0909b465-a9b7-4b94-af54-3a8e745ec4a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004758541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.1004758541
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.149009465
Short name T628
Test name
Test status
Simulation time 225562935 ps
CPU time 0.89 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:47:48 PM PST 23
Peak memory 196116 kb
Host smart-ab67e632-a0aa-41b1-aedd-94a95642306d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149009465 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.149009465
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1781776349
Short name T763
Test name
Test status
Simulation time 7557740830 ps
CPU time 349.48 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 12:54:30 PM PST 23
Peak memory 198884 kb
Host smart-9ca87a26-9875-447d-84f2-95c6033b88e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781776349 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1781776349
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2096992392
Short name T612
Test name
Test status
Simulation time 31305493994 ps
CPU time 53.18 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:49:36 PM PST 23
Peak memory 198840 kb
Host smart-b96b4956-79b8-47cb-983e-1f3d38f983eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096992392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2096992392
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.1954349151
Short name T383
Test name
Test status
Simulation time 1032707583320 ps
CPU time 3164.23 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 01:39:11 PM PST 23
Peak memory 251696 kb
Host smart-c4b7af54-2d11-471c-b174-f2ca50219036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954349151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.1954349151
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3396828232
Short name T812
Test name
Test status
Simulation time 285227375464 ps
CPU time 823.03 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 01:00:16 PM PST 23
Peak memory 215312 kb
Host smart-a02de8d4-ca0f-4658-85ac-ce67b04b7b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396828232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.3396828232
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.192481544
Short name T11
Test name
Test status
Simulation time 218179630917 ps
CPU time 725.72 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 12:58:37 PM PST 23
Peak memory 247920 kb
Host smart-6fb3a178-04f4-4f7a-86a6-9eb3534a1905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192481544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.192481544
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.570410811
Short name T541
Test name
Test status
Simulation time 14375478398 ps
CPU time 285.61 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:51:19 PM PST 23
Peak memory 246308 kb
Host smart-beaaf676-55ea-47f3-8c6b-e564a8466f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570410811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.570410811
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.1553440525
Short name T769
Test name
Test status
Simulation time 35706419025 ps
CPU time 336.1 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 214404 kb
Host smart-4ab46347-6a0b-4176-8e51-33cc709f9935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553440525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.1553440525
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.4188484013
Short name T837
Test name
Test status
Simulation time 140269801640 ps
CPU time 1189.21 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 01:06:23 PM PST 23
Peak memory 214480 kb
Host smart-1057478b-b551-403b-8a8c-4ec89a2f25d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188484013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.4188484013
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.3054017847
Short name T595
Test name
Test status
Simulation time 68349086916 ps
CPU time 3134.27 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 01:39:23 PM PST 23
Peak memory 231528 kb
Host smart-1e652c6f-fbf1-4d1b-b188-818c530d43fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054017847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.3054017847
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.3764827759
Short name T790
Test name
Test status
Simulation time 94519398004 ps
CPU time 339.53 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:52:13 PM PST 23
Peak memory 223464 kb
Host smart-1624793b-bb59-4e8f-972e-5c99aa54b0a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764827759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.3764827759
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.1648633732
Short name T116
Test name
Test status
Simulation time 27326898668 ps
CPU time 1293.54 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 01:08:08 PM PST 23
Peak memory 223500 kb
Host smart-21171ae3-75b2-4e40-a5f8-d16983b7be3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648633732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.1648633732
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4094573730
Short name T455
Test name
Test status
Simulation time 14934942 ps
CPU time 0.55 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:48:03 PM PST 23
Peak memory 193260 kb
Host smart-05c78f87-d49b-4885-ab6d-16f4a7a264fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094573730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4094573730
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1021397509
Short name T519
Test name
Test status
Simulation time 1188079416 ps
CPU time 40.21 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:47:52 PM PST 23
Peak memory 216180 kb
Host smart-18293d54-6e9d-41d1-977e-5f616ce9a2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021397509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1021397509
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2310248376
Short name T549
Test name
Test status
Simulation time 362790919 ps
CPU time 6.49 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:25 PM PST 23
Peak memory 198856 kb
Host smart-6491614b-d531-447d-bf74-64daeab11fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310248376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2310248376
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2545237339
Short name T395
Test name
Test status
Simulation time 17321056304 ps
CPU time 60.27 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:48:42 PM PST 23
Peak memory 198828 kb
Host smart-594cb0b7-9738-4b0c-ad3f-b06890a56586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545237339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2545237339
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2089332785
Short name T665
Test name
Test status
Simulation time 19293403493 ps
CPU time 155.13 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:50:40 PM PST 23
Peak memory 198928 kb
Host smart-b2ef9693-56e2-4b10-a3e3-ccd2c8e2d5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089332785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2089332785
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3795673173
Short name T795
Test name
Test status
Simulation time 2292929424 ps
CPU time 27.84 seconds
Started Dec 20 12:46:58 PM PST 23
Finished Dec 20 12:48:06 PM PST 23
Peak memory 198752 kb
Host smart-9761beef-7ac6-4dda-a08c-789c60c483d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795673173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3795673173
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2036984928
Short name T673
Test name
Test status
Simulation time 247326333 ps
CPU time 2.66 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:20 PM PST 23
Peak memory 198452 kb
Host smart-c4acf1fd-071a-4705-8b15-6d25cb0ad2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036984928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2036984928
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2935776973
Short name T593
Test name
Test status
Simulation time 4774759657 ps
CPU time 183.31 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:51:23 PM PST 23
Peak memory 220536 kb
Host smart-9ba0c27d-bf44-4a2d-9f2d-875a0c3e4587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935776973 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2935776973
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.3737322227
Short name T838
Test name
Test status
Simulation time 165770140000 ps
CPU time 583.77 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 231460 kb
Host smart-bff784f6-be92-4f71-9bab-cdeeaf5e98ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737322227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.3737322227
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1632197756
Short name T777
Test name
Test status
Simulation time 51046018 ps
CPU time 0.91 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 12:48:31 PM PST 23
Peak memory 196024 kb
Host smart-8d31c450-5677-4b4c-930d-351ba10825b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632197756 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1632197756
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.61537354
Short name T424
Test name
Test status
Simulation time 99090354706 ps
CPU time 331.63 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 12:54:10 PM PST 23
Peak memory 198952 kb
Host smart-0c3abdbe-8d3c-4a80-bda6-d4c786cf7031
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61537354 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.hmac_test_sha_vectors.61537354
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1288979287
Short name T664
Test name
Test status
Simulation time 2678694401 ps
CPU time 61.88 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:49:02 PM PST 23
Peak memory 198916 kb
Host smart-ca3146f4-3d50-4df9-bcb3-6cccf612230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288979287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1288979287
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3677035928
Short name T781
Test name
Test status
Simulation time 518168561983 ps
CPU time 1048.06 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 01:04:01 PM PST 23
Peak memory 214584 kb
Host smart-88fe66c3-e5f3-4463-8a50-31345ebf45d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677035928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3677035928
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.1011071995
Short name T616
Test name
Test status
Simulation time 136493683423 ps
CPU time 1617.1 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 01:13:34 PM PST 23
Peak memory 256368 kb
Host smart-dbbdacdf-b771-4054-888a-f9d71dd99513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011071995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.1011071995
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.3188253519
Short name T834
Test name
Test status
Simulation time 113945679492 ps
CPU time 1521.52 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 01:12:11 PM PST 23
Peak memory 250028 kb
Host smart-60237291-5d5b-4a8d-9d35-846b3f34435d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188253519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.3188253519
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3850153474
Short name T656
Test name
Test status
Simulation time 100889933289 ps
CPU time 435.63 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 223520 kb
Host smart-9c781d41-8fca-447b-8282-b00afe56e97d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850153474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3850153474
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.3456016962
Short name T416
Test name
Test status
Simulation time 47218386089 ps
CPU time 789.42 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:59:52 PM PST 23
Peak memory 215380 kb
Host smart-2b78d96c-cf83-4b13-a396-75474521c7f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456016962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.3456016962
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.3222548430
Short name T461
Test name
Test status
Simulation time 237208194554 ps
CPU time 472.59 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 207196 kb
Host smart-17b48f49-e6ad-4ae9-b519-2ed9346e9788
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222548430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.3222548430
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3487822365
Short name T199
Test name
Test status
Simulation time 323360261703 ps
CPU time 762.7 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:59:54 PM PST 23
Peak memory 247080 kb
Host smart-4b773785-1463-44f8-8b52-cc4924a974da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487822365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.3487822365
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.2497307902
Short name T266
Test name
Test status
Simulation time 71130282035 ps
CPU time 898.02 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 01:01:41 PM PST 23
Peak memory 223808 kb
Host smart-57b78275-ef9f-4c90-a168-dc80e649814f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497307902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.2497307902
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3342119158
Short name T599
Test name
Test status
Simulation time 2183875544131 ps
CPU time 2335.16 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 01:25:38 PM PST 23
Peak memory 259396 kb
Host smart-799e70d8-082c-4115-ae30-cb7018036b2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342119158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3342119158
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4114083543
Short name T618
Test name
Test status
Simulation time 98925035 ps
CPU time 0.55 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:43:04 PM PST 23
Peak memory 192904 kb
Host smart-5e64fd69-08e5-485d-a97a-01a7b9a640c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114083543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4114083543
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.412126459
Short name T562
Test name
Test status
Simulation time 4649153500 ps
CPU time 32.27 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:34 PM PST 23
Peak memory 215228 kb
Host smart-0909a4a4-e6a9-4605-b52f-501b61c38a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412126459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.412126459
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2496704374
Short name T720
Test name
Test status
Simulation time 11194885567 ps
CPU time 39.08 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:43:39 PM PST 23
Peak memory 198876 kb
Host smart-8245f3cb-d182-4b6d-959d-36309ccf0a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496704374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2496704374
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.537613000
Short name T8
Test name
Test status
Simulation time 9057561179 ps
CPU time 111.06 seconds
Started Dec 20 12:42:05 PM PST 23
Finished Dec 20 12:44:56 PM PST 23
Peak memory 198576 kb
Host smart-b03949a3-20ce-4033-992b-03c53b87bd04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537613000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.537613000
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3802937013
Short name T343
Test name
Test status
Simulation time 12397863733 ps
CPU time 147.15 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:45:23 PM PST 23
Peak memory 198828 kb
Host smart-677d9ca9-d8e4-4a11-8214-5288231d40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802937013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3802937013
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.678702096
Short name T115
Test name
Test status
Simulation time 12576823338 ps
CPU time 99.05 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:44:44 PM PST 23
Peak memory 198568 kb
Host smart-c1500bb4-6b0a-41ee-9102-1705dd0ce1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678702096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.678702096
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1897809512
Short name T310
Test name
Test status
Simulation time 779479284 ps
CPU time 2.74 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:04 PM PST 23
Peak memory 198544 kb
Host smart-c1c20781-18b2-4b0d-92d0-d950b85eef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897809512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1897809512
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.578361097
Short name T707
Test name
Test status
Simulation time 59791285141 ps
CPU time 961.47 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:59:04 PM PST 23
Peak memory 215228 kb
Host smart-f02a5035-e98d-4234-990d-6a900e1c9b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578361097 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.578361097
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.962112628
Short name T415
Test name
Test status
Simulation time 52341962496 ps
CPU time 507.44 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:51:25 PM PST 23
Peak memory 214500 kb
Host smart-01c94b1c-e9b3-4503-ab8f-dabb1ea29b4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962112628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.962112628
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3727300913
Short name T286
Test name
Test status
Simulation time 38253176 ps
CPU time 0.91 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 195864 kb
Host smart-b5b2ac49-d0ff-4b9d-a47f-ed5761c947f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727300913 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3727300913
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.932725455
Short name T403
Test name
Test status
Simulation time 67520217073 ps
CPU time 404.14 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 198608 kb
Host smart-b2e4a2d9-b728-4ac4-bf73-d1ec49457d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932725455 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_sha_vectors.932725455
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2836860223
Short name T679
Test name
Test status
Simulation time 2355280804 ps
CPU time 16.38 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:17 PM PST 23
Peak memory 198836 kb
Host smart-1e960917-9f72-4a1b-a4c1-567d7bfd9e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836860223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2836860223
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3560882852
Short name T236
Test name
Test status
Simulation time 48442130 ps
CPU time 0.54 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 12:48:31 PM PST 23
Peak memory 192872 kb
Host smart-a188d8e7-aa69-452e-88de-6af908990382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560882852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3560882852
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.839485691
Short name T388
Test name
Test status
Simulation time 1026777419 ps
CPU time 7.33 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:47:59 PM PST 23
Peak memory 231064 kb
Host smart-c0ea935a-284a-42bd-b5ff-e3dfa45d98e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839485691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.839485691
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3361530437
Short name T117
Test name
Test status
Simulation time 6453667157 ps
CPU time 38.12 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:49:09 PM PST 23
Peak memory 198920 kb
Host smart-16b6f403-93f4-4ca0-9559-15531c6190da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361530437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3361530437
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.994037324
Short name T291
Test name
Test status
Simulation time 15945770931 ps
CPU time 67.01 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:49:24 PM PST 23
Peak memory 198844 kb
Host smart-f95c4fd7-539e-4e3d-877d-75450472a586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994037324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.994037324
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.181874127
Short name T509
Test name
Test status
Simulation time 16536488761 ps
CPU time 122.27 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:50:22 PM PST 23
Peak memory 198712 kb
Host smart-06fcbeb3-b730-4361-a486-a819266273f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181874127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.181874127
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4133404224
Short name T623
Test name
Test status
Simulation time 425453418 ps
CPU time 19.15 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:48:13 PM PST 23
Peak memory 198600 kb
Host smart-4e3ec0cc-8ea3-47ce-a3b7-1ab06ffe21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133404224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4133404224
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2628698658
Short name T249
Test name
Test status
Simulation time 5148373042 ps
CPU time 213.63 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:51:58 PM PST 23
Peak memory 198680 kb
Host smart-3e70f056-9d6e-4adb-9292-9e6e3d9bafd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628698658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2628698658
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1608849020
Short name T493
Test name
Test status
Simulation time 128113155771 ps
CPU time 2577.47 seconds
Started Dec 20 12:46:45 PM PST 23
Finished Dec 20 01:30:18 PM PST 23
Peak memory 248100 kb
Host smart-90d17b8a-e0a9-4a0f-9c7a-f5a4b7de8126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608849020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1608849020
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2430491244
Short name T336
Test name
Test status
Simulation time 117369700 ps
CPU time 1.02 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:48:37 PM PST 23
Peak memory 197536 kb
Host smart-501ef75f-3950-40a1-a84e-285b8f345cfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430491244 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2430491244
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2417375502
Short name T446
Test name
Test status
Simulation time 184932418335 ps
CPU time 429.05 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 198600 kb
Host smart-47815699-0eee-42c6-987d-600feabe85e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417375502 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.2417375502
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3375611131
Short name T498
Test name
Test status
Simulation time 820368773 ps
CPU time 32.82 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:49:15 PM PST 23
Peak memory 198580 kb
Host smart-7d799ce9-2489-43b1-80d0-60d3353aa782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375611131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3375611131
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2272844262
Short name T530
Test name
Test status
Simulation time 18400238 ps
CPU time 0.54 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 12:47:31 PM PST 23
Peak memory 193160 kb
Host smart-8e486986-d204-4851-adc4-eb8e0b0e4ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272844262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2272844262
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.261462084
Short name T421
Test name
Test status
Simulation time 2682037503 ps
CPU time 19.33 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:48:08 PM PST 23
Peak memory 207084 kb
Host smart-e02d0d01-4d49-4d2b-93ac-b277388a26bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261462084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.261462084
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3162365855
Short name T354
Test name
Test status
Simulation time 686640261 ps
CPU time 31.21 seconds
Started Dec 20 12:46:57 PM PST 23
Finished Dec 20 12:48:10 PM PST 23
Peak memory 198688 kb
Host smart-07119578-a8af-41d9-8fed-0469b07fa16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162365855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3162365855
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1628917529
Short name T480
Test name
Test status
Simulation time 4963689289 ps
CPU time 59.7 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 12:48:15 PM PST 23
Peak memory 198840 kb
Host smart-7e6791bf-864b-4250-b60e-d07676b2bca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628917529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1628917529
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2394259829
Short name T609
Test name
Test status
Simulation time 21914554514 ps
CPU time 239.44 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:52:06 PM PST 23
Peak memory 198688 kb
Host smart-9ac5946e-fb8a-49ca-9466-213e5b0d5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394259829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2394259829
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1550457187
Short name T186
Test name
Test status
Simulation time 8326503261 ps
CPU time 58.22 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:49:00 PM PST 23
Peak memory 198884 kb
Host smart-c16d3ac9-3038-4e5d-b2e5-551aa1a3c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550457187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1550457187
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1827968357
Short name T182
Test name
Test status
Simulation time 254223505 ps
CPU time 3.2 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:33 PM PST 23
Peak memory 198444 kb
Host smart-5d67d9f7-53f5-46d4-9b50-39b18ab59a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827968357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1827968357
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2919733650
Short name T698
Test name
Test status
Simulation time 70426894651 ps
CPU time 1742.44 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 01:16:34 PM PST 23
Peak memory 229932 kb
Host smart-684548d7-728e-4975-aadf-3857aa45ed9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919733650 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2919733650
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.2169988519
Short name T251
Test name
Test status
Simulation time 79431529875 ps
CPU time 1019.85 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 01:04:51 PM PST 23
Peak memory 223452 kb
Host smart-23db51b7-f0a6-476c-9c5f-fbb4c681e061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169988519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.2169988519
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2507193865
Short name T329
Test name
Test status
Simulation time 55046313 ps
CPU time 1.11 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:21 PM PST 23
Peak memory 197052 kb
Host smart-2b73cbd3-feb5-46c7-a385-51ea42e2b1c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507193865 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2507193865
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1090282688
Short name T58
Test name
Test status
Simulation time 35672621963 ps
CPU time 477.53 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 198940 kb
Host smart-0270661e-1b43-4ffd-8d61-5b8ba39436ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090282688 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.1090282688
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2465793850
Short name T703
Test name
Test status
Simulation time 936427278 ps
CPU time 9.08 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:47:57 PM PST 23
Peak memory 198756 kb
Host smart-412cf591-094b-46bb-8070-3d8c4fbbc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465793850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2465793850
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2493843238
Short name T582
Test name
Test status
Simulation time 35149473 ps
CPU time 0.59 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:48:27 PM PST 23
Peak memory 193172 kb
Host smart-8e6b23b5-4ee6-4068-a4c2-e16dcf30f8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493843238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2493843238
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.946019242
Short name T391
Test name
Test status
Simulation time 1946162120 ps
CPU time 16.56 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:48:43 PM PST 23
Peak memory 215224 kb
Host smart-944341f1-68c5-472b-9e24-4cc430c859de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946019242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.946019242
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2207757314
Short name T313
Test name
Test status
Simulation time 2118946411 ps
CPU time 25.01 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:48:08 PM PST 23
Peak memory 198676 kb
Host smart-17fe1d4e-6dd2-42ed-b939-8ea508e5fb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207757314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2207757314
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2427810059
Short name T400
Test name
Test status
Simulation time 1466754544 ps
CPU time 72.58 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:49:01 PM PST 23
Peak memory 198712 kb
Host smart-bf9e0286-a834-4d23-8b65-1bd39afdd410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427810059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2427810059
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.763733923
Short name T121
Test name
Test status
Simulation time 8002741814 ps
CPU time 119.92 seconds
Started Dec 20 12:46:58 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 198900 kb
Host smart-9fde12ca-416f-4ed3-8a88-7e097de14b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763733923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.763733923
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.753012584
Short name T179
Test name
Test status
Simulation time 13344411370 ps
CPU time 50.77 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:49:06 PM PST 23
Peak memory 198900 kb
Host smart-8f189282-a74d-467c-8074-86f14d8bfd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753012584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.753012584
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3378380200
Short name T597
Test name
Test status
Simulation time 627677127 ps
CPU time 3.38 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 12:48:51 PM PST 23
Peak memory 198704 kb
Host smart-1df4d999-b6d3-4054-8deb-1f6974e1216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378380200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3378380200
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.236976632
Short name T687
Test name
Test status
Simulation time 21409195180 ps
CPU time 234.07 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 12:52:31 PM PST 23
Peak memory 233280 kb
Host smart-2fe08e6f-790a-4b93-b0cf-065720497af5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236976632 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.236976632
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.116596902
Short name T396
Test name
Test status
Simulation time 545083281007 ps
CPU time 2252.24 seconds
Started Dec 20 12:47:29 PM PST 23
Finished Dec 20 01:26:24 PM PST 23
Peak memory 240960 kb
Host smart-f53dc9d7-b5e4-4a0d-9b62-3a719b80cb03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116596902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.116596902
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2948900121
Short name T445
Test name
Test status
Simulation time 50852711 ps
CPU time 1.07 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:48:43 PM PST 23
Peak memory 196244 kb
Host smart-d7e54d87-34e8-476f-9643-59bf4b639584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948900121 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2948900121
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.859401836
Short name T485
Test name
Test status
Simulation time 37995233488 ps
CPU time 352.59 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 198852 kb
Host smart-6a358edd-85f0-4fc2-b939-239ed3e0e8ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859401836 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.hmac_test_sha_vectors.859401836
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.788280772
Short name T496
Test name
Test status
Simulation time 64890127 ps
CPU time 0.64 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:47:57 PM PST 23
Peak memory 194208 kb
Host smart-42823cd2-0fbd-40ce-94ae-5f77baadcf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788280772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.788280772
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1518534913
Short name T316
Test name
Test status
Simulation time 29192991 ps
CPU time 0.54 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 192964 kb
Host smart-12b9c2b2-88bf-44e8-a885-d760fdf82cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518534913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1518534913
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3419350608
Short name T831
Test name
Test status
Simulation time 1542887017 ps
CPU time 39.72 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:48:53 PM PST 23
Peak memory 215192 kb
Host smart-cf27145a-25f0-4883-bd1d-a142e8a71e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419350608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3419350608
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3382120853
Short name T319
Test name
Test status
Simulation time 6039014989 ps
CPU time 52.04 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:49:05 PM PST 23
Peak memory 198844 kb
Host smart-7befc6e5-de29-4f86-a6fa-c9f601572650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382120853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3382120853
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4016327881
Short name T324
Test name
Test status
Simulation time 1606702061 ps
CPU time 38.26 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:48:26 PM PST 23
Peak memory 198456 kb
Host smart-0efed357-81c0-4bb9-a283-71defe83a3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016327881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4016327881
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1770257609
Short name T389
Test name
Test status
Simulation time 4967087567 ps
CPU time 115.49 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 198952 kb
Host smart-0b1bf40d-cbd4-43c6-bae0-b6f47717bd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770257609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1770257609
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2468496654
Short name T353
Test name
Test status
Simulation time 4157927680 ps
CPU time 52.25 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:48 PM PST 23
Peak memory 198952 kb
Host smart-775a9182-83e7-42e6-9089-8921bb5e19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468496654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2468496654
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3150857076
Short name T736
Test name
Test status
Simulation time 27006408 ps
CPU time 0.88 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 12:48:48 PM PST 23
Peak memory 196628 kb
Host smart-0d84cd47-869e-4059-b2c5-0eaeaa22e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150857076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3150857076
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1568342170
Short name T515
Test name
Test status
Simulation time 9018567644 ps
CPU time 74.64 seconds
Started Dec 20 12:46:06 PM PST 23
Finished Dec 20 12:47:21 PM PST 23
Peak memory 198928 kb
Host smart-4c194202-6388-4e09-a87a-1609e3eb1a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568342170 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1568342170
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.3057274741
Short name T196
Test name
Test status
Simulation time 51188543562 ps
CPU time 744.46 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 01:00:43 PM PST 23
Peak memory 214328 kb
Host smart-b2fd6c67-9297-46dd-b3fa-aaa7f59c6bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057274741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.3057274741
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.645543480
Short name T394
Test name
Test status
Simulation time 55132072 ps
CPU time 0.96 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:18 PM PST 23
Peak memory 196808 kb
Host smart-f5841e58-c83f-4f83-9eaa-58fce106660c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645543480 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.645543480
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3880696020
Short name T230
Test name
Test status
Simulation time 62567536129 ps
CPU time 394.82 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:54:43 PM PST 23
Peak memory 198596 kb
Host smart-adaf7103-0126-4ed2-9482-f83f0b20cb8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880696020 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.3880696020
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.204998007
Short name T456
Test name
Test status
Simulation time 711004274 ps
CPU time 27.2 seconds
Started Dec 20 12:47:36 PM PST 23
Finished Dec 20 12:49:22 PM PST 23
Peak memory 198716 kb
Host smart-3d6f64e4-5663-402a-b762-dea965a509fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204998007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.204998007
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.446122053
Short name T325
Test name
Test status
Simulation time 25482084 ps
CPU time 0.57 seconds
Started Dec 20 12:46:55 PM PST 23
Finished Dec 20 12:47:36 PM PST 23
Peak memory 193168 kb
Host smart-7e622dc5-6b4f-4131-83bd-82e20a240586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446122053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.446122053
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4274278518
Short name T33
Test name
Test status
Simulation time 2581148065 ps
CPU time 38.85 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:49:17 PM PST 23
Peak memory 231052 kb
Host smart-7a28be4a-3a45-478a-a343-e0aa05c40ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274278518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4274278518
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3136088044
Short name T262
Test name
Test status
Simulation time 130364950 ps
CPU time 5.73 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:48:35 PM PST 23
Peak memory 198596 kb
Host smart-7e88ce91-a1cf-4841-9256-d5625f7744fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136088044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3136088044
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3962443268
Short name T422
Test name
Test status
Simulation time 3942577618 ps
CPU time 49.79 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:49:05 PM PST 23
Peak memory 198912 kb
Host smart-01f5b776-08f0-40ea-b42d-628ed45925d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962443268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3962443268
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4038662081
Short name T649
Test name
Test status
Simulation time 12676031988 ps
CPU time 63.45 seconds
Started Dec 20 12:48:53 PM PST 23
Finished Dec 20 12:50:58 PM PST 23
Peak memory 198548 kb
Host smart-66bc8a28-195c-464b-8622-f7fa88ccc550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038662081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4038662081
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3032128068
Short name T727
Test name
Test status
Simulation time 934105799 ps
CPU time 43.84 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:48:50 PM PST 23
Peak memory 198736 kb
Host smart-dc91c74a-ff2b-4fae-846d-7bfb6703678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032128068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3032128068
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3915210118
Short name T234
Test name
Test status
Simulation time 49368314 ps
CPU time 1.09 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:48:11 PM PST 23
Peak memory 197844 kb
Host smart-e41b77ae-4d05-44b2-95b4-dfd7ce5f6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915210118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3915210118
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4031787715
Short name T250
Test name
Test status
Simulation time 71476650787 ps
CPU time 534.79 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:56:38 PM PST 23
Peak memory 218916 kb
Host smart-87dc8249-39d3-4510-8409-2b372c9a4f79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031787715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4031787715
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.367660386
Short name T40
Test name
Test status
Simulation time 156149453315 ps
CPU time 2743.05 seconds
Started Dec 20 12:47:04 PM PST 23
Finished Dec 20 01:33:30 PM PST 23
Peak memory 255784 kb
Host smart-3fe5a7af-ae73-4796-8c04-d08172bea473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367660386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.367660386
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.453005086
Short name T323
Test name
Test status
Simulation time 35251023 ps
CPU time 1.12 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 12:47:32 PM PST 23
Peak memory 198268 kb
Host smart-ff7bea06-90d7-4fb8-8f4c-0c6303a2d49b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453005086 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.453005086
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1971696098
Short name T437
Test name
Test status
Simulation time 9144942063 ps
CPU time 38.34 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 12:48:23 PM PST 23
Peak memory 198852 kb
Host smart-3422f302-5d7e-4785-a19a-478be78e41b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971696098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1971696098
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2230285276
Short name T368
Test name
Test status
Simulation time 34275464 ps
CPU time 0.54 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:21 PM PST 23
Peak memory 193164 kb
Host smart-b548aa5a-f872-4eb8-9f60-f2d89aa420eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230285276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2230285276
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3426124111
Short name T636
Test name
Test status
Simulation time 699173872 ps
CPU time 21.81 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:20 PM PST 23
Peak memory 231800 kb
Host smart-520c1fc4-29a8-49e3-b7d9-2248221cad31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426124111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3426124111
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1777947892
Short name T721
Test name
Test status
Simulation time 1741459392 ps
CPU time 37.5 seconds
Started Dec 20 12:46:57 PM PST 23
Finished Dec 20 12:48:16 PM PST 23
Peak memory 198636 kb
Host smart-be01e6a3-9495-48ac-ac70-f7bab710da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777947892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1777947892
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.900328847
Short name T734
Test name
Test status
Simulation time 2735266341 ps
CPU time 135.86 seconds
Started Dec 20 12:47:04 PM PST 23
Finished Dec 20 12:50:20 PM PST 23
Peak memory 198716 kb
Host smart-2025f136-78bb-42cc-b61e-9510045f4426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900328847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.900328847
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3888275042
Short name T56
Test name
Test status
Simulation time 8097088774 ps
CPU time 75.35 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:49:16 PM PST 23
Peak memory 198860 kb
Host smart-912b8e8d-0016-4886-bc48-628faf522353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888275042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3888275042
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2436435517
Short name T402
Test name
Test status
Simulation time 2934282402 ps
CPU time 36.86 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:48:32 PM PST 23
Peak memory 198828 kb
Host smart-379636e1-82d0-4e19-9558-7e949a5202c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436435517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2436435517
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3355615793
Short name T257
Test name
Test status
Simulation time 268028009 ps
CPU time 2.93 seconds
Started Dec 20 12:46:46 PM PST 23
Finished Dec 20 12:47:25 PM PST 23
Peak memory 198620 kb
Host smart-204dcae5-0343-4791-ae0f-4f1e40e4d60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355615793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3355615793
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3915024682
Short name T695
Test name
Test status
Simulation time 120973625434 ps
CPU time 494.65 seconds
Started Dec 20 12:47:22 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 198772 kb
Host smart-92b11944-1774-48fe-b425-90128f9920a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915024682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3915024682
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2262782145
Short name T726
Test name
Test status
Simulation time 47324787001 ps
CPU time 1901.4 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 01:19:39 PM PST 23
Peak memory 255908 kb
Host smart-63869720-b8d1-4891-aec2-378d4cc978a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262782145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.2262782145
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1043246027
Short name T467
Test name
Test status
Simulation time 554133292 ps
CPU time 1.05 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:00 PM PST 23
Peak memory 196428 kb
Host smart-ffbf9bef-adb8-4eaa-8610-fe065a58a316
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043246027 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1043246027
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1836805955
Short name T678
Test name
Test status
Simulation time 35244310877 ps
CPU time 333.22 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 198728 kb
Host smart-3a772bb2-5aa2-4d57-b4de-2c0746059f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836805955 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.1836805955
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2993026149
Short name T716
Test name
Test status
Simulation time 5500706503 ps
CPU time 69.99 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:48:52 PM PST 23
Peak memory 198964 kb
Host smart-1f364a79-b426-4b89-9eb8-401f654d6d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993026149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2993026149
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.492861242
Short name T822
Test name
Test status
Simulation time 24882351 ps
CPU time 0.58 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 12:47:46 PM PST 23
Peak memory 193164 kb
Host smart-73492627-35c9-4b9f-b6b7-1b9521583859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492861242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.492861242
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.700357750
Short name T824
Test name
Test status
Simulation time 1449167610 ps
CPU time 22.12 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:48:15 PM PST 23
Peak memory 214940 kb
Host smart-f9467f71-2049-4426-b276-962b5de54eb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700357750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.700357750
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2352207353
Short name T775
Test name
Test status
Simulation time 5296579443 ps
CPU time 53.93 seconds
Started Dec 20 12:47:39 PM PST 23
Finished Dec 20 12:49:52 PM PST 23
Peak memory 198888 kb
Host smart-1b8e0c3b-27a4-46db-84f3-eaec28f7d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352207353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2352207353
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.502748050
Short name T820
Test name
Test status
Simulation time 1942332292 ps
CPU time 50.11 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:49:10 PM PST 23
Peak memory 198760 kb
Host smart-2491057d-97e1-4171-a92c-4f5797835fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502748050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.502748050
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.94415845
Short name T587
Test name
Test status
Simulation time 551604005 ps
CPU time 24.88 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:24 PM PST 23
Peak memory 198784 kb
Host smart-e95284cb-aec7-4370-80e9-8aed76e57f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94415845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.94415845
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2874415034
Short name T425
Test name
Test status
Simulation time 1537455827 ps
CPU time 73.07 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:49:26 PM PST 23
Peak memory 198576 kb
Host smart-f8bac4af-7d4a-42d2-a3ed-20873cef1b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874415034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2874415034
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4146988565
Short name T247
Test name
Test status
Simulation time 771948339 ps
CPU time 2.27 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:00 PM PST 23
Peak memory 198732 kb
Host smart-622cc97f-4af8-4659-a63b-be2d45b8d8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146988565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4146988565
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3425486074
Short name T819
Test name
Test status
Simulation time 149479497421 ps
CPU time 632.18 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 218204 kb
Host smart-04b71425-e55b-4a0f-853b-cddaaa75b315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425486074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3425486074
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.1186803379
Short name T279
Test name
Test status
Simulation time 38640435730 ps
CPU time 524.86 seconds
Started Dec 20 12:46:55 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 215396 kb
Host smart-ce22c027-7873-47e0-92a2-b7dc96f8ae6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186803379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.1186803379
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1525163914
Short name T548
Test name
Test status
Simulation time 84277575 ps
CPU time 0.83 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 12:47:44 PM PST 23
Peak memory 196648 kb
Host smart-f7dc237f-2ac2-4241-9f68-7affeff4937e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525163914 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1525163914
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.4156037089
Short name T810
Test name
Test status
Simulation time 7471542692 ps
CPU time 339 seconds
Started Dec 20 12:46:56 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 198832 kb
Host smart-a24b148a-a30e-4ea3-967a-8550af6b65f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156037089 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.4156037089
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2327399760
Short name T215
Test name
Test status
Simulation time 24391767712 ps
CPU time 75.51 seconds
Started Dec 20 12:47:31 PM PST 23
Finished Dec 20 12:50:06 PM PST 23
Peak memory 198856 kb
Host smart-bd18b218-673b-4dfe-8e5c-4b13fa5edf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327399760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2327399760
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2905793103
Short name T224
Test name
Test status
Simulation time 39167210 ps
CPU time 0.54 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:47:55 PM PST 23
Peak memory 193220 kb
Host smart-6b6599f7-560d-4760-8e8e-30e97961e037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905793103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2905793103
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3010381778
Short name T635
Test name
Test status
Simulation time 604815941 ps
CPU time 20.22 seconds
Started Dec 20 12:46:48 PM PST 23
Finished Dec 20 12:47:44 PM PST 23
Peak memory 215148 kb
Host smart-9cb9ca45-ae51-41a7-9bc4-f3f4a57cbc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010381778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3010381778
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.704587002
Short name T825
Test name
Test status
Simulation time 460604770 ps
CPU time 12.12 seconds
Started Dec 20 12:47:22 PM PST 23
Finished Dec 20 12:48:38 PM PST 23
Peak memory 198784 kb
Host smart-77091940-3d7c-4cf0-a902-8a60f54061ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704587002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.704587002
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2041886087
Short name T675
Test name
Test status
Simulation time 731574676 ps
CPU time 37.14 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 12:48:42 PM PST 23
Peak memory 198776 kb
Host smart-6ef91862-c94b-4e3c-863b-65fbf9a9aee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041886087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2041886087
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1850264952
Short name T650
Test name
Test status
Simulation time 7128874292 ps
CPU time 105.51 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 198904 kb
Host smart-e498afc8-92fa-4ea8-8e48-f9107c6cdf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850264952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1850264952
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3212250848
Short name T60
Test name
Test status
Simulation time 20174948491 ps
CPU time 112.96 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:49:48 PM PST 23
Peak memory 198908 kb
Host smart-a1e9dc7f-7a6c-4529-b7ad-4de7f7caecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212250848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3212250848
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.229785546
Short name T321
Test name
Test status
Simulation time 394703936 ps
CPU time 4.02 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:48:23 PM PST 23
Peak memory 198580 kb
Host smart-06fd796e-3bf7-4f4d-a288-6f05c6b84f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229785546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.229785546
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.837492096
Short name T124
Test name
Test status
Simulation time 24612393688 ps
CPU time 1185.82 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 01:08:03 PM PST 23
Peak memory 231396 kb
Host smart-e4e5f832-fe38-4d0c-874b-f8409099bd94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837492096 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.837492096
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1425489455
Short name T748
Test name
Test status
Simulation time 103244820 ps
CPU time 0.85 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:47:59 PM PST 23
Peak memory 195856 kb
Host smart-3f286a48-fa6b-45d1-b6df-b06bcf7b7431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425489455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1425489455
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2901121822
Short name T566
Test name
Test status
Simulation time 1811291524 ps
CPU time 73.82 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:49:25 PM PST 23
Peak memory 198692 kb
Host smart-b8c4b7b1-4885-4a71-9935-4bcc596ee556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901121822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2901121822
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.230702023
Short name T45
Test name
Test status
Simulation time 13800764 ps
CPU time 0.57 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:48:27 PM PST 23
Peak memory 193168 kb
Host smart-dc52bffa-21c8-4d30-8eaa-92113e7166a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230702023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.230702023
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2776475508
Short name T217
Test name
Test status
Simulation time 1621746839 ps
CPU time 11.9 seconds
Started Dec 20 12:47:53 PM PST 23
Finished Dec 20 12:49:20 PM PST 23
Peak memory 206736 kb
Host smart-d09258d4-ff93-4ae8-8fef-f46248898f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776475508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2776475508
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1968691096
Short name T38
Test name
Test status
Simulation time 718740491 ps
CPU time 3.41 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 198540 kb
Host smart-a3b7d640-c8b6-47cd-8f83-7bf2dca9aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968691096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1968691096
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.221008453
Short name T410
Test name
Test status
Simulation time 1992562983 ps
CPU time 24.53 seconds
Started Dec 20 12:46:44 PM PST 23
Finished Dec 20 12:47:43 PM PST 23
Peak memory 198780 kb
Host smart-6eb5898c-57b3-4b40-a70e-d520e67d1d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221008453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.221008453
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1639659888
Short name T210
Test name
Test status
Simulation time 38341441914 ps
CPU time 114.18 seconds
Started Dec 20 12:47:32 PM PST 23
Finished Dec 20 12:50:45 PM PST 23
Peak memory 198712 kb
Host smart-f9f70d32-9cb8-4486-a30f-6d5610124a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639659888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1639659888
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1122497017
Short name T845
Test name
Test status
Simulation time 8129348733 ps
CPU time 23.57 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:48:35 PM PST 23
Peak memory 198852 kb
Host smart-fd8dd438-d447-4ab7-a45d-dc7e181db8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122497017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1122497017
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2148139665
Short name T453
Test name
Test status
Simulation time 1491368517 ps
CPU time 4.23 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:20 PM PST 23
Peak memory 198544 kb
Host smart-b720b908-abdf-4ca5-9c6b-67d9d3a48a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148139665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2148139665
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.633362751
Short name T488
Test name
Test status
Simulation time 919477897615 ps
CPU time 1085.63 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 01:05:52 PM PST 23
Peak memory 198776 kb
Host smart-4fb58748-d149-48c6-9bd2-041ec56bace3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633362751 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.633362751
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.2215992862
Short name T384
Test name
Test status
Simulation time 39923733295 ps
CPU time 742.43 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 12:59:52 PM PST 23
Peak memory 245564 kb
Host smart-5ab47624-5295-44aa-b73c-88474471e5f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215992862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.2215992862
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3597478332
Short name T385
Test name
Test status
Simulation time 70473678 ps
CPU time 1.08 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:47:59 PM PST 23
Peak memory 197108 kb
Host smart-ccfa70f4-3ea0-4749-9dc1-69756b1e4c9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597478332 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3597478332
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1602085940
Short name T39
Test name
Test status
Simulation time 25498727099 ps
CPU time 371.65 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 198956 kb
Host smart-7c9badb5-2617-4e1f-a799-9dac9ad895b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602085940 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1602085940
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.137782180
Short name T280
Test name
Test status
Simulation time 18601251635 ps
CPU time 55.01 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:49:04 PM PST 23
Peak memory 198700 kb
Host smart-b74cacee-8a45-4078-a8a8-8006289bfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137782180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.137782180
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4121334339
Short name T363
Test name
Test status
Simulation time 46735913 ps
CPU time 0.55 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 194124 kb
Host smart-9be3f5a8-b79c-46fe-9bba-1caf18681b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121334339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4121334339
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1229540501
Short name T631
Test name
Test status
Simulation time 831711831 ps
CPU time 24.8 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:48:24 PM PST 23
Peak memory 215192 kb
Host smart-2a4b18f7-ce14-402b-95ce-18e1bc22420d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229540501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1229540501
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2678293108
Short name T429
Test name
Test status
Simulation time 28945677145 ps
CPU time 52.67 seconds
Started Dec 20 12:46:56 PM PST 23
Finished Dec 20 12:48:29 PM PST 23
Peak memory 198808 kb
Host smart-6b994461-07cd-460e-bdbf-a4d20f7d6145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678293108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2678293108
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3091327450
Short name T605
Test name
Test status
Simulation time 1990519433 ps
CPU time 49.82 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 12:48:20 PM PST 23
Peak memory 198764 kb
Host smart-4fc66018-daa2-47fe-9870-c60a4eebc525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091327450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3091327450
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3675070152
Short name T379
Test name
Test status
Simulation time 15563752371 ps
CPU time 118.27 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:50:24 PM PST 23
Peak memory 198904 kb
Host smart-5b8b5703-282d-4c63-a365-6ee0afc5d546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675070152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3675070152
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1602694914
Short name T798
Test name
Test status
Simulation time 1447330477 ps
CPU time 70.99 seconds
Started Dec 20 12:46:55 PM PST 23
Finished Dec 20 12:48:46 PM PST 23
Peak memory 198796 kb
Host smart-c2544da8-f1e3-4c8a-8e34-7b398fa6a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602694914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1602694914
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4230592849
Short name T782
Test name
Test status
Simulation time 220543879 ps
CPU time 1.44 seconds
Started Dec 20 12:46:55 PM PST 23
Finished Dec 20 12:47:38 PM PST 23
Peak memory 198428 kb
Host smart-69572639-e780-4f71-9a39-f7ce6a392728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230592849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4230592849
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.37961633
Short name T830
Test name
Test status
Simulation time 124965583545 ps
CPU time 145.65 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:50:18 PM PST 23
Peak memory 198996 kb
Host smart-2db8f17a-3d10-4eca-b29a-6bcf921f25d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961633 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.37961633
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.4270639969
Short name T133
Test name
Test status
Simulation time 62192024114 ps
CPU time 878.26 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 01:02:21 PM PST 23
Peak memory 242600 kb
Host smart-e3c4d2b4-3144-4901-b160-fc45a532fa97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270639969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.4270639969
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2718363649
Short name T180
Test name
Test status
Simulation time 110077076 ps
CPU time 1.05 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:48:04 PM PST 23
Peak memory 197188 kb
Host smart-6b334176-97ae-4cb3-8575-f8eda731b1fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718363649 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2718363649
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3443317580
Short name T759
Test name
Test status
Simulation time 19354990325 ps
CPU time 412.22 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:54:45 PM PST 23
Peak memory 198928 kb
Host smart-1f2e7e4a-2fae-4489-a758-e8ed65301568
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443317580 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3443317580
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3464372639
Short name T481
Test name
Test status
Simulation time 20870517794 ps
CPU time 38.82 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:56 PM PST 23
Peak memory 198844 kb
Host smart-3d23e7a1-7865-4afc-bbf3-c15221a809bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464372639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3464372639
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.151515074
Short name T59
Test name
Test status
Simulation time 18266845 ps
CPU time 0.58 seconds
Started Dec 20 12:42:02 PM PST 23
Finished Dec 20 12:43:03 PM PST 23
Peak memory 194184 kb
Host smart-d022aa2c-f784-49bb-93b5-d68a3e37e976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151515074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.151515074
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3237596829
Short name T558
Test name
Test status
Simulation time 904999193 ps
CPU time 27.68 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 206808 kb
Host smart-105ae403-58ee-423f-9622-73289e6a08e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237596829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3237596829
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1986302671
Short name T418
Test name
Test status
Simulation time 1110236496 ps
CPU time 50.27 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:51 PM PST 23
Peak memory 198780 kb
Host smart-b538f2b6-10c2-44ee-9230-f0c1177c703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986302671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1986302671
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.789319889
Short name T674
Test name
Test status
Simulation time 3593097707 ps
CPU time 85.24 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:44:22 PM PST 23
Peak memory 198792 kb
Host smart-77cf8ccf-07f3-4a56-880f-5a1f20b93f53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789319889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.789319889
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1469126007
Short name T779
Test name
Test status
Simulation time 18304017093 ps
CPU time 199.02 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:46:27 PM PST 23
Peak memory 198944 kb
Host smart-0cce5314-e071-44c7-9279-e1738c7e770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469126007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1469126007
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2609106859
Short name T426
Test name
Test status
Simulation time 10538489548 ps
CPU time 39.26 seconds
Started Dec 20 12:42:05 PM PST 23
Finished Dec 20 12:43:44 PM PST 23
Peak memory 198596 kb
Host smart-7cf09dc0-a038-4792-a639-37047b30709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609106859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2609106859
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.704296126
Short name T50
Test name
Test status
Simulation time 56132981 ps
CPU time 0.82 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:42:59 PM PST 23
Peak memory 215640 kb
Host smart-88724f5d-c155-4076-88a7-ee1d3b635efb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704296126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.704296126
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1459912952
Short name T317
Test name
Test status
Simulation time 380297834 ps
CPU time 3.81 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:43:08 PM PST 23
Peak memory 197728 kb
Host smart-b6e7073b-8792-4dd4-a4f8-716a82fc2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459912952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1459912952
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.538982745
Short name T265
Test name
Test status
Simulation time 870845790857 ps
CPU time 1125.4 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 01:01:43 PM PST 23
Peak memory 228408 kb
Host smart-411480b6-0ef7-4e75-a323-54ae975bc72e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538982745 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.538982745
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2638578345
Short name T364
Test name
Test status
Simulation time 97891404947 ps
CPU time 4009.43 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 01:50:00 PM PST 23
Peak memory 246568 kb
Host smart-9d1e2b5d-64ca-4ce5-8bbd-c8e606a9ac7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638578345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2638578345
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2239442131
Short name T690
Test name
Test status
Simulation time 98031195 ps
CPU time 0.84 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:08 PM PST 23
Peak memory 195976 kb
Host smart-2ea60b17-5b54-4863-a367-68f4eccf1e8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239442131 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2239442131
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.596123800
Short name T440
Test name
Test status
Simulation time 7486028842 ps
CPU time 338.04 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:48:40 PM PST 23
Peak memory 198848 kb
Host smart-04e7aafd-d1f0-4eff-be67-d4c661aa409c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596123800 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.hmac_test_sha_vectors.596123800
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3394816747
Short name T774
Test name
Test status
Simulation time 4936724244 ps
CPU time 51.15 seconds
Started Dec 20 12:42:07 PM PST 23
Finished Dec 20 12:43:57 PM PST 23
Peak memory 198896 kb
Host smart-a4c5371e-42f9-4a88-845b-1b76979b6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394816747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3394816747
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.979977451
Short name T629
Test name
Test status
Simulation time 42393485 ps
CPU time 0.55 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:48:03 PM PST 23
Peak memory 193216 kb
Host smart-5a5968ec-9306-4363-81c6-5512222bc5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979977451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.979977451
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.83434994
Short name T598
Test name
Test status
Simulation time 14698927377 ps
CPU time 24.82 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:49:07 PM PST 23
Peak memory 207056 kb
Host smart-2cd15576-9fd1-4d76-a548-6dbd3cfac2ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83434994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.83434994
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2404368520
Short name T294
Test name
Test status
Simulation time 769385756 ps
CPU time 13 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:48:15 PM PST 23
Peak memory 198780 kb
Host smart-b2f563d6-6dbc-4aa3-bd44-58687812dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404368520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2404368520
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.34610854
Short name T287
Test name
Test status
Simulation time 670592866 ps
CPU time 30.96 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 12:48:51 PM PST 23
Peak memory 198868 kb
Host smart-8911489f-4021-460e-a842-a32e2dc3b21c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34610854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.34610854
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1184696808
Short name T188
Test name
Test status
Simulation time 1905455651 ps
CPU time 93.17 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:49:29 PM PST 23
Peak memory 198820 kb
Host smart-a390d023-864d-46f8-a38e-a6e06775e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184696808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1184696808
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.713968812
Short name T333
Test name
Test status
Simulation time 30490845494 ps
CPU time 24.52 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:48:54 PM PST 23
Peak memory 198860 kb
Host smart-711c1711-8e62-46ec-8d27-24fca98ac126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713968812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.713968812
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.939562667
Short name T494
Test name
Test status
Simulation time 695970717 ps
CPU time 2.32 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:48:41 PM PST 23
Peak memory 198464 kb
Host smart-e08c55c4-482e-4e90-bd2d-21c8e75c066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939562667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.939562667
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3236878535
Short name T512
Test name
Test status
Simulation time 654686026349 ps
CPU time 1589.56 seconds
Started Dec 20 12:47:04 PM PST 23
Finished Dec 20 01:14:15 PM PST 23
Peak memory 242208 kb
Host smart-eab13d38-6a2a-4fcf-9104-34bdc5b28d00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236878535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3236878535
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3178592938
Short name T729
Test name
Test status
Simulation time 61409370206 ps
CPU time 877.28 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 01:02:29 PM PST 23
Peak memory 247560 kb
Host smart-21014cdd-2b42-4129-9a61-46858de4d43d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178592938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.3178592938
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.382720244
Short name T378
Test name
Test status
Simulation time 103048006 ps
CPU time 0.9 seconds
Started Dec 20 12:46:54 PM PST 23
Finished Dec 20 12:47:34 PM PST 23
Peak memory 196512 kb
Host smart-b2ec4e8f-9e63-484b-b670-e3f26bea9b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382720244 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.382720244
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3679601583
Short name T420
Test name
Test status
Simulation time 37891179363 ps
CPU time 397.69 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 198656 kb
Host smart-1132259e-4141-4553-b69c-5820405a859f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679601583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.3679601583
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2499473908
Short name T497
Test name
Test status
Simulation time 12054520111 ps
CPU time 36.92 seconds
Started Dec 20 12:47:47 PM PST 23
Finished Dec 20 12:49:44 PM PST 23
Peak memory 198896 kb
Host smart-5d0cbf61-8d1e-401b-82d6-d2f91aec9994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499473908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2499473908
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2877547887
Short name T282
Test name
Test status
Simulation time 12550180 ps
CPU time 0.55 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:48:12 PM PST 23
Peak memory 193136 kb
Host smart-38ef4910-fdc2-475d-9ac4-3d09ee49b878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877547887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2877547887
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3454567711
Short name T439
Test name
Test status
Simulation time 1288698688 ps
CPU time 9.54 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:47:52 PM PST 23
Peak memory 207016 kb
Host smart-13d5c8fd-ffc5-46e1-b718-b626c74e6218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454567711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3454567711
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3788484810
Short name T123
Test name
Test status
Simulation time 8858726866 ps
CPU time 24.96 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:48:20 PM PST 23
Peak memory 198820 kb
Host smart-99db1a3c-e340-4454-8b3e-6b27dff5a806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788484810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3788484810
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1156779644
Short name T563
Test name
Test status
Simulation time 723935600 ps
CPU time 35.65 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:48:23 PM PST 23
Peak memory 198800 kb
Host smart-9b82a9e5-8b60-47ea-8343-8d0910b3d324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156779644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1156779644
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.357527045
Short name T791
Test name
Test status
Simulation time 1098527195 ps
CPU time 51.69 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:49:09 PM PST 23
Peak memory 198676 kb
Host smart-b7e75be0-f545-4176-b532-90b77ca448fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357527045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.357527045
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3967463137
Short name T527
Test name
Test status
Simulation time 2004830998 ps
CPU time 99.47 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:49:52 PM PST 23
Peak memory 198752 kb
Host smart-27506f17-48b0-4c5c-9861-c189b6e75d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967463137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3967463137
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1549388678
Short name T608
Test name
Test status
Simulation time 1477924437 ps
CPU time 3.85 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:12 PM PST 23
Peak memory 198624 kb
Host smart-bfa61b3a-f5ac-4b0c-a397-8eeb58440c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549388678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1549388678
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1082955461
Short name T390
Test name
Test status
Simulation time 290520901690 ps
CPU time 1128.44 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 01:07:01 PM PST 23
Peak memory 198876 kb
Host smart-1ef0bca9-6280-4337-b110-a6a0762f3cf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082955461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1082955461
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.1608557323
Short name T361
Test name
Test status
Simulation time 74379083944 ps
CPU time 2500.7 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 01:30:01 PM PST 23
Peak memory 252180 kb
Host smart-5dc8e786-1834-499a-9fe7-e7cff394a4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608557323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.1608557323
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2438604084
Short name T801
Test name
Test status
Simulation time 187364380 ps
CPU time 0.86 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 12:48:07 PM PST 23
Peak memory 195972 kb
Host smart-e6c2fceb-fcd0-4f11-ba9c-83d826ba9314
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438604084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2438604084
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1720940209
Short name T740
Test name
Test status
Simulation time 122168424719 ps
CPU time 419.37 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 198784 kb
Host smart-f2e1beed-1096-4841-8877-d013da147071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720940209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1720940209
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.300258269
Short name T659
Test name
Test status
Simulation time 12387786133 ps
CPU time 51.59 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:49:03 PM PST 23
Peak memory 198860 kb
Host smart-ba948b82-6187-44cb-9612-0623867e48c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300258269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.300258269
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1925696792
Short name T468
Test name
Test status
Simulation time 11346455 ps
CPU time 0.54 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:48:17 PM PST 23
Peak memory 192892 kb
Host smart-1c5128fc-aef8-4c53-bcb0-cff37e7c8334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925696792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1925696792
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.766232451
Short name T194
Test name
Test status
Simulation time 360214943 ps
CPU time 2.96 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:48:16 PM PST 23
Peak memory 198812 kb
Host smart-4c0f3ac0-663e-43b3-bdce-122d9d3b51e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766232451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.766232451
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1660299257
Short name T232
Test name
Test status
Simulation time 241469875 ps
CPU time 5.11 seconds
Started Dec 20 12:47:04 PM PST 23
Finished Dec 20 12:47:50 PM PST 23
Peak memory 198536 kb
Host smart-8c9f6f16-8972-4f94-a8a4-29a5cc258506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660299257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1660299257
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3322526028
Short name T239
Test name
Test status
Simulation time 1079506940 ps
CPU time 26.74 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:48:16 PM PST 23
Peak memory 198740 kb
Host smart-ebf248fa-108c-4268-991d-b1bcefb4457c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322526028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3322526028
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.452255785
Short name T492
Test name
Test status
Simulation time 3699796360 ps
CPU time 176.4 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:50:54 PM PST 23
Peak memory 198928 kb
Host smart-36d17ab4-0490-41c8-9d04-9e030a72e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452255785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.452255785
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3090503006
Short name T473
Test name
Test status
Simulation time 16690170250 ps
CPU time 71.79 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:49:12 PM PST 23
Peak memory 198924 kb
Host smart-4aa33d6a-fd10-438e-9089-7427d79a8b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090503006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3090503006
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3075803100
Short name T427
Test name
Test status
Simulation time 304447534 ps
CPU time 3.06 seconds
Started Dec 20 12:47:09 PM PST 23
Finished Dec 20 12:47:59 PM PST 23
Peak memory 198488 kb
Host smart-0392fa9b-d6de-46a9-be56-c3e89f934ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075803100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3075803100
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.770456564
Short name T602
Test name
Test status
Simulation time 17242589585 ps
CPU time 71.1 seconds
Started Dec 20 12:47:30 PM PST 23
Finished Dec 20 12:49:56 PM PST 23
Peak memory 198872 kb
Host smart-3e5f4e35-c182-47a2-8fb6-df74266b60fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770456564 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.770456564
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.1605403250
Short name T800
Test name
Test status
Simulation time 77024014124 ps
CPU time 3213.77 seconds
Started Dec 20 12:47:35 PM PST 23
Finished Dec 20 01:42:28 PM PST 23
Peak memory 245404 kb
Host smart-8b40d6ee-fcb4-4b51-b6a7-a2f907731657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605403250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.1605403250
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1437116861
Short name T454
Test name
Test status
Simulation time 67057456 ps
CPU time 0.92 seconds
Started Dec 20 12:46:05 PM PST 23
Finished Dec 20 12:46:06 PM PST 23
Peak memory 196036 kb
Host smart-874ddfd6-325a-45d7-9a57-eae71768bdd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437116861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1437116861
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2030994039
Short name T764
Test name
Test status
Simulation time 160858981344 ps
CPU time 425.21 seconds
Started Dec 20 12:47:40 PM PST 23
Finished Dec 20 12:56:02 PM PST 23
Peak memory 198788 kb
Host smart-afc63ff2-a1a2-4481-aac8-4d5e13decb47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030994039 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.2030994039
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1341476156
Short name T589
Test name
Test status
Simulation time 6059831049 ps
CPU time 49.97 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:48:42 PM PST 23
Peak memory 198708 kb
Host smart-78d8681b-9777-46dd-b364-dea19278e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341476156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1341476156
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2633077837
Short name T802
Test name
Test status
Simulation time 161604536 ps
CPU time 0.6 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 12:46:30 PM PST 23
Peak memory 193132 kb
Host smart-349906b5-eefd-4164-92a6-a44210a4a792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633077837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2633077837
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3641936956
Short name T620
Test name
Test status
Simulation time 2120036183 ps
CPU time 38.83 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:48:42 PM PST 23
Peak memory 229524 kb
Host smart-6973e6d3-886f-44a0-8d67-914793b15831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641936956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3641936956
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1602458411
Short name T373
Test name
Test status
Simulation time 83178764 ps
CPU time 3.26 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:48:05 PM PST 23
Peak memory 198568 kb
Host smart-6cabb98b-ead4-4f91-bd53-8a0ffa9f5a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602458411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1602458411
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1384786053
Short name T457
Test name
Test status
Simulation time 8483521026 ps
CPU time 65.08 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:49:08 PM PST 23
Peak memory 198872 kb
Host smart-82a043ac-755f-40d0-b087-013edc27a674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384786053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1384786053
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.682431572
Short name T508
Test name
Test status
Simulation time 574914284 ps
CPU time 27.36 seconds
Started Dec 20 12:47:22 PM PST 23
Finished Dec 20 12:48:52 PM PST 23
Peak memory 198824 kb
Host smart-e47b1323-9656-45e9-b9b1-befdb4dfb0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682431572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.682431572
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2045206825
Short name T370
Test name
Test status
Simulation time 1770549409 ps
CPU time 78.75 seconds
Started Dec 20 12:47:22 PM PST 23
Finished Dec 20 12:49:47 PM PST 23
Peak memory 198852 kb
Host smart-fb352421-d716-4494-b5e1-fbf00a7dcc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045206825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2045206825
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1820257271
Short name T743
Test name
Test status
Simulation time 274875100 ps
CPU time 1.91 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 12:48:10 PM PST 23
Peak memory 198440 kb
Host smart-c1bfdbff-bb18-42a5-bd63-b4de8f620d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820257271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1820257271
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1532300456
Short name T459
Test name
Test status
Simulation time 203023288911 ps
CPU time 876.5 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 01:01:16 PM PST 23
Peak memory 207164 kb
Host smart-4a9c2730-2028-4819-bbf3-2a48560b98fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532300456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1532300456
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.571692148
Short name T204
Test name
Test status
Simulation time 81853420332 ps
CPU time 1343.58 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 01:08:54 PM PST 23
Peak memory 256368 kb
Host smart-35d6324c-b722-4a68-9195-c7048793de0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571692148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.571692148
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3240374465
Short name T462
Test name
Test status
Simulation time 62829337 ps
CPU time 1.24 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:46:34 PM PST 23
Peak memory 197468 kb
Host smart-a6b5a264-6591-4669-b6d5-68d84b4935c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240374465 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3240374465
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3394958780
Short name T352
Test name
Test status
Simulation time 8584138798 ps
CPU time 389.76 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 198924 kb
Host smart-b81b4419-b903-4b23-b11b-34766763a412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394958780 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3394958780
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2125715986
Short name T586
Test name
Test status
Simulation time 2096390512 ps
CPU time 35.3 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 12:48:42 PM PST 23
Peak memory 198848 kb
Host smart-5aec03aa-2032-47ad-ab79-2038387c820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125715986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2125715986
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2076418739
Short name T504
Test name
Test status
Simulation time 42565964 ps
CPU time 0.55 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:46:52 PM PST 23
Peak memory 193064 kb
Host smart-a80cadad-eb9c-4370-bdc0-6b6b3234e209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076418739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2076418739
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2329719660
Short name T617
Test name
Test status
Simulation time 4799248121 ps
CPU time 41.52 seconds
Started Dec 20 12:45:28 PM PST 23
Finished Dec 20 12:46:10 PM PST 23
Peak memory 231628 kb
Host smart-a97ebcc3-59b9-4e17-8a1d-3b35f0afb534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329719660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2329719660
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2061814126
Short name T235
Test name
Test status
Simulation time 1237987077 ps
CPU time 29.31 seconds
Started Dec 20 12:46:19 PM PST 23
Finished Dec 20 12:46:58 PM PST 23
Peak memory 198768 kb
Host smart-9bd9d405-fcd4-4e8e-b70d-1ed73739329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061814126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2061814126
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1210353922
Short name T472
Test name
Test status
Simulation time 2292615073 ps
CPU time 29.69 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:47:04 PM PST 23
Peak memory 198836 kb
Host smart-4405761e-98d2-4b7f-bc54-ea057dff7e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210353922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1210353922
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2161480339
Short name T696
Test name
Test status
Simulation time 9907770430 ps
CPU time 123.52 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:48:37 PM PST 23
Peak memory 199044 kb
Host smart-941b0864-df6c-4254-b339-d0080830ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161480339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2161480339
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3334385588
Short name T680
Test name
Test status
Simulation time 693891319 ps
CPU time 16.72 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 12:46:47 PM PST 23
Peak memory 198824 kb
Host smart-1e0dba93-86b9-47f0-a740-5238597ba2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334385588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3334385588
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1368826767
Short name T560
Test name
Test status
Simulation time 531991229 ps
CPU time 3.53 seconds
Started Dec 20 12:46:20 PM PST 23
Finished Dec 20 12:46:34 PM PST 23
Peak memory 198756 kb
Host smart-c56ded09-c027-4541-887a-e504ccd1d489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368826767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1368826767
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.241931325
Short name T578
Test name
Test status
Simulation time 333979853764 ps
CPU time 1222.85 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 01:06:57 PM PST 23
Peak memory 221436 kb
Host smart-fd86ad41-2246-44bc-959b-d3749ce362d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241931325 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.241931325
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.4060939230
Short name T768
Test name
Test status
Simulation time 138122258360 ps
CPU time 1761.66 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 01:15:56 PM PST 23
Peak memory 242544 kb
Host smart-836e444c-8d49-4dfd-9d08-989df8b7556d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060939230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.4060939230
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.789839504
Short name T638
Test name
Test status
Simulation time 78933141 ps
CPU time 1.19 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:35 PM PST 23
Peak memory 197912 kb
Host smart-d06179d0-4be1-44ce-b1d1-548fc0b9301a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789839504 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.789839504
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2817243399
Short name T482
Test name
Test status
Simulation time 28867139848 ps
CPU time 342.02 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:52:16 PM PST 23
Peak memory 198856 kb
Host smart-c30e9ba7-c65d-4faa-9d8b-22704dce858a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817243399 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.2817243399
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3742063478
Short name T634
Test name
Test status
Simulation time 376089781 ps
CPU time 5.78 seconds
Started Dec 20 12:46:21 PM PST 23
Finished Dec 20 12:46:38 PM PST 23
Peak memory 198852 kb
Host smart-f78c424d-0e7c-4614-b009-6ac8894c6e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742063478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3742063478
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3946818525
Short name T44
Test name
Test status
Simulation time 16598341 ps
CPU time 0.55 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:47:08 PM PST 23
Peak memory 193180 kb
Host smart-ef2355c8-0086-4941-b541-cf01e543f061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946818525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3946818525
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1024393155
Short name T486
Test name
Test status
Simulation time 1694383136 ps
CPU time 48.23 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 12:47:27 PM PST 23
Peak memory 213176 kb
Host smart-4e435582-bacb-4d54-84d6-718f2a584f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024393155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1024393155
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2967903998
Short name T298
Test name
Test status
Simulation time 851384705 ps
CPU time 18.33 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:15 PM PST 23
Peak memory 198604 kb
Host smart-ad3e6a44-549c-4c37-b818-18523733cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967903998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2967903998
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1339165842
Short name T817
Test name
Test status
Simulation time 66919409 ps
CPU time 0.62 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:46:34 PM PST 23
Peak memory 193856 kb
Host smart-ef00f332-3102-4b5a-bb52-59425fa95045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339165842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1339165842
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2578083398
Short name T303
Test name
Test status
Simulation time 1195054823 ps
CPU time 18.76 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:47:08 PM PST 23
Peak memory 198716 kb
Host smart-f4ac7403-9f41-4b5b-b8ad-99cde6ebf66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578083398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2578083398
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.407151692
Short name T786
Test name
Test status
Simulation time 2014370950 ps
CPU time 16.9 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:46:50 PM PST 23
Peak memory 198812 kb
Host smart-3b385c06-9bb8-4c6b-92f4-69342b8db4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407151692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.407151692
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2590033296
Short name T655
Test name
Test status
Simulation time 168740872 ps
CPU time 1.04 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 12:46:34 PM PST 23
Peak memory 197216 kb
Host smart-05306ddc-7183-4af3-b1d8-32334e507615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590033296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2590033296
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4097925371
Short name T606
Test name
Test status
Simulation time 184848816153 ps
CPU time 510.57 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 12:55:27 PM PST 23
Peak memory 207756 kb
Host smart-c58406e8-1ea8-4456-b216-3ceb6413d819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097925371 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4097925371
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.3625122564
Short name T591
Test name
Test status
Simulation time 359285688875 ps
CPU time 1312.38 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 01:08:35 PM PST 23
Peak memory 250512 kb
Host smart-f51e18ae-0150-4954-87cb-23123afc9888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625122564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.3625122564
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1496040920
Short name T535
Test name
Test status
Simulation time 165702514 ps
CPU time 0.88 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:47:03 PM PST 23
Peak memory 195684 kb
Host smart-758dfdc2-a3ba-4083-8231-884c93658b75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496040920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1496040920
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.275442507
Short name T753
Test name
Test status
Simulation time 121854908105 ps
CPU time 424.58 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 198952 kb
Host smart-0399e504-8e53-4826-a7d0-249034b7dbe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275442507 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_sha_vectors.275442507
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1175479556
Short name T808
Test name
Test status
Simulation time 2801926616 ps
CPU time 56.93 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:53 PM PST 23
Peak memory 198800 kb
Host smart-655f2e25-7637-4610-b9fb-4c581faecc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175479556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1175479556
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2214182571
Short name T778
Test name
Test status
Simulation time 64930647 ps
CPU time 0.59 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:46:57 PM PST 23
Peak memory 193000 kb
Host smart-c1727032-9f19-48b2-955e-d82c0e058e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214182571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2214182571
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1448136398
Short name T411
Test name
Test status
Simulation time 2366359823 ps
CPU time 16.5 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:51 PM PST 23
Peak memory 198812 kb
Host smart-59ffb878-aee1-48d5-8e53-92fa7420998c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448136398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1448136398
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1649180393
Short name T621
Test name
Test status
Simulation time 456874413 ps
CPU time 7.06 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:46:56 PM PST 23
Peak memory 198584 kb
Host smart-857de342-3188-49a3-82ac-c79a1bd07de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649180393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1649180393
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2849252756
Short name T452
Test name
Test status
Simulation time 564965019 ps
CPU time 6.33 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:46:49 PM PST 23
Peak memory 198804 kb
Host smart-185f6aea-18ba-4dcf-8bbe-e848b767f719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849252756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2849252756
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3452737575
Short name T54
Test name
Test status
Simulation time 106011723532 ps
CPU time 171.97 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 198900 kb
Host smart-490ba06b-8411-4be6-9f5e-f947923a3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452737575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3452737575
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2333185850
Short name T528
Test name
Test status
Simulation time 1622178840 ps
CPU time 69 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:47:54 PM PST 23
Peak memory 198828 kb
Host smart-6b54979a-a9bc-49c6-8c7f-42a2b579a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333185850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2333185850
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1425393791
Short name T829
Test name
Test status
Simulation time 1305571288 ps
CPU time 2.92 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:46:51 PM PST 23
Peak memory 198576 kb
Host smart-6e638b61-06a3-4f70-8830-5c0d6eb65731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425393791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1425393791
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1283258300
Short name T417
Test name
Test status
Simulation time 20465769079 ps
CPU time 955.99 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:03:07 PM PST 23
Peak memory 239552 kb
Host smart-99f9be53-042b-423a-a0c8-733daacebc0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283258300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1283258300
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.3158544064
Short name T222
Test name
Test status
Simulation time 57111554241 ps
CPU time 2802.43 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 01:33:58 PM PST 23
Peak memory 256692 kb
Host smart-1bb1f265-3933-4068-a9e9-618f7ae406ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158544064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.3158544064
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2045360523
Short name T821
Test name
Test status
Simulation time 76353474 ps
CPU time 0.91 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:46:49 PM PST 23
Peak memory 196412 kb
Host smart-ddd76abd-0298-4a6b-9ca7-f50ddeec9370
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045360523 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2045360523
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.656554537
Short name T491
Test name
Test status
Simulation time 45957475344 ps
CPU time 471.91 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 12:54:33 PM PST 23
Peak memory 198772 kb
Host smart-310ad3fe-6c5d-4039-a3e1-c204950d79ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656554537 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.656554537
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3361298108
Short name T809
Test name
Test status
Simulation time 3146179479 ps
CPU time 39.88 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:47:25 PM PST 23
Peak memory 198856 kb
Host smart-c2645607-35d7-4d5a-8686-b1957ecca52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361298108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3361298108
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1854858542
Short name T430
Test name
Test status
Simulation time 13085832 ps
CPU time 0.55 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:21 PM PST 23
Peak memory 193136 kb
Host smart-c6312350-8c11-45d4-a957-37c901b89817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854858542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1854858542
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.177461805
Short name T507
Test name
Test status
Simulation time 1512173262 ps
CPU time 45.07 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:47:50 PM PST 23
Peak memory 214848 kb
Host smart-0e1b97f1-0165-42d2-805c-860e704aba68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177461805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.177461805
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2608110889
Short name T681
Test name
Test status
Simulation time 1842747148 ps
CPU time 25.06 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:22 PM PST 23
Peak memory 198804 kb
Host smart-fd9d3273-1b41-40e6-bde9-684994a2cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608110889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2608110889
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.685518160
Short name T433
Test name
Test status
Simulation time 4801503270 ps
CPU time 45.59 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:47:35 PM PST 23
Peak memory 198936 kb
Host smart-7f655380-4ba4-46fc-b1a8-0ddf77c7580f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685518160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.685518160
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.689858511
Short name T326
Test name
Test status
Simulation time 48076123091 ps
CPU time 144.77 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 198872 kb
Host smart-209f7779-3a0d-4483-ba7a-0d968c48e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689858511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.689858511
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1362427314
Short name T732
Test name
Test status
Simulation time 19245399919 ps
CPU time 86.59 seconds
Started Dec 20 12:47:00 PM PST 23
Finished Dec 20 12:49:08 PM PST 23
Peak memory 198996 kb
Host smart-94157a71-2ca3-44a8-94a1-3cf7a5644a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362427314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1362427314
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3256644654
Short name T641
Test name
Test status
Simulation time 105967639 ps
CPU time 2.51 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:14 PM PST 23
Peak memory 198720 kb
Host smart-54623892-2e02-4ed0-9e46-78db3c27fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256644654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3256644654
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1567836763
Short name T112
Test name
Test status
Simulation time 152269611858 ps
CPU time 605.69 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 238932 kb
Host smart-2a6a519b-4d37-42a3-abac-167586a02f2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567836763 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1567836763
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.3678921057
Short name T406
Test name
Test status
Simulation time 7313383639 ps
CPU time 224.08 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 12:50:17 PM PST 23
Peak memory 198952 kb
Host smart-8f9f15b6-ecc5-4b3c-8641-74ed393ac71f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678921057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.3678921057
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1046482567
Short name T387
Test name
Test status
Simulation time 109523879 ps
CPU time 0.99 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 196812 kb
Host smart-30508eba-97f4-4add-aff3-34807dd1a75b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046482567 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1046482567
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.327375162
Short name T762
Test name
Test status
Simulation time 48495574519 ps
CPU time 497.76 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 198804 kb
Host smart-88c35a06-1516-4b3a-a037-dedc8bad7843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327375162 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.hmac_test_sha_vectors.327375162
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1295242375
Short name T322
Test name
Test status
Simulation time 429168413 ps
CPU time 6.09 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:47:21 PM PST 23
Peak memory 198856 kb
Host smart-e8aeee0e-efd6-4f68-8458-b73cdc51a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295242375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1295242375
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2590746077
Short name T288
Test name
Test status
Simulation time 49842535 ps
CPU time 0.56 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:07 PM PST 23
Peak memory 193160 kb
Host smart-f90143fe-1ea2-492d-8ffe-05f1dac85c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590746077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2590746077
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.673597153
Short name T511
Test name
Test status
Simulation time 4299613774 ps
CPU time 28.75 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:47:03 PM PST 23
Peak memory 215616 kb
Host smart-e66fec72-49f0-442f-a9ff-cc72a6f5b382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673597153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.673597153
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2391288923
Short name T666
Test name
Test status
Simulation time 3140398559 ps
CPU time 46.19 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 12:47:20 PM PST 23
Peak memory 198780 kb
Host smart-55e73d8a-52ef-45c5-93d0-90886e6a61b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391288923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2391288923
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.873409255
Short name T293
Test name
Test status
Simulation time 2093644592 ps
CPU time 25.63 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:47:20 PM PST 23
Peak memory 198704 kb
Host smart-6ba72373-50b1-4ace-87e5-a4da5989927b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873409255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.873409255
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1431420375
Short name T443
Test name
Test status
Simulation time 9719629960 ps
CPU time 130.77 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:48:45 PM PST 23
Peak memory 198908 kb
Host smart-6564c931-5d14-4195-b7cb-e7d07e194334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431420375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1431420375
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1297070731
Short name T201
Test name
Test status
Simulation time 15522783703 ps
CPU time 92.39 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:48:06 PM PST 23
Peak memory 198860 kb
Host smart-1e14b504-604a-4387-bd3c-ba52fd8e4d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297070731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1297070731
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2548494874
Short name T62
Test name
Test status
Simulation time 182938072 ps
CPU time 2.4 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:46:36 PM PST 23
Peak memory 198784 kb
Host smart-26857608-a9c6-4044-8bdf-aac8cd34f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548494874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2548494874
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1012740550
Short name T216
Test name
Test status
Simulation time 262987700 ps
CPU time 7.58 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:47:02 PM PST 23
Peak memory 198780 kb
Host smart-8d0791b8-7c3e-48c6-b72b-45a74aa4d86b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012740550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1012740550
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.1423423613
Short name T686
Test name
Test status
Simulation time 120015828503 ps
CPU time 185.73 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:49:51 PM PST 23
Peak memory 207056 kb
Host smart-509bcb06-feff-4e28-b820-b2edbc079d59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423423613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.1423423613
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.653184640
Short name T397
Test name
Test status
Simulation time 60728382 ps
CPU time 1.05 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:46:51 PM PST 23
Peak memory 197256 kb
Host smart-f00cd616-fc61-46e9-b7bf-1e5278d10eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653184640 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.653184640
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1086012784
Short name T328
Test name
Test status
Simulation time 26736900547 ps
CPU time 355.91 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:52:30 PM PST 23
Peak memory 198808 kb
Host smart-37e2644f-d765-4778-8b67-91ae3175fb75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086012784 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.1086012784
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.575610058
Short name T537
Test name
Test status
Simulation time 570049459 ps
CPU time 26.01 seconds
Started Dec 20 12:46:22 PM PST 23
Finished Dec 20 12:46:59 PM PST 23
Peak memory 198804 kb
Host smart-ba001693-f0c1-443c-82e8-4df3de10b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575610058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.575610058
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4163925640
Short name T46
Test name
Test status
Simulation time 127857612 ps
CPU time 0.58 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:38 PM PST 23
Peak memory 193116 kb
Host smart-f31a0f07-4e1e-49de-ab06-b9b6b030dcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163925640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4163925640
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4046574031
Short name T714
Test name
Test status
Simulation time 1641014138 ps
CPU time 26.2 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:35 PM PST 23
Peak memory 226080 kb
Host smart-a52f5c13-dc49-4e09-a008-bc952f5d4b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046574031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4046574031
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1526045944
Short name T393
Test name
Test status
Simulation time 6076346021 ps
CPU time 53.71 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:47:54 PM PST 23
Peak memory 198780 kb
Host smart-68772f56-1275-4414-a977-e354d5101b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526045944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1526045944
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2339594385
Short name T814
Test name
Test status
Simulation time 2634938878 ps
CPU time 127.59 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:49:19 PM PST 23
Peak memory 198860 kb
Host smart-312abc85-7dc6-451e-9392-2a2bf641a84b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339594385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2339594385
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3065847259
Short name T531
Test name
Test status
Simulation time 6519139364 ps
CPU time 48.33 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:47:38 PM PST 23
Peak memory 198756 kb
Host smart-7a93c0a9-5fae-48da-bf72-b6aeafdeaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065847259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3065847259
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1813405689
Short name T362
Test name
Test status
Simulation time 1306035543 ps
CPU time 66.56 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 198772 kb
Host smart-558c78a0-d7cb-45d5-9abf-041f8fea9305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813405689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1813405689
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3716683187
Short name T832
Test name
Test status
Simulation time 991753284 ps
CPU time 1.09 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:47:06 PM PST 23
Peak memory 197664 kb
Host smart-5fb75a6a-02ef-426e-b126-ceb5adc566bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716683187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3716683187
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3196818094
Short name T567
Test name
Test status
Simulation time 122800596902 ps
CPU time 928.51 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:02:33 PM PST 23
Peak memory 215152 kb
Host smart-3c387257-cc54-4328-a063-cbeafc9bded7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196818094 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3196818094
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3608964724
Short name T375
Test name
Test status
Simulation time 55492902276 ps
CPU time 790.16 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:59:57 PM PST 23
Peak memory 249056 kb
Host smart-621f0c65-692a-4825-87a3-0b6fdaf64c43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608964724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.3608964724
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.245810447
Short name T766
Test name
Test status
Simulation time 770900150 ps
CPU time 1.23 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 12:46:56 PM PST 23
Peak memory 197568 kb
Host smart-ea2d4e7f-3f00-499c-b392-e436fe677d0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245810447 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_hmac_vectors.245810447
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1034619755
Short name T340
Test name
Test status
Simulation time 52015178722 ps
CPU time 364.75 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 198720 kb
Host smart-20c00b51-6398-4d62-9631-1da89d81c287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034619755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.1034619755
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.809108670
Short name T601
Test name
Test status
Simulation time 958865549 ps
CPU time 34.34 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:47:39 PM PST 23
Peak memory 198660 kb
Host smart-c4b32d44-fad4-499c-9b37-228b8c42efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809108670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.809108670
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.361783624
Short name T594
Test name
Test status
Simulation time 41212834 ps
CPU time 0.54 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:43:00 PM PST 23
Peak memory 192952 kb
Host smart-cd8ee6d7-2d69-431b-ad50-982ecf8b1a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361783624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.361783624
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1854881396
Short name T533
Test name
Test status
Simulation time 4429857173 ps
CPU time 34.15 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:43:38 PM PST 23
Peak memory 223552 kb
Host smart-957bfcd1-f155-41c0-9cb5-9235728e4c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854881396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1854881396
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3006907422
Short name T335
Test name
Test status
Simulation time 575904166 ps
CPU time 7.59 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:43:01 PM PST 23
Peak memory 198700 kb
Host smart-b34c9785-e7b6-4672-a47c-b245abd4efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006907422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3006907422
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1941388804
Short name T211
Test name
Test status
Simulation time 3524421929 ps
CPU time 42.25 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:43:40 PM PST 23
Peak memory 198912 kb
Host smart-cd389942-aad3-4a99-a33d-2b095f2ec6d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941388804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1941388804
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3804966158
Short name T848
Test name
Test status
Simulation time 1599096225 ps
CPU time 2.7 seconds
Started Dec 20 12:41:53 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 198752 kb
Host smart-0879366b-2b46-43e8-b4e7-af96b384ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804966158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3804966158
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3151710352
Short name T253
Test name
Test status
Simulation time 1694722153 ps
CPU time 7.7 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 198828 kb
Host smart-5dda66c0-4452-4c5c-819a-ca0b147f4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151710352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3151710352
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1920800116
Short name T51
Test name
Test status
Simulation time 223800910 ps
CPU time 0.9 seconds
Started Dec 20 12:41:53 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 216540 kb
Host smart-ee5439e0-686a-4524-9868-c18ab92ce5fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920800116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1920800116
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2369882110
Short name T676
Test name
Test status
Simulation time 548152864 ps
CPU time 1.77 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 198768 kb
Host smart-c29b165b-4696-453d-a1b8-b62921d15f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369882110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2369882110
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.589765352
Short name T632
Test name
Test status
Simulation time 8086752107 ps
CPU time 394.49 seconds
Started Dec 20 12:41:51 PM PST 23
Finished Dec 20 12:49:28 PM PST 23
Peak memory 198872 kb
Host smart-e2548956-4014-4f35-8e71-4e4a877cfc3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589765352 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.589765352
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.726613323
Short name T827
Test name
Test status
Simulation time 47376634426 ps
CPU time 740.94 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 237192 kb
Host smart-c37effd1-a034-4c50-9a6c-ea05e6e5e56e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726613323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.726613323
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1450824730
Short name T818
Test name
Test status
Simulation time 59499669 ps
CPU time 0.84 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 195872 kb
Host smart-f86a2a78-188f-4a19-b153-46792038091c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450824730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1450824730
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1506266137
Short name T42
Test name
Test status
Simulation time 8370614794 ps
CPU time 404.86 seconds
Started Dec 20 12:41:53 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 198764 kb
Host smart-95f472c9-6b40-40a2-b820-bb24e014f505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506266137 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.1506266137
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1730374632
Short name T205
Test name
Test status
Simulation time 2843696224 ps
CPU time 10.32 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 198920 kb
Host smart-c61f418a-30f3-4a61-904e-2bc944a9a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730374632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1730374632
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2877886467
Short name T297
Test name
Test status
Simulation time 14227504 ps
CPU time 0.55 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 12:47:15 PM PST 23
Peak memory 193172 kb
Host smart-e05670e9-d177-43c3-84f6-94a9fc5cf1a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877886467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2877886467
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1039121106
Short name T209
Test name
Test status
Simulation time 268437599 ps
CPU time 7.64 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:43 PM PST 23
Peak memory 206804 kb
Host smart-85ec291f-0310-4e4c-9c13-a732cc66cb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039121106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1039121106
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3483199001
Short name T435
Test name
Test status
Simulation time 12709485704 ps
CPU time 44.54 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:41 PM PST 23
Peak memory 198960 kb
Host smart-63b6ea24-b5a4-4f03-a8da-6027a004ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483199001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3483199001
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2516338232
Short name T625
Test name
Test status
Simulation time 10587398078 ps
CPU time 81.7 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:48:13 PM PST 23
Peak memory 198956 kb
Host smart-8e8e2139-354f-4c19-b1db-de417ec914a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516338232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2516338232
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3004820628
Short name T296
Test name
Test status
Simulation time 85043091012 ps
CPU time 150.93 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:49:36 PM PST 23
Peak memory 198892 kb
Host smart-e599a342-1804-4a3f-99e6-f5455a76ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004820628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3004820628
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.386989101
Short name T749
Test name
Test status
Simulation time 21364970007 ps
CPU time 51.29 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:48:03 PM PST 23
Peak memory 198804 kb
Host smart-44d7160d-f628-46dc-859c-3f14cdd16497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386989101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.386989101
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2925532562
Short name T271
Test name
Test status
Simulation time 201522328 ps
CPU time 2.48 seconds
Started Dec 20 12:46:35 PM PST 23
Finished Dec 20 12:47:07 PM PST 23
Peak memory 198600 kb
Host smart-3043f4e7-d213-4b31-8c73-f9638630bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925532562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2925532562
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2272357226
Short name T534
Test name
Test status
Simulation time 119422263678 ps
CPU time 1844.61 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 01:17:44 PM PST 23
Peak memory 207164 kb
Host smart-2addaf92-2426-46eb-980b-17231f35b560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272357226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2272357226
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.889479083
Short name T119
Test name
Test status
Simulation time 62116044066 ps
CPU time 2817.62 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:34:08 PM PST 23
Peak memory 253036 kb
Host smart-04a0b7d0-2727-4e50-93b0-7a51998062f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889479083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.889479083
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2440747978
Short name T773
Test name
Test status
Simulation time 52936092 ps
CPU time 1.11 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:46:59 PM PST 23
Peak memory 197488 kb
Host smart-e34717f1-a379-4e83-b85f-2cc0f403909b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440747978 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2440747978
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.903043082
Short name T553
Test name
Test status
Simulation time 38081971753 ps
CPU time 445.05 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:54:15 PM PST 23
Peak memory 198896 kb
Host smart-3087ab53-9c0a-4307-aeed-854028c5ac6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903043082 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_sha_vectors.903043082
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3302549638
Short name T573
Test name
Test status
Simulation time 1653590296 ps
CPU time 55.93 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:48:01 PM PST 23
Peak memory 198716 kb
Host smart-bd3cd9ca-11c0-4100-be75-5e63df395148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302549638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3302549638
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3019540067
Short name T244
Test name
Test status
Simulation time 49948506 ps
CPU time 0.54 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:47:05 PM PST 23
Peak memory 193156 kb
Host smart-07dc3a1e-de09-4506-89ac-5998feaae7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019540067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3019540067
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3434837818
Short name T826
Test name
Test status
Simulation time 3825965487 ps
CPU time 47.01 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:58 PM PST 23
Peak memory 223208 kb
Host smart-e28193d5-9e75-4d36-8dfc-d6dd99964f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434837818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3434837818
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1041134437
Short name T349
Test name
Test status
Simulation time 1922334288 ps
CPU time 30.96 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:47:25 PM PST 23
Peak memory 198752 kb
Host smart-5aeb133f-7ce7-4505-b1af-e362d082f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041134437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1041134437
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2091295432
Short name T221
Test name
Test status
Simulation time 357084473 ps
CPU time 17.92 seconds
Started Dec 20 12:46:42 PM PST 23
Finished Dec 20 12:47:34 PM PST 23
Peak memory 198664 kb
Host smart-9d971684-54a5-44c1-861d-225d66df169c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091295432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2091295432
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3770180925
Short name T292
Test name
Test status
Simulation time 2054873163 ps
CPU time 22.55 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:47:35 PM PST 23
Peak memory 198748 kb
Host smart-7f0eac22-fd27-44a1-b956-d3b1b3b0d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770180925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3770180925
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3355581833
Short name T342
Test name
Test status
Simulation time 1226491777 ps
CPU time 62.78 seconds
Started Dec 20 12:46:42 PM PST 23
Finished Dec 20 12:48:19 PM PST 23
Peak memory 198820 kb
Host smart-d8124796-9016-40ae-a6a1-e09678c09a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355581833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3355581833
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.608703629
Short name T295
Test name
Test status
Simulation time 1744402273 ps
CPU time 2.79 seconds
Started Dec 20 12:46:44 PM PST 23
Finished Dec 20 12:47:22 PM PST 23
Peak memory 198440 kb
Host smart-e980ae92-01f2-4f7a-b741-629e1d9388c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608703629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.608703629
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2947410832
Short name T813
Test name
Test status
Simulation time 2361941066 ps
CPU time 33.42 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:47:38 PM PST 23
Peak memory 207064 kb
Host smart-bb878f48-f792-41cb-8313-902eccf25d4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947410832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2947410832
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1063041142
Short name T191
Test name
Test status
Simulation time 104931844626 ps
CPU time 418.3 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 214692 kb
Host smart-958b2952-33d0-49a0-a521-6a2616ea790e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063041142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1063041142
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3597168767
Short name T358
Test name
Test status
Simulation time 43987318 ps
CPU time 0.92 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 195876 kb
Host smart-7fcf7ad4-3e04-4ab4-baf9-4847f5aaa6f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597168767 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3597168767
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.965180438
Short name T200
Test name
Test status
Simulation time 29066558452 ps
CPU time 448.13 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:54:22 PM PST 23
Peak memory 198884 kb
Host smart-6f265005-9ecc-49d3-bb3d-581b8d09818f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965180438 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_sha_vectors.965180438
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.412193822
Short name T412
Test name
Test status
Simulation time 4404343426 ps
CPU time 69.33 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:48:06 PM PST 23
Peak memory 198856 kb
Host smart-644ee315-ae7a-4291-bd5d-da35d8d7f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412193822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.412193822
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.215878416
Short name T846
Test name
Test status
Simulation time 14037985 ps
CPU time 0.55 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:46:46 PM PST 23
Peak memory 193236 kb
Host smart-0718845a-ac57-4d2d-87aa-67686a14ce5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215878416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.215878416
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3634076090
Short name T346
Test name
Test status
Simulation time 4572419787 ps
CPU time 32.45 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:47:07 PM PST 23
Peak memory 207060 kb
Host smart-c37a5e1d-3cfd-43ba-a9b7-c7147159a006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634076090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3634076090
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3329669766
Short name T483
Test name
Test status
Simulation time 65149158 ps
CPU time 1.58 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:38 PM PST 23
Peak memory 198736 kb
Host smart-cfc20d9b-20a7-467b-b14e-c93a42b8a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329669766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3329669766
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1939676810
Short name T836
Test name
Test status
Simulation time 4555495724 ps
CPU time 63.46 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:47:37 PM PST 23
Peak memory 198824 kb
Host smart-28e79a23-be39-4f9e-b410-e97f05540cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939676810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1939676810
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.121462292
Short name T610
Test name
Test status
Simulation time 10918089498 ps
CPU time 125.04 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 198860 kb
Host smart-01a184b8-4218-43ab-a03d-28be3be5264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121462292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.121462292
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2851413253
Short name T536
Test name
Test status
Simulation time 22948985964 ps
CPU time 99.02 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:48:13 PM PST 23
Peak memory 198920 kb
Host smart-0c8b7e03-560c-47b1-abc6-c749bb6c0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851413253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2851413253
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2697986503
Short name T208
Test name
Test status
Simulation time 480182872 ps
CPU time 3.22 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:46:37 PM PST 23
Peak memory 198816 kb
Host smart-d230f555-38a5-4b39-a543-fadd28ac7b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697986503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2697986503
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.261806522
Short name T243
Test name
Test status
Simulation time 3956520790 ps
CPU time 71.43 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:47:54 PM PST 23
Peak memory 198872 kb
Host smart-b37a4a21-207c-4eb4-972e-3c89b319ed61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261806522 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.261806522
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.95673060
Short name T574
Test name
Test status
Simulation time 803854900141 ps
CPU time 1146.51 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 01:05:44 PM PST 23
Peak memory 248108 kb
Host smart-e106ece3-2568-4ca9-b272-ffef6560ff91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95673060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.95673060
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3378144916
Short name T717
Test name
Test status
Simulation time 125050144 ps
CPU time 0.86 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:46:35 PM PST 23
Peak memory 196456 kb
Host smart-eca0500b-90e8-46d5-aae2-2f0882ec22a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378144916 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3378144916
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1851119733
Short name T190
Test name
Test status
Simulation time 28317495106 ps
CPU time 334.75 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:52:24 PM PST 23
Peak memory 198888 kb
Host smart-2be8dcfc-d548-434a-8553-290749fc2d07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851119733 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.1851119733
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1463215952
Short name T761
Test name
Test status
Simulation time 952903249 ps
CPU time 36.92 seconds
Started Dec 20 12:46:23 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 198812 kb
Host smart-effdf37e-2411-4c43-8441-b82011dc2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463215952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1463215952
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.378516316
Short name T479
Test name
Test status
Simulation time 28884739 ps
CPU time 0.56 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:46:46 PM PST 23
Peak memory 194316 kb
Host smart-f39d6483-1a3f-467c-80d2-315606a4593b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378516316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.378516316
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4272828023
Short name T441
Test name
Test status
Simulation time 1339695676 ps
CPU time 43.91 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:47:20 PM PST 23
Peak memory 215124 kb
Host smart-736a7702-27bc-4347-ac9a-6dd65c434f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272828023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4272828023
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4205581516
Short name T754
Test name
Test status
Simulation time 1325627789 ps
CPU time 61.63 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:48:06 PM PST 23
Peak memory 198720 kb
Host smart-b1e7326e-263e-46aa-989c-ec2e74a48451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205581516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4205581516
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2643321147
Short name T803
Test name
Test status
Simulation time 396295672 ps
CPU time 18.93 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:47:27 PM PST 23
Peak memory 198800 kb
Host smart-741fc158-f57b-4db2-9b30-879131bdd5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643321147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2643321147
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4000478598
Short name T532
Test name
Test status
Simulation time 20081648863 ps
CPU time 120.36 seconds
Started Dec 20 12:46:28 PM PST 23
Finished Dec 20 12:48:43 PM PST 23
Peak memory 198860 kb
Host smart-3b7ca64f-fe55-4ab5-8140-ebc975cf6769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000478598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4000478598
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3303307
Short name T654
Test name
Test status
Simulation time 1618074108 ps
CPU time 81.49 seconds
Started Dec 20 12:46:25 PM PST 23
Finished Dec 20 12:47:55 PM PST 23
Peak memory 198740 kb
Host smart-929c8821-2275-421b-b359-b1777e6450d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3303307
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2994496794
Short name T588
Test name
Test status
Simulation time 641547353 ps
CPU time 3.61 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:47:06 PM PST 23
Peak memory 198800 kb
Host smart-63d2dbf5-b058-4602-8aa3-c9eb45ba317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994496794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2994496794
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1127232986
Short name T844
Test name
Test status
Simulation time 31259445437 ps
CPU time 311.71 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:52:05 PM PST 23
Peak memory 206960 kb
Host smart-e8ae1e78-e9fa-4a85-b146-5d51b6bbb6b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127232986 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1127232986
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.1012126429
Short name T381
Test name
Test status
Simulation time 361171368064 ps
CPU time 758.39 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:59:28 PM PST 23
Peak memory 248216 kb
Host smart-b25c2f6e-9f69-4e07-b569-6c3fc3f9e54d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012126429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.1012126429
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2676555518
Short name T704
Test name
Test status
Simulation time 28556783 ps
CPU time 0.89 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:46:51 PM PST 23
Peak memory 196016 kb
Host smart-d90fe46d-fbe4-43ea-b5fc-830e5aceb507
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676555518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2676555518
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.299193622
Short name T785
Test name
Test status
Simulation time 9341472045 ps
CPU time 345.34 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:52:30 PM PST 23
Peak memory 198916 kb
Host smart-9f44f0ac-4d52-4b4c-ae6a-17844882c5a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299193622 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_sha_vectors.299193622
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3921854858
Short name T828
Test name
Test status
Simulation time 2872376996 ps
CPU time 34.61 seconds
Started Dec 20 12:46:27 PM PST 23
Finished Dec 20 12:47:13 PM PST 23
Peak memory 198920 kb
Host smart-67077697-7f04-4b48-9977-f6ee8d7b84e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921854858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3921854858
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2141720767
Short name T258
Test name
Test status
Simulation time 33054067 ps
CPU time 0.55 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:09 PM PST 23
Peak memory 192964 kb
Host smart-7812257c-8517-420c-ab1f-1d9f5c48288d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141720767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2141720767
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.432231045
Short name T339
Test name
Test status
Simulation time 205259927 ps
CPU time 10.12 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:19 PM PST 23
Peak memory 228688 kb
Host smart-8ced4f0b-3f2f-4ce5-af8e-dcadd1452a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432231045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.432231045
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3679272380
Short name T847
Test name
Test status
Simulation time 5371256113 ps
CPU time 17.64 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:47:07 PM PST 23
Peak memory 198908 kb
Host smart-b67afe30-d036-41ce-9431-95f9dcb3bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679272380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3679272380
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1776595060
Short name T579
Test name
Test status
Simulation time 2248839987 ps
CPU time 54.65 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:47:29 PM PST 23
Peak memory 198784 kb
Host smart-9d087d78-90ce-47a9-ac9a-e3e47d52805f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776595060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1776595060
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2919439713
Short name T312
Test name
Test status
Simulation time 10625756752 ps
CPU time 114.14 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 12:48:59 PM PST 23
Peak memory 198848 kb
Host smart-32b7b414-f305-45ee-88c5-05e1167cee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919439713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2919439713
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.419979574
Short name T187
Test name
Test status
Simulation time 191254698 ps
CPU time 3.02 seconds
Started Dec 20 12:46:26 PM PST 23
Finished Dec 20 12:46:39 PM PST 23
Peak memory 198736 kb
Host smart-822e771d-bc6d-41ff-bb69-0fd2646f5b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419979574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.419979574
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2250565826
Short name T733
Test name
Test status
Simulation time 371100355 ps
CPU time 3.68 seconds
Started Dec 20 12:46:30 PM PST 23
Finished Dec 20 12:46:53 PM PST 23
Peak memory 198736 kb
Host smart-9ddd6bdf-4102-4d5b-b38f-3d631b0f55a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250565826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2250565826
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1581704533
Short name T61
Test name
Test status
Simulation time 100016005108 ps
CPU time 1199.63 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 01:06:53 PM PST 23
Peak memory 231620 kb
Host smart-b7d19076-acce-4fe6-bbe0-c57275f1e2db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581704533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1581704533
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.868124409
Short name T245
Test name
Test status
Simulation time 62397116 ps
CPU time 1.11 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 12:46:56 PM PST 23
Peak memory 196544 kb
Host smart-2dc4b704-4de6-4909-a92c-371fd2097b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868124409 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.868124409
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1193828633
Short name T738
Test name
Test status
Simulation time 14251643654 ps
CPU time 310.9 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:52:19 PM PST 23
Peak memory 198656 kb
Host smart-9af69219-7248-4737-a5a4-1436e0d84185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193828633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.1193828633
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1229977317
Short name T840
Test name
Test status
Simulation time 1446246364 ps
CPU time 11.08 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:07 PM PST 23
Peak memory 198468 kb
Host smart-cbe66ab3-a83d-41ee-ae30-5db0f9f01ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229977317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1229977317
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3046279308
Short name T431
Test name
Test status
Simulation time 23895677 ps
CPU time 0.62 seconds
Started Dec 20 12:46:35 PM PST 23
Finished Dec 20 12:47:04 PM PST 23
Peak memory 194192 kb
Host smart-f28b2ede-e168-414d-a748-2fd617bc270d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046279308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3046279308
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1683746008
Short name T639
Test name
Test status
Simulation time 112275236 ps
CPU time 1.09 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:20 PM PST 23
Peak memory 198720 kb
Host smart-6c059aba-87b7-49ed-a821-6b16caeba63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683746008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1683746008
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3309904460
Short name T660
Test name
Test status
Simulation time 175523383 ps
CPU time 1.2 seconds
Started Dec 20 12:46:35 PM PST 23
Finished Dec 20 12:47:06 PM PST 23
Peak memory 197908 kb
Host smart-0ad528c4-bd05-4aa8-81a3-52c83f1880a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309904460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3309904460
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2103426643
Short name T756
Test name
Test status
Simulation time 1695943568 ps
CPU time 83.57 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:48:23 PM PST 23
Peak memory 198720 kb
Host smart-edac5fa7-0294-4e19-aa06-7ff0ba45e6a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103426643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2103426643
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1705566406
Short name T757
Test name
Test status
Simulation time 12495133836 ps
CPU time 183.8 seconds
Started Dec 20 12:46:32 PM PST 23
Finished Dec 20 12:49:59 PM PST 23
Peak memory 199004 kb
Host smart-c1d84859-4401-484b-8215-10cec5c7b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705566406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1705566406
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3320810025
Short name T1
Test name
Test status
Simulation time 3299291772 ps
CPU time 56.76 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:53 PM PST 23
Peak memory 198980 kb
Host smart-49cf4661-41e8-41a4-b958-28a63f66e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320810025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3320810025
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2303720037
Short name T307
Test name
Test status
Simulation time 2817358380 ps
CPU time 3.83 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 12:47:00 PM PST 23
Peak memory 198956 kb
Host smart-80589fa8-b65b-42e4-af9f-da1588af0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303720037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2303720037
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.183050334
Short name T302
Test name
Test status
Simulation time 649758422 ps
CPU time 7.2 seconds
Started Dec 20 12:46:24 PM PST 23
Finished Dec 20 12:46:40 PM PST 23
Peak memory 198800 kb
Host smart-3b693fb8-58e2-4231-91ce-5f8367897efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183050334 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.183050334
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.2845479638
Short name T741
Test name
Test status
Simulation time 253687954143 ps
CPU time 2809.66 seconds
Started Dec 20 12:46:33 PM PST 23
Finished Dec 20 01:33:46 PM PST 23
Peak memory 259424 kb
Host smart-cee788bc-276f-41aa-aaa5-74ede0c7e361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845479638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.2845479638
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.239676417
Short name T627
Test name
Test status
Simulation time 393137337 ps
CPU time 0.84 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:46:55 PM PST 23
Peak memory 195952 kb
Host smart-84464827-88fd-4fbc-8268-7ab1baea0472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239676417 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.239676417
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3097149514
Short name T823
Test name
Test status
Simulation time 74114938172 ps
CPU time 345.09 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:52:58 PM PST 23
Peak memory 198996 kb
Host smart-8598e262-f20e-4987-bd87-1774825f9ccf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097149514 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.3097149514
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3697480162
Short name T715
Test name
Test status
Simulation time 192676785 ps
CPU time 5.95 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:15 PM PST 23
Peak memory 198844 kb
Host smart-986d9312-def8-43ac-a6db-82b9753fa2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697480162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3697480162
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1074382293
Short name T581
Test name
Test status
Simulation time 12123542 ps
CPU time 0.53 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:11 PM PST 23
Peak memory 193136 kb
Host smart-25081e85-835f-46e8-af58-eb56d64bc385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074382293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1074382293
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4082328024
Short name T311
Test name
Test status
Simulation time 715822821 ps
CPU time 23.54 seconds
Started Dec 20 12:46:48 PM PST 23
Finished Dec 20 12:47:47 PM PST 23
Peak memory 231524 kb
Host smart-c5b5b63a-58b1-405b-beaa-9e7385981288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082328024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4082328024
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2859807140
Short name T184
Test name
Test status
Simulation time 55103212 ps
CPU time 2.4 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 198784 kb
Host smart-e5b27664-4141-471d-a519-a7048b0d06fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859807140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2859807140
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1049732447
Short name T702
Test name
Test status
Simulation time 8441041639 ps
CPU time 62.1 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:48:10 PM PST 23
Peak memory 198892 kb
Host smart-220cd1c4-b917-4434-a4af-45fc7f80da3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049732447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1049732447
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.686718241
Short name T477
Test name
Test status
Simulation time 213793078 ps
CPU time 10.45 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:47:13 PM PST 23
Peak memory 198420 kb
Host smart-22615c98-f5eb-48be-b42d-2728a9e11e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686718241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.686718241
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3369176588
Short name T43
Test name
Test status
Simulation time 2057120301 ps
CPU time 91.69 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 12:48:40 PM PST 23
Peak memory 198752 kb
Host smart-ddc5091a-e821-49d6-a98e-3be2f89ebba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369176588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3369176588
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.276661677
Short name T772
Test name
Test status
Simulation time 781593653 ps
CPU time 2.54 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 12:47:18 PM PST 23
Peak memory 198752 kb
Host smart-a0d5679d-648c-404c-9a39-cdfebfdef77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276661677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.276661677
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2238802193
Short name T274
Test name
Test status
Simulation time 467926401 ps
CPU time 1.74 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 12:47:15 PM PST 23
Peak memory 197784 kb
Host smart-81214e4c-bf27-4bee-916a-58602ec5b9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238802193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2238802193
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.1039345632
Short name T275
Test name
Test status
Simulation time 73312712908 ps
CPU time 1091.63 seconds
Started Dec 20 12:46:46 PM PST 23
Finished Dec 20 01:05:34 PM PST 23
Peak memory 215356 kb
Host smart-efaa18da-88df-49ea-8dc4-df9c54ab3586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039345632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.1039345632
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2522279962
Short name T225
Test name
Test status
Simulation time 207367587 ps
CPU time 0.9 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:47:14 PM PST 23
Peak memory 196500 kb
Host smart-286dbfc8-3770-4094-8f74-c384510fc682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522279962 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2522279962
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3159475517
Short name T299
Test name
Test status
Simulation time 8858470500 ps
CPU time 72.27 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 12:48:28 PM PST 23
Peak memory 198888 kb
Host smart-9b6d9019-bf0e-44b4-b6ff-1ba7165bcd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159475517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3159475517
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.787779910
Short name T465
Test name
Test status
Simulation time 35367025 ps
CPU time 0.54 seconds
Started Dec 20 12:46:49 PM PST 23
Finished Dec 20 12:47:27 PM PST 23
Peak memory 193124 kb
Host smart-58192aab-24b7-4fdd-a649-e04583621f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787779910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.787779910
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2032058758
Short name T583
Test name
Test status
Simulation time 720617083 ps
CPU time 24.29 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 12:47:51 PM PST 23
Peak memory 218212 kb
Host smart-e81f638d-324f-4280-80a0-e4bfbf18086c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032058758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2032058758
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.817057730
Short name T523
Test name
Test status
Simulation time 2228695751 ps
CPU time 49.31 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:49:24 PM PST 23
Peak memory 198844 kb
Host smart-07274b7d-d4f9-4305-839a-283de9cb0cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817057730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.817057730
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1987503761
Short name T398
Test name
Test status
Simulation time 98016436 ps
CPU time 3.89 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:47:15 PM PST 23
Peak memory 198752 kb
Host smart-a14c1710-9024-4945-b463-a41f62af01cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987503761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1987503761
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2653370623
Short name T357
Test name
Test status
Simulation time 1719484462 ps
CPU time 41.22 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 12:48:08 PM PST 23
Peak memory 198720 kb
Host smart-535e1de0-fbcf-4efe-99e4-699216520167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653370623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2653370623
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3021915995
Short name T622
Test name
Test status
Simulation time 138230055570 ps
CPU time 103.24 seconds
Started Dec 20 12:46:35 PM PST 23
Finished Dec 20 12:48:48 PM PST 23
Peak memory 198928 kb
Host smart-93504397-54e4-4496-a413-f6041328fbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021915995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3021915995
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1089130165
Short name T386
Test name
Test status
Simulation time 187229113 ps
CPU time 3.97 seconds
Started Dec 20 12:46:34 PM PST 23
Finished Dec 20 12:47:04 PM PST 23
Peak memory 198748 kb
Host smart-1136e766-6dd5-479d-af7b-2fe46a795da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089130165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1089130165
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2497939741
Short name T31
Test name
Test status
Simulation time 75780252003 ps
CPU time 989.04 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 01:03:44 PM PST 23
Peak memory 215232 kb
Host smart-7538916f-e56c-4ae5-9443-e857d707dbf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497939741 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2497939741
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.1781002864
Short name T308
Test name
Test status
Simulation time 83151364381 ps
CPU time 3331.22 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 01:43:03 PM PST 23
Peak memory 236396 kb
Host smart-39db2365-f657-4a00-9c42-5d151d77e033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781002864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.1781002864
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2116334968
Short name T651
Test name
Test status
Simulation time 42573637 ps
CPU time 0.94 seconds
Started Dec 20 12:46:45 PM PST 23
Finished Dec 20 12:47:21 PM PST 23
Peak memory 195980 kb
Host smart-0cd35f68-4bea-48db-8b07-8cb560c24737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116334968 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2116334968
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1472226559
Short name T571
Test name
Test status
Simulation time 124433856707 ps
CPU time 440.16 seconds
Started Dec 20 12:45:39 PM PST 23
Finished Dec 20 12:52:59 PM PST 23
Peak memory 198836 kb
Host smart-3e041b00-9523-4888-8a2e-dfe50bcf4832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472226559 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.1472226559
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2540276942
Short name T345
Test name
Test status
Simulation time 2901200349 ps
CPU time 65.34 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:48:14 PM PST 23
Peak memory 198816 kb
Host smart-c6bed00e-5092-45b4-8eb8-a19c403d3997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540276942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2540276942
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4036559598
Short name T495
Test name
Test status
Simulation time 18548868 ps
CPU time 0.54 seconds
Started Dec 20 12:47:18 PM PST 23
Finished Dec 20 12:48:12 PM PST 23
Peak memory 193168 kb
Host smart-201e019f-ea3b-48ad-9508-7cf599d13190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036559598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4036559598
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4124341461
Short name T382
Test name
Test status
Simulation time 3485037866 ps
CPU time 24.12 seconds
Started Dec 20 12:46:50 PM PST 23
Finished Dec 20 12:47:52 PM PST 23
Peak memory 215212 kb
Host smart-11aca4c4-bd54-4a29-8e56-de4c2d05c881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124341461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4124341461
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4160732042
Short name T668
Test name
Test status
Simulation time 3745025257 ps
CPU time 50.11 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 12:49:19 PM PST 23
Peak memory 198860 kb
Host smart-7ff1dd61-3d68-402e-b5f6-8127e1030377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160732042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4160732042
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3694062690
Short name T556
Test name
Test status
Simulation time 2038339493 ps
CPU time 100.58 seconds
Started Dec 20 12:46:51 PM PST 23
Finished Dec 20 12:49:10 PM PST 23
Peak memory 198792 kb
Host smart-0fe56a8d-f5cd-421b-aba2-bdae02b4fcfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694062690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3694062690
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3159848573
Short name T731
Test name
Test status
Simulation time 721270071 ps
CPU time 17.65 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:48:07 PM PST 23
Peak memory 198736 kb
Host smart-71e6696a-0465-42e6-af10-8a363bad246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159848573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3159848573
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1527957997
Short name T309
Test name
Test status
Simulation time 713662197 ps
CPU time 5.04 seconds
Started Dec 20 12:46:43 PM PST 23
Finished Dec 20 12:47:22 PM PST 23
Peak memory 198744 kb
Host smart-6e936dab-a0c7-4ba8-b497-4473e8780d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527957997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1527957997
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2716549587
Short name T490
Test name
Test status
Simulation time 693443748 ps
CPU time 4.43 seconds
Started Dec 20 12:46:49 PM PST 23
Finished Dec 20 12:47:33 PM PST 23
Peak memory 198628 kb
Host smart-db3ce140-5e65-4e17-b1d4-a87ac60977a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716549587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2716549587
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1443173050
Short name T450
Test name
Test status
Simulation time 174498783137 ps
CPU time 1306.14 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 01:09:53 PM PST 23
Peak memory 198900 kb
Host smart-a63853c8-0498-4615-8164-faeff7003101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443173050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1443173050
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.318665737
Short name T276
Test name
Test status
Simulation time 82692523789 ps
CPU time 780.42 seconds
Started Dec 20 12:46:53 PM PST 23
Finished Dec 20 01:00:34 PM PST 23
Peak memory 239980 kb
Host smart-f47ed921-5d1a-4c17-9892-888858273eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318665737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.318665737
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2290763769
Short name T405
Test name
Test status
Simulation time 119593323 ps
CPU time 1.16 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:47:57 PM PST 23
Peak memory 197416 kb
Host smart-7894473e-d25a-4f0e-8f73-9a4dc1d5c575
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290763769 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2290763769
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1498460863
Short name T692
Test name
Test status
Simulation time 49904022586 ps
CPU time 375.52 seconds
Started Dec 20 12:47:00 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 198868 kb
Host smart-7fabbf48-b2f5-4a6f-94a0-067a52d67d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498460863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.1498460863
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.264550137
Short name T611
Test name
Test status
Simulation time 668760501 ps
CPU time 29.89 seconds
Started Dec 20 12:46:48 PM PST 23
Finished Dec 20 12:47:54 PM PST 23
Peak memory 198712 kb
Host smart-90238ebf-f46e-4527-bd57-1b58df028253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264550137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.264550137
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1694021786
Short name T259
Test name
Test status
Simulation time 14669983 ps
CPU time 0.55 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:48:11 PM PST 23
Peak memory 192960 kb
Host smart-5c0f2899-6f33-461f-a22d-af7c7b3c7cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694021786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1694021786
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.171171567
Short name T252
Test name
Test status
Simulation time 6617509745 ps
CPU time 40.49 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:48:39 PM PST 23
Peak memory 207052 kb
Host smart-6b4f7431-534f-41fb-8d75-c7449c62c4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171171567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.171171567
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1435931211
Short name T765
Test name
Test status
Simulation time 24349174912 ps
CPU time 38.16 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:48:56 PM PST 23
Peak memory 198872 kb
Host smart-f7e5dd96-5844-4a6d-922c-d10b9d279321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435931211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1435931211
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3806670022
Short name T551
Test name
Test status
Simulation time 11823851709 ps
CPU time 87.3 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:49:28 PM PST 23
Peak memory 198436 kb
Host smart-15fa9da8-dc05-446b-8193-becbc4d31f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806670022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3806670022
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3406991323
Short name T712
Test name
Test status
Simulation time 5738829551 ps
CPU time 67.02 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:49:06 PM PST 23
Peak memory 198896 kb
Host smart-891af7ad-d5e6-4d84-b17d-f803cb25b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406991323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3406991323
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1193113325
Short name T360
Test name
Test status
Simulation time 4190324614 ps
CPU time 70.58 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:49:03 PM PST 23
Peak memory 198944 kb
Host smart-c3680cca-a549-4030-a7a0-1df660d9ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193113325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1193113325
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.134365972
Short name T376
Test name
Test status
Simulation time 343022526 ps
CPU time 2.65 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:02 PM PST 23
Peak memory 198708 kb
Host smart-43ed5b02-3573-47f8-8d90-e9719bc9be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134365972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.134365972
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.880857310
Short name T694
Test name
Test status
Simulation time 14167412938 ps
CPU time 83.23 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:49:27 PM PST 23
Peak memory 198808 kb
Host smart-70ed59f4-19b0-4f99-8016-0b00bd460c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880857310 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.880857310
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.664385893
Short name T667
Test name
Test status
Simulation time 19304259436 ps
CPU time 770.92 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 01:01:29 PM PST 23
Peak memory 207280 kb
Host smart-efb78c8b-bc2d-45c3-a1f3-7dd700e6faf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664385893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.664385893
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3083393332
Short name T570
Test name
Test status
Simulation time 183668912 ps
CPU time 1.04 seconds
Started Dec 20 12:47:02 PM PST 23
Finished Dec 20 12:47:44 PM PST 23
Peak memory 197192 kb
Host smart-8f988c79-e97b-4872-b4dc-c5dce7e59682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083393332 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3083393332
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2636626555
Short name T728
Test name
Test status
Simulation time 12553526826 ps
CPU time 76.54 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:49:08 PM PST 23
Peak memory 198816 kb
Host smart-ecda0957-045b-4373-9591-13821d1331d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636626555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2636626555
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2091125282
Short name T380
Test name
Test status
Simulation time 45778139 ps
CPU time 0.54 seconds
Started Dec 20 12:42:05 PM PST 23
Finished Dec 20 12:43:05 PM PST 23
Peak memory 193100 kb
Host smart-876fcdb4-bc1e-4ccc-8ac5-f1c78f300ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091125282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2091125282
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3538429101
Short name T642
Test name
Test status
Simulation time 1241458556 ps
CPU time 2.16 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 198544 kb
Host smart-55e78641-bf9d-4701-9988-b7d3828cc064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538429101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3538429101
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.828736068
Short name T640
Test name
Test status
Simulation time 1497136721 ps
CPU time 31.28 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 198764 kb
Host smart-e182abca-aa33-4594-87d2-64bccd4e67dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828736068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.828736068
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.229734627
Short name T392
Test name
Test status
Simulation time 9658860492 ps
CPU time 77.58 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:44:13 PM PST 23
Peak memory 198924 kb
Host smart-1e9279d8-870e-40d4-bbf0-65984d67fae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229734627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.229734627
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3974248173
Short name T57
Test name
Test status
Simulation time 9597661854 ps
CPU time 26.5 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:43:24 PM PST 23
Peak memory 198776 kb
Host smart-a240a06d-3a6b-452f-ae7a-9e88c0ee9228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974248173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3974248173
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3140940294
Short name T559
Test name
Test status
Simulation time 20009959759 ps
CPU time 83.83 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:44:25 PM PST 23
Peak memory 198924 kb
Host smart-85515f9b-5522-42f8-a0d9-11ba4a8788b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140940294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3140940294
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1359569153
Short name T615
Test name
Test status
Simulation time 1738304582 ps
CPU time 4.61 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 198704 kb
Host smart-02236e07-19a0-47fa-9133-e8fa1bdda01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359569153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1359569153
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.621775432
Short name T220
Test name
Test status
Simulation time 79348586538 ps
CPU time 991.67 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:59:32 PM PST 23
Peak memory 198908 kb
Host smart-5656989e-40bd-435b-be99-c33a5c17916c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621775432 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.621775432
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.316625361
Short name T91
Test name
Test status
Simulation time 428571994066 ps
CPU time 1878.48 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 01:14:19 PM PST 23
Peak memory 239924 kb
Host smart-fcaf700c-69af-41e4-98c8-c15595e14d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316625361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.316625361
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.525031361
Short name T780
Test name
Test status
Simulation time 54422521 ps
CPU time 1 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:42:56 PM PST 23
Peak memory 196380 kb
Host smart-ecfb2591-42d4-4d08-a53b-e2595c59d5d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525031361 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.525031361
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2878285059
Short name T233
Test name
Test status
Simulation time 28236049118 ps
CPU time 430.34 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:50:11 PM PST 23
Peak memory 198764 kb
Host smart-62558f20-96a3-49b8-b4ab-07850ccd3566
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878285059 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2878285059
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4103106447
Short name T126
Test name
Test status
Simulation time 39014583947 ps
CPU time 49.99 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 198648 kb
Host smart-e3f6dd15-daed-43a5-8fb8-2822738bb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103106447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4103106447
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.446852425
Short name T331
Test name
Test status
Simulation time 96860436113 ps
CPU time 456.72 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 247644 kb
Host smart-0ab064d6-499d-45f9-95af-b13aa88f2550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446852425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.446852425
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3075123287
Short name T705
Test name
Test status
Simulation time 110375762785 ps
CPU time 966.7 seconds
Started Dec 20 12:47:15 PM PST 23
Finished Dec 20 01:04:12 PM PST 23
Peak memory 240012 kb
Host smart-1f76e073-0556-48e0-9072-40cfa01117f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075123287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.3075123287
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.4233461177
Short name T518
Test name
Test status
Simulation time 244398149788 ps
CPU time 1023.91 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 01:04:12 PM PST 23
Peak memory 228360 kb
Host smart-183a5c89-a88a-4761-93a0-81ca14588a74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233461177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.4233461177
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.541225441
Short name T189
Test name
Test status
Simulation time 54551221016 ps
CPU time 953.27 seconds
Started Dec 20 12:46:41 PM PST 23
Finished Dec 20 01:03:08 PM PST 23
Peak memory 215332 kb
Host smart-d566dcbf-0e72-4137-9f6e-e26ff009c01c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541225441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.541225441
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.732654779
Short name T471
Test name
Test status
Simulation time 23181219511 ps
CPU time 340.94 seconds
Started Dec 20 12:46:31 PM PST 23
Finished Dec 20 12:52:33 PM PST 23
Peak memory 215344 kb
Host smart-8f8b2ba9-0d4c-49e2-912c-e74cff0f0c07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732654779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.732654779
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.3235944667
Short name T301
Test name
Test status
Simulation time 398915677916 ps
CPU time 499.02 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 247848 kb
Host smart-00c0ca33-c158-4770-a8ea-57a90c38a431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235944667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.3235944667
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3532278002
Short name T284
Test name
Test status
Simulation time 66196743209 ps
CPU time 446.12 seconds
Started Dec 20 12:46:38 PM PST 23
Finished Dec 20 12:54:36 PM PST 23
Peak memory 223432 kb
Host smart-206e87fc-2ae1-4b63-9eb5-12d31b92f764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532278002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.3532278002
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3412868990
Short name T337
Test name
Test status
Simulation time 57084565 ps
CPU time 0.56 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:43:05 PM PST 23
Peak memory 192908 kb
Host smart-2192e34e-fc87-461e-a5ea-3acbde47b691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412868990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3412868990
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1071977388
Short name T564
Test name
Test status
Simulation time 468854855 ps
CPU time 14.27 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:43:14 PM PST 23
Peak memory 206928 kb
Host smart-c93b251b-b6d8-4b89-84ff-0b91c5dcb9d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071977388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1071977388
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1251689651
Short name T725
Test name
Test status
Simulation time 3190285182 ps
CPU time 30.17 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 198620 kb
Host smart-8b5e67bc-e55d-4f8b-9172-f33d9791fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251689651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1251689651
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2077735002
Short name T776
Test name
Test status
Simulation time 3119202209 ps
CPU time 77.8 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:44:15 PM PST 23
Peak memory 198896 kb
Host smart-2739a973-1840-415e-bab5-0636280461e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077735002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2077735002
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3915804311
Short name T767
Test name
Test status
Simulation time 2540165777 ps
CPU time 117.95 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:44:56 PM PST 23
Peak memory 198852 kb
Host smart-c8aeb694-1189-474f-9fc0-8573dca18f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915804311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3915804311
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3100519754
Short name T327
Test name
Test status
Simulation time 787419414 ps
CPU time 40.26 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:43:38 PM PST 23
Peak memory 198704 kb
Host smart-b66d8df2-72c5-468d-ae33-ef4746b0a5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100519754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3100519754
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.150692748
Short name T181
Test name
Test status
Simulation time 57839857 ps
CPU time 1.05 seconds
Started Dec 20 12:42:05 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 196836 kb
Host smart-3af229ad-2d13-43f7-b6b3-cd349cb28dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150692748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.150692748
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2416188151
Short name T514
Test name
Test status
Simulation time 24228077978 ps
CPU time 269.64 seconds
Started Dec 20 12:41:59 PM PST 23
Finished Dec 20 12:47:29 PM PST 23
Peak memory 198888 kb
Host smart-8defc4ae-27b7-4a94-b808-468396a4c618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416188151 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2416188151
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1013539449
Short name T746
Test name
Test status
Simulation time 291776249267 ps
CPU time 1299.84 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 01:04:36 PM PST 23
Peak memory 215240 kb
Host smart-244d918b-dd0b-4b85-84ed-e6fb0a18e079
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013539449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1013539449
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3818517083
Short name T289
Test name
Test status
Simulation time 151986877 ps
CPU time 0.88 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:43:05 PM PST 23
Peak memory 195536 kb
Host smart-41e2b70e-16d8-4117-bce4-ebb2b932822f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818517083 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3818517083
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2539619435
Short name T240
Test name
Test status
Simulation time 2086674559 ps
CPU time 34.58 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 198728 kb
Host smart-4e33efd4-4e8a-4376-936d-3dc1f1a340d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539619435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2539619435
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1390349582
Short name T807
Test name
Test status
Simulation time 331931473948 ps
CPU time 2116.25 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 01:22:48 PM PST 23
Peak memory 257360 kb
Host smart-cab58ef5-8fe2-4ee7-9b57-cf94c4e3f5c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390349582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.1390349582
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.4174148058
Short name T374
Test name
Test status
Simulation time 90308375363 ps
CPU time 3196.3 seconds
Started Dec 20 12:46:36 PM PST 23
Finished Dec 20 01:40:21 PM PST 23
Peak memory 263552 kb
Host smart-f136a2ca-74f2-431d-aa96-f2cb0fa57d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174148058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.4174148058
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.3168625476
Short name T805
Test name
Test status
Simulation time 405718116298 ps
CPU time 1064.73 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 01:04:56 PM PST 23
Peak memory 244956 kb
Host smart-09144066-fb02-40c7-830e-f8fad9209a2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168625476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.3168625476
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.943777614
Short name T653
Test name
Test status
Simulation time 24033984899 ps
CPU time 344.66 seconds
Started Dec 20 12:46:52 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 215096 kb
Host smart-2c31da84-d001-478f-8625-46c95b87dd32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943777614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.943777614
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.4241721647
Short name T219
Test name
Test status
Simulation time 17754293416 ps
CPU time 289.05 seconds
Started Dec 20 12:46:39 PM PST 23
Finished Dec 20 12:52:11 PM PST 23
Peak memory 207152 kb
Host smart-b7549e23-a677-4cb6-ba65-e343746e42c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241721647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.4241721647
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3640081257
Short name T788
Test name
Test status
Simulation time 15803333654 ps
CPU time 663.96 seconds
Started Dec 20 12:46:42 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 215296 kb
Host smart-1bc14fcd-2acb-42f1-847c-588320cde57d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640081257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3640081257
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.3171049061
Short name T320
Test name
Test status
Simulation time 126841415739 ps
CPU time 1109.15 seconds
Started Dec 20 12:46:40 PM PST 23
Finished Dec 20 01:05:41 PM PST 23
Peak memory 239868 kb
Host smart-67036e3e-5e0d-4bc4-aa15-3bab835de4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171049061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.3171049061
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.3483825666
Short name T475
Test name
Test status
Simulation time 37060095923 ps
CPU time 841.34 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 01:01:09 PM PST 23
Peak memory 227480 kb
Host smart-d7edfe48-5d17-47b3-bb41-110c904e22aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483825666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.3483825666
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.1811744294
Short name T771
Test name
Test status
Simulation time 53123421911 ps
CPU time 890.35 seconds
Started Dec 20 12:46:45 PM PST 23
Finished Dec 20 01:02:11 PM PST 23
Peak memory 247380 kb
Host smart-a2d1fa59-a09a-4272-9930-bc7c23bc712e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811744294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.1811744294
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1697273363
Short name T693
Test name
Test status
Simulation time 11921244 ps
CPU time 0.55 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:01 PM PST 23
Peak memory 193092 kb
Host smart-9516823a-d06a-41e1-9fbe-76bdde0aa93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697273363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1697273363
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4270041015
Short name T489
Test name
Test status
Simulation time 1098692314 ps
CPU time 30.86 seconds
Started Dec 20 12:42:00 PM PST 23
Finished Dec 20 12:43:32 PM PST 23
Peak memory 207000 kb
Host smart-69d471a8-b016-422c-acbb-a9cb980a8bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270041015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4270041015
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1738267596
Short name T577
Test name
Test status
Simulation time 1156898736 ps
CPU time 20.43 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:28 PM PST 23
Peak memory 198484 kb
Host smart-5da8456b-1277-47ea-9a7b-707dd70932ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738267596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1738267596
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3847582918
Short name T314
Test name
Test status
Simulation time 8649901218 ps
CPU time 107.18 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:44:49 PM PST 23
Peak memory 198864 kb
Host smart-2075310b-197b-4b01-a2c8-9e981cd2f1f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847582918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3847582918
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1938106864
Short name T513
Test name
Test status
Simulation time 29409076166 ps
CPU time 115.4 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:45:01 PM PST 23
Peak memory 198940 kb
Host smart-0f5804cd-7d6a-420f-8230-5788c985180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938106864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1938106864
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2196944782
Short name T404
Test name
Test status
Simulation time 836596333 ps
CPU time 9.63 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:43:08 PM PST 23
Peak memory 198732 kb
Host smart-ebd025ab-9215-4b87-bdaa-fae169d20f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196944782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2196944782
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1759426513
Short name T685
Test name
Test status
Simulation time 1324333543 ps
CPU time 4.21 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 198596 kb
Host smart-14b15d64-2da0-4ee2-8250-c7c01b585bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759426513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1759426513
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3435184758
Short name T365
Test name
Test status
Simulation time 298024430150 ps
CPU time 1182.45 seconds
Started Dec 20 12:41:56 PM PST 23
Finished Dec 20 01:02:39 PM PST 23
Peak memory 231696 kb
Host smart-6b28e057-f5be-4b28-8641-0f77b0e3cc15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435184758 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3435184758
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.433070211
Short name T129
Test name
Test status
Simulation time 199033421245 ps
CPU time 775.82 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 231396 kb
Host smart-5cb20d9a-6831-4a43-8bbd-18b6dd16a77b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433070211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.433070211
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3356747170
Short name T273
Test name
Test status
Simulation time 29772243 ps
CPU time 1.02 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 197400 kb
Host smart-5d2771ca-6f05-425b-9d5d-2ba36d2481f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356747170 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3356747170
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.614952738
Short name T706
Test name
Test status
Simulation time 64255786629 ps
CPU time 361.31 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:49:05 PM PST 23
Peak memory 198612 kb
Host smart-ff70122c-d126-434c-917b-dcf6170791ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614952738 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.614952738
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3774131887
Short name T719
Test name
Test status
Simulation time 6630180236 ps
CPU time 26.05 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:34 PM PST 23
Peak memory 198948 kb
Host smart-281840db-2260-48d3-9db4-2dfa2e08c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774131887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3774131887
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2557980125
Short name T600
Test name
Test status
Simulation time 66822610018 ps
CPU time 1303.96 seconds
Started Dec 20 12:46:37 PM PST 23
Finished Dec 20 01:08:50 PM PST 23
Peak memory 248056 kb
Host smart-86e42a5b-174c-4773-a0b0-1e9a039c7c03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557980125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2557980125
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3297896797
Short name T37
Test name
Test status
Simulation time 30025207666 ps
CPU time 1339.26 seconds
Started Dec 20 12:46:42 PM PST 23
Finished Dec 20 01:09:35 PM PST 23
Peak memory 247100 kb
Host smart-8373ab1a-d4fc-4a88-9d0d-0a2224bc1605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297896797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3297896797
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.2597995241
Short name T110
Test name
Test status
Simulation time 82188670989 ps
CPU time 860.87 seconds
Started Dec 20 12:46:43 PM PST 23
Finished Dec 20 01:01:37 PM PST 23
Peak memory 243576 kb
Host smart-832febd6-d4ac-4fd2-bda3-7282c130bc5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597995241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.2597995241
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2956279807
Short name T4
Test name
Test status
Simulation time 101060160906 ps
CPU time 1413.11 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 01:11:17 PM PST 23
Peak memory 248088 kb
Host smart-ae68fe8b-8bd4-46d7-9c58-7ecb2e9bcdeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956279807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2956279807
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.4157574716
Short name T708
Test name
Test status
Simulation time 58922032220 ps
CPU time 797.2 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 01:01:02 PM PST 23
Peak memory 215348 kb
Host smart-330b4bc9-d60d-4a52-93f3-d2daa5f0bbc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157574716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.4157574716
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.1724761264
Short name T624
Test name
Test status
Simulation time 462432330505 ps
CPU time 1452.96 seconds
Started Dec 20 12:46:47 PM PST 23
Finished Dec 20 01:11:36 PM PST 23
Peak memory 215340 kb
Host smart-cb90ca1a-df4d-439b-bc8c-0a264c38e05d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724761264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.1724761264
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.589358400
Short name T684
Test name
Test status
Simulation time 508074854504 ps
CPU time 4165.97 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 01:58:03 PM PST 23
Peak memory 263628 kb
Host smart-dd9c0b5c-9bb4-457f-b87f-c41f402293f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589358400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.589358400
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3435464167
Short name T699
Test name
Test status
Simulation time 32429966390 ps
CPU time 420.95 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 214516 kb
Host smart-f2f0aac7-a881-4489-8d2c-bb68f0391a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435464167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3435464167
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1943174365
Short name T713
Test name
Test status
Simulation time 241760778251 ps
CPU time 3102.81 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 01:39:54 PM PST 23
Peak memory 236928 kb
Host smart-2a4754c7-222f-40e8-aa49-a838b987bcb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943174365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.1943174365
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.3893046626
Short name T539
Test name
Test status
Simulation time 69973232300 ps
CPU time 528.66 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 242004 kb
Host smart-3153a820-0ddc-4f8e-9f19-f333c1574a89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893046626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.3893046626
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2309125096
Short name T784
Test name
Test status
Simulation time 23535202 ps
CPU time 0.56 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 193164 kb
Host smart-232efa16-69fb-4ad1-a4f3-e7dbcd9fd835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309125096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2309125096
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2433135328
Short name T510
Test name
Test status
Simulation time 13986685791 ps
CPU time 58.08 seconds
Started Dec 20 12:41:58 PM PST 23
Finished Dec 20 12:43:57 PM PST 23
Peak memory 233440 kb
Host smart-028eb981-643d-4840-8637-d16e6a1de1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433135328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2433135328
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3468936998
Short name T849
Test name
Test status
Simulation time 3571892231 ps
CPU time 59.75 seconds
Started Dec 20 12:41:54 PM PST 23
Finished Dec 20 12:43:54 PM PST 23
Peak memory 198924 kb
Host smart-344ea9f8-6ff1-4953-bb79-f609cbdb8c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468936998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3468936998
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1470610397
Short name T682
Test name
Test status
Simulation time 35506757 ps
CPU time 0.62 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 194036 kb
Host smart-1ab55f41-6299-49d9-98dd-94b63f346c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470610397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1470610397
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2765079571
Short name T330
Test name
Test status
Simulation time 2628141043 ps
CPU time 60.66 seconds
Started Dec 20 12:42:04 PM PST 23
Finished Dec 20 12:44:05 PM PST 23
Peak memory 198852 kb
Host smart-1d4cadca-eb57-47e7-b1b8-8fe1885e9c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765079571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2765079571
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3073096124
Short name T195
Test name
Test status
Simulation time 77652118 ps
CPU time 3.98 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:43:01 PM PST 23
Peak memory 198832 kb
Host smart-129d7381-972d-4566-b99a-992e767711a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073096124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3073096124
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1256680839
Short name T334
Test name
Test status
Simulation time 331001721 ps
CPU time 3.38 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 198792 kb
Host smart-db719c20-1bde-42cf-8cd3-27aa2bf9c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256680839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1256680839
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3689116172
Short name T3
Test name
Test status
Simulation time 220853324681 ps
CPU time 1298.46 seconds
Started Dec 20 12:42:08 PM PST 23
Finished Dec 20 01:04:46 PM PST 23
Peak memory 210064 kb
Host smart-6033cd01-495b-48fc-8be4-beb5b686f6d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689116172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3689116172
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2038315949
Short name T630
Test name
Test status
Simulation time 115561757625 ps
CPU time 1672.84 seconds
Started Dec 20 12:42:07 PM PST 23
Finished Dec 20 01:10:59 PM PST 23
Peak memory 248104 kb
Host smart-a6b485a2-0344-4767-a9c5-5a812a830c42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038315949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2038315949
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2418369993
Short name T500
Test name
Test status
Simulation time 51985720 ps
CPU time 0.9 seconds
Started Dec 20 12:42:05 PM PST 23
Finished Dec 20 12:43:05 PM PST 23
Peak memory 195868 kb
Host smart-bae3da36-3e42-4b6b-8b9d-967a70703e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418369993 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2418369993
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3454448641
Short name T770
Test name
Test status
Simulation time 114218707320 ps
CPU time 425.79 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:50:17 PM PST 23
Peak memory 198920 kb
Host smart-1debc584-7d97-4334-93c4-70da8438a313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454448641 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.3454448641
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2720766618
Short name T447
Test name
Test status
Simulation time 2266266192 ps
CPU time 50.83 seconds
Started Dec 20 12:42:18 PM PST 23
Finished Dec 20 12:44:04 PM PST 23
Peak memory 198832 kb
Host smart-2ec5ba66-2ebb-4da9-94db-37ff21e7eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720766618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2720766618
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.959159964
Short name T300
Test name
Test status
Simulation time 27783856337 ps
CPU time 852.65 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 01:02:01 PM PST 23
Peak memory 198968 kb
Host smart-2b4e5086-36c3-4ea9-9846-06ffabc0df9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959159964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.959159964
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3645196869
Short name T793
Test name
Test status
Simulation time 76868309409 ps
CPU time 687.86 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:59:24 PM PST 23
Peak memory 209188 kb
Host smart-0ea9f409-9376-4a76-ae02-de38d7e25d28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645196869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.3645196869
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.3123891062
Short name T55
Test name
Test status
Simulation time 302081790301 ps
CPU time 1740.81 seconds
Started Dec 20 12:46:58 PM PST 23
Finished Dec 20 01:16:40 PM PST 23
Peak memory 223612 kb
Host smart-d060218b-c342-4f51-8bd3-5f9e8aa4b7e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123891062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.3123891062
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.4073623246
Short name T228
Test name
Test status
Simulation time 357418510136 ps
CPU time 874.39 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 01:02:18 PM PST 23
Peak memory 222592 kb
Host smart-5fafa37c-a57b-4049-ab94-8d7c311326b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073623246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.4073623246
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2687239839
Short name T506
Test name
Test status
Simulation time 146154859024 ps
CPU time 1664.08 seconds
Started Dec 20 12:46:51 PM PST 23
Finished Dec 20 01:15:21 PM PST 23
Peak memory 248132 kb
Host smart-93b53a4f-8d1e-4a92-bed1-716ade0d3332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687239839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.2687239839
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.73826063
Short name T356
Test name
Test status
Simulation time 75922806080 ps
CPU time 865.75 seconds
Started Dec 20 12:47:31 PM PST 23
Finished Dec 20 01:03:16 PM PST 23
Peak memory 224544 kb
Host smart-bfeca078-87fe-4681-a4fa-07bbec1280c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73826063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.73826063
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2230392193
Short name T118
Test name
Test status
Simulation time 220939774581 ps
CPU time 3465.61 seconds
Started Dec 20 12:46:56 PM PST 23
Finished Dec 20 01:45:23 PM PST 23
Peak memory 248124 kb
Host smart-dbfd67b6-2f1e-4aab-b24a-06dff745c0cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230392193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.2230392193
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.800938915
Short name T722
Test name
Test status
Simulation time 76914578848 ps
CPU time 3522.35 seconds
Started Dec 20 12:47:27 PM PST 23
Finished Dec 20 01:47:21 PM PST 23
Peak memory 262176 kb
Host smart-ebad4ed7-126d-4b18-9ac3-559dc0f3f629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800938915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.800938915
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.1742231629
Short name T710
Test name
Test status
Simulation time 161907212035 ps
CPU time 3579.3 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 01:47:31 PM PST 23
Peak memory 256264 kb
Host smart-dfbc1bbf-b481-4fbf-ad1b-f0f92b158348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742231629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.1742231629
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2295394657
Short name T438
Test name
Test status
Simulation time 14667847 ps
CPU time 0.58 seconds
Started Dec 20 12:42:08 PM PST 23
Finished Dec 20 12:43:08 PM PST 23
Peak memory 193180 kb
Host smart-ae4ac30f-aff6-4295-882f-6ade904703aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295394657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2295394657
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.33882948
Short name T783
Test name
Test status
Simulation time 649243258 ps
CPU time 20.97 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 215092 kb
Host smart-2dd9eb9f-2293-4b8d-841a-02b50001ada8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33882948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.33882948
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.438364849
Short name T755
Test name
Test status
Simulation time 425661907 ps
CPU time 4.23 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 198788 kb
Host smart-346fadfb-c8a4-477c-85e7-372b8c4c8689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438364849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.438364849
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2609615918
Short name T521
Test name
Test status
Simulation time 2977153588 ps
CPU time 76.13 seconds
Started Dec 20 12:42:14 PM PST 23
Finished Dec 20 12:44:27 PM PST 23
Peak memory 198900 kb
Host smart-576c5f9f-b726-4380-ae54-2b7d32f5f3a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609615918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2609615918
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4129176326
Short name T318
Test name
Test status
Simulation time 8830110168 ps
CPU time 94.65 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 12:44:45 PM PST 23
Peak memory 198716 kb
Host smart-b13f111a-a6e7-48c8-bcb7-61318b41119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129176326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4129176326
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2264374065
Short name T663
Test name
Test status
Simulation time 10977788254 ps
CPU time 37.11 seconds
Started Dec 20 12:42:11 PM PST 23
Finished Dec 20 12:43:46 PM PST 23
Peak memory 198912 kb
Host smart-3dab1167-7da5-4dcf-b4ca-5954aa885290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264374065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2264374065
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1038820873
Short name T557
Test name
Test status
Simulation time 240522710 ps
CPU time 2.8 seconds
Started Dec 20 12:42:09 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 198616 kb
Host smart-e5120948-141c-47c0-9333-e9b121509f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038820873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1038820873
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3250776451
Short name T122
Test name
Test status
Simulation time 267712830648 ps
CPU time 1500.12 seconds
Started Dec 20 12:42:12 PM PST 23
Finished Dec 20 01:08:11 PM PST 23
Peak memory 214636 kb
Host smart-3703d0f2-89db-4425-a747-0f6deac24312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250776451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3250776451
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2693202583
Short name T516
Test name
Test status
Simulation time 55537114462 ps
CPU time 536.73 seconds
Started Dec 20 12:42:13 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 238416 kb
Host smart-41b8eb74-3171-4ecb-843f-aa18f0e1d523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693202583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2693202583
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3848232703
Short name T576
Test name
Test status
Simulation time 134342544 ps
CPU time 0.88 seconds
Started Dec 20 12:42:10 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 196616 kb
Host smart-e0d557d5-6985-482d-adf5-276aabeeccd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848232703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3848232703
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.359638098
Short name T448
Test name
Test status
Simulation time 32644492013 ps
CPU time 374.36 seconds
Started Dec 20 12:42:08 PM PST 23
Finished Dec 20 12:49:22 PM PST 23
Peak memory 198736 kb
Host smart-3950d0f7-fe9a-4716-8eb7-8022234d1afd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359638098 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.359638098
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1998972251
Short name T648
Test name
Test status
Simulation time 4477188139 ps
CPU time 46.84 seconds
Started Dec 20 12:42:06 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 198852 kb
Host smart-3de3c4b7-8477-454d-8745-f6b0aa72ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998972251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1998972251
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1712699398
Short name T751
Test name
Test status
Simulation time 230498759670 ps
CPU time 787.6 seconds
Started Dec 20 12:47:46 PM PST 23
Finished Dec 20 01:02:17 PM PST 23
Peak memory 229060 kb
Host smart-a75a7b63-5182-4285-95f5-084ad12b28ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712699398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.1712699398
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.2025065073
Short name T503
Test name
Test status
Simulation time 95316305505 ps
CPU time 1517.56 seconds
Started Dec 20 12:47:03 PM PST 23
Finished Dec 20 01:13:04 PM PST 23
Peak memory 239956 kb
Host smart-a74bb20a-62f5-432e-9deb-735fcb3bd5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025065073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.2025065073
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1431997215
Short name T592
Test name
Test status
Simulation time 319740325647 ps
CPU time 1134.28 seconds
Started Dec 20 12:47:29 PM PST 23
Finished Dec 20 01:07:40 PM PST 23
Peak memory 247848 kb
Host smart-5136cfcb-59b1-4b09-8029-5873593c8e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431997215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.1431997215
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.3954492410
Short name T372
Test name
Test status
Simulation time 120066545827 ps
CPU time 619.33 seconds
Started Dec 20 12:47:33 PM PST 23
Finished Dec 20 12:59:12 PM PST 23
Peak memory 215120 kb
Host smart-eceb4ca4-1007-4ee8-b39b-9336ac499f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954492410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.3954492410
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.4159843296
Short name T839
Test name
Test status
Simulation time 38613993492 ps
CPU time 168.87 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:51:00 PM PST 23
Peak memory 228372 kb
Host smart-9dc5d639-faf6-4426-a930-b20a89b3d68c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159843296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.4159843296
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.4167037959
Short name T647
Test name
Test status
Simulation time 57695829053 ps
CPU time 780.69 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 01:01:04 PM PST 23
Peak memory 231668 kb
Host smart-8a95331f-eadd-42eb-b03a-65a61d49c4ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167037959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.4167037959
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.535428790
Short name T547
Test name
Test status
Simulation time 50899669481 ps
CPU time 681.51 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:59:26 PM PST 23
Peak memory 246892 kb
Host smart-c621e7e6-a1c4-4dbc-bfa0-bae83e7eadf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535428790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.535428790
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.3260765931
Short name T550
Test name
Test status
Simulation time 341694458806 ps
CPU time 1221.63 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 01:08:31 PM PST 23
Peak memory 223364 kb
Host smart-44c24303-b938-4bac-84d5-4ee020857428
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260765931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.3260765931
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.512556282
Short name T127
Test name
Test status
Simulation time 112795095139 ps
CPU time 378.19 seconds
Started Dec 20 12:47:34 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 239636 kb
Host smart-c453d840-2e5b-4c81-8e90-76998506b783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512556282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.512556282
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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