Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	101786355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115058373

1

T11

625

T12

26

T13

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85423859	1			T11	183		T12	29		T13	10
values[0x0]	61012076	1			T11	224		T12	11		T13	4
values[0x1]	70408793	1			T11	279		T12	18		T13	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74393397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142451331

1

T11

657

T12

29

T13

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1181941	1			T11	9		T15	1		T16	5
valid_sources[0x01]	834934	1			T15	1		T16	2		T18	762
valid_sources[0x02]	832668	1			T14	2		T15	3		T16	3
valid_sources[0x03]	826939	1			T14	1		T16	6		T18	819
valid_sources[0x04]	842692	1			T11	1		T15	1		T16	3
valid_sources[0x05]	835579	1			T11	4		T14	1		T15	1
valid_sources[0x06]	813228	1			T16	4		T18	761		T19	1
valid_sources[0x07]	826189	1			T14	4		T16	3		T17	1
valid_sources[0x08]	796413	1			T11	1		T14	1		T15	1
valid_sources[0x09]	826613	1			T12	1		T14	1		T15	3
valid_sources[0x0a]	815166	1			T11	4		T14	1		T16	5
valid_sources[0x0b]	818684	1			T11	4		T12	2		T16	2
valid_sources[0x0c]	831997	1			T14	1		T16	1		T17	1
valid_sources[0x0d]	827562	1			T14	1		T16	4		T18	750
valid_sources[0x0e]	828573	1			T11	1		T14	1		T15	1
valid_sources[0x0f]	851384	1			T16	6		T17	3		T18	779
valid_sources[0x10]	819376	1			T11	7		T12	2		T14	3
valid_sources[0x11]	848664	1			T11	18		T16	1		T18	734
valid_sources[0x12]	810338	1			T11	2		T12	1		T14	1
valid_sources[0x13]	827759	1			T14	1		T16	2		T17	1
valid_sources[0x14]	835032	1			T14	2		T16	1		T18	751
valid_sources[0x15]	827047	1			T11	2		T15	1		T16	2
valid_sources[0x16]	853515	1			T14	5		T16	3		T18	743
valid_sources[0x17]	793961	1			T11	14		T14	2		T16	3
valid_sources[0x18]	858035	1			T14	1		T15	1		T16	2
valid_sources[0x19]	832711	1			T14	2		T16	2		T18	746
valid_sources[0x1a]	832190	1			T14	1		T16	3		T17	10
valid_sources[0x1b]	851261	1			T14	1		T15	2		T16	2
valid_sources[0x1c]	819704	1			T11	21		T14	1		T18	717
valid_sources[0x1d]	809261	1			T15	2		T16	7		T18	762
valid_sources[0x1e]	849350	1			T11	3		T12	1		T14	2
valid_sources[0x1f]	799850	1			T11	5		T14	2		T15	1
valid_sources[0x20]	817636	1			T11	3		T14	1		T15	3
valid_sources[0x21]	811492	1			T11	9		T14	2		T15	1
valid_sources[0x22]	859625	1			T14	4		T15	2		T18	687
valid_sources[0x23]	812926	1			T11	3		T12	1		T14	1
valid_sources[0x24]	856707	1			T16	2		T18	780		T91	1
valid_sources[0x25]	822479	1			T16	1		T18	700		T41	2
valid_sources[0x26]	817571	1			T14	4		T15	1		T16	4
valid_sources[0x27]	803379	1			T14	1		T15	1		T16	1
valid_sources[0x28]	825145	1			T15	2		T16	6		T17	2
valid_sources[0x29]	829538	1			T14	2		T16	5		T18	755
valid_sources[0x2a]	869915	1			T11	7		T12	1		T14	5
valid_sources[0x2b]	828685	1			T11	1		T14	1		T16	6
valid_sources[0x2c]	783010	1			T11	13		T14	1		T18	768
valid_sources[0x2d]	1204664	1			T15	1		T16	5		T18	731
valid_sources[0x2e]	1199458	1			T11	9		T14	4		T16	1
valid_sources[0x2f]	853303	1			T15	1		T16	5		T17	1
valid_sources[0x30]	831068	1			T11	16		T14	3		T16	2
valid_sources[0x31]	821953	1			T15	1		T16	4		T18	752
valid_sources[0x32]	820919	1			T11	1		T14	4		T16	3
valid_sources[0x33]	798028	1			T15	2		T16	5		T18	735
valid_sources[0x34]	816995	1			T14	2		T15	2		T16	1
valid_sources[0x35]	826229	1			T11	2		T16	7		T18	778
valid_sources[0x36]	777996	1			T12	1		T15	3		T16	2
valid_sources[0x37]	824889	1			T14	2		T15	3		T16	2
valid_sources[0x38]	800051	1			T11	2		T14	2		T15	1
valid_sources[0x39]	809294	1			T11	2		T14	5		T15	1
valid_sources[0x3a]	1271582	1			T11	1		T14	1		T16	2
valid_sources[0x3b]	794073	1			T14	6		T15	1		T16	6
valid_sources[0x3c]	836329	1			T14	5		T15	1		T16	3
valid_sources[0x3d]	813832	1			T12	1		T14	2		T16	4
valid_sources[0x3e]	796220	1			T11	1		T14	2		T15	2
valid_sources[0x3f]	1086963	1			T15	2		T16	1		T18	772
valid_sources[0x40]	844751	1			T14	1		T15	1		T16	5
valid_sources[0x41]	812847	1			T14	4		T16	5		T18	745
valid_sources[0x42]	798287	1			T11	1		T16	4		T18	703
valid_sources[0x43]	823570	1			T14	1		T16	3		T18	828
valid_sources[0x44]	839227	1			T14	2		T15	1		T16	8
valid_sources[0x45]	831095	1			T14	3		T16	5		T18	770
valid_sources[0x46]	843119	1			T16	6		T18	776		T20	20
valid_sources[0x47]	813278	1			T11	1		T14	1		T15	1
valid_sources[0x48]	859867	1			T14	1		T15	1		T16	1
valid_sources[0x49]	840759	1			T11	11		T14	1		T15	1
valid_sources[0x4a]	807304	1			T11	3		T15	1		T16	4
valid_sources[0x4b]	825440	1			T11	3		T14	1		T15	1
valid_sources[0x4c]	813110	1			T14	2		T16	3		T18	738
valid_sources[0x4d]	835536	1			T13	20		T14	2		T15	1
valid_sources[0x4e]	832591	1			T11	2		T12	1		T14	1
valid_sources[0x4f]	787924	1			T14	4		T16	2		T18	754
valid_sources[0x50]	834003	1			T12	1		T14	3		T16	2
valid_sources[0x51]	833939	1			T16	3		T18	709		T19	2
valid_sources[0x52]	836612	1			T11	8		T14	2		T16	3
valid_sources[0x53]	812677	1			T11	2		T14	3		T15	1
valid_sources[0x54]	791946	1			T11	2		T16	1		T17	1
valid_sources[0x55]	859702	1			T14	1		T15	2		T16	2
valid_sources[0x56]	893978	1			T14	3		T15	2		T16	2
valid_sources[0x57]	1209925	1			T11	2		T14	3		T15	1
valid_sources[0x58]	812089	1			T12	1		T14	3		T15	1
valid_sources[0x59]	810364	1			T14	3		T15	2		T16	4
valid_sources[0x5a]	824708	1			T11	2		T14	5		T16	3
valid_sources[0x5b]	859510	1			T14	1		T15	1		T16	3
valid_sources[0x5c]	812598	1			T11	14		T16	4		T18	777
valid_sources[0x5d]	805518	1			T14	1		T16	3		T18	762
valid_sources[0x5e]	804478	1			T14	1		T18	700		T42	2
valid_sources[0x5f]	929735	1			T14	3		T15	2		T16	5
valid_sources[0x60]	864733	1			T14	1		T16	1		T18	711
valid_sources[0x61]	816475	1			T14	1		T15	1		T16	3
valid_sources[0x62]	814039	1			T11	1		T15	2		T16	5
valid_sources[0x63]	878962	1			T12	1		T14	1		T16	5
valid_sources[0x64]	787776	1			T14	1		T15	1		T16	3
valid_sources[0x65]	832290	1			T14	3		T16	6		T18	737
valid_sources[0x66]	860565	1			T15	1		T16	4		T18	798
valid_sources[0x67]	830133	1			T11	3		T14	2		T16	3
valid_sources[0x68]	843761	1			T11	5		T14	3		T16	3
valid_sources[0x69]	822194	1			T11	21		T14	2		T16	4
valid_sources[0x6a]	795546	1			T11	5		T18	726		T19	6
valid_sources[0x6b]	818302	1			T14	1		T16	6		T18	810
valid_sources[0x6c]	819929	1			T14	1		T16	6		T18	720
valid_sources[0x6d]	834079	1			T11	2		T14	1		T15	1
valid_sources[0x6e]	822818	1			T11	6		T12	1		T14	2
valid_sources[0x6f]	804222	1			T11	8		T12	1		T14	5
valid_sources[0x70]	843410	1			T11	3		T14	2		T15	1
valid_sources[0x71]	1562684	1			T14	3		T15	1		T16	6
valid_sources[0x72]	813552	1			T14	3		T15	1		T16	7
valid_sources[0x73]	821978	1			T11	4		T14	3		T16	1
valid_sources[0x74]	836955	1			T11	7		T16	4		T17	3
valid_sources[0x75]	809945	1			T14	1		T16	5		T17	1
valid_sources[0x76]	823356	1			T15	1		T16	6		T17	1
valid_sources[0x77]	824944	1			T12	1		T14	1		T15	1
valid_sources[0x78]	821105	1			T14	6		T16	1		T18	796
valid_sources[0x79]	799961	1			T14	1		T15	1		T16	2
valid_sources[0x7a]	799244	1			T11	2		T14	2		T15	2
valid_sources[0x7b]	836300	1			T16	4		T18	720		T19	4
valid_sources[0x7c]	800459	1			T11	4		T14	2		T15	1
valid_sources[0x7d]	818196	1			T11	1		T14	1		T15	1
valid_sources[0x7e]	807536	1			T11	9		T12	1		T14	2
valid_sources[0x7f]	817050	1			T14	1		T15	1		T16	8
valid_sources[0x80]	828254	1			T12	2		T14	2		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41317928

1

T11

155

T12

19

T13

3

values[0x0]

all_enables

biggest_size

38396190

1

T11

220

T12

4

T14

121

values[0x1]

all_enables

biggest_size

35344255

1

T11

250

T12

3

T13

1