Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

153923174

1

T11

682

T12

32

T13

16

full_word

118993899

1

T11

676

T12

26

T13

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	272916663	1			T11	1358		T12	58		T13	20
auto[TlIntgErrCmd]	117	1			T41	2		T56	8		T57	3
auto[TlIntgErrData]	173	1			T41	4		T56	15		T57	10
auto[TlIntgErrBoth]	120	1			T41	4		T56	7		T57	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106014403

1

T11

458

T12

29

T13

10

auto[1]

166902670

1

T11

900

T12

29

T13

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	63128177	1			T11	283		T12	10		T13	7
auto[TlIntgErrNone]	partial	auto[1]	90794616	1			T11	399		T12	22		T13	9
auto[TlIntgErrNone]	full_word	auto[0]	42886036	1			T11	175		T12	19		T13	3
auto[TlIntgErrNone]	full_word	auto[1]	76107834	1			T11	501		T12	7		T13	1
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T41	1		T56	4		T57	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T41	1		T56	3		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T56	1		T59	1		T99	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T100	1		T101	2		-	-
auto[TlIntgErrData]	partial	auto[0]	81	1			T41	3		T56	7		T57	7
auto[TlIntgErrData]	partial	auto[1]	75	1			T41	1		T56	7		T57	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T57	1		T98	1		T59	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T56	1		T57	1		T66	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T41	2		T56	3		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T41	2		T56	3		T57	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T99	1		T102	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T56	1		T103	1		T104	1