Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.89			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.22	100.00	96.89			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.89			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.48	99.44	97.95	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_2	100.00	100.00
u_key_3	100.00	100.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_msg_length_lower	95.83	87.50	100.00			100.00
u_msg_length_upper	95.83	87.50	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		197	197	100.00
ALWAYS	76	4	4	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	780	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	822	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
ALWAYS	1055	28	28	100.00
CONT_ASSIGN	1085	1	1	100.00
ALWAYS	1089	1	1	100.00
CONT_ASSIGN	1120	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1124	1	1	100.00
CONT_ASSIGN	1126	1	1	100.00
CONT_ASSIGN	1127	1	1	100.00
CONT_ASSIGN	1129	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1134	1	1	100.00
CONT_ASSIGN	1136	1	1	100.00
CONT_ASSIGN	1138	1	1	100.00
CONT_ASSIGN	1140	1	1	100.00
CONT_ASSIGN	1141	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1144	1	1	100.00
CONT_ASSIGN	1145	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1151	1	1	100.00
CONT_ASSIGN	1153	1	1	100.00
CONT_ASSIGN	1154	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1158	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1160	1	1	100.00
CONT_ASSIGN	1162	1	1	100.00
CONT_ASSIGN	1163	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1168	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1174	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	1177	1	1	100.00
CONT_ASSIGN	1178	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
CONT_ASSIGN	1183	1	1	100.00
CONT_ASSIGN	1184	1	1	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1187	1	1	100.00
CONT_ASSIGN	1188	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1191	1	1	100.00
CONT_ASSIGN	1192	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1194	1	1	100.00
ALWAYS	1198	28	28	100.00
ALWAYS	1230	41	41	100.00
CONT_ASSIGN	1363	0	0
CONT_ASSIGN	1371	1	1	100.00
CONT_ASSIGN	1372	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
78	1	1
79	1	1
			MISSING_ELSE
85	1	1
103	1	1
104	1	1
106	1	1
107	1	1
133	1	1
139	1	1
140	1	1
			MISSING_ELSE
170	1	1
171	1	1
421	1	1
436	1	1
452	1	1
468	1	1
474	1	1
488	1	1
494	1	1
509	1	1
525	1	1
541	1	1
557	1	1
563	1	1
578	1	1
594	1	1
675	1	1
689	1	1
696	1	1
710	1	1
717	1	1
731	1	1
738	1	1
752	1	1
759	1	1
773	1	1
780	1	1
794	1	1
801	1	1
815	1	1
822	1	1
836	1	1
843	1	1
857	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1
1070	1	1
1071	1	1
1072	1	1
1073	1	1
1074	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1085	1	1
1089	1	1
1120	1	1
1122	1	1
1124	1	1
1126	1	1
1127	1	1
1129	1	1
1131	1	1
1133	1	1
1134	1	1
1136	1	1
1138	1	1
1140	1	1
1141	1	1
1143	1	1
1144	1	1
1145	1	1
1147	1	1
1149	1	1
1151	1	1
1153	1	1
1154	1	1
1156	1	1
1158	1	1
1159	1	1
1160	1	1
1162	1	1
1163	1	1
1165	1	1
1166	1	1
1168	1	1
1169	1	1
1171	1	1
1172	1	1
1174	1	1
1175	1	1
1177	1	1
1178	1	1
1180	1	1
1181	1	1
1183	1	1
1184	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
1202	1	1
1203	1	1
1204	1	1
1205	1	1
1206	1	1
1207	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
1212	1	1
1213	1	1
1214	1	1
1215	1	1
1216	1	1
1217	1	1
1218	1	1
1219	1	1
1220	1	1
1221	1	1
1222	1	1
1223	1	1
1224	1	1
1225	1	1
1230	1	1
1231	1	1
1233	1	1
1234	1	1
1235	1	1
1239	1	1
1240	1	1
1241	1	1
1245	1	1
1246	1	1
1247	1	1
1251	1	1
1255	1	1
1256	1	1
1257	1	1
1258	1	1
1262	1	1
1263	1	1
1267	1	1
1268	1	1
1269	1	1
1273	1	1
1277	1	1
1281	1	1
1285	1	1
1289	1	1
1293	1	1
1297	1	1
1301	1	1
1305	1	1
1309	1	1
1313	1	1
1317	1	1
1321	1	1
1325	1	1
1329	1	1
1333	1	1
1337	1	1
1341	1	1
1345	1	1
1349	1	1
1363		unreachable
1371	1	1
1372	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	289	280	96.89
Logical	289	280	96.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T17,T18
1	1	Covered	T11,T12,T13

 LINE       78
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T44,T45,T46
1	0	Covered	T41,T56,T57

 LINE       85
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T11,T12,T13
0	0	1	Covered	T44,T45,T46
0	1	0	Covered	T41,T56,T57
1	0	0	Covered	T41,T56,T57

 LINE       133
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T16

 LINE       171
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T11,T12,T13
0	0	1	Covered	T41,T56,T57
0	1	0	Covered	T11,T14,T17
1	0	0	Covered	T11,T14,T17

 LINE       171
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T14,T17

 LINE       1056
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       1057
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       1058
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       1059
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1060
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CFG_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1061
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T16

 LINE       1062
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1063
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1064
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1065
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1066
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1067
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1068
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1069
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1070
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_5_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1071
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_6_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1072
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_7_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1073
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1074
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1075
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1076
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1077
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1078
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1079
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1080
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1081
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1082
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T15

 LINE       1085
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       1085
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       1089
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T12,T13,T14
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T11,T12,T13
27 (addr_hit[26] & ((|(4'...	Covered	T11,T14,T15
26 (addr_hit[25] & ((|(4'...	Covered	T11,T14,T15
25 (addr_hit[24] & ((|(4'...	Covered	T11,T14,T15
24 (addr_hit[23] & ((|(4'...	Covered	T11,T14,T16
23 (addr_hit[22] & ((|(4'...	Covered	T11,T14,T16
22 (addr_hit[21] & ((|(4'...	Covered	T11,T14,T15
21 (addr_hit[20] & ((|(4'...	Covered	T11,T14,T17
20 (addr_hit[19] & ((|(4'...	Covered	T11,T14,T17
19 (addr_hit[18] & ((|(4'...	Covered	T11,T14,T17
18 (addr_hit[17] & ((|(4'...	Covered	T11,T14,T15
17 (addr_hit[16] & ((|(4'...	Covered	T11,T14,T15
16 (addr_hit[15] & ((|(4'...	Covered	T11,T14,T15
15 (addr_hit[14] & ((|(4'...	Covered	T11,T14,T17
14 (addr_hit[13] & ((|(4'...	Covered	T11,T14,T15
13 (addr_hit[12] & ((|(4'...	Covered	T11,T14,T16
12 (addr_hit[11] & ((|(4'...	Covered	T11,T14,T15
11 (addr_hit[10] & ((|(4'...	Covered	T11,T14,T16
10 (addr_hit[9] & ((|(4'b...	Covered	T11,T14,T15
9 (addr_hit[8] & ((|(4'b...	Covered	T11,T14,T15
8 (addr_hit[7] & ((|(4'b...	Covered	T11,T14,T15
7 (addr_hit[6] & ((|(4'b...	Covered	T11,T14,T15
6 (addr_hit[5] & ((|(4'b...	Covered	T11,T14,T17
5 (addr_hit[4] & ((|(4'b...	Covered	T11,T14,T15
4 (addr_hit[3] & ((|(4'b...	Covered	T11,T14,T17
3 (addr_hit[2] & ((|(4'b...	Covered	T11,T12,T13
2 (addr_hit[1] & ((|(4'b...	Covered	T11,T12,T13
1 (addr_hit[0] & ((|(4'b...	Covered	T11,T12,T13

 LINE       1089
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       1089
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       1089
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T12,T13,T14
1	1	Covered	T11,T12,T13

 LINE       1089
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T16
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T16,T18
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T16

 LINE       1089
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T16

 LINE       1089
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T17

 LINE       1089
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T16

 LINE       1089
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T16

 LINE       1089
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T16
1	1	Covered	T11,T14,T15

 LINE       1089
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T16,T18
1	1	Covered	T11,T14,T15

 LINE       1120
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T18,T23,T25
1	1	1	Covered	T12,T13,T18

 LINE       1127
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T14,T18,T23
1	1	1	Covered	T12,T13,T15

 LINE       1134
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T17,T18
1	1	1	Covered	T12,T13,T42

 LINE       1141
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T18,T26
1	1	1	Covered	T15,T16,T18

 LINE       1144
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1145
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T17
1	1	1	Covered	T15,T16,T18

 LINE       1154
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T16
1	1	0	Covered	T18,T23,T58
1	1	1	Covered	T1,T2,T3

 LINE       1159
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1160
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T18,T23,T26
1	1	1	Covered	T15,T16,T18

 LINE       1163
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T18,T23
1	1	1	Covered	T15,T16,T18

 LINE       1166
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T18
1	1	1	Covered	T15,T16,T18

 LINE       1169
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T18
1	1	1	Covered	T15,T16,T18

 LINE       1172
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T17
1	1	1	Covered	T15,T16,T18

 LINE       1175
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T18
1	1	1	Covered	T15,T16,T18

 LINE       1178
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T18,T23
1	1	1	Covered	T15,T16,T18

 LINE       1181
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T18,T25,T26
1	1	1	Covered	T15,T16,T18

 LINE       1184
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T15
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T14,T17
1	1	1	Covered	T15,T16,T18

 LINE       1187
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1188
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1189
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1190
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1191
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1192
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1193
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T18

 LINE       1194
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T59
1	1	1	Covered	T15,T16,T18

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		37	37	100.00
TERNARY	1085	2	2	100.00
IF	76	3	3	100.00
TERNARY	133	2	2	100.00
IF	139	2	2	100.00
CASE	1231	28	28	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1085	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T41,T56,T57
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	133	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T16
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	139	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T41,T56,T57
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	1231	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T11,T12,T13
addr_hit[1]	Covered	T11,T12,T13
addr_hit[2]	Covered	T11,T12,T13
addr_hit[3]	Covered	T11,T12,T13
addr_hit[4]	Covered	T11,T12,T13
addr_hit[5]	Covered	T11,T12,T13
addr_hit[6]	Covered	T11,T12,T13
addr_hit[7]	Covered	T11,T12,T13
addr_hit[8]	Covered	T11,T12,T13
addr_hit[9]	Covered	T11,T12,T13
addr_hit[10]	Covered	T11,T12,T13
addr_hit[11]	Covered	T11,T12,T13
addr_hit[12]	Covered	T11,T12,T13
addr_hit[13]	Covered	T11,T12,T13
addr_hit[14]	Covered	T11,T12,T13
addr_hit[15]	Covered	T11,T12,T13
addr_hit[16]	Covered	T11,T12,T13
addr_hit[17]	Covered	T11,T12,T13
addr_hit[18]	Covered	T11,T12,T13
addr_hit[19]	Covered	T11,T12,T13
addr_hit[20]	Covered	T11,T12,T13
addr_hit[21]	Covered	T11,T12,T13
addr_hit[22]	Covered	T11,T12,T13
addr_hit[23]	Covered	T11,T12,T13
addr_hit[24]	Covered	T11,T12,T13
addr_hit[25]	Covered	T11,T12,T13
addr_hit[26]	Covered	T11,T12,T13
default	Covered	T11,T12,T13

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1418987436	138538545	0	0
reAfterRv	1418987436	138538406	0	0
rePulse	1418987436	78737159	0	0
wePulse	1418987436	59801247	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418987436	138538545	0	0
T11	3554	36	0	0
T12	1531	58	0	0
T13	1346	20	0	0
T14	4573	32	0	0
T15	1025	150	0	0
T16	2594	880	0	0
T17	12116	13	0	0
T18	103269	16974	0	0
T19	2755	269	0	0
T20	4328	554	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418987436	138538406	0	0
T11	3554	36	0	0
T12	1531	58	0	0
T13	1346	20	0	0
T14	4573	32	0	0
T15	1025	150	0	0
T16	2594	880	0	0
T17	12116	13	0	0
T18	103269	16974	0	0
T19	2755	269	0	0
T20	4328	554	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418987436	78737159	0	0
T11	3554	3	0	0
T12	1531	29	0	0
T13	1346	10	0	0
T14	4573	8	0	0
T15	1025	79	0	0
T16	2594	463	0	0
T17	12116	3	0	0
T18	103269	2359	0	0
T19	2755	136	0	0
T20	4328	301	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418987436	59801247	0	0
T11	3554	33	0	0
T12	1531	29	0	0
T13	1346	10	0	0
T14	4573	24	0	0
T15	1025	71	0	0
T16	2594	417	0	0
T17	12116	10	0	0
T18	103269	14615	0	0
T19	2755	133	0	0
T20	4328	253	0	0