Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	40852906	1			T16	5		T17	1		T19	8
all_values[1]	40852906	1			T16	5		T17	1		T19	8
all_values[2]	40852906	1			T16	5		T17	1		T19	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149523

1

T16

6

T17

3

T19

12

auto[1]

122409195

1

T16

9

T19

12

T21

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88796260

1

T16

10

T17

3

T19

13

auto[1]

33762458

1

T16

5

T19

11

T21

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	47058	1			T17	1		T19	3		T20	1
all_values[0]	auto[0]	auto[1]	1379	1			T16	1		T19	1		T47	3
all_values[0]	auto[1]	auto[0]	40631107	1			T16	3		T19	3		T21	1
all_values[0]	auto[1]	auto[1]	173362	1			T16	1		T19	1		T21	1
all_values[1]	auto[0]	auto[0]	34775	1			T16	4		T17	1		T19	1
all_values[1]	auto[0]	auto[1]	21207	1			T19	2		T47	2		T104	1
all_values[1]	auto[1]	auto[0]	22667326	1			T19	4		T21	1		T47	2
all_values[1]	auto[1]	auto[1]	18129598	1			T16	1		T19	1		T47	1
all_values[2]	auto[0]	auto[0]	32403	1			T16	1		T17	1		T19	1
all_values[2]	auto[0]	auto[1]	12701	1			T19	4		T21	1		T47	2
all_values[2]	auto[1]	auto[0]	25383591	1			T16	2		T19	1		T21	1
all_values[2]	auto[1]	auto[1]	15424211	1			T16	2		T19	2		T21	2