Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.53 98.47 100.00 100.00 99.76 99.49 99.72


Total tests in report: 909
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
49.68 49.68 40.00 40.00 38.58 38.58 57.16 57.16 100.00 100.00 26.59 26.59 81.31 81.31 4.13 4.13 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1782096536
79.51 29.83 97.35 57.35 78.58 40.00 61.31 4.15 100.00 0.00 93.41 66.82 94.44 13.13 31.50 27.37 /workspace/coverage/default/28.hmac_wipe_secret.2993184129
89.47 9.95 97.51 0.16 85.90 7.32 97.86 36.56 100.00 0.00 95.06 1.65 95.45 1.01 54.47 22.97 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3608434573
94.89 5.43 98.29 0.78 92.13 6.23 98.24 0.38 100.00 0.00 97.18 2.12 96.72 1.26 81.71 27.24 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.722723922
96.87 1.98 99.07 0.78 94.64 2.51 98.99 0.75 100.00 0.00 98.59 1.41 96.72 0.00 90.10 8.39 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3151883892
97.87 1.00 99.46 0.39 97.60 2.95 99.50 0.50 100.00 0.00 99.06 0.47 97.47 0.76 92.02 1.93 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1020025546
98.21 0.34 99.46 0.00 97.92 0.33 99.50 0.00 100.00 0.00 99.06 0.00 97.47 0.00 94.09 2.06 /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.68536795
98.49 0.28 99.46 0.00 97.92 0.00 99.50 0.00 100.00 0.00 99.06 0.00 97.47 0.00 96.01 1.93 /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1423465646
98.67 0.18 99.46 0.00 98.14 0.22 100.00 0.50 100.00 0.00 99.06 0.00 97.73 0.25 96.29 0.28 /workspace/coverage/default/2.hmac_sec_cm.3779302554
98.77 0.10 99.46 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.06 0.00 97.73 0.00 96.97 0.69 /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1640082183
98.86 0.09 99.53 0.08 98.25 0.11 100.00 0.00 100.00 0.00 99.53 0.47 97.73 0.00 96.97 0.00 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2964019077
98.94 0.08 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 97.73 0.00 97.52 0.55 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2392867262
99.01 0.07 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.23 0.51 97.52 0.00 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4223624468
99.07 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.23 0.00 97.94 0.41 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2035995775
99.13 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.23 0.00 98.35 0.41 /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.2840788160
99.19 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.23 0.00 98.76 0.41 /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.4166081107
99.23 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.23 0.00 99.04 0.28 /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.789944776
99.26 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.25 99.04 0.00 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3421543427
99.30 0.03 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.24 98.48 0.00 99.04 0.00 /workspace/coverage/default/0.hmac_long_msg.3458068453
99.33 0.03 99.53 0.00 98.47 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.04 0.00 /workspace/coverage/default/11.hmac_alert_test.1261236496
99.35 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.14 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.516708495
99.37 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.374003957
99.39 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.607175121
99.41 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.4032217627
99.43 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2425412907

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3803291241
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.675602323
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.831955065
/workspace/coverage/cover_reg_top/0.hmac_intr_test.4242405339
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.1144003593
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2494308320
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1922201771
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4222451420
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3970354446
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2208730667
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.679771630
/workspace/coverage/cover_reg_top/1.hmac_intr_test.3374811760
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1385453559
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.31294364
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1276848563
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.3123637105
/workspace/coverage/cover_reg_top/10.hmac_intr_test.1068599188
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.450270542
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.3201296564
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1758965786
/workspace/coverage/cover_reg_top/11.hmac_intr_test.1896468807
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4240687349
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.198365489
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2027376024
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2880493545
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.4264945364
/workspace/coverage/cover_reg_top/12.hmac_intr_test.2555068572
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3812398915
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.136233626
/workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1830298231
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3480494689
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.719812282
/workspace/coverage/cover_reg_top/13.hmac_intr_test.2348555044
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.582499720
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.513201703
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2820519827
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3492023586
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.4145360108
/workspace/coverage/cover_reg_top/14.hmac_intr_test.3620325373
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2833056418
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.4060317111
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.386362795
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3618414512
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.4168880990
/workspace/coverage/cover_reg_top/15.hmac_intr_test.4223464074
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.348901302
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.1490338061
/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1964662755
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2177837090
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.1135450304
/workspace/coverage/cover_reg_top/16.hmac_intr_test.2133425977
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3226176364
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.3997925176
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3775115900
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1444663934
/workspace/coverage/cover_reg_top/17.hmac_intr_test.581672035
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2236681352
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.1387098863
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3896790980
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1020011804
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.1073384124
/workspace/coverage/cover_reg_top/18.hmac_intr_test.3539192318
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3789265850
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3114954020
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2668933441
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.1439082397
/workspace/coverage/cover_reg_top/19.hmac_intr_test.1984835149
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.823752616
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.3760038714
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.632309934
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4037967183
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1305384378
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.806376170
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.219887444
/workspace/coverage/cover_reg_top/2.hmac_intr_test.2954023827
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3301869913
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.1949149715
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4272334437
/workspace/coverage/cover_reg_top/20.hmac_intr_test.2571498605
/workspace/coverage/cover_reg_top/21.hmac_intr_test.4076026142
/workspace/coverage/cover_reg_top/22.hmac_intr_test.3183525398
/workspace/coverage/cover_reg_top/23.hmac_intr_test.423297296
/workspace/coverage/cover_reg_top/24.hmac_intr_test.94973624
/workspace/coverage/cover_reg_top/25.hmac_intr_test.2949605780
/workspace/coverage/cover_reg_top/26.hmac_intr_test.392609223
/workspace/coverage/cover_reg_top/27.hmac_intr_test.2372093633
/workspace/coverage/cover_reg_top/28.hmac_intr_test.4294238482
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2298006486
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1606882780
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3449992114
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2670607707
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.899845771
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.1525494477
/workspace/coverage/cover_reg_top/3.hmac_intr_test.50417897
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.223360842
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.1988321063
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.212680781
/workspace/coverage/cover_reg_top/30.hmac_intr_test.2112579577
/workspace/coverage/cover_reg_top/31.hmac_intr_test.966691052
/workspace/coverage/cover_reg_top/32.hmac_intr_test.3357910643
/workspace/coverage/cover_reg_top/33.hmac_intr_test.3912467609
/workspace/coverage/cover_reg_top/34.hmac_intr_test.806823606
/workspace/coverage/cover_reg_top/35.hmac_intr_test.2614903935
/workspace/coverage/cover_reg_top/36.hmac_intr_test.455772817
/workspace/coverage/cover_reg_top/37.hmac_intr_test.2071183361
/workspace/coverage/cover_reg_top/38.hmac_intr_test.3509484960
/workspace/coverage/cover_reg_top/39.hmac_intr_test.515295723
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1084830651
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4213386799
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3398251610
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2375012109
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.2493667754
/workspace/coverage/cover_reg_top/4.hmac_intr_test.3062432450
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1657598398
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.4014054217
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3241471132
/workspace/coverage/cover_reg_top/40.hmac_intr_test.3362131810
/workspace/coverage/cover_reg_top/41.hmac_intr_test.2087289207
/workspace/coverage/cover_reg_top/43.hmac_intr_test.975296222
/workspace/coverage/cover_reg_top/44.hmac_intr_test.2288940301
/workspace/coverage/cover_reg_top/46.hmac_intr_test.2257710241
/workspace/coverage/cover_reg_top/47.hmac_intr_test.2844913508
/workspace/coverage/cover_reg_top/48.hmac_intr_test.3751657019
/workspace/coverage/cover_reg_top/49.hmac_intr_test.3676959806
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1877536809
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.302479171
/workspace/coverage/cover_reg_top/5.hmac_intr_test.1858823335
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2816688751
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.1043956480
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1352361639
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3837793563
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.1437406128
/workspace/coverage/cover_reg_top/6.hmac_intr_test.372009000
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1604839561
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.715208483
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1311125409
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.556819423
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2557801287
/workspace/coverage/cover_reg_top/7.hmac_intr_test.2673370110
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3584260507
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.1387006985
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3208275925
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1839513369
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.4146687286
/workspace/coverage/cover_reg_top/8.hmac_intr_test.1235814557
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.55523836
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.567076400
/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.173563001
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1038488604
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.18160290
/workspace/coverage/cover_reg_top/9.hmac_intr_test.1252997252
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4286720034
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.66743571
/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.840865622
/workspace/coverage/default/0.hmac_alert_test.2316946493
/workspace/coverage/default/0.hmac_back_pressure.550459827
/workspace/coverage/default/0.hmac_burst_wr.1104939394
/workspace/coverage/default/0.hmac_datapath_stress.3290295123
/workspace/coverage/default/0.hmac_error.557151485
/workspace/coverage/default/0.hmac_sec_cm.3325796355
/workspace/coverage/default/0.hmac_smoke.2171458665
/workspace/coverage/default/0.hmac_stress_all.644281085
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1348518828
/workspace/coverage/default/0.hmac_test_hmac_vectors.2688818756
/workspace/coverage/default/0.hmac_test_sha_vectors.3732713047
/workspace/coverage/default/0.hmac_wipe_secret.299508434
/workspace/coverage/default/1.hmac_alert_test.1773403320
/workspace/coverage/default/1.hmac_back_pressure.3413430510
/workspace/coverage/default/1.hmac_burst_wr.985051501
/workspace/coverage/default/1.hmac_datapath_stress.815395928
/workspace/coverage/default/1.hmac_error.1495947289
/workspace/coverage/default/1.hmac_long_msg.2530568882
/workspace/coverage/default/1.hmac_sec_cm.824582225
/workspace/coverage/default/1.hmac_smoke.2346197591
/workspace/coverage/default/1.hmac_stress_all.3354974822
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.4118871689
/workspace/coverage/default/1.hmac_test_hmac_vectors.1798021867
/workspace/coverage/default/1.hmac_test_sha_vectors.4058952009
/workspace/coverage/default/1.hmac_wipe_secret.3888502261
/workspace/coverage/default/10.hmac_alert_test.2688766598
/workspace/coverage/default/10.hmac_back_pressure.2679547777
/workspace/coverage/default/10.hmac_burst_wr.2281498661
/workspace/coverage/default/10.hmac_datapath_stress.623425296
/workspace/coverage/default/10.hmac_error.232054367
/workspace/coverage/default/10.hmac_long_msg.1996517808
/workspace/coverage/default/10.hmac_smoke.1472849955
/workspace/coverage/default/10.hmac_stress_all.2994214258
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.4107508860
/workspace/coverage/default/10.hmac_test_hmac_vectors.1286056071
/workspace/coverage/default/10.hmac_test_sha_vectors.2947634997
/workspace/coverage/default/10.hmac_wipe_secret.2313777122
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2794055135
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.890332162
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.1828407651
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1562915514
/workspace/coverage/default/11.hmac_back_pressure.3241022200
/workspace/coverage/default/11.hmac_burst_wr.4263925725
/workspace/coverage/default/11.hmac_datapath_stress.373289053
/workspace/coverage/default/11.hmac_error.1298787453
/workspace/coverage/default/11.hmac_long_msg.221123846
/workspace/coverage/default/11.hmac_smoke.536138071
/workspace/coverage/default/11.hmac_stress_all.2608320826
/workspace/coverage/default/11.hmac_stress_all_with_rand_reset.297425230
/workspace/coverage/default/11.hmac_test_hmac_vectors.267911231
/workspace/coverage/default/11.hmac_wipe_secret.3874846461
/workspace/coverage/default/110.hmac_stress_all_with_rand_reset.1166305470
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/workspace/coverage/default/73.hmac_stress_all_with_rand_reset.4199464178
/workspace/coverage/default/74.hmac_stress_all_with_rand_reset.314951323
/workspace/coverage/default/75.hmac_stress_all_with_rand_reset.3792964989
/workspace/coverage/default/76.hmac_stress_all_with_rand_reset.2015281448
/workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3355554832
/workspace/coverage/default/78.hmac_stress_all_with_rand_reset.865687577
/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.2865983280
/workspace/coverage/default/8.hmac_alert_test.337857135
/workspace/coverage/default/8.hmac_back_pressure.3289773746
/workspace/coverage/default/8.hmac_burst_wr.1838200920
/workspace/coverage/default/8.hmac_datapath_stress.19849803
/workspace/coverage/default/8.hmac_error.2165912743
/workspace/coverage/default/8.hmac_long_msg.1061249371
/workspace/coverage/default/8.hmac_smoke.2690389239
/workspace/coverage/default/8.hmac_stress_all.577421526
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1747524232
/workspace/coverage/default/8.hmac_test_hmac_vectors.2146465200
/workspace/coverage/default/8.hmac_test_sha_vectors.1750825696
/workspace/coverage/default/8.hmac_wipe_secret.1624828103
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1846799363
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.2889358265
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.1296486959
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2862297917
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1202144657
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2068767770
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.2293209293
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1198553039
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.2522090978
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.275987054
/workspace/coverage/default/9.hmac_alert_test.3793727759
/workspace/coverage/default/9.hmac_back_pressure.1617872610
/workspace/coverage/default/9.hmac_burst_wr.3766849734
/workspace/coverage/default/9.hmac_datapath_stress.204765920
/workspace/coverage/default/9.hmac_error.1026053708
/workspace/coverage/default/9.hmac_long_msg.4034091990
/workspace/coverage/default/9.hmac_smoke.2532568021
/workspace/coverage/default/9.hmac_stress_all.1542567364
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.566958483
/workspace/coverage/default/9.hmac_test_hmac_vectors.2007359708
/workspace/coverage/default/9.hmac_wipe_secret.3425792199
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2500060201
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3275656842
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1471867952
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1738967549
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3952983782
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2192611333
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.2036521877
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.4294061802
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.931566348



Total test records in report: 909
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T14 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1782096536 Dec 31 12:23:00 PM PST 23 Dec 31 12:23:02 PM PST 23 65248582 ps
T15 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.899845771 Dec 31 12:23:18 PM PST 23 Dec 31 12:23:20 PM PST 23 19708064 ps
T16 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1896468807 Dec 31 12:24:00 PM PST 23 Dec 31 12:24:07 PM PST 23 43454875 ps
T17 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1020025546 Dec 31 12:34:34 PM PST 23 Dec 31 12:34:39 PM PST 23 148887382 ps
T18 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4146687286 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:50 PM PST 23 41117078 ps
T19 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3751657019 Dec 31 12:25:14 PM PST 23 Dec 31 12:25:18 PM PST 23 30233980 ps
T20 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.136233626 Dec 31 12:22:51 PM PST 23 Dec 31 12:22:54 PM PST 23 301941140 ps
T21 /workspace/coverage/cover_reg_top/3.hmac_intr_test.50417897 Dec 31 12:24:22 PM PST 23 Dec 31 12:24:25 PM PST 23 29491624 ps
T22 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3608434573 Dec 31 12:25:05 PM PST 23 Dec 31 12:25:11 PM PST 23 572654954 ps
T23 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.198365489 Dec 31 12:24:24 PM PST 23 Dec 31 12:24:29 PM PST 23 1049833889 ps
T24 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1038488604 Dec 31 12:24:07 PM PST 23 Dec 31 12:24:14 PM PST 23 40639883 ps
T61 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.516708495 Dec 31 12:19:30 PM PST 23 Dec 31 12:19:33 PM PST 23 112905821 ps
T25 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1387098863 Dec 31 12:25:48 PM PST 23 Dec 31 12:25:58 PM PST 23 74486754 ps
T26 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.806376170 Dec 31 12:27:10 PM PST 23 Dec 31 12:27:13 PM PST 23 160407101 ps
T97 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4286720034 Dec 31 12:24:44 PM PST 23 Dec 31 12:24:53 PM PST 23 63187291 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1385453559 Dec 31 12:21:25 PM PST 23 Dec 31 12:21:27 PM PST 23 54355869 ps
T76 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4264945364 Dec 31 12:19:17 PM PST 23 Dec 31 12:19:20 PM PST 23 24623401 ps
T47 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3151883892 Dec 31 12:19:13 PM PST 23 Dec 31 12:19:14 PM PST 23 16619422 ps
T27 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1988321063 Dec 31 12:34:30 PM PST 23 Dec 31 12:34:33 PM PST 23 116261774 ps
T77 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1657598398 Dec 31 12:22:52 PM PST 23 Dec 31 12:22:54 PM PST 23 32531599 ps
T62 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3208275925 Dec 31 12:22:29 PM PST 23 Dec 31 12:22:31 PM PST 23 63851043 ps
T28 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1758965786 Dec 31 12:24:00 PM PST 23 Dec 31 12:24:08 PM PST 23 15974170 ps
T104 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1252997252 Dec 31 12:28:08 PM PST 23 Dec 31 12:28:12 PM PST 23 14108633 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3398251610 Dec 31 12:27:12 PM PST 23 Dec 31 12:27:14 PM PST 23 17597625 ps
T148 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2087289207 Dec 31 12:23:38 PM PST 23 Dec 31 12:23:42 PM PST 23 53945869 ps
T29 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1387006985 Dec 31 12:23:10 PM PST 23 Dec 31 12:23:13 PM PST 23 964261891 ps
T66 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.386362795 Dec 31 12:19:08 PM PST 23 Dec 31 12:19:10 PM PST 23 106127076 ps
T67 /workspace/coverage/cover_reg_top/24.hmac_intr_test.94973624 Dec 31 12:25:37 PM PST 23 Dec 31 12:25:46 PM PST 23 17016605 ps
T68 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3362131810 Dec 31 12:23:12 PM PST 23 Dec 31 12:23:13 PM PST 23 54865842 ps
T157 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1858823335 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:34 PM PST 23 54025492 ps
T158 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3775115900 Dec 31 12:24:23 PM PST 23 Dec 31 12:24:28 PM PST 23 35535459 ps
T74 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1830298231 Dec 31 12:24:00 PM PST 23 Dec 31 12:24:08 PM PST 23 94866086 ps
T78 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3803291241 Dec 31 12:28:30 PM PST 23 Dec 31 12:28:42 PM PST 23 347199995 ps
T69 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1135450304 Dec 31 12:21:17 PM PST 23 Dec 31 12:21:18 PM PST 23 22026213 ps
T79 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2236681352 Dec 31 12:18:25 PM PST 23 Dec 31 12:18:27 PM PST 23 107509655 ps
T70 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4222451420 Dec 31 12:26:58 PM PST 23 Dec 31 12:27:08 PM PST 23 1630943731 ps
T91 /workspace/coverage/cover_reg_top/26.hmac_intr_test.392609223 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 18224920 ps
T71 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1305384378 Dec 31 12:24:20 PM PST 23 Dec 31 12:24:23 PM PST 23 82941825 ps
T80 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.582499720 Dec 31 12:18:42 PM PST 23 Dec 31 12:18:43 PM PST 23 52936148 ps
T72 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.632309934 Dec 31 12:25:58 PM PST 23 Dec 31 12:26:10 PM PST 23 63734967 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3301869913 Dec 31 12:25:53 PM PST 23 Dec 31 12:26:01 PM PST 23 237795713 ps
T155 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3480494689 Dec 31 12:25:37 PM PST 23 Dec 31 12:25:46 PM PST 23 53823236 ps
T73 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4272334437 Dec 31 12:21:25 PM PST 23 Dec 31 12:21:28 PM PST 23 107487145 ps
T156 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2964019077 Dec 31 12:22:55 PM PST 23 Dec 31 12:22:58 PM PST 23 16652847 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.223360842 Dec 31 12:25:25 PM PST 23 Dec 31 12:25:31 PM PST 23 222866643 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3421543427 Dec 31 12:22:55 PM PST 23 Dec 31 12:22:57 PM PST 23 16719972 ps
T159 /workspace/coverage/cover_reg_top/34.hmac_intr_test.806823606 Dec 31 12:24:51 PM PST 23 Dec 31 12:24:58 PM PST 23 93137019 ps
T81 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1437406128 Dec 31 12:18:07 PM PST 23 Dec 31 12:18:08 PM PST 23 150336997 ps
T102 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4240687349 Dec 31 12:24:31 PM PST 23 Dec 31 12:24:35 PM PST 23 80530280 ps
T160 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2668933441 Dec 31 12:25:15 PM PST 23 Dec 31 12:25:20 PM PST 23 680572295 ps
T161 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.450270542 Dec 31 12:18:22 PM PST 23 Dec 31 12:18:24 PM PST 23 38534866 ps
T162 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1877536809 Dec 31 12:26:52 PM PST 23 Dec 31 12:26:55 PM PST 23 23254319 ps
T163 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2670607707 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:08 PM PST 23 16245250 ps
T164 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3620325373 Dec 31 12:28:43 PM PST 23 Dec 31 12:28:50 PM PST 23 210673728 ps
T165 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2392867262 Dec 31 12:24:55 PM PST 23 Dec 31 12:25:00 PM PST 23 39105948 ps
T166 /workspace/coverage/cover_reg_top/17.hmac_intr_test.581672035 Dec 31 12:25:45 PM PST 23 Dec 31 12:25:54 PM PST 23 17521130 ps
T167 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2844913508 Dec 31 12:24:47 PM PST 23 Dec 31 12:24:54 PM PST 23 16601906 ps
T168 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2493667754 Dec 31 12:25:07 PM PST 23 Dec 31 12:25:10 PM PST 23 26591430 ps
T82 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1444663934 Dec 31 12:23:36 PM PST 23 Dec 31 12:23:39 PM PST 23 51678639 ps
T94 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.840865622 Dec 31 12:27:38 PM PST 23 Dec 31 12:27:40 PM PST 23 84895046 ps
T169 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2816688751 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:46 PM PST 23 102561384 ps
T170 /workspace/coverage/cover_reg_top/6.hmac_intr_test.372009000 Dec 31 12:23:06 PM PST 23 Dec 31 12:23:07 PM PST 23 41014426 ps
T75 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2820519827 Dec 31 12:23:06 PM PST 23 Dec 31 12:23:09 PM PST 23 1128904670 ps
T171 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2833056418 Dec 31 12:19:32 PM PST 23 Dec 31 12:19:34 PM PST 23 45860239 ps
T172 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3062432450 Dec 31 12:23:24 PM PST 23 Dec 31 12:23:26 PM PST 23 47700746 ps
T173 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.18160290 Dec 31 12:26:44 PM PST 23 Dec 31 12:26:46 PM PST 23 162659246 ps
T174 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3123637105 Dec 31 12:24:32 PM PST 23 Dec 31 12:24:40 PM PST 23 68809003 ps
T175 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2133425977 Dec 31 12:24:43 PM PST 23 Dec 31 12:24:52 PM PST 23 47581736 ps
T176 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.679771630 Dec 31 12:26:34 PM PST 23 Dec 31 12:26:38 PM PST 23 23428991 ps
T63 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3201296564 Dec 31 12:22:54 PM PST 23 Dec 31 12:22:56 PM PST 23 138551249 ps
T64 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.567076400 Dec 31 12:23:07 PM PST 23 Dec 31 12:23:09 PM PST 23 36219015 ps
T177 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2949605780 Dec 31 12:20:58 PM PST 23 Dec 31 12:20:59 PM PST 23 48918015 ps
T178 /workspace/coverage/cover_reg_top/23.hmac_intr_test.423297296 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:08 PM PST 23 43327210 ps
T179 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3676959806 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:23 PM PST 23 71137674 ps
T153 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.212680781 Dec 31 12:29:39 PM PST 23 Dec 31 12:29:43 PM PST 23 1259743533 ps
T180 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4294238482 Dec 31 12:22:51 PM PST 23 Dec 31 12:22:52 PM PST 23 14480857 ps
T65 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.715208483 Dec 31 12:26:55 PM PST 23 Dec 31 12:26:59 PM PST 23 280953487 ps
T181 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2071183361 Dec 31 12:22:52 PM PST 23 Dec 31 12:22:53 PM PST 23 17221979 ps
T151 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2027376024 Dec 31 12:19:06 PM PST 23 Dec 31 12:19:08 PM PST 23 192445637 ps
T182 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1068599188 Dec 31 12:20:33 PM PST 23 Dec 31 12:20:34 PM PST 23 13121058 ps
T183 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1604839561 Dec 31 12:24:14 PM PST 23 Dec 31 12:24:18 PM PST 23 17727899 ps
T152 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3241471132 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 59782496 ps
T83 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.219887444 Dec 31 12:21:25 PM PST 23 Dec 31 12:21:26 PM PST 23 19813174 ps
T184 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2372093633 Dec 31 12:22:31 PM PST 23 Dec 31 12:22:32 PM PST 23 54684681 ps
T185 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2375012109 Dec 31 12:25:22 PM PST 23 Dec 31 12:25:28 PM PST 23 80562615 ps
T84 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1084830651 Dec 31 12:23:21 PM PST 23 Dec 31 12:23:24 PM PST 23 639590341 ps
T186 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.823752616 Dec 31 12:25:15 PM PST 23 Dec 31 12:25:20 PM PST 23 34161827 ps
T187 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3970354446 Dec 31 12:20:26 PM PST 23 Dec 31 12:20:27 PM PST 23 17009047 ps
T188 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1311125409 Dec 31 12:26:00 PM PST 23 Dec 31 12:26:09 PM PST 23 653256733 ps
T189 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2177837090 Dec 31 12:25:59 PM PST 23 Dec 31 12:26:06 PM PST 23 17452336 ps
T190 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1276848563 Dec 31 12:29:40 PM PST 23 Dec 31 12:29:43 PM PST 23 576077263 ps
T191 /workspace/coverage/cover_reg_top/43.hmac_intr_test.975296222 Dec 31 12:23:08 PM PST 23 Dec 31 12:23:10 PM PST 23 47902397 ps
T192 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4223464074 Dec 31 12:18:17 PM PST 23 Dec 31 12:18:18 PM PST 23 55551041 ps
T193 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2673370110 Dec 31 12:24:08 PM PST 23 Dec 31 12:24:14 PM PST 23 70674140 ps
T194 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.31294364 Dec 31 12:26:58 PM PST 23 Dec 31 12:27:00 PM PST 23 161094247 ps
T195 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.831955065 Dec 31 12:24:50 PM PST 23 Dec 31 12:24:56 PM PST 23 18566602 ps
T196 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1949149715 Dec 31 12:18:24 PM PST 23 Dec 31 12:18:27 PM PST 23 141836792 ps
T197 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4014054217 Dec 31 12:26:00 PM PST 23 Dec 31 12:26:10 PM PST 23 62233664 ps
T198 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.55523836 Dec 31 12:25:54 PM PST 23 Dec 31 12:26:03 PM PST 23 325591381 ps
T199 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3896790980 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:55 PM PST 23 278975386 ps
T200 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1235814557 Dec 31 12:22:31 PM PST 23 Dec 31 12:22:32 PM PST 23 22259320 ps
T201 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3584260507 Dec 31 12:18:23 PM PST 23 Dec 31 12:18:24 PM PST 23 27671238 ps
T202 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3812398915 Dec 31 12:27:16 PM PST 23 Dec 31 12:27:18 PM PST 23 57214204 ps
T203 /workspace/coverage/cover_reg_top/0.hmac_intr_test.4242405339 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:58 PM PST 23 21552463 ps
T204 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.513201703 Dec 31 12:26:34 PM PST 23 Dec 31 12:26:40 PM PST 23 189948285 ps
T85 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4223624468 Dec 31 12:22:56 PM PST 23 Dec 31 12:22:58 PM PST 23 65476912 ps
T205 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2614903935 Dec 31 12:23:25 PM PST 23 Dec 31 12:23:27 PM PST 23 49991045 ps
T206 /workspace/coverage/cover_reg_top/31.hmac_intr_test.966691052 Dec 31 12:25:44 PM PST 23 Dec 31 12:25:53 PM PST 23 46650274 ps
T92 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2557801287 Dec 31 12:24:14 PM PST 23 Dec 31 12:24:18 PM PST 23 47318010 ps
T1 /workspace/coverage/default/28.hmac_wipe_secret.2993184129 Dec 31 12:27:34 PM PST 23 Dec 31 12:28:03 PM PST 23 3040776585 ps
T2 /workspace/coverage/default/0.hmac_long_msg.3458068453 Dec 31 12:23:26 PM PST 23 Dec 31 12:24:49 PM PST 23 7940555721 ps
T3 /workspace/coverage/default/14.hmac_test_hmac_vectors.1023878235 Dec 31 12:26:21 PM PST 23 Dec 31 12:26:23 PM PST 23 145999116 ps
T10 /workspace/coverage/default/23.hmac_long_msg.3736990728 Dec 31 12:28:22 PM PST 23 Dec 31 12:28:35 PM PST 23 15568056414 ps
T7 /workspace/coverage/default/36.hmac_datapath_stress.97388978 Dec 31 12:27:26 PM PST 23 Dec 31 12:28:00 PM PST 23 2877561214 ps
T8 /workspace/coverage/default/26.hmac_back_pressure.3577578854 Dec 31 12:27:32 PM PST 23 Dec 31 12:28:04 PM PST 23 995455940 ps
T11 /workspace/coverage/default/20.hmac_smoke.3924625378 Dec 31 12:26:15 PM PST 23 Dec 31 12:26:20 PM PST 23 165947164 ps
T12 /workspace/coverage/default/9.hmac_error.1026053708 Dec 31 12:27:55 PM PST 23 Dec 31 12:29:08 PM PST 23 30781573277 ps
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