Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20437948

1

T1

2520

T2

5855

T3

32

auto[1]

9986138

1

T1

2285

T2

7110

T10

487

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9924784

1

T1

3168

T2

6300

T10

487

auto[1]

20499302

1

T1

1637

T2

6665

T3

32

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17843048

1

T1

2124

T2

5079

T10

163

auto[1]

12581038

1

T1

2681

T2

7886

T3

32

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	17308283	1			T1	1695		T2	11982		T3	32
fifo_depth[1]	1539582	1			T1	328		T2	629		T10	102
fifo_depth[2]	1387800	1			T1	358		T2	245		T10	44
fifo_depth[3]	1168676	1			T1	335		T2	91		T10	14
fifo_depth[4]	1122613	1			T1	345		T2	14		T10	2
fifo_depth[5]	955505	1			T1	363		T2	2		T7	408
fifo_depth[6]	978676	1			T1	360		T2	2		T7	424
fifo_depth[7]	834233	1			T1	289		T7	392		T8	2
fifo_depth[8]	991154	1			T1	252		T7	330		T8	5
fifo_depth[9]	581651	1			T1	199		T7	252		T8	7
fifo_depth[10]	593823	1			T1	153		T7	167		T8	2
fifo_depth[11]	361181	1			T1	66		T7	82		T8	2
fifo_depth[12]	601020	1			T1	45		T7	47		T8	3
fifo_depth[13]	271971	1			T1	11		T7	20		T9	1
fifo_depth[14]	444749	1			T1	4		T7	8		T8	4
fifo_depth[15]	251878	1			T1	2		T7	4		T8	3
fifo_depth[16]	1031291	1			T7	1		T8	4		T9	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13115803

1

T1

3110

T2

983

T10

162

auto[1]

17308283

1

T1

1695

T2

11982

T3

32

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29392795

1

T1

4805

T2

12965

T3

32

auto[1]

1031291

1

T7

1

T8

4

T9

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

947224

1

T1

457

T2

143

T8

8

auto[0]

auto[0]

auto[0]

auto[1]

973471

1

T1

277

T2

71

T10

14

auto[0]

auto[0]

auto[1]

auto[0]

3608555

1

T1

116

T2

123

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

1009037

1

T1

458

T2

43

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

1627064

1

T1

954

T2

62

T7

373

auto[0]

auto[1]

auto[0]

auto[1]

1676493

1

T1

372

T2

218

T10

36

auto[0]

auto[1]

auto[1]

auto[0]

1644044

1

T1

119

T2

107

T10

112

auto[0]

auto[1]

auto[1]

auto[1]

1629915

1

T1

357

T2

216

T7

866

auto[1]

auto[0]

auto[0]

auto[0]

872348

1

T1

301

T2

1756

T11

18

auto[1]

auto[0]

auto[0]

auto[1]

862449

1

T1

161

T2

886

T10

149

auto[1]

auto[0]

auto[1]

auto[0]

8729524

1

T1

77

T2

1582

T11

7

auto[1]

auto[0]

auto[1]

auto[1]

840440

1

T1

277

T2

475

T11

4

auto[1]

auto[1]

auto[0]

auto[0]

1477129

1

T1

434

T2

704

T7

240

auto[1]

auto[1]

auto[0]

auto[1]

1488606

1

T1

212

T2

2460

T10

288

auto[1]

auto[1]

auto[1]

auto[0]

1532060

1

T1

62

T2

1378

T3

32

auto[1]

auto[1]

auto[1]

auto[1]

1505727

1

T1

171

T2

2741

T7

445

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1704699

1

T1

758

T2

1899

T8

7

auto[0]

auto[0]

auto[0]

auto[1]

1704660

1

T1

438

T2

957

T10

163

auto[0]

auto[0]

auto[1]

auto[0]

12216235

1

T1

193

T2

1705

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

1722779

1

T1

735

T2

518

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

2978365

1

T1

1388

T2

766

T7

613

auto[0]

auto[1]

auto[0]

auto[1]

3018721

1

T1

584

T2

2678

T10

324

auto[0]

auto[1]

auto[1]

auto[0]

3041529

1

T1

181

T2

1485

T3

32

auto[0]

auto[1]

auto[1]

auto[1]

3005807

1

T1

528

T2

2957

T7

1311

auto[1]

auto[0]

auto[0]

auto[0]

114873

1

T8

1

T38

613

T30

2778

auto[1]

auto[0]

auto[0]

auto[1]

131260

1

T8

2

T9

1

T38

296

auto[1]

auto[0]

auto[1]

auto[0]

121844

1

T38

636

T30

3322

T34

7

auto[1]

auto[0]

auto[1]

auto[1]

126698

1

T38

204

T30

3123

T34

2

auto[1]

auto[1]

auto[0]

auto[0]

125828

1

T38

3175

T30

2089

T34

2

auto[1]

auto[1]

auto[0]

auto[1]

146378

1

T9

1

T38

839

T30

1701

auto[1]

auto[1]

auto[1]

auto[0]

134575

1

T7

1

T38

930

T30

2973

auto[1]

auto[1]

auto[1]

auto[1]

129835

1

T8

1

T38

2767

T30

3025

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	872348	1			T1	301		T2	1756		T11	18
fifo_depth[0]	auto[0]	auto[0]	auto[1]	862449	1			T1	161		T2	886		T10	149
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8729524	1			T1	77		T2	1582		T11	7
fifo_depth[0]	auto[0]	auto[1]	auto[1]	840440	1			T1	277		T2	475		T11	4
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1477129	1			T1	434		T2	704		T7	240
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1488606	1			T1	212		T2	2460		T10	288
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1532060	1			T1	62		T2	1378		T3	32
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1505727	1			T1	171		T2	2741		T7	445
fifo_depth[1]	auto[0]	auto[0]	auto[0]	78025	1			T1	58		T2	92		T12	24
fifo_depth[1]	auto[0]	auto[0]	auto[1]	75155	1			T1	22		T2	47		T10	4
fifo_depth[1]	auto[0]	auto[1]	auto[0]	653484	1			T1	4		T2	82		T13	121
fifo_depth[1]	auto[0]	auto[1]	auto[1]	76121	1			T1	49		T2	24		T13	65
fifo_depth[1]	auto[1]	auto[0]	auto[0]	163221	1			T1	108		T2	45		T7	45
fifo_depth[1]	auto[1]	auto[0]	auto[1]	163364	1			T1	45		T2	136		T10	27
fifo_depth[1]	auto[1]	auto[1]	auto[0]	167872	1			T1	11		T2	66		T10	71
fifo_depth[1]	auto[1]	auto[1]	auto[1]	162340	1			T1	31		T2	137		T7	86
fifo_depth[2]	auto[0]	auto[0]	auto[0]	72358	1			T1	63		T2	35		T12	4
fifo_depth[2]	auto[0]	auto[0]	auto[1]	70930	1			T1	29		T2	14		T10	7
fifo_depth[2]	auto[0]	auto[1]	auto[0]	567664	1			T1	21		T2	32		T13	43
fifo_depth[2]	auto[0]	auto[1]	auto[1]	73332	1			T1	51		T2	12		T13	31
fifo_depth[2]	auto[1]	auto[0]	auto[0]	151080	1			T1	102		T2	12		T7	52
fifo_depth[2]	auto[1]	auto[0]	auto[1]	149548	1			T1	45		T2	56		T10	6
fifo_depth[2]	auto[1]	auto[1]	auto[0]	154167	1			T1	10		T2	30		T10	31
fifo_depth[2]	auto[1]	auto[1]	auto[1]	148721	1			T1	37		T2	54		T7	104
fifo_depth[3]	auto[0]	auto[0]	auto[0]	61062	1			T1	52		T2	13		T12	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	59158	1			T1	38		T2	7		T10	3
fifo_depth[3]	auto[0]	auto[1]	auto[0]	455165	1			T1	8		T2	8		T13	14
fifo_depth[3]	auto[0]	auto[1]	auto[1]	62999	1			T1	46		T2	4		T13	5
fifo_depth[3]	auto[1]	auto[0]	auto[0]	132449	1			T1	97		T2	4		T7	44
fifo_depth[3]	auto[1]	auto[0]	auto[1]	131069	1			T1	43		T2	25		T10	2
fifo_depth[3]	auto[1]	auto[1]	auto[0]	135778	1			T1	14		T2	9		T10	9
fifo_depth[3]	auto[1]	auto[1]	auto[1]	130996	1			T1	37		T2	21		T7	102
fifo_depth[4]	auto[0]	auto[0]	auto[0]	71116	1			T1	52		T2	3		T13	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	68600	1			T1	24		T2	2		T12	2
fifo_depth[4]	auto[0]	auto[1]	auto[0]	357637	1			T1	17		T2	1		T13	1
fifo_depth[4]	auto[0]	auto[1]	auto[1]	72494	1			T1	55		T2	2		T13	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	137763	1			T1	101		T2	1		T7	43
fifo_depth[4]	auto[1]	auto[0]	auto[1]	137905	1			T1	37		T10	1		T7	162
fifo_depth[4]	auto[1]	auto[1]	auto[0]	141506	1			T1	19		T2	1		T10	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	135592	1			T1	40		T2	4		T7	99
fifo_depth[5]	auto[0]	auto[0]	auto[0]	56762	1			T1	41		T13	1		T38	108
fifo_depth[5]	auto[0]	auto[0]	auto[1]	55881	1			T1	39		T2	1		T38	7
fifo_depth[5]	auto[0]	auto[1]	auto[0]	294945	1			T1	15		T13	3		T38	40
fifo_depth[5]	auto[0]	auto[1]	auto[1]	59399	1			T1	64		T2	1		T38	60
fifo_depth[5]	auto[1]	auto[0]	auto[0]	121888	1			T1	110		T7	36		T38	90
fifo_depth[5]	auto[1]	auto[0]	auto[1]	121291	1			T1	41		T7	153		T38	69
fifo_depth[5]	auto[1]	auto[1]	auto[0]	124438	1			T1	14		T7	121		T38	42
fifo_depth[5]	auto[1]	auto[1]	auto[1]	120901	1			T1	39		T7	98		T13	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	66048	1			T1	57		T8	1		T38	219
fifo_depth[6]	auto[0]	auto[0]	auto[1]	63797	1			T1	32		T9	1		T13	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	265742	1			T1	14		T13	1		T38	105
fifo_depth[6]	auto[0]	auto[1]	auto[1]	66782	1			T1	48		T38	133		T4	24
fifo_depth[6]	auto[1]	auto[0]	auto[0]	128833	1			T1	113		T7	45		T38	94
fifo_depth[6]	auto[1]	auto[0]	auto[1]	128172	1			T1	49		T2	1		T7	178
fifo_depth[6]	auto[1]	auto[1]	auto[0]	131735	1			T1	9		T2	1		T7	105
fifo_depth[6]	auto[1]	auto[1]	auto[1]	127567	1			T1	38		T7	96		T8	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	54488	1			T1	47		T38	168		T4	20
fifo_depth[7]	auto[0]	auto[0]	auto[1]	54072	1			T1	29		T4	9		T5	12
fifo_depth[7]	auto[0]	auto[1]	auto[0]	212804	1			T1	12		T38	102		T4	11
fifo_depth[7]	auto[0]	auto[1]	auto[1]	57084	1			T1	37		T38	124		T4	6
fifo_depth[7]	auto[1]	auto[0]	auto[0]	114431	1			T1	87		T7	31		T38	103
fifo_depth[7]	auto[1]	auto[0]	auto[1]	113577	1			T1	28		T7	169		T8	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	114845	1			T1	13		T7	113		T38	97
fifo_depth[7]	auto[1]	auto[1]	auto[1]	112932	1			T1	36		T7	79		T8	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	80217	1			T1	32		T38	196		T4	12
fifo_depth[8]	auto[0]	auto[0]	auto[1]	82126	1			T1	24		T8	1		T38	20
fifo_depth[8]	auto[0]	auto[1]	auto[0]	197606	1			T1	8		T38	157		T4	12
fifo_depth[8]	auto[0]	auto[1]	auto[1]	84668	1			T1	24		T8	1		T38	149
fifo_depth[8]	auto[1]	auto[0]	auto[0]	135020	1			T1	76		T7	31		T38	134
fifo_depth[8]	auto[1]	auto[0]	auto[1]	137782	1			T1	35		T7	137		T8	2
fifo_depth[8]	auto[1]	auto[1]	auto[0]	136929	1			T1	9		T7	93		T8	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	136806	1			T1	44		T7	69		T38	374
fifo_depth[9]	auto[0]	auto[0]	auto[0]	42558	1			T1	19		T9	1		T38	155
fifo_depth[9]	auto[0]	auto[0]	auto[1]	42800	1			T1	14		T8	1		T4	3
fifo_depth[9]	auto[0]	auto[1]	auto[0]	120629	1			T1	9		T8	1		T38	88
fifo_depth[9]	auto[0]	auto[1]	auto[1]	46803	1			T1	36		T38	155		T4	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	81831	1			T1	64		T7	24		T8	3
fifo_depth[9]	auto[1]	auto[0]	auto[1]	83566	1			T1	24		T7	112		T8	2
fifo_depth[9]	auto[1]	auto[1]	auto[0]	81763	1			T1	10		T7	63		T38	185
fifo_depth[9]	auto[1]	auto[1]	auto[1]	81701	1			T1	23		T7	53		T38	87
fifo_depth[10]	auto[0]	auto[0]	auto[0]	53884	1			T1	26		T8	2		T38	202
fifo_depth[10]	auto[0]	auto[0]	auto[1]	54980	1			T1	9		T30	802		T106	2
fifo_depth[10]	auto[0]	auto[1]	auto[0]	100726	1			T1	4		T38	89		T4	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	54279	1			T1	25		T38	149		T4	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	83496	1			T1	52		T7	11		T9	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	83951	1			T1	15		T7	77		T38	81
fifo_depth[10]	auto[1]	auto[1]	auto[0]	81561	1			T1	4		T7	43		T38	145
fifo_depth[10]	auto[1]	auto[1]	auto[1]	80946	1			T1	18		T7	36		T38	271
fifo_depth[11]	auto[0]	auto[0]	auto[0]	31572	1			T1	5		T8	1		T38	101
fifo_depth[11]	auto[0]	auto[0]	auto[1]	32783	1			T1	12		T38	10		T30	505
fifo_depth[11]	auto[0]	auto[1]	auto[0]	60682	1			T1	3		T38	72		T5	1
fifo_depth[11]	auto[0]	auto[1]	auto[1]	36402	1			T1	15		T38	120		T31	4
fifo_depth[11]	auto[1]	auto[0]	auto[0]	49363	1			T1	14		T7	7		T38	101
fifo_depth[11]	auto[1]	auto[0]	auto[1]	52564	1			T1	8		T7	31		T38	84
fifo_depth[11]	auto[1]	auto[1]	auto[0]	47779	1			T1	3		T7	22		T38	125
fifo_depth[11]	auto[1]	auto[1]	auto[1]	50036	1			T1	6		T7	22		T8	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	62918	1			T1	3		T38	299		T30	1793
fifo_depth[12]	auto[0]	auto[0]	auto[1]	68520	1			T1	4		T38	30		T30	1465
fifo_depth[12]	auto[0]	auto[1]	auto[0]	78728	1			T1	1		T38	410		T30	1321
fifo_depth[12]	auto[0]	auto[1]	auto[1]	70300	1			T1	4		T8	1		T38	327
fifo_depth[12]	auto[1]	auto[0]	auto[0]	77080	1			T1	23		T7	3		T8	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	87477	1			T1	2		T7	18		T8	1
fifo_depth[12]	auto[1]	auto[1]	auto[0]	74692	1			T1	3		T7	11		T38	136
fifo_depth[12]	auto[1]	auto[1]	auto[1]	81305	1			T1	5		T7	15		T38	247
fifo_depth[13]	auto[0]	auto[0]	auto[0]	27879	1			T1	2		T38	106		T30	991
fifo_depth[13]	auto[0]	auto[0]	auto[1]	30092	1			T38	10		T30	459		T32	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	36340	1			T38	69		T30	674		T34	135
fifo_depth[13]	auto[0]	auto[1]	auto[1]	35561	1			T1	1		T38	109		T30	344
fifo_depth[13]	auto[1]	auto[0]	auto[0]	34399	1			T1	6		T7	1		T38	101
fifo_depth[13]	auto[1]	auto[0]	auto[1]	38479	1			T7	7		T38	76		T30	597
fifo_depth[13]	auto[1]	auto[1]	auto[0]	31927	1			T7	6		T38	129		T30	818
fifo_depth[13]	auto[1]	auto[1]	auto[1]	37294	1			T1	2		T7	6		T9	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	48377	1			T8	1		T38	441		T30	1392
fifo_depth[14]	auto[0]	auto[0]	auto[1]	54516	1			T1	1		T8	1		T38	10
fifo_depth[14]	auto[0]	auto[1]	auto[0]	54115	1			T8	1		T38	295		T30	1807
fifo_depth[14]	auto[0]	auto[1]	auto[1]	53010	1			T1	1		T9	1		T38	264
fifo_depth[14]	auto[1]	auto[0]	auto[0]	58103	1			T1	1		T9	1		T38	105
fifo_depth[14]	auto[1]	auto[0]	auto[1]	64676	1			T7	5		T38	52		T30	798
fifo_depth[14]	auto[1]	auto[1]	auto[0]	54241	1			T7	2		T38	277		T30	1268
fifo_depth[14]	auto[1]	auto[1]	auto[1]	57711	1			T1	1		T7	1		T8	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	25087	1			T8	2		T38	280		T30	740
fifo_depth[15]	auto[0]	auto[0]	auto[1]	28801	1			T38	10		T30	502		T34	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	30444	1			T8	1		T38	37		T30	1201
fifo_depth[15]	auto[0]	auto[1]	auto[1]	33105	1			T1	2		T38	65		T30	412
fifo_depth[15]	auto[1]	auto[0]	auto[0]	32279	1			T38	101		T30	1139		T33	3
fifo_depth[15]	auto[1]	auto[0]	auto[1]	36694	1			T7	2		T38	75		T30	640
fifo_depth[15]	auto[1]	auto[1]	auto[0]	30236	1			T7	2		T38	293		T30	764
fifo_depth[15]	auto[1]	auto[1]	auto[1]	35232	1			T38	89		T30	962		T32	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	114873	1			T8	1		T38	613		T30	2778
fifo_depth[16]	auto[0]	auto[0]	auto[1]	131260	1			T8	2		T9	1		T38	296
fifo_depth[16]	auto[0]	auto[1]	auto[0]	121844	1			T38	636		T30	3322		T34	7
fifo_depth[16]	auto[0]	auto[1]	auto[1]	126698	1			T38	204		T30	3123		T34	2
fifo_depth[16]	auto[1]	auto[0]	auto[0]	125828	1			T38	3175		T30	2089		T34	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	146378	1			T9	1		T38	839		T30	1701
fifo_depth[16]	auto[1]	auto[1]	auto[0]	134575	1			T7	1		T38	930		T30	2973
fifo_depth[16]	auto[1]	auto[1]	auto[1]	129835	1			T8	1		T38	2767		T30	3025