Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	40852906	1			T16	5		T17	1		T19	8
all_pins[1]	40852906	1			T16	5		T17	1		T19	8
all_pins[2]	40852906	1			T16	5		T17	1		T19	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88603497	1			T16	11		T17	3		T19	20
values[0x1]	33955221	1			T16	4		T19	4		T21	3
transitions[0x0=>0x1]	29914319	1			T16	3		T19	2		T21	3
transitions[0x1=>0x0]	29914340	1			T16	3		T19	2		T21	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	40675650	1			T16	4		T17	1		T19	7
all_pins[0]	values[0x1]	177256	1			T16	1		T19	1		T21	1
all_pins[0]	transitions[0x0=>0x1]	177012	1			T16	1		T21	1		T47	2
all_pins[0]	transitions[0x1=>0x0]	15423988	1			T16	2		T19	1		T21	2
all_pins[1]	values[0x0]	22499152	1			T16	4		T17	1		T19	7
all_pins[1]	values[0x1]	18353754	1			T16	1		T19	1		T47	1
all_pins[1]	transitions[0x0=>0x1]	18215858	1			T47	1		T104	2		T148	1
all_pins[1]	transitions[0x1=>0x0]	39360	1			T21	1		T47	4		T148	3
all_pins[2]	values[0x0]	25428695	1			T16	3		T17	1		T19	6
all_pins[2]	values[0x1]	15424211	1			T16	2		T19	2		T21	2
all_pins[2]	transitions[0x0=>0x1]	11521449	1			T16	2		T19	2		T21	2
all_pins[2]	transitions[0x1=>0x0]	14450992	1			T16	1		T19	1		T47	1