Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4271 1 T16 4 T19 7 T21 4
all_values[1] 4271 1 T16 4 T19 7 T21 4
all_values[2] 4271 1 T16 4 T19 7 T21 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6175 1 T16 7 T19 10 T21 7
auto[1] 6638 1 T16 5 T19 11 T21 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4841 1 T16 7 T19 6 T21 7
auto[1] 7972 1 T16 5 T19 15 T21 5


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7352 1 T16 8 T19 12 T21 9
auto[1] 5461 1 T16 4 T19 9 T21 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 737 1 T19 2 T21 2 T47 1
all_values[0] auto[0] auto[0] auto[1] 437 1 T47 2 T104 1 T148 1
all_values[0] auto[0] auto[1] auto[0] 875 1 T16 2 T19 1 T104 1
all_values[0] auto[0] auto[1] auto[1] 398 1 T19 1 T47 2 T148 2
all_values[0] auto[1] auto[0] auto[1] 888 1 T16 2 T19 2 T47 3
all_values[0] auto[1] auto[1] auto[1] 936 1 T19 1 T21 2 T47 2
all_values[1] auto[0] auto[0] auto[0] 750 1 T16 2 T21 3 T47 3
all_values[1] auto[0] auto[0] auto[1] 448 1 T19 1 T47 1 T148 2
all_values[1] auto[0] auto[1] auto[0] 865 1 T16 1 T19 3 T21 1
all_values[1] auto[0] auto[1] auto[1] 381 1 T19 1 T67 1 T68 2
all_values[1] auto[1] auto[0] auto[1] 891 1 T16 1 T19 1 T47 3
all_values[1] auto[1] auto[1] auto[1] 936 1 T19 1 T47 1 T104 1
all_values[2] auto[0] auto[0] auto[0] 725 1 T16 1 T21 1 T47 4
all_values[2] auto[0] auto[0] auto[1] 433 1 T19 2 T47 1 T104 1
all_values[2] auto[0] auto[1] auto[0] 889 1 T16 1 T148 4 T67 7
all_values[2] auto[0] auto[1] auto[1] 414 1 T16 1 T19 1 T21 2
all_values[2] auto[1] auto[0] auto[1] 866 1 T16 1 T19 2 T21 1
all_values[2] auto[1] auto[1] auto[1] 944 1 T19 2 T104 5 T148 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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