Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.53 98.47 100.00 100.00 99.76 99.49 99.72


Total test records in report: 909
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T760 /workspace/coverage/default/20.hmac_test_sha_vectors.3788217635 Dec 31 12:28:35 PM PST 23 Dec 31 12:34:49 PM PST 23 15797400957 ps
T761 /workspace/coverage/default/5.hmac_test_hmac_vectors.3483471265 Dec 31 12:25:39 PM PST 23 Dec 31 12:25:49 PM PST 23 27093715 ps
T762 /workspace/coverage/default/14.hmac_stress_all.2175726117 Dec 31 12:26:22 PM PST 23 Dec 31 12:44:57 PM PST 23 48325741101 ps
T763 /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.1038889035 Dec 31 12:28:22 PM PST 23 Dec 31 12:31:27 PM PST 23 25918563838 ps
T764 /workspace/coverage/default/25.hmac_burst_wr.1230978183 Dec 31 12:27:36 PM PST 23 Dec 31 12:28:27 PM PST 23 18932041322 ps
T765 /workspace/coverage/default/7.hmac_burst_wr.4230256636 Dec 31 12:27:31 PM PST 23 Dec 31 12:27:54 PM PST 23 1534467446 ps
T766 /workspace/coverage/default/11.hmac_smoke.536138071 Dec 31 12:26:18 PM PST 23 Dec 31 12:26:23 PM PST 23 727502731 ps
T767 /workspace/coverage/default/33.hmac_smoke.2773407639 Dec 31 12:28:26 PM PST 23 Dec 31 12:28:32 PM PST 23 364696206 ps
T768 /workspace/coverage/default/37.hmac_datapath_stress.3690195382 Dec 31 12:27:10 PM PST 23 Dec 31 12:28:19 PM PST 23 1922124119 ps
T769 /workspace/coverage/default/38.hmac_test_hmac_vectors.162221725 Dec 31 12:26:54 PM PST 23 Dec 31 12:26:57 PM PST 23 177044982 ps
T770 /workspace/coverage/default/19.hmac_test_sha_vectors.3699162732 Dec 31 12:27:20 PM PST 23 Dec 31 12:34:04 PM PST 23 108780280899 ps
T771 /workspace/coverage/default/23.hmac_wipe_secret.3299197688 Dec 31 12:27:59 PM PST 23 Dec 31 12:28:32 PM PST 23 3062553510 ps
T772 /workspace/coverage/default/14.hmac_back_pressure.2758049724 Dec 31 12:25:57 PM PST 23 Dec 31 12:26:13 PM PST 23 1427861269 ps
T773 /workspace/coverage/default/37.hmac_long_msg.2485910091 Dec 31 12:27:11 PM PST 23 Dec 31 12:28:03 PM PST 23 14418670834 ps
T774 /workspace/coverage/default/19.hmac_test_hmac_vectors.549740322 Dec 31 12:28:41 PM PST 23 Dec 31 12:28:50 PM PST 23 60397282 ps
T775 /workspace/coverage/default/3.hmac_stress_all.2754845390 Dec 31 12:24:03 PM PST 23 Dec 31 12:47:25 PM PST 23 85324693813 ps
T776 /workspace/coverage/default/41.hmac_wipe_secret.396666331 Dec 31 12:27:36 PM PST 23 Dec 31 12:27:50 PM PST 23 508055088 ps
T777 /workspace/coverage/default/18.hmac_burst_wr.1773806183 Dec 31 12:27:09 PM PST 23 Dec 31 12:27:12 PM PST 23 105471893 ps
T778 /workspace/coverage/default/34.hmac_burst_wr.743304634 Dec 31 12:27:41 PM PST 23 Dec 31 12:27:51 PM PST 23 2723394456 ps
T779 /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.2544106274 Dec 31 12:28:04 PM PST 23 Dec 31 12:40:27 PM PST 23 44171262399 ps
T780 /workspace/coverage/default/22.hmac_back_pressure.975850266 Dec 31 12:26:55 PM PST 23 Dec 31 12:27:03 PM PST 23 487242842 ps
T781 /workspace/coverage/default/2.hmac_test_hmac_vectors.2992309212 Dec 31 12:26:33 PM PST 23 Dec 31 12:26:36 PM PST 23 79980683 ps
T782 /workspace/coverage/default/10.hmac_stress_all.2994214258 Dec 31 12:28:02 PM PST 23 Dec 31 12:36:40 PM PST 23 18881282582 ps
T783 /workspace/coverage/default/20.hmac_back_pressure.2209541028 Dec 31 12:26:52 PM PST 23 Dec 31 12:27:00 PM PST 23 227760975 ps
T784 /workspace/coverage/default/33.hmac_burst_wr.1141476322 Dec 31 12:27:02 PM PST 23 Dec 31 12:27:31 PM PST 23 1218644716 ps
T785 /workspace/coverage/default/31.hmac_error.491432449 Dec 31 12:28:12 PM PST 23 Dec 31 12:28:37 PM PST 23 1006913588 ps
T786 /workspace/coverage/default/10.hmac_wipe_secret.2313777122 Dec 31 12:26:33 PM PST 23 Dec 31 12:27:47 PM PST 23 8788860662 ps
T787 /workspace/coverage/default/23.hmac_test_sha_vectors.715711644 Dec 31 12:26:54 PM PST 23 Dec 31 12:32:59 PM PST 23 7500830343 ps
T788 /workspace/coverage/default/35.hmac_back_pressure.751106604 Dec 31 12:26:57 PM PST 23 Dec 31 12:27:43 PM PST 23 1524755984 ps
T789 /workspace/coverage/default/21.hmac_alert_test.2051343424 Dec 31 12:30:06 PM PST 23 Dec 31 12:30:09 PM PST 23 27980308 ps
T790 /workspace/coverage/default/30.hmac_stress_all.1225457324 Dec 31 12:29:03 PM PST 23 Dec 31 12:50:49 PM PST 23 87125505309 ps
T791 /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.147066220 Dec 31 12:27:15 PM PST 23 Dec 31 12:49:23 PM PST 23 160909977745 ps
T792 /workspace/coverage/default/2.hmac_long_msg.2235510231 Dec 31 12:25:23 PM PST 23 Dec 31 12:26:27 PM PST 23 4931187617 ps
T793 /workspace/coverage/default/1.hmac_datapath_stress.815395928 Dec 31 12:23:26 PM PST 23 Dec 31 12:25:02 PM PST 23 3973177708 ps
T794 /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.474058470 Dec 31 12:28:25 PM PST 23 Dec 31 12:44:42 PM PST 23 55419078700 ps
T795 /workspace/coverage/default/13.hmac_alert_test.3231402459 Dec 31 12:27:39 PM PST 23 Dec 31 12:27:41 PM PST 23 29685323 ps
T796 /workspace/coverage/default/36.hmac_burst_wr.1160430999 Dec 31 12:27:40 PM PST 23 Dec 31 12:28:20 PM PST 23 824188039 ps
T797 /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3174558456 Dec 31 12:27:29 PM PST 23 Dec 31 01:01:47 PM PST 23 144640987513 ps
T798 /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.302747042 Dec 31 12:28:58 PM PST 23 Dec 31 12:32:29 PM PST 23 17624732219 ps
T799 /workspace/coverage/default/49.hmac_error.3408120111 Dec 31 12:27:59 PM PST 23 Dec 31 12:28:30 PM PST 23 1616027594 ps
T800 /workspace/coverage/default/28.hmac_test_sha_vectors.741128770 Dec 31 12:26:41 PM PST 23 Dec 31 12:33:29 PM PST 23 118851200245 ps
T801 /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.262573448 Dec 31 12:27:30 PM PST 23 Dec 31 12:44:55 PM PST 23 288974375599 ps
T802 /workspace/coverage/default/6.hmac_burst_wr.4166012633 Dec 31 12:27:03 PM PST 23 Dec 31 12:27:46 PM PST 23 1868244603 ps
T803 /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.3849361736 Dec 31 12:27:11 PM PST 23 Dec 31 12:32:07 PM PST 23 16853747286 ps
T804 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.749211549 Dec 31 12:28:34 PM PST 23 Dec 31 01:10:52 PM PST 23 275434210272 ps
T805 /workspace/coverage/default/5.hmac_test_sha_vectors.1516599552 Dec 31 12:27:29 PM PST 23 Dec 31 12:33:19 PM PST 23 7207720784 ps
T806 /workspace/coverage/default/23.hmac_test_hmac_vectors.2581296499 Dec 31 12:27:00 PM PST 23 Dec 31 12:27:04 PM PST 23 219686137 ps
T807 /workspace/coverage/default/0.hmac_smoke.2171458665 Dec 31 12:25:40 PM PST 23 Dec 31 12:25:53 PM PST 23 1107715355 ps
T808 /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3008093555 Dec 31 12:29:44 PM PST 23 Dec 31 12:34:09 PM PST 23 31865567228 ps
T809 /workspace/coverage/default/31.hmac_datapath_stress.3987998040 Dec 31 12:27:18 PM PST 23 Dec 31 12:29:01 PM PST 23 2149514537 ps
T810 /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3868445037 Dec 31 12:29:58 PM PST 23 Dec 31 12:50:07 PM PST 23 97301678615 ps
T811 /workspace/coverage/default/34.hmac_error.2995098593 Dec 31 12:27:12 PM PST 23 Dec 31 12:29:03 PM PST 23 2513305997 ps
T812 /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2098563355 Dec 31 12:27:52 PM PST 23 Dec 31 12:48:27 PM PST 23 330174452438 ps
T813 /workspace/coverage/default/8.hmac_long_msg.1061249371 Dec 31 12:27:24 PM PST 23 Dec 31 12:28:45 PM PST 23 1655976736 ps
T814 /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1788129511 Dec 31 12:27:47 PM PST 23 Dec 31 12:31:08 PM PST 23 60482441059 ps
T815 /workspace/coverage/default/16.hmac_burst_wr.1723723084 Dec 31 12:26:27 PM PST 23 Dec 31 12:27:02 PM PST 23 12028032613 ps
T816 /workspace/coverage/default/30.hmac_wipe_secret.2377847753 Dec 31 12:27:45 PM PST 23 Dec 31 12:27:53 PM PST 23 1994503684 ps
T817 /workspace/coverage/default/32.hmac_wipe_secret.1493652282 Dec 31 12:26:40 PM PST 23 Dec 31 12:27:25 PM PST 23 4683541720 ps
T818 /workspace/coverage/default/41.hmac_datapath_stress.1215423884 Dec 31 12:28:30 PM PST 23 Dec 31 12:29:46 PM PST 23 5159182645 ps
T819 /workspace/coverage/default/25.hmac_stress_all.2597701280 Dec 31 12:27:34 PM PST 23 Dec 31 12:34:09 PM PST 23 32723158553 ps
T820 /workspace/coverage/default/43.hmac_test_hmac_vectors.1053701900 Dec 31 12:28:29 PM PST 23 Dec 31 12:28:41 PM PST 23 232066332 ps
T821 /workspace/coverage/default/10.hmac_burst_wr.2281498661 Dec 31 12:29:05 PM PST 23 Dec 31 12:29:38 PM PST 23 2778307605 ps
T822 /workspace/coverage/default/12.hmac_back_pressure.355298035 Dec 31 12:26:54 PM PST 23 Dec 31 12:27:55 PM PST 23 6664279761 ps
T823 /workspace/coverage/default/45.hmac_long_msg.1895856001 Dec 31 12:27:23 PM PST 23 Dec 31 12:28:51 PM PST 23 5452686207 ps
T824 /workspace/coverage/default/44.hmac_test_hmac_vectors.2169534307 Dec 31 12:27:06 PM PST 23 Dec 31 12:27:10 PM PST 23 119954680 ps
T825 /workspace/coverage/default/19.hmac_long_msg.3016710734 Dec 31 12:27:11 PM PST 23 Dec 31 12:28:29 PM PST 23 22385104575 ps
T826 /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3275656842 Dec 31 12:28:05 PM PST 23 Dec 31 12:42:37 PM PST 23 91727716087 ps
T827 /workspace/coverage/default/18.hmac_back_pressure.1557455507 Dec 31 12:27:39 PM PST 23 Dec 31 12:27:56 PM PST 23 1024087387 ps
T828 /workspace/coverage/default/27.hmac_datapath_stress.3362860462 Dec 31 12:27:06 PM PST 23 Dec 31 12:27:54 PM PST 23 921940672 ps
T829 /workspace/coverage/default/39.hmac_back_pressure.2822108118 Dec 31 12:27:17 PM PST 23 Dec 31 12:27:49 PM PST 23 2389806155 ps
T830 /workspace/coverage/default/39.hmac_smoke.520430547 Dec 31 12:27:08 PM PST 23 Dec 31 12:27:11 PM PST 23 115664608 ps
T831 /workspace/coverage/default/0.hmac_alert_test.2316946493 Dec 31 12:23:37 PM PST 23 Dec 31 12:23:41 PM PST 23 31692027 ps
T832 /workspace/coverage/default/46.hmac_test_hmac_vectors.4110863025 Dec 31 12:29:38 PM PST 23 Dec 31 12:29:41 PM PST 23 189368761 ps
T833 /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3213630847 Dec 31 12:27:54 PM PST 23 Dec 31 12:34:01 PM PST 23 55079183008 ps
T834 /workspace/coverage/default/6.hmac_datapath_stress.2012749110 Dec 31 12:25:49 PM PST 23 Dec 31 12:27:00 PM PST 23 2426506198 ps
T835 /workspace/coverage/default/39.hmac_alert_test.826650646 Dec 31 12:28:53 PM PST 23 Dec 31 12:28:59 PM PST 23 21649830 ps
T836 /workspace/coverage/default/32.hmac_test_hmac_vectors.4006056005 Dec 31 12:29:13 PM PST 23 Dec 31 12:29:19 PM PST 23 100604416 ps
T837 /workspace/coverage/default/43.hmac_stress_all.2926175800 Dec 31 12:27:14 PM PST 23 Dec 31 12:32:16 PM PST 23 94120576578 ps
T838 /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.2308424338 Dec 31 12:28:23 PM PST 23 Dec 31 12:41:16 PM PST 23 62232590446 ps
T839 /workspace/coverage/default/23.hmac_datapath_stress.935128648 Dec 31 12:26:30 PM PST 23 Dec 31 12:26:42 PM PST 23 864281664 ps
T840 /workspace/coverage/default/11.hmac_stress_all.2608320826 Dec 31 12:28:32 PM PST 23 Dec 31 12:40:24 PM PST 23 87112835391 ps
T841 /workspace/coverage/default/21.hmac_back_pressure.4029284023 Dec 31 12:26:46 PM PST 23 Dec 31 12:27:24 PM PST 23 12547032204 ps
T842 /workspace/coverage/default/15.hmac_wipe_secret.3683474906 Dec 31 12:27:58 PM PST 23 Dec 31 12:28:44 PM PST 23 2375804266 ps
T843 /workspace/coverage/default/14.hmac_burst_wr.3073139294 Dec 31 12:26:45 PM PST 23 Dec 31 12:27:25 PM PST 23 11106013485 ps
T844 /workspace/coverage/default/6.hmac_error.1087370693 Dec 31 12:26:32 PM PST 23 Dec 31 12:27:19 PM PST 23 5530199952 ps
T845 /workspace/coverage/default/19.hmac_smoke.3604377680 Dec 31 12:26:24 PM PST 23 Dec 31 12:26:32 PM PST 23 42156386 ps
T846 /workspace/coverage/default/4.hmac_test_hmac_vectors.2228144048 Dec 31 12:24:21 PM PST 23 Dec 31 12:24:25 PM PST 23 52129766 ps
T847 /workspace/coverage/default/28.hmac_back_pressure.1267795903 Dec 31 12:26:45 PM PST 23 Dec 31 12:27:07 PM PST 23 7152243299 ps
T848 /workspace/coverage/default/38.hmac_long_msg.547532898 Dec 31 12:28:13 PM PST 23 Dec 31 12:29:50 PM PST 23 31723413523 ps
T849 /workspace/coverage/default/43.hmac_test_sha_vectors.28751873 Dec 31 12:28:07 PM PST 23 Dec 31 12:34:31 PM PST 23 29540419961 ps
T850 /workspace/coverage/default/37.hmac_back_pressure.376333770 Dec 31 12:28:16 PM PST 23 Dec 31 12:28:42 PM PST 23 3082297527 ps
T851 /workspace/coverage/default/46.hmac_stress_all.2136822912 Dec 31 12:26:54 PM PST 23 Dec 31 12:29:25 PM PST 23 47744420049 ps
T852 /workspace/coverage/default/8.hmac_burst_wr.1838200920 Dec 31 12:27:01 PM PST 23 Dec 31 12:27:12 PM PST 23 246096226 ps
T853 /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.2015281448 Dec 31 12:28:05 PM PST 23 Dec 31 01:18:27 PM PST 23 339441288943 ps
T854 /workspace/coverage/default/43.hmac_alert_test.1372920373 Dec 31 12:28:11 PM PST 23 Dec 31 12:28:14 PM PST 23 72616772 ps
T855 /workspace/coverage/default/33.hmac_wipe_secret.778884345 Dec 31 12:27:56 PM PST 23 Dec 31 12:29:05 PM PST 23 8345135471 ps
T856 /workspace/coverage/default/15.hmac_long_msg.533317781 Dec 31 12:28:05 PM PST 23 Dec 31 12:28:46 PM PST 23 8444752828 ps
T143 /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.789944776 Dec 31 12:28:42 PM PST 23 Dec 31 01:16:19 PM PST 23 239270783923 ps
T857 /workspace/coverage/default/29.hmac_test_hmac_vectors.2854143905 Dec 31 12:26:30 PM PST 23 Dec 31 12:26:33 PM PST 23 65124464 ps
T858 /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.359773769 Dec 31 12:27:42 PM PST 23 Dec 31 12:49:36 PM PST 23 28961641288 ps
T859 /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.857660192 Dec 31 12:27:55 PM PST 23 Dec 31 12:35:42 PM PST 23 24069926174 ps
T860 /workspace/coverage/default/4.hmac_back_pressure.2527025884 Dec 31 12:20:16 PM PST 23 Dec 31 12:20:56 PM PST 23 1408792122 ps
T861 /workspace/coverage/default/22.hmac_wipe_secret.1197125946 Dec 31 12:28:54 PM PST 23 Dec 31 12:30:10 PM PST 23 8912979783 ps
T862 /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.4294061802 Dec 31 12:27:25 PM PST 23 Dec 31 01:20:21 PM PST 23 134307215606 ps
T863 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2571498605 Dec 31 12:25:30 PM PST 23 Dec 31 12:25:38 PM PST 23 13544593 ps
T86 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1922201771 Dec 31 12:27:40 PM PST 23 Dec 31 12:27:43 PM PST 23 141348880 ps
T864 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3449992114 Dec 31 12:22:55 PM PST 23 Dec 31 12:23:05 PM PST 23 2700510350 ps
T865 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4060317111 Dec 31 12:24:43 PM PST 23 Dec 31 12:24:54 PM PST 23 206456703 ps
T866 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1606882780 Dec 31 12:19:16 PM PST 23 Dec 31 12:19:20 PM PST 23 537176572 ps
T87 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.302479171 Dec 31 12:22:52 PM PST 23 Dec 31 12:22:54 PM PST 23 46948149 ps
T867 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3837793563 Dec 31 12:22:29 PM PST 23 Dec 31 12:22:32 PM PST 23 161525188 ps
T868 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3357910643 Dec 31 12:27:22 PM PST 23 Dec 31 12:27:23 PM PST 23 11163086 ps
T869 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1984835149 Dec 31 12:24:05 PM PST 23 Dec 31 12:24:11 PM PST 23 46878472 ps
T149 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1964662755 Dec 31 12:21:17 PM PST 23 Dec 31 12:21:20 PM PST 23 1400712148 ps
T870 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3509484960 Dec 31 12:25:07 PM PST 23 Dec 31 12:25:11 PM PST 23 25178071 ps
T871 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3183525398 Dec 31 12:24:05 PM PST 23 Dec 31 12:24:11 PM PST 23 39989814 ps
T872 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3226176364 Dec 31 12:25:17 PM PST 23 Dec 31 12:25:22 PM PST 23 55312434 ps
T873 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2257710241 Dec 31 12:26:39 PM PST 23 Dec 31 12:26:40 PM PST 23 34905704 ps
T154 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3114954020 Dec 31 12:24:22 PM PST 23 Dec 31 12:24:27 PM PST 23 108622450 ps
T874 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1490338061 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 248295679 ps
T875 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2880493545 Dec 31 12:24:32 PM PST 23 Dec 31 12:24:37 PM PST 23 96244395 ps
T876 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1839513369 Dec 31 12:25:25 PM PST 23 Dec 31 12:25:32 PM PST 23 82256533 ps
T877 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3912467609 Dec 31 12:24:28 PM PST 23 Dec 31 12:24:31 PM PST 23 21747530 ps
T878 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2288940301 Dec 31 12:25:46 PM PST 23 Dec 31 12:25:54 PM PST 23 21156495 ps
T879 /workspace/coverage/cover_reg_top/39.hmac_intr_test.515295723 Dec 31 12:23:55 PM PST 23 Dec 31 12:24:02 PM PST 23 11262382 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.675602323 Dec 31 12:28:17 PM PST 23 Dec 31 12:28:25 PM PST 23 674457535 ps
T880 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4213386799 Dec 31 12:23:24 PM PST 23 Dec 31 12:23:28 PM PST 23 240397680 ps
T881 /workspace/coverage/cover_reg_top/36.hmac_intr_test.455772817 Dec 31 12:27:49 PM PST 23 Dec 31 12:27:51 PM PST 23 53451668 ps
T882 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2298006486 Dec 31 12:22:56 PM PST 23 Dec 31 12:22:59 PM PST 23 48926041 ps
T883 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3997925176 Dec 31 12:25:24 PM PST 23 Dec 31 12:25:31 PM PST 23 376740348 ps
T884 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3374811760 Dec 31 12:22:54 PM PST 23 Dec 31 12:22:56 PM PST 23 13019480 ps
T885 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1144003593 Dec 31 12:20:38 PM PST 23 Dec 31 12:20:41 PM PST 23 446221307 ps
T886 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1525494477 Dec 31 12:23:23 PM PST 23 Dec 31 12:23:24 PM PST 23 25077579 ps
T887 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1043956480 Dec 31 12:26:00 PM PST 23 Dec 31 12:26:08 PM PST 23 393684948 ps
T888 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.556819423 Dec 31 12:23:42 PM PST 23 Dec 31 12:23:47 PM PST 23 76293764 ps
T889 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3760038714 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:37 PM PST 23 157260742 ps
T890 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3492023586 Dec 31 12:28:43 PM PST 23 Dec 31 12:28:51 PM PST 23 37987029 ps
T891 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2494308320 Dec 31 12:26:55 PM PST 23 Dec 31 12:26:58 PM PST 23 229403404 ps
T892 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2112579577 Dec 31 12:26:36 PM PST 23 Dec 31 12:26:38 PM PST 23 46703185 ps
T893 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2208730667 Dec 31 12:20:06 PM PST 23 Dec 31 12:20:08 PM PST 23 109583095 ps
T894 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1439082397 Dec 31 12:25:21 PM PST 23 Dec 31 12:25:25 PM PST 23 48035543 ps
T89 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1073384124 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:34 PM PST 23 86361663 ps
T895 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3539192318 Dec 31 12:22:00 PM PST 23 Dec 31 12:22:05 PM PST 23 15507201 ps
T896 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.173563001 Dec 31 12:25:06 PM PST 23 Dec 31 12:25:11 PM PST 23 121462831 ps
T150 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2035995775 Dec 31 12:23:06 PM PST 23 Dec 31 12:23:09 PM PST 23 185088276 ps
T897 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2555068572 Dec 31 12:22:51 PM PST 23 Dec 31 12:22:52 PM PST 23 15011234 ps
T898 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2348555044 Dec 31 12:22:51 PM PST 23 Dec 31 12:22:53 PM PST 23 136037939 ps
T899 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4037967183 Dec 31 12:25:38 PM PST 23 Dec 31 12:25:56 PM PST 23 1801630382 ps
T900 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4076026142 Dec 31 12:25:55 PM PST 23 Dec 31 12:26:03 PM PST 23 30586861 ps
T901 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.719812282 Dec 31 12:24:22 PM PST 23 Dec 31 12:24:26 PM PST 23 83272368 ps
T902 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1352361639 Dec 31 12:25:26 PM PST 23 Dec 31 12:25:34 PM PST 23 167837577 ps
T903 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.348901302 Dec 31 12:21:30 PM PST 23 Dec 31 12:21:37 PM PST 23 664740591 ps
T904 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.66743571 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:23 PM PST 23 56803265 ps
T905 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1020011804 Dec 31 12:24:24 PM PST 23 Dec 31 12:24:28 PM PST 23 22648196 ps
T906 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2954023827 Dec 31 12:27:44 PM PST 23 Dec 31 12:27:45 PM PST 23 42009168 ps
T90 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4168880990 Dec 31 12:22:50 PM PST 23 Dec 31 12:22:51 PM PST 23 68999360 ps
T907 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3789265850 Dec 31 12:25:07 PM PST 23 Dec 31 12:25:11 PM PST 23 54265946 ps
T908 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4145360108 Dec 31 12:29:49 PM PST 23 Dec 31 12:29:52 PM PST 23 36181616 ps
T909 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3618414512 Dec 31 12:21:18 PM PST 23 Dec 31 12:21:21 PM PST 23 59660931 ps

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1782096536
Short name T14
Test name
Test status
Simulation time 65248582 ps
CPU time 0.69 seconds
Started Dec 31 12:23:00 PM PST 23
Finished Dec 31 12:23:02 PM PST 23
Peak memory 194044 kb
Host smart-de0beac5-4ada-4364-8d31-0d6fd54cb420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782096536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1782096536
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2993184129
Short name T1
Test name
Test status
Simulation time 3040776585 ps
CPU time 27.47 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 198648 kb
Host smart-cd0ae23c-bb2f-4000-8bfb-e337fdf738d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993184129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2993184129
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3608434573
Short name T22
Test name
Test status
Simulation time 572654954 ps
CPU time 2.26 seconds
Started Dec 31 12:25:05 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 197196 kb
Host smart-095bc3d6-46a6-4740-8299-1c21fb02e1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608434573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3608434573
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.722723922
Short name T30
Test name
Test status
Simulation time 71773675737 ps
CPU time 3173.52 seconds
Started Dec 31 12:30:20 PM PST 23
Finished Dec 31 01:23:19 PM PST 23
Peak memory 264268 kb
Host smart-023c6691-657d-4a24-9d3b-69953d242b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722723922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.722723922
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3151883892
Short name T47
Test name
Test status
Simulation time 16619422 ps
CPU time 0.63 seconds
Started Dec 31 12:19:13 PM PST 23
Finished Dec 31 12:19:14 PM PST 23
Peak memory 183536 kb
Host smart-9b02ac52-9123-4943-9989-293a4b916b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151883892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3151883892
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1020025546
Short name T17
Test name
Test status
Simulation time 148887382 ps
CPU time 2.34 seconds
Started Dec 31 12:34:34 PM PST 23
Finished Dec 31 12:34:39 PM PST 23
Peak memory 198400 kb
Host smart-cbeae9f2-2905-488d-b6b4-f1841679f384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020025546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1020025546
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.68536795
Short name T4
Test name
Test status
Simulation time 20350709328 ps
CPU time 361.36 seconds
Started Dec 31 12:28:23 PM PST 23
Finished Dec 31 12:34:26 PM PST 23
Peak memory 231648 kb
Host smart-3b84d2c7-5857-4ff8-82bc-315073721377
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68536795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.68536795
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1423465646
Short name T111
Test name
Test status
Simulation time 266526978352 ps
CPU time 5776.14 seconds
Started Dec 31 12:27:37 PM PST 23
Finished Dec 31 02:03:54 PM PST 23
Peak memory 274576 kb
Host smart-c47d7dc5-c5a6-4eca-93f3-c775c31c8535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423465646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.1423465646
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3779302554
Short name T48
Test name
Test status
Simulation time 91723800 ps
CPU time 0.97 seconds
Started Dec 31 12:19:25 PM PST 23
Finished Dec 31 12:19:28 PM PST 23
Peak memory 216952 kb
Host smart-f411cddd-abb5-4c47-a330-2bb69066d865
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779302554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3779302554
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1640082183
Short name T126
Test name
Test status
Simulation time 551222974515 ps
CPU time 4097.4 seconds
Started Dec 31 12:28:03 PM PST 23
Finished Dec 31 01:36:29 PM PST 23
Peak memory 255756 kb
Host smart-a1e487e8-cede-462b-8c88-36da8b924509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640082183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.1640082183
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2964019077
Short name T156
Test name
Test status
Simulation time 16652847 ps
CPU time 0.79 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 198168 kb
Host smart-f5b6334d-126a-44a3-8dd3-0ac062b426f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964019077 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2964019077
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2392867262
Short name T165
Test name
Test status
Simulation time 39105948 ps
CPU time 0.54 seconds
Started Dec 31 12:24:55 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 183464 kb
Host smart-384437b7-b77c-4411-9c87-314273ec7b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392867262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2392867262
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4223624468
Short name T85
Test name
Test status
Simulation time 65476912 ps
CPU time 0.65 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 193944 kb
Host smart-c5e11d2e-825f-42e8-97aa-9ac1a983a436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223624468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4223624468
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2035995775
Short name T150
Test name
Test status
Simulation time 185088276 ps
CPU time 2.48 seconds
Started Dec 31 12:23:06 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 196412 kb
Host smart-4a24da58-90a6-4c3f-8cc8-5b78a4646aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035995775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2035995775
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.2840788160
Short name T138
Test name
Test status
Simulation time 192778831259 ps
CPU time 2193.31 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 01:04:03 PM PST 23
Peak memory 241616 kb
Host smart-641fa885-a404-4cc5-8dfa-011f2526f7c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840788160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.2840788160
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.4166081107
Short name T34
Test name
Test status
Simulation time 68473118022 ps
CPU time 3041.37 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 01:18:43 PM PST 23
Peak memory 224816 kb
Host smart-f4c3faf9-7009-4a4b-aa9b-ba40bc9071c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166081107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.4166081107
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.789944776
Short name T143
Test name
Test status
Simulation time 239270783923 ps
CPU time 2850.07 seconds
Started Dec 31 12:28:42 PM PST 23
Finished Dec 31 01:16:19 PM PST 23
Peak memory 263636 kb
Host smart-9acd3a37-2b59-4d61-9bd0-478db40e4e73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789944776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.789944776
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3421543427
Short name T101
Test name
Test status
Simulation time 16719972 ps
CPU time 0.77 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:57 PM PST 23
Peak memory 195068 kb
Host smart-b833c13c-f133-49b9-9c97-c23bf24e669f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421543427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3421543427
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3458068453
Short name T2
Test name
Test status
Simulation time 7940555721 ps
CPU time 82.14 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:24:49 PM PST 23
Peak memory 198460 kb
Host smart-50e46f2c-ede5-4702-ba06-97e74ee6c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458068453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3458068453
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1261236496
Short name T234
Test name
Test status
Simulation time 42766583 ps
CPU time 0.56 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 193304 kb
Host smart-09643459-ac17-4fb5-801f-faed12f72809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261236496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1261236496
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.516708495
Short name T61
Test name
Test status
Simulation time 112905821 ps
CPU time 2.3 seconds
Started Dec 31 12:19:30 PM PST 23
Finished Dec 31 12:19:33 PM PST 23
Peak memory 198496 kb
Host smart-2bb5fef1-6b55-4b2a-b236-87af1a137116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516708495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.516708495
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.374003957
Short name T714
Test name
Test status
Simulation time 501798656073 ps
CPU time 1075.11 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:45:31 PM PST 23
Peak memory 241820 kb
Host smart-2f7edf72-9ea9-49bb-aadc-4eb6090c9eb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374003957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.374003957
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.607175121
Short name T125
Test name
Test status
Simulation time 55800596741 ps
CPU time 848.57 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:41:44 PM PST 23
Peak memory 215188 kb
Host smart-bde3de74-b16a-4ac8-93c4-9f61907b02b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607175121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.607175121
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.4032217627
Short name T745
Test name
Test status
Simulation time 1142649688871 ps
CPU time 7897.06 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 02:38:53 PM PST 23
Peak memory 280532 kb
Host smart-1f4cf977-dfe8-4c82-8774-8f849928d9f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032217627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.4032217627
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2425412907
Short name T114
Test name
Test status
Simulation time 183208901213 ps
CPU time 2127.01 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 01:02:42 PM PST 23
Peak memory 245128 kb
Host smart-6def0a11-b360-47dd-b04f-1365aae756f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425412907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2425412907
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3803291241
Short name T78
Test name
Test status
Simulation time 347199995 ps
CPU time 1.82 seconds
Started Dec 31 12:28:30 PM PST 23
Finished Dec 31 12:28:42 PM PST 23
Peak memory 192032 kb
Host smart-d8ac2e11-f166-4652-b183-a55855f84d86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803291241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3803291241
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.675602323
Short name T88
Test name
Test status
Simulation time 674457535 ps
CPU time 6.43 seconds
Started Dec 31 12:28:17 PM PST 23
Finished Dec 31 12:28:25 PM PST 23
Peak memory 191984 kb
Host smart-31dba9bf-39c1-4fc2-b9d7-c00a23422641
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675602323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.675602323
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.831955065
Short name T195
Test name
Test status
Simulation time 18566602 ps
CPU time 0.62 seconds
Started Dec 31 12:24:50 PM PST 23
Finished Dec 31 12:24:56 PM PST 23
Peak memory 193144 kb
Host smart-0fdb1eb4-7838-4d05-b4ed-45ab8189bfb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831955065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.831955065
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.4242405339
Short name T203
Test name
Test status
Simulation time 21552463 ps
CPU time 0.56 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:58 PM PST 23
Peak memory 183572 kb
Host smart-8de636c1-1507-4d6a-88d9-a3c56e51795d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242405339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.4242405339
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1144003593
Short name T885
Test name
Test status
Simulation time 446221307 ps
CPU time 2.13 seconds
Started Dec 31 12:20:38 PM PST 23
Finished Dec 31 12:20:41 PM PST 23
Peak memory 198700 kb
Host smart-6ae0bfa6-ea5d-466c-9a4c-751578d9de28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144003593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1144003593
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2494308320
Short name T891
Test name
Test status
Simulation time 229403404 ps
CPU time 2.15 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:26:58 PM PST 23
Peak memory 198072 kb
Host smart-792ddf94-75b5-4d24-8758-70d8bf818d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494308320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2494308320
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1922201771
Short name T86
Test name
Test status
Simulation time 141348880 ps
CPU time 1.6 seconds
Started Dec 31 12:27:40 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 191980 kb
Host smart-6562f5ae-70f4-4938-9242-11406769ef1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922201771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1922201771
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4222451420
Short name T70
Test name
Test status
Simulation time 1630943731 ps
CPU time 8.68 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:27:08 PM PST 23
Peak memory 191936 kb
Host smart-6b6b225b-a0f0-4662-a7b2-6bfced61e8c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222451420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4222451420
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3970354446
Short name T187
Test name
Test status
Simulation time 17009047 ps
CPU time 0.64 seconds
Started Dec 31 12:20:26 PM PST 23
Finished Dec 31 12:20:27 PM PST 23
Peak memory 193312 kb
Host smart-c32f52c8-9f9f-4a33-9ffe-468e070096d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970354446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3970354446
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2208730667
Short name T893
Test name
Test status
Simulation time 109583095 ps
CPU time 1.46 seconds
Started Dec 31 12:20:06 PM PST 23
Finished Dec 31 12:20:08 PM PST 23
Peak memory 198412 kb
Host smart-60f2abd2-a0bf-4971-8374-c16b4f041736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208730667 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2208730667
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.679771630
Short name T176
Test name
Test status
Simulation time 23428991 ps
CPU time 0.7 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:26:38 PM PST 23
Peak memory 194660 kb
Host smart-24af253f-11ea-4f5d-8d54-c0e1c27537f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679771630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.679771630
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3374811760
Short name T884
Test name
Test status
Simulation time 13019480 ps
CPU time 0.55 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 183520 kb
Host smart-7e75d6d9-e2ae-4eac-80f9-92695743cdd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374811760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3374811760
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1385453559
Short name T98
Test name
Test status
Simulation time 54355869 ps
CPU time 0.83 seconds
Started Dec 31 12:21:25 PM PST 23
Finished Dec 31 12:21:27 PM PST 23
Peak memory 194960 kb
Host smart-9e17dafa-bec7-40c7-ac02-916bb96d71d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385453559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1385453559
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.31294364
Short name T194
Test name
Test status
Simulation time 161094247 ps
CPU time 1.21 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198408 kb
Host smart-ee843c97-c5ce-4e67-ba92-2f13fe27e392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.31294364
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1276848563
Short name T190
Test name
Test status
Simulation time 576077263 ps
CPU time 1.62 seconds
Started Dec 31 12:29:40 PM PST 23
Finished Dec 31 12:29:43 PM PST 23
Peak memory 198392 kb
Host smart-01bcd9cc-5265-4814-9a02-988a7572c5c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276848563 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1276848563
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3123637105
Short name T174
Test name
Test status
Simulation time 68809003 ps
CPU time 0.77 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:40 PM PST 23
Peak memory 193648 kb
Host smart-9bdd55b1-5bc6-4064-bcbf-4ff9f0fb787f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123637105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3123637105
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1068599188
Short name T182
Test name
Test status
Simulation time 13121058 ps
CPU time 0.55 seconds
Started Dec 31 12:20:33 PM PST 23
Finished Dec 31 12:20:34 PM PST 23
Peak memory 183472 kb
Host smart-537516d0-5629-4253-8dfc-8f572870de4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068599188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1068599188
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.450270542
Short name T161
Test name
Test status
Simulation time 38534866 ps
CPU time 1.04 seconds
Started Dec 31 12:18:22 PM PST 23
Finished Dec 31 12:18:24 PM PST 23
Peak memory 190972 kb
Host smart-4b676415-9caa-49a0-9b5c-53002300523f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450270542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.450270542
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3201296564
Short name T63
Test name
Test status
Simulation time 138551249 ps
CPU time 1.01 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 197612 kb
Host smart-7c4467f9-6fc7-4974-9dea-0ca536852cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201296564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3201296564
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1758965786
Short name T28
Test name
Test status
Simulation time 15974170 ps
CPU time 1.07 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 195936 kb
Host smart-28fac2a5-6c59-4816-854c-3cb3b8b7cfc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758965786 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1758965786
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1896468807
Short name T16
Test name
Test status
Simulation time 43454875 ps
CPU time 0.6 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:07 PM PST 23
Peak memory 181664 kb
Host smart-0395eb10-13df-4c40-8525-24407a712f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896468807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1896468807
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4240687349
Short name T102
Test name
Test status
Simulation time 80530280 ps
CPU time 1 seconds
Started Dec 31 12:24:31 PM PST 23
Finished Dec 31 12:24:35 PM PST 23
Peak memory 191148 kb
Host smart-cd7ebc92-240d-4fb5-8e08-f51c3b2a0ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240687349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4240687349
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.198365489
Short name T23
Test name
Test status
Simulation time 1049833889 ps
CPU time 1.76 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:29 PM PST 23
Peak memory 198368 kb
Host smart-d4580725-9dcf-4768-adeb-e1f640da7215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198365489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.198365489
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2027376024
Short name T151
Test name
Test status
Simulation time 192445637 ps
CPU time 1.21 seconds
Started Dec 31 12:19:06 PM PST 23
Finished Dec 31 12:19:08 PM PST 23
Peak memory 198284 kb
Host smart-d750d32e-ff2e-424f-9f74-4055a9bb0571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027376024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2027376024
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2880493545
Short name T875
Test name
Test status
Simulation time 96244395 ps
CPU time 1.76 seconds
Started Dec 31 12:24:32 PM PST 23
Finished Dec 31 12:24:37 PM PST 23
Peak memory 197420 kb
Host smart-dab716db-2137-4d8a-8acd-35a8aa7bbf60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880493545 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2880493545
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4264945364
Short name T76
Test name
Test status
Simulation time 24623401 ps
CPU time 0.73 seconds
Started Dec 31 12:19:17 PM PST 23
Finished Dec 31 12:19:20 PM PST 23
Peak memory 194564 kb
Host smart-a805088a-a04c-4abe-b86a-ab2b8ea1eff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264945364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4264945364
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2555068572
Short name T897
Test name
Test status
Simulation time 15011234 ps
CPU time 0.6 seconds
Started Dec 31 12:22:51 PM PST 23
Finished Dec 31 12:22:52 PM PST 23
Peak memory 183248 kb
Host smart-a683f860-aa49-4d9f-9c62-2867f92ed849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555068572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2555068572
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3812398915
Short name T202
Test name
Test status
Simulation time 57214204 ps
CPU time 0.75 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:27:18 PM PST 23
Peak memory 191704 kb
Host smart-9b26f164-7e74-4b94-bf67-da680f8cda4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812398915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3812398915
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.136233626
Short name T20
Test name
Test status
Simulation time 301941140 ps
CPU time 3.11 seconds
Started Dec 31 12:22:51 PM PST 23
Finished Dec 31 12:22:54 PM PST 23
Peak memory 198084 kb
Host smart-60c24734-d0f3-447c-87d1-7c6dd1dbff3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136233626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.136233626
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1830298231
Short name T74
Test name
Test status
Simulation time 94866086 ps
CPU time 1.27 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 195640 kb
Host smart-498629e5-cb9f-464f-b475-a3fd757d5735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830298231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1830298231
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3480494689
Short name T155
Test name
Test status
Simulation time 53823236 ps
CPU time 0.86 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:46 PM PST 23
Peak memory 198072 kb
Host smart-97799c9e-e522-436b-b97f-117704eb1ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480494689 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3480494689
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.719812282
Short name T901
Test name
Test status
Simulation time 83272368 ps
CPU time 0.69 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 194432 kb
Host smart-ae80da6f-d5c6-4aa9-8711-f70264aed1a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719812282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.719812282
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2348555044
Short name T898
Test name
Test status
Simulation time 136037939 ps
CPU time 0.63 seconds
Started Dec 31 12:22:51 PM PST 23
Finished Dec 31 12:22:53 PM PST 23
Peak memory 181756 kb
Host smart-36a149d3-c5ec-47c9-a284-555def8f7115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348555044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2348555044
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.582499720
Short name T80
Test name
Test status
Simulation time 52936148 ps
CPU time 0.84 seconds
Started Dec 31 12:18:42 PM PST 23
Finished Dec 31 12:18:43 PM PST 23
Peak memory 195012 kb
Host smart-34b72f6f-ffca-4230-a089-ed3c6d045e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582499720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.582499720
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.513201703
Short name T204
Test name
Test status
Simulation time 189948285 ps
CPU time 2.65 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 198352 kb
Host smart-496a6a64-aa42-476d-9bf1-5d023cc8c64c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513201703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.513201703
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2820519827
Short name T75
Test name
Test status
Simulation time 1128904670 ps
CPU time 2.3 seconds
Started Dec 31 12:23:06 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 198136 kb
Host smart-b1325874-8872-434b-98bf-8c289fcb6446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820519827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2820519827
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3492023586
Short name T890
Test name
Test status
Simulation time 37987029 ps
CPU time 1.11 seconds
Started Dec 31 12:28:43 PM PST 23
Finished Dec 31 12:28:51 PM PST 23
Peak memory 196900 kb
Host smart-4203fd2f-f1ea-4c10-a9ef-625f81cfe0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492023586 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3492023586
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4145360108
Short name T908
Test name
Test status
Simulation time 36181616 ps
CPU time 0.67 seconds
Started Dec 31 12:29:49 PM PST 23
Finished Dec 31 12:29:52 PM PST 23
Peak memory 194312 kb
Host smart-b375dd03-82e4-404b-96a9-9e4da58fc341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145360108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4145360108
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3620325373
Short name T164
Test name
Test status
Simulation time 210673728 ps
CPU time 0.61 seconds
Started Dec 31 12:28:43 PM PST 23
Finished Dec 31 12:28:50 PM PST 23
Peak memory 182200 kb
Host smart-26307524-418e-4d7b-b67a-d1224bcc3093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620325373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3620325373
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2833056418
Short name T171
Test name
Test status
Simulation time 45860239 ps
CPU time 1.08 seconds
Started Dec 31 12:19:32 PM PST 23
Finished Dec 31 12:19:34 PM PST 23
Peak memory 196612 kb
Host smart-58387627-2e01-4118-89bc-814655399a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833056418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2833056418
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4060317111
Short name T865
Test name
Test status
Simulation time 206456703 ps
CPU time 2.03 seconds
Started Dec 31 12:24:43 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 196900 kb
Host smart-8168b664-ef55-40e0-aac1-6e108939f14c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060317111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4060317111
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.386362795
Short name T66
Test name
Test status
Simulation time 106127076 ps
CPU time 1.96 seconds
Started Dec 31 12:19:08 PM PST 23
Finished Dec 31 12:19:10 PM PST 23
Peak memory 198420 kb
Host smart-7951c7d4-3252-4921-8061-2050373a0a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386362795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.386362795
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3618414512
Short name T909
Test name
Test status
Simulation time 59660931 ps
CPU time 2.4 seconds
Started Dec 31 12:21:18 PM PST 23
Finished Dec 31 12:21:21 PM PST 23
Peak memory 198500 kb
Host smart-22455fab-4634-4468-bc4a-292bd8e50e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618414512 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3618414512
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4168880990
Short name T90
Test name
Test status
Simulation time 68999360 ps
CPU time 0.66 seconds
Started Dec 31 12:22:50 PM PST 23
Finished Dec 31 12:22:51 PM PST 23
Peak memory 193636 kb
Host smart-25f0fc97-204c-478f-aa3a-805f2d62a88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168880990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.4168880990
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4223464074
Short name T192
Test name
Test status
Simulation time 55551041 ps
CPU time 0.59 seconds
Started Dec 31 12:18:17 PM PST 23
Finished Dec 31 12:18:18 PM PST 23
Peak memory 183964 kb
Host smart-d5437816-8cd6-4654-ba37-8be00f7b31c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223464074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4223464074
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.348901302
Short name T903
Test name
Test status
Simulation time 664740591 ps
CPU time 1.12 seconds
Started Dec 31 12:21:30 PM PST 23
Finished Dec 31 12:21:37 PM PST 23
Peak memory 192408 kb
Host smart-d03e4ecf-5c0d-4595-94d6-87b397965636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348901302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.348901302
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1490338061
Short name T874
Test name
Test status
Simulation time 248295679 ps
CPU time 1.3 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 197912 kb
Host smart-f62d149c-af3c-4d3c-bc32-e1c700350ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490338061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1490338061
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1964662755
Short name T149
Test name
Test status
Simulation time 1400712148 ps
CPU time 2.49 seconds
Started Dec 31 12:21:17 PM PST 23
Finished Dec 31 12:21:20 PM PST 23
Peak memory 198108 kb
Host smart-6451abbf-9ca0-4431-a75f-7ca5837b1046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964662755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1964662755
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2177837090
Short name T189
Test name
Test status
Simulation time 17452336 ps
CPU time 0.9 seconds
Started Dec 31 12:25:59 PM PST 23
Finished Dec 31 12:26:06 PM PST 23
Peak memory 198156 kb
Host smart-f5ef97fb-dd73-4159-9975-225962570f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177837090 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2177837090
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1135450304
Short name T69
Test name
Test status
Simulation time 22026213 ps
CPU time 0.76 seconds
Started Dec 31 12:21:17 PM PST 23
Finished Dec 31 12:21:18 PM PST 23
Peak memory 194692 kb
Host smart-35ed381a-6479-4f14-b59d-503dbb6f088e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135450304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1135450304
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2133425977
Short name T175
Test name
Test status
Simulation time 47581736 ps
CPU time 0.58 seconds
Started Dec 31 12:24:43 PM PST 23
Finished Dec 31 12:24:52 PM PST 23
Peak memory 182028 kb
Host smart-f10ae44c-9382-4307-8013-4372dff29ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133425977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2133425977
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3226176364
Short name T872
Test name
Test status
Simulation time 55312434 ps
CPU time 0.78 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 194708 kb
Host smart-33c86a97-76f2-48a7-8705-fc234e474d50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226176364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3226176364
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3997925176
Short name T883
Test name
Test status
Simulation time 376740348 ps
CPU time 2.37 seconds
Started Dec 31 12:25:24 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 198296 kb
Host smart-81dc31c1-ea29-4bef-930c-107f35d1f589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997925176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3997925176
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3775115900
Short name T158
Test name
Test status
Simulation time 35535459 ps
CPU time 1.78 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 197180 kb
Host smart-4814e97f-e962-4b52-8a48-093322f074ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775115900 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3775115900
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1444663934
Short name T82
Test name
Test status
Simulation time 51678639 ps
CPU time 0.59 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:39 PM PST 23
Peak memory 193916 kb
Host smart-5b246e5f-9ccb-42c8-892d-e79e43e89bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444663934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1444663934
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.581672035
Short name T166
Test name
Test status
Simulation time 17521130 ps
CPU time 0.58 seconds
Started Dec 31 12:25:45 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 183488 kb
Host smart-50e7540d-0093-42f8-8510-d430ef9e024b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581672035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.581672035
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2236681352
Short name T79
Test name
Test status
Simulation time 107509655 ps
CPU time 1.47 seconds
Started Dec 31 12:18:25 PM PST 23
Finished Dec 31 12:18:27 PM PST 23
Peak memory 197220 kb
Host smart-33063e70-52ce-4f7f-a7ea-63736947e827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236681352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2236681352
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1387098863
Short name T25
Test name
Test status
Simulation time 74486754 ps
CPU time 1.52 seconds
Started Dec 31 12:25:48 PM PST 23
Finished Dec 31 12:25:58 PM PST 23
Peak memory 198360 kb
Host smart-a0e2e844-ba44-4ee3-9eeb-8084c9e36c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387098863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1387098863
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3896790980
Short name T199
Test name
Test status
Simulation time 278975386 ps
CPU time 1.57 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 198060 kb
Host smart-1d79ce13-18ea-4327-ae9f-f3856b75b214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896790980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3896790980
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1020011804
Short name T905
Test name
Test status
Simulation time 22648196 ps
CPU time 0.96 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 197796 kb
Host smart-ecbefe61-e7b9-462e-a9f8-f9187edd4cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020011804 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1020011804
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1073384124
Short name T89
Test name
Test status
Simulation time 86361663 ps
CPU time 0.7 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 194252 kb
Host smart-8bec1dae-bab3-4e27-8486-235266fd1bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073384124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1073384124
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3539192318
Short name T895
Test name
Test status
Simulation time 15507201 ps
CPU time 0.59 seconds
Started Dec 31 12:22:00 PM PST 23
Finished Dec 31 12:22:05 PM PST 23
Peak memory 183520 kb
Host smart-41610aef-9839-4e7e-90cc-2d071879ff88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539192318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3539192318
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3789265850
Short name T907
Test name
Test status
Simulation time 54265946 ps
CPU time 1.21 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 191640 kb
Host smart-2a5f9096-e0db-492a-a9fc-e529466eef50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789265850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3789265850
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3114954020
Short name T154
Test name
Test status
Simulation time 108622450 ps
CPU time 2.1 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 197672 kb
Host smart-d47e91b3-c182-4d47-84e0-fae779ad656b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114954020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3114954020
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2668933441
Short name T160
Test name
Test status
Simulation time 680572295 ps
CPU time 1.82 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 198300 kb
Host smart-44f77bfc-363a-41cd-89dd-d0df3f6f04e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668933441 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2668933441
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1439082397
Short name T894
Test name
Test status
Simulation time 48035543 ps
CPU time 0.69 seconds
Started Dec 31 12:25:21 PM PST 23
Finished Dec 31 12:25:25 PM PST 23
Peak memory 194676 kb
Host smart-c7446ec2-807b-48a5-9769-d9ef7b5152cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439082397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1439082397
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1984835149
Short name T869
Test name
Test status
Simulation time 46878472 ps
CPU time 0.6 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 182104 kb
Host smart-3029f048-418f-42b2-8f9c-02eef14c8dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984835149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1984835149
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.823752616
Short name T186
Test name
Test status
Simulation time 34161827 ps
CPU time 0.86 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:20 PM PST 23
Peak memory 190864 kb
Host smart-886b82f2-55d4-4784-9c89-ef48d9e8123d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823752616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.823752616
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3760038714
Short name T889
Test name
Test status
Simulation time 157260742 ps
CPU time 2.81 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:37 PM PST 23
Peak memory 198408 kb
Host smart-395a4c46-5df7-4ce5-9596-72d5e292689e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760038714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3760038714
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.632309934
Short name T72
Test name
Test status
Simulation time 63734967 ps
CPU time 1.26 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 183704 kb
Host smart-6bb42b3e-6e8c-4688-9737-f8d94f6d91cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632309934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.632309934
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4037967183
Short name T899
Test name
Test status
Simulation time 1801630382 ps
CPU time 8.49 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 191680 kb
Host smart-0502a4e8-23dc-43f9-90da-a782fd3508f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037967183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4037967183
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1305384378
Short name T71
Test name
Test status
Simulation time 82941825 ps
CPU time 0.71 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 193648 kb
Host smart-c3b82ea4-ba93-402b-ad60-01f259d6734a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305384378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1305384378
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.806376170
Short name T26
Test name
Test status
Simulation time 160407101 ps
CPU time 1.58 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:13 PM PST 23
Peak memory 198420 kb
Host smart-17a6a4b9-1120-4299-b1cd-b3c946b096cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806376170 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.806376170
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.219887444
Short name T83
Test name
Test status
Simulation time 19813174 ps
CPU time 0.68 seconds
Started Dec 31 12:21:25 PM PST 23
Finished Dec 31 12:21:26 PM PST 23
Peak memory 194220 kb
Host smart-0e5644e9-078e-408f-8113-ffa5aa158456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219887444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.219887444
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2954023827
Short name T906
Test name
Test status
Simulation time 42009168 ps
CPU time 0.56 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:27:45 PM PST 23
Peak memory 183540 kb
Host smart-71f59024-6979-4f3d-b317-a04b23d58d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954023827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2954023827
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3301869913
Short name T99
Test name
Test status
Simulation time 237795713 ps
CPU time 1.27 seconds
Started Dec 31 12:25:53 PM PST 23
Finished Dec 31 12:26:01 PM PST 23
Peak memory 192108 kb
Host smart-0f7eb0a8-a691-4c4e-a42f-85646a19d234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301869913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3301869913
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1949149715
Short name T196
Test name
Test status
Simulation time 141836792 ps
CPU time 1.68 seconds
Started Dec 31 12:18:24 PM PST 23
Finished Dec 31 12:18:27 PM PST 23
Peak memory 197204 kb
Host smart-2db9bcb8-ba11-44c3-8d4a-9dea3583aed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949149715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1949149715
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4272334437
Short name T73
Test name
Test status
Simulation time 107487145 ps
CPU time 2.24 seconds
Started Dec 31 12:21:25 PM PST 23
Finished Dec 31 12:21:28 PM PST 23
Peak memory 198116 kb
Host smart-a243d8af-af73-43df-8e59-d3e27ad5ed80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272334437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4272334437
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2571498605
Short name T863
Test name
Test status
Simulation time 13544593 ps
CPU time 0.55 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:25:38 PM PST 23
Peak memory 183492 kb
Host smart-52ce00e0-f992-40fd-804a-e53d5fe00b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571498605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2571498605
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4076026142
Short name T900
Test name
Test status
Simulation time 30586861 ps
CPU time 0.56 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 183572 kb
Host smart-cc0db869-9868-41a3-88ec-d2fe40e7e636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076026142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4076026142
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3183525398
Short name T871
Test name
Test status
Simulation time 39989814 ps
CPU time 0.55 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 183068 kb
Host smart-b6d8e1c6-06eb-4f6d-a051-bad39ba7e00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183525398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3183525398
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.423297296
Short name T178
Test name
Test status
Simulation time 43327210 ps
CPU time 0.57 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 182544 kb
Host smart-e4ec7f82-91e4-44f9-abd7-b0e2024585c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423297296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.423297296
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.94973624
Short name T67
Test name
Test status
Simulation time 17016605 ps
CPU time 0.58 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:46 PM PST 23
Peak memory 183452 kb
Host smart-32f6aa1e-ffa6-444a-b530-10a5cbb22859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94973624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.94973624
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2949605780
Short name T177
Test name
Test status
Simulation time 48918015 ps
CPU time 0.63 seconds
Started Dec 31 12:20:58 PM PST 23
Finished Dec 31 12:20:59 PM PST 23
Peak memory 183508 kb
Host smart-bf769006-152c-45aa-a754-5ca01f7c2237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949605780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2949605780
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.392609223
Short name T91
Test name
Test status
Simulation time 18224920 ps
CPU time 0.53 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 183104 kb
Host smart-8831d24c-0023-4f52-a63f-5f99f7c8fd9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392609223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.392609223
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2372093633
Short name T184
Test name
Test status
Simulation time 54684681 ps
CPU time 0.66 seconds
Started Dec 31 12:22:31 PM PST 23
Finished Dec 31 12:22:32 PM PST 23
Peak memory 182296 kb
Host smart-6fabdccc-6c5c-499d-a94b-d32f43bbdb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372093633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2372093633
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4294238482
Short name T180
Test name
Test status
Simulation time 14480857 ps
CPU time 0.58 seconds
Started Dec 31 12:22:51 PM PST 23
Finished Dec 31 12:22:52 PM PST 23
Peak memory 183248 kb
Host smart-8c0a6f67-3b19-44e6-a184-abe3d68e96c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294238482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4294238482
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2298006486
Short name T882
Test name
Test status
Simulation time 48926041 ps
CPU time 0.68 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 183480 kb
Host smart-0e5647fc-ae56-476a-bc89-97ef5cdcb73d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298006486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2298006486
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1606882780
Short name T866
Test name
Test status
Simulation time 537176572 ps
CPU time 2.58 seconds
Started Dec 31 12:19:16 PM PST 23
Finished Dec 31 12:19:20 PM PST 23
Peak memory 195536 kb
Host smart-e699fbba-d5d3-4197-a9ff-94a89e08155b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606882780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1606882780
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3449992114
Short name T864
Test name
Test status
Simulation time 2700510350 ps
CPU time 8.52 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:23:05 PM PST 23
Peak memory 191096 kb
Host smart-0a084eee-2c52-4d32-a354-c30fc10b10c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449992114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3449992114
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2670607707
Short name T163
Test name
Test status
Simulation time 16245250 ps
CPU time 0.74 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 192052 kb
Host smart-0f205155-964f-4a1d-a6cb-bebb7bfe9f9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670607707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2670607707
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.899845771
Short name T15
Test name
Test status
Simulation time 19708064 ps
CPU time 0.95 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 198108 kb
Host smart-f1362589-c3d4-4b00-af88-c9bbe72689d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899845771 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.899845771
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1525494477
Short name T886
Test name
Test status
Simulation time 25077579 ps
CPU time 0.66 seconds
Started Dec 31 12:23:23 PM PST 23
Finished Dec 31 12:23:24 PM PST 23
Peak memory 194208 kb
Host smart-9a418de2-b5f0-4a2f-8caa-5f940342a4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525494477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1525494477
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.50417897
Short name T21
Test name
Test status
Simulation time 29491624 ps
CPU time 0.55 seconds
Started Dec 31 12:24:22 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 183492 kb
Host smart-fc79405f-e2b3-45f4-9222-6bf92852db4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50417897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.50417897
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.223360842
Short name T100
Test name
Test status
Simulation time 222866643 ps
CPU time 1.03 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 195720 kb
Host smart-cecaf19d-a154-450b-a7e7-698945418e10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223360842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.223360842
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1988321063
Short name T27
Test name
Test status
Simulation time 116261774 ps
CPU time 1.82 seconds
Started Dec 31 12:34:30 PM PST 23
Finished Dec 31 12:34:33 PM PST 23
Peak memory 198480 kb
Host smart-c9bae080-e332-4f7d-9985-ad75371cc516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988321063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1988321063
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.212680781
Short name T153
Test name
Test status
Simulation time 1259743533 ps
CPU time 2.12 seconds
Started Dec 31 12:29:39 PM PST 23
Finished Dec 31 12:29:43 PM PST 23
Peak memory 198020 kb
Host smart-a8efff8f-f089-45fa-a88b-384e8c38b8da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212680781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.212680781
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2112579577
Short name T892
Test name
Test status
Simulation time 46703185 ps
CPU time 0.56 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:38 PM PST 23
Peak memory 183516 kb
Host smart-5a846718-a4ce-490a-81a3-ea12d04601b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112579577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2112579577
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.966691052
Short name T206
Test name
Test status
Simulation time 46650274 ps
CPU time 0.58 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 182360 kb
Host smart-8d6c2301-f00b-4987-abb6-362a2f4f490d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966691052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.966691052
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3357910643
Short name T868
Test name
Test status
Simulation time 11163086 ps
CPU time 0.54 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 183496 kb
Host smart-31ae8972-283f-4bea-838c-51ebd47d3c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357910643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3357910643
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3912467609
Short name T877
Test name
Test status
Simulation time 21747530 ps
CPU time 0.54 seconds
Started Dec 31 12:24:28 PM PST 23
Finished Dec 31 12:24:31 PM PST 23
Peak memory 183592 kb
Host smart-9aa382a3-65d1-4c62-842e-1d73412e24e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912467609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3912467609
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.806823606
Short name T159
Test name
Test status
Simulation time 93137019 ps
CPU time 0.53 seconds
Started Dec 31 12:24:51 PM PST 23
Finished Dec 31 12:24:58 PM PST 23
Peak memory 183072 kb
Host smart-f58c4521-14a7-4378-a6aa-9ec5c43d8933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806823606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.806823606
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2614903935
Short name T205
Test name
Test status
Simulation time 49991045 ps
CPU time 0.64 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:23:27 PM PST 23
Peak memory 182516 kb
Host smart-95f05b89-b02c-4a95-913a-94e0ff16b700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614903935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2614903935
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.455772817
Short name T881
Test name
Test status
Simulation time 53451668 ps
CPU time 0.53 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 183512 kb
Host smart-fb1faf92-2a0d-4194-a223-4909e3b8f8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455772817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.455772817
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2071183361
Short name T181
Test name
Test status
Simulation time 17221979 ps
CPU time 0.55 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:53 PM PST 23
Peak memory 182472 kb
Host smart-b04a0e6d-642b-421e-84af-e06981e5a84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071183361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2071183361
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3509484960
Short name T870
Test name
Test status
Simulation time 25178071 ps
CPU time 0.6 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 183464 kb
Host smart-82af44a2-5fab-49e1-b48c-69bb77b2f955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509484960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3509484960
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.515295723
Short name T879
Test name
Test status
Simulation time 11262382 ps
CPU time 0.62 seconds
Started Dec 31 12:23:55 PM PST 23
Finished Dec 31 12:24:02 PM PST 23
Peak memory 182720 kb
Host smart-9aba320f-3194-4c94-9d53-0fe2b9945293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515295723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.515295723
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1084830651
Short name T84
Test name
Test status
Simulation time 639590341 ps
CPU time 2.54 seconds
Started Dec 31 12:23:21 PM PST 23
Finished Dec 31 12:23:24 PM PST 23
Peak memory 191952 kb
Host smart-78da82ff-5529-4500-9efb-d7180f202795
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084830651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1084830651
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4213386799
Short name T880
Test name
Test status
Simulation time 240397680 ps
CPU time 3.39 seconds
Started Dec 31 12:23:24 PM PST 23
Finished Dec 31 12:23:28 PM PST 23
Peak memory 183780 kb
Host smart-428ebd4a-0683-4495-9441-f8c929cb69dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213386799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4213386799
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3398251610
Short name T103
Test name
Test status
Simulation time 17597625 ps
CPU time 0.59 seconds
Started Dec 31 12:27:12 PM PST 23
Finished Dec 31 12:27:14 PM PST 23
Peak memory 193248 kb
Host smart-3a821425-d150-4c51-8921-d1b5aac8fe36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398251610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3398251610
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2375012109
Short name T185
Test name
Test status
Simulation time 80562615 ps
CPU time 0.86 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:25:28 PM PST 23
Peak memory 198056 kb
Host smart-06f1095d-4895-4410-8f26-c60d9b0faedb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375012109 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2375012109
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2493667754
Short name T168
Test name
Test status
Simulation time 26591430 ps
CPU time 0.66 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 192392 kb
Host smart-06d9f747-6f9f-4efb-9e1b-fad218376f76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493667754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2493667754
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3062432450
Short name T172
Test name
Test status
Simulation time 47700746 ps
CPU time 0.59 seconds
Started Dec 31 12:23:24 PM PST 23
Finished Dec 31 12:23:26 PM PST 23
Peak memory 183520 kb
Host smart-72aa6903-355f-4acd-a854-a3cf5dcefe62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062432450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3062432450
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1657598398
Short name T77
Test name
Test status
Simulation time 32531599 ps
CPU time 0.73 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:54 PM PST 23
Peak memory 191352 kb
Host smart-be444a53-8689-475e-935a-97341151d80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657598398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1657598398
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4014054217
Short name T197
Test name
Test status
Simulation time 62233664 ps
CPU time 3.17 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 198416 kb
Host smart-5cf1c435-1c0e-413c-bc6c-e2a594f2ee05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014054217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4014054217
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3241471132
Short name T152
Test name
Test status
Simulation time 59782496 ps
CPU time 1.21 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 195988 kb
Host smart-98970761-8a63-4bca-a2fa-838b39aa037a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241471132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3241471132
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3362131810
Short name T68
Test name
Test status
Simulation time 54865842 ps
CPU time 0.67 seconds
Started Dec 31 12:23:12 PM PST 23
Finished Dec 31 12:23:13 PM PST 23
Peak memory 182476 kb
Host smart-155920bc-3ade-4074-b745-7e1e739f4fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362131810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3362131810
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2087289207
Short name T148
Test name
Test status
Simulation time 53945869 ps
CPU time 0.58 seconds
Started Dec 31 12:23:38 PM PST 23
Finished Dec 31 12:23:42 PM PST 23
Peak memory 183448 kb
Host smart-bb28426e-5fe1-4882-9827-3e370b4cee5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087289207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2087289207
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.975296222
Short name T191
Test name
Test status
Simulation time 47902397 ps
CPU time 0.55 seconds
Started Dec 31 12:23:08 PM PST 23
Finished Dec 31 12:23:10 PM PST 23
Peak memory 183480 kb
Host smart-5e5969fe-ee78-4ac3-96f9-3d68e6015388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975296222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.975296222
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2288940301
Short name T878
Test name
Test status
Simulation time 21156495 ps
CPU time 0.53 seconds
Started Dec 31 12:25:46 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 183516 kb
Host smart-f58f7827-1301-4183-ab15-6a751dbb9d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288940301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2288940301
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2257710241
Short name T873
Test name
Test status
Simulation time 34905704 ps
CPU time 0.56 seconds
Started Dec 31 12:26:39 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 183440 kb
Host smart-1e2974cf-04c4-420f-9da7-cb04367c500b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257710241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2257710241
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2844913508
Short name T167
Test name
Test status
Simulation time 16601906 ps
CPU time 0.6 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 182296 kb
Host smart-372bf7f6-7406-49ed-9a17-487fc344a31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844913508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2844913508
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3751657019
Short name T19
Test name
Test status
Simulation time 30233980 ps
CPU time 0.55 seconds
Started Dec 31 12:25:14 PM PST 23
Finished Dec 31 12:25:18 PM PST 23
Peak memory 183336 kb
Host smart-af1125ed-9389-47d3-9387-9a1c993e76ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751657019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3751657019
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3676959806
Short name T179
Test name
Test status
Simulation time 71137674 ps
CPU time 0.53 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 183544 kb
Host smart-85624ac0-6361-46b8-aa0c-88d23269f85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676959806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3676959806
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1877536809
Short name T162
Test name
Test status
Simulation time 23254319 ps
CPU time 1.13 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 198348 kb
Host smart-6aeee413-343d-46ad-a92b-0c3f599323c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877536809 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1877536809
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.302479171
Short name T87
Test name
Test status
Simulation time 46948149 ps
CPU time 0.7 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:54 PM PST 23
Peak memory 193260 kb
Host smart-499c43e7-c3e6-4cb0-b1c4-0d0a84ea328a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302479171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.302479171
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1858823335
Short name T157
Test name
Test status
Simulation time 54025492 ps
CPU time 0.57 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 183456 kb
Host smart-e85f4510-0ca1-458a-9329-4ec864672bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858823335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1858823335
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2816688751
Short name T169
Test name
Test status
Simulation time 102561384 ps
CPU time 1.17 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 196736 kb
Host smart-47aec15a-fcf2-478b-9083-47b6725ee25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816688751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2816688751
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1043956480
Short name T887
Test name
Test status
Simulation time 393684948 ps
CPU time 2.08 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:08 PM PST 23
Peak memory 198400 kb
Host smart-9497cba5-59c5-459e-bb58-452e2071e806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043956480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1043956480
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1352361639
Short name T902
Test name
Test status
Simulation time 167837577 ps
CPU time 2.31 seconds
Started Dec 31 12:25:26 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 198016 kb
Host smart-f65341fb-6529-439e-bf6d-18ded2b8b3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352361639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1352361639
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3837793563
Short name T867
Test name
Test status
Simulation time 161525188 ps
CPU time 1.86 seconds
Started Dec 31 12:22:29 PM PST 23
Finished Dec 31 12:22:32 PM PST 23
Peak memory 197484 kb
Host smart-b1821d01-9c83-4e8f-8798-789c96b4a5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837793563 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3837793563
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1437406128
Short name T81
Test name
Test status
Simulation time 150336997 ps
CPU time 0.69 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:08 PM PST 23
Peak memory 194288 kb
Host smart-c6a51250-6ba9-4656-9690-7aa6481a8988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437406128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1437406128
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.372009000
Short name T170
Test name
Test status
Simulation time 41014426 ps
CPU time 0.64 seconds
Started Dec 31 12:23:06 PM PST 23
Finished Dec 31 12:23:07 PM PST 23
Peak memory 181640 kb
Host smart-45bcaac5-49b0-49c5-9e9d-630158447295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372009000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.372009000
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1604839561
Short name T183
Test name
Test status
Simulation time 17727899 ps
CPU time 0.78 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 190984 kb
Host smart-54c6e2b9-62e8-49c4-88ad-830ae9989c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604839561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1604839561
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.715208483
Short name T65
Test name
Test status
Simulation time 280953487 ps
CPU time 2.78 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:26:59 PM PST 23
Peak memory 198412 kb
Host smart-74deef91-a46d-4a1d-9482-f08b7d63a853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715208483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.715208483
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1311125409
Short name T188
Test name
Test status
Simulation time 653256733 ps
CPU time 2.38 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 198080 kb
Host smart-5b699a1e-ca98-4dde-afbe-6536600f6f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311125409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1311125409
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.556819423
Short name T888
Test name
Test status
Simulation time 76293764 ps
CPU time 2.5 seconds
Started Dec 31 12:23:42 PM PST 23
Finished Dec 31 12:23:47 PM PST 23
Peak memory 197384 kb
Host smart-dead5ef6-80ac-43af-91e0-b6c7ade87100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556819423 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.556819423
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2557801287
Short name T92
Test name
Test status
Simulation time 47318010 ps
CPU time 0.75 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 193192 kb
Host smart-73f17009-f0b8-42f4-80de-d67e768288b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557801287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2557801287
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2673370110
Short name T193
Test name
Test status
Simulation time 70674140 ps
CPU time 0.56 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:14 PM PST 23
Peak memory 183468 kb
Host smart-9090d363-603e-4f67-b7e3-80c147142da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673370110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2673370110
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3584260507
Short name T201
Test name
Test status
Simulation time 27671238 ps
CPU time 0.8 seconds
Started Dec 31 12:18:23 PM PST 23
Finished Dec 31 12:18:24 PM PST 23
Peak memory 191744 kb
Host smart-ad97e118-d713-4414-94ee-2e5b6656dbbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584260507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3584260507
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1387006985
Short name T29
Test name
Test status
Simulation time 964261891 ps
CPU time 1.75 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:13 PM PST 23
Peak memory 197140 kb
Host smart-d8bbfdd2-dca0-46d1-9fa5-a948980a89c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387006985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1387006985
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3208275925
Short name T62
Test name
Test status
Simulation time 63851043 ps
CPU time 1.29 seconds
Started Dec 31 12:22:29 PM PST 23
Finished Dec 31 12:22:31 PM PST 23
Peak memory 196456 kb
Host smart-a71f845b-c224-4449-81fa-86d8c134ccaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208275925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3208275925
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1839513369
Short name T876
Test name
Test status
Simulation time 82256533 ps
CPU time 1.42 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 197492 kb
Host smart-3f5a9d9e-b1b7-4915-bb85-02d1e26d3e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839513369 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1839513369
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4146687286
Short name T18
Test name
Test status
Simulation time 41117078 ps
CPU time 0.59 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 193620 kb
Host smart-a287bea3-936c-4c33-81ac-966350fc2289
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146687286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4146687286
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1235814557
Short name T200
Test name
Test status
Simulation time 22259320 ps
CPU time 0.6 seconds
Started Dec 31 12:22:31 PM PST 23
Finished Dec 31 12:22:32 PM PST 23
Peak memory 183136 kb
Host smart-9d375f8d-e5be-4af0-ba45-a5a63232f3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235814557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1235814557
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.55523836
Short name T198
Test name
Test status
Simulation time 325591381 ps
CPU time 1.39 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 196116 kb
Host smart-6126c831-ce60-40e4-a82e-b58e7d90050e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55523836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_o
utstanding.55523836
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.567076400
Short name T64
Test name
Test status
Simulation time 36219015 ps
CPU time 1.85 seconds
Started Dec 31 12:23:07 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 198272 kb
Host smart-5b811697-0ec7-49f0-a387-84a662129d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567076400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.567076400
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.173563001
Short name T896
Test name
Test status
Simulation time 121462831 ps
CPU time 1.29 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 196692 kb
Host smart-84a6b32a-0c1d-40a9-8d7a-a87526f87713
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173563001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.173563001
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1038488604
Short name T24
Test name
Test status
Simulation time 40639883 ps
CPU time 0.84 seconds
Started Dec 31 12:24:07 PM PST 23
Finished Dec 31 12:24:14 PM PST 23
Peak memory 198144 kb
Host smart-68e749e4-6d42-4e97-9008-4c1749e69396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038488604 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1038488604
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.18160290
Short name T173
Test name
Test status
Simulation time 162659246 ps
CPU time 0.59 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:26:46 PM PST 23
Peak memory 193724 kb
Host smart-6f3813fd-988d-4f8c-ba52-aba452a4596b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.18160290
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1252997252
Short name T104
Test name
Test status
Simulation time 14108633 ps
CPU time 0.56 seconds
Started Dec 31 12:28:08 PM PST 23
Finished Dec 31 12:28:12 PM PST 23
Peak memory 183552 kb
Host smart-76a9ea5e-81b3-4607-b3a0-fd446db9ab80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252997252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1252997252
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4286720034
Short name T97
Test name
Test status
Simulation time 63187291 ps
CPU time 1.29 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 190644 kb
Host smart-d673eccb-7e5a-45e9-bbc9-0b9b59dad98d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286720034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4286720034
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.66743571
Short name T904
Test name
Test status
Simulation time 56803265 ps
CPU time 1.48 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 198196 kb
Host smart-e842d81a-284b-4e69-933f-705a324e226c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66743571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.66743571
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.840865622
Short name T94
Test name
Test status
Simulation time 84895046 ps
CPU time 1.09 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:27:40 PM PST 23
Peak memory 197932 kb
Host smart-f4bb643f-52a0-4375-b701-18ba4c0b6d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840865622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.840865622
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2316946493
Short name T831
Test name
Test status
Simulation time 31692027 ps
CPU time 0.65 seconds
Started Dec 31 12:23:37 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 192620 kb
Host smart-4e33e352-43c3-4022-90c6-5a266926ed84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316946493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2316946493
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.550459827
Short name T354
Test name
Test status
Simulation time 1771783523 ps
CPU time 30.41 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:41 PM PST 23
Peak memory 229080 kb
Host smart-0524ace0-9f88-41d4-b00f-648904381293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550459827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.550459827
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1104939394
Short name T304
Test name
Test status
Simulation time 2043018587 ps
CPU time 33.21 seconds
Started Dec 31 12:28:57 PM PST 23
Finished Dec 31 12:29:34 PM PST 23
Peak memory 198612 kb
Host smart-ce95bd78-452f-4406-a378-263562e3da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104939394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1104939394
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3290295123
Short name T477
Test name
Test status
Simulation time 4664778613 ps
CPU time 119.24 seconds
Started Dec 31 12:22:39 PM PST 23
Finished Dec 31 12:24:39 PM PST 23
Peak memory 198780 kb
Host smart-287a71e1-ae19-43cd-b4f3-6b9b77a0f16a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290295123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3290295123
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.557151485
Short name T425
Test name
Test status
Simulation time 5774508918 ps
CPU time 69.51 seconds
Started Dec 31 12:22:53 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 198692 kb
Host smart-e5cbf6a1-3901-4584-badb-3cb2d6b5a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557151485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.557151485
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3325796355
Short name T51
Test name
Test status
Simulation time 68991610 ps
CPU time 0.81 seconds
Started Dec 31 12:23:56 PM PST 23
Finished Dec 31 12:24:02 PM PST 23
Peak memory 215076 kb
Host smart-02b547f9-f83f-4fc9-8b15-0fafd326f905
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325796355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3325796355
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2171458665
Short name T807
Test name
Test status
Simulation time 1107715355 ps
CPU time 4.1 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:53 PM PST 23
Peak memory 198464 kb
Host smart-49ba9724-07b7-496d-9720-bee39a9e35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171458665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2171458665
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.644281085
Short name T240
Test name
Test status
Simulation time 6696528010 ps
CPU time 299.18 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:30:23 PM PST 23
Peak memory 198544 kb
Host smart-d2f8aa92-a998-4583-837b-2f53df266d7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644281085 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.644281085
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1348518828
Short name T445
Test name
Test status
Simulation time 50460846953 ps
CPU time 586.9 seconds
Started Dec 31 12:22:53 PM PST 23
Finished Dec 31 12:32:41 PM PST 23
Peak memory 215068 kb
Host smart-a6fa5eb1-8561-463f-839c-c4990520de44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348518828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1348518828
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2688818756
Short name T577
Test name
Test status
Simulation time 40047637 ps
CPU time 1.01 seconds
Started Dec 31 12:21:32 PM PST 23
Finished Dec 31 12:21:37 PM PST 23
Peak memory 195660 kb
Host smart-242a551e-5170-4cae-a2eb-f34822eba35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688818756 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2688818756
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3732713047
Short name T540
Test name
Test status
Simulation time 29441837445 ps
CPU time 441.85 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:33:09 PM PST 23
Peak memory 198716 kb
Host smart-cb35b3e3-a468-4d61-81e3-1f02c5199643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732713047 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.3732713047
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.299508434
Short name T615
Test name
Test status
Simulation time 10040372329 ps
CPU time 31.34 seconds
Started Dec 31 12:24:13 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 198676 kb
Host smart-626031e3-d1fa-467f-bee6-e356e3e2d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299508434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.299508434
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1773403320
Short name T275
Test name
Test status
Simulation time 23302801 ps
CPU time 0.59 seconds
Started Dec 31 12:24:40 PM PST 23
Finished Dec 31 12:24:48 PM PST 23
Peak memory 192944 kb
Host smart-67265c82-05db-49bb-b4df-50bf724bb983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773403320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1773403320
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3413430510
Short name T456
Test name
Test status
Simulation time 3583963018 ps
CPU time 52.15 seconds
Started Dec 31 12:24:53 PM PST 23
Finished Dec 31 12:25:51 PM PST 23
Peak memory 227936 kb
Host smart-eddfdee8-f5b1-429c-8563-d07b55462e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413430510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3413430510
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.985051501
Short name T707
Test name
Test status
Simulation time 1370564831 ps
CPU time 59.65 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 197528 kb
Host smart-7ee6166b-bdfa-4a6c-87ca-d5f95ed7fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985051501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.985051501
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.815395928
Short name T793
Test name
Test status
Simulation time 3973177708 ps
CPU time 94.54 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:25:02 PM PST 23
Peak memory 198404 kb
Host smart-9eb65302-dec4-493e-920a-f268c590bcf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815395928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.815395928
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1495947289
Short name T604
Test name
Test status
Simulation time 3815372440 ps
CPU time 139.08 seconds
Started Dec 31 12:18:46 PM PST 23
Finished Dec 31 12:21:06 PM PST 23
Peak memory 198784 kb
Host smart-b5efd418-50c0-41c1-b395-e1a8205f4951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495947289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1495947289
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2530568882
Short name T672
Test name
Test status
Simulation time 4736247695 ps
CPU time 43.93 seconds
Started Dec 31 12:23:56 PM PST 23
Finished Dec 31 12:24:45 PM PST 23
Peak memory 198384 kb
Host smart-9c298892-a18d-4098-9e96-a92b34fe2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530568882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2530568882
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.824582225
Short name T49
Test name
Test status
Simulation time 110382535 ps
CPU time 0.99 seconds
Started Dec 31 12:22:45 PM PST 23
Finished Dec 31 12:22:46 PM PST 23
Peak memory 215896 kb
Host smart-c075b838-9ec2-462a-9e24-4f34c9f3982d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824582225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.824582225
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2346197591
Short name T350
Test name
Test status
Simulation time 1655695000 ps
CPU time 4.2 seconds
Started Dec 31 12:25:14 PM PST 23
Finished Dec 31 12:25:21 PM PST 23
Peak memory 197824 kb
Host smart-f9584ff2-c66b-457f-8634-e7b519f9a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346197591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2346197591
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3354974822
Short name T342
Test name
Test status
Simulation time 6697640829 ps
CPU time 108.06 seconds
Started Dec 31 12:24:24 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 231380 kb
Host smart-6b67237b-5e2c-4b72-8ec3-ab837f97303e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354974822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3354974822
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.4118871689
Short name T726
Test name
Test status
Simulation time 141220730788 ps
CPU time 1859.01 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:55:53 PM PST 23
Peak memory 247228 kb
Host smart-1a89515d-046d-4d59-ba37-ff8f03b1efe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118871689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.4118871689
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1798021867
Short name T491
Test name
Test status
Simulation time 96400965 ps
CPU time 0.85 seconds
Started Dec 31 12:25:11 PM PST 23
Finished Dec 31 12:25:15 PM PST 23
Peak memory 195556 kb
Host smart-231b6193-2851-4ce7-aabc-ea396d4522b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798021867 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1798021867
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.4058952009
Short name T384
Test name
Test status
Simulation time 34427130988 ps
CPU time 373.34 seconds
Started Dec 31 12:25:31 PM PST 23
Finished Dec 31 12:31:52 PM PST 23
Peak memory 198492 kb
Host smart-89732efb-5ebf-44be-a11f-849570c65114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058952009 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.4058952009
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3888502261
Short name T372
Test name
Test status
Simulation time 16674578044 ps
CPU time 50.62 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:49 PM PST 23
Peak memory 197616 kb
Host smart-5013b50a-8b61-40e5-a79a-37b0991a626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888502261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3888502261
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2688766598
Short name T565
Test name
Test status
Simulation time 51816723 ps
CPU time 0.54 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:24 PM PST 23
Peak memory 192912 kb
Host smart-678d39b5-c35c-412c-bad4-dc109d25f4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688766598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2688766598
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2679547777
Short name T460
Test name
Test status
Simulation time 5182823752 ps
CPU time 36.79 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:28:13 PM PST 23
Peak memory 217316 kb
Host smart-81d2dc3e-8974-4d18-b782-f662988b58fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679547777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2679547777
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2281498661
Short name T821
Test name
Test status
Simulation time 2778307605 ps
CPU time 27.24 seconds
Started Dec 31 12:29:05 PM PST 23
Finished Dec 31 12:29:38 PM PST 23
Peak memory 198636 kb
Host smart-368ab518-1a3b-4e25-a3ff-6097db9bf620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281498661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2281498661
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.623425296
Short name T688
Test name
Test status
Simulation time 3574353875 ps
CPU time 40.79 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 198688 kb
Host smart-c38be08b-0a1f-4d92-b38c-3e99a60acb61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623425296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.623425296
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.232054367
Short name T414
Test name
Test status
Simulation time 317605024 ps
CPU time 14.14 seconds
Started Dec 31 12:27:40 PM PST 23
Finished Dec 31 12:27:56 PM PST 23
Peak memory 198508 kb
Host smart-9d5e4b91-169e-4683-909c-6f54fd58517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232054367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.232054367
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1996517808
Short name T358
Test name
Test status
Simulation time 1615730986 ps
CPU time 80.86 seconds
Started Dec 31 12:27:36 PM PST 23
Finished Dec 31 12:28:58 PM PST 23
Peak memory 198480 kb
Host smart-bcfcaf59-e152-480e-9ea3-32fc9db73cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996517808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1996517808
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1472849955
Short name T488
Test name
Test status
Simulation time 305947741 ps
CPU time 3.5 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198636 kb
Host smart-5894c78d-c062-4c67-8c07-6d21cad5504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472849955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1472849955
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2994214258
Short name T782
Test name
Test status
Simulation time 18881282582 ps
CPU time 511.02 seconds
Started Dec 31 12:28:02 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 198668 kb
Host smart-d68d0170-dfed-4b6d-bbea-e3f91a696cbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994214258 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2994214258
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.4107508860
Short name T378
Test name
Test status
Simulation time 91100328502 ps
CPU time 4493.41 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 01:41:15 PM PST 23
Peak memory 259076 kb
Host smart-38a7023e-252c-423e-a072-9a8abda9b8d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107508860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.4107508860
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1286056071
Short name T37
Test name
Test status
Simulation time 41925700 ps
CPU time 0.94 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:26:35 PM PST 23
Peak memory 195868 kb
Host smart-b9509ea5-9a47-43d5-9ee0-7ca7593e9199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286056071 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1286056071
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2947634997
Short name T504
Test name
Test status
Simulation time 8737979744 ps
CPU time 401.24 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:33:35 PM PST 23
Peak memory 198400 kb
Host smart-9e1da424-6ad3-4a7c-8584-c8ff547896e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947634997 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.2947634997
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2313777122
Short name T786
Test name
Test status
Simulation time 8788860662 ps
CPU time 72.46 seconds
Started Dec 31 12:26:33 PM PST 23
Finished Dec 31 12:27:47 PM PST 23
Peak memory 198704 kb
Host smart-237065f6-2ba4-49ef-aafe-63841d905470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313777122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2313777122
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2794055135
Short name T321
Test name
Test status
Simulation time 18755464372 ps
CPU time 251.09 seconds
Started Dec 31 12:28:25 PM PST 23
Finished Dec 31 12:32:38 PM PST 23
Peak memory 243804 kb
Host smart-ece44d10-477e-4966-9a89-ab6d985fb508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794055135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.2794055135
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.890332162
Short name T278
Test name
Test status
Simulation time 171221851233 ps
CPU time 675.67 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:38:28 PM PST 23
Peak memory 225256 kb
Host smart-1a248a46-9096-4ddd-b140-920c7cac0b64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890332162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.890332162
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.1828407651
Short name T680
Test name
Test status
Simulation time 18144450329 ps
CPU time 901.87 seconds
Started Dec 31 12:27:56 PM PST 23
Finished Dec 31 12:43:04 PM PST 23
Peak memory 206268 kb
Host smart-d9714585-d124-4a82-a6eb-0355da8b1d5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828407651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.1828407651
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1562915514
Short name T584
Test name
Test status
Simulation time 208850141903 ps
CPU time 1522.91 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:53:09 PM PST 23
Peak memory 228848 kb
Host smart-10a5e7f9-b3d3-4071-8652-7dd77b99e2ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562915514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.1562915514
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3241022200
Short name T728
Test name
Test status
Simulation time 924885834 ps
CPU time 13.75 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:43 PM PST 23
Peak memory 214168 kb
Host smart-dc793b33-2134-4a12-b000-12bcd75203b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241022200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3241022200
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4263925725
Short name T474
Test name
Test status
Simulation time 2545171396 ps
CPU time 55.59 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:27:25 PM PST 23
Peak memory 198656 kb
Host smart-955dacae-d835-4d25-b8ad-0a2c33b1e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263925725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4263925725
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.373289053
Short name T434
Test name
Test status
Simulation time 2931612178 ps
CPU time 73.15 seconds
Started Dec 31 12:28:31 PM PST 23
Finished Dec 31 12:29:53 PM PST 23
Peak memory 198600 kb
Host smart-c2f06305-bd88-4d9b-b3f9-090843d2a9bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373289053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.373289053
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1298787453
Short name T704
Test name
Test status
Simulation time 2560849835 ps
CPU time 115.51 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:28:10 PM PST 23
Peak memory 198720 kb
Host smart-6f608bef-2b53-4cb2-8cd1-13189b409952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298787453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1298787453
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.221123846
Short name T631
Test name
Test status
Simulation time 17491270445 ps
CPU time 74.67 seconds
Started Dec 31 12:27:03 PM PST 23
Finished Dec 31 12:28:21 PM PST 23
Peak memory 198728 kb
Host smart-dfab2646-357b-48c0-80cb-20d1c5cf3baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221123846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.221123846
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.536138071
Short name T766
Test name
Test status
Simulation time 727502731 ps
CPU time 2.61 seconds
Started Dec 31 12:26:18 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 198556 kb
Host smart-e58e63d4-dccd-4ec8-83f5-114dc203678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536138071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.536138071
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2608320826
Short name T840
Test name
Test status
Simulation time 87112835391 ps
CPU time 703.71 seconds
Started Dec 31 12:28:32 PM PST 23
Finished Dec 31 12:40:24 PM PST 23
Peak memory 220764 kb
Host smart-360e7731-e902-4eb3-a265-e31c4805ca24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608320826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2608320826
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.297425230
Short name T353
Test name
Test status
Simulation time 37863377835 ps
CPU time 1302.85 seconds
Started Dec 31 12:27:40 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 235884 kb
Host smart-dc3b87a7-7c8a-4e45-b5bf-ab92d981be58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297425230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.297425230
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.267911231
Short name T561
Test name
Test status
Simulation time 199562653 ps
CPU time 1.02 seconds
Started Dec 31 12:28:26 PM PST 23
Finished Dec 31 12:28:29 PM PST 23
Peak memory 196900 kb
Host smart-1c8f4d41-98a2-40d9-b977-b1f1130d2763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267911231 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.267911231
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3874846461
Short name T313
Test name
Test status
Simulation time 1879736399 ps
CPU time 9.55 seconds
Started Dec 31 12:29:02 PM PST 23
Finished Dec 31 12:29:20 PM PST 23
Peak memory 198488 kb
Host smart-d3ca22e9-c3ca-4b8e-9eee-e6fc40adef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874846461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3874846461
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.1166305470
Short name T117
Test name
Test status
Simulation time 384264209054 ps
CPU time 2017.55 seconds
Started Dec 31 12:28:36 PM PST 23
Finished Dec 31 01:02:23 PM PST 23
Peak memory 244164 kb
Host smart-31896b66-ec69-4f1d-acfd-259721a58127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166305470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.1166305470
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1562326618
Short name T753
Test name
Test status
Simulation time 149452568178 ps
CPU time 1827.95 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:58:27 PM PST 23
Peak memory 240692 kb
Host smart-4b5c6ff8-fdcf-4151-b101-7a6cbe287d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562326618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.1562326618
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.4249093870
Short name T490
Test name
Test status
Simulation time 36000187532 ps
CPU time 488.4 seconds
Started Dec 31 12:27:57 PM PST 23
Finished Dec 31 12:36:10 PM PST 23
Peak memory 214900 kb
Host smart-a3964386-8ffd-4ab8-8b15-e608e2acc455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249093870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.4249093870
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.77137606
Short name T281
Test name
Test status
Simulation time 251674536965 ps
CPU time 305.32 seconds
Started Dec 31 12:27:25 PM PST 23
Finished Dec 31 12:32:37 PM PST 23
Peak memory 242712 kb
Host smart-8663a63f-00a7-4922-af77-5436f9a2ca1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77137606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.77137606
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.2946778640
Short name T292
Test name
Test status
Simulation time 255174101951 ps
CPU time 969.48 seconds
Started Dec 31 12:28:08 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 215192 kb
Host smart-8b5c9336-4dee-47a5-b5d4-304c19ff3ed9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946778640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.2946778640
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1990110278
Short name T113
Test name
Test status
Simulation time 251481702625 ps
CPU time 676.23 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:38:45 PM PST 23
Peak memory 211408 kb
Host smart-45e24294-89e3-4b33-b195-090c2c7e5330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990110278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.1990110278
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.3597550363
Short name T684
Test name
Test status
Simulation time 526773110725 ps
CPU time 1095.94 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:45:51 PM PST 23
Peak memory 227608 kb
Host smart-bb637320-a973-4cfb-becd-d459246b8f1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597550363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.3597550363
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.1615164199
Short name T387
Test name
Test status
Simulation time 462226100478 ps
CPU time 2100.04 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 01:02:49 PM PST 23
Peak memory 247964 kb
Host smart-53cebc88-9aa4-4cb8-9d80-ddd123f0f3b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615164199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.1615164199
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.117218896
Short name T524
Test name
Test status
Simulation time 11971346019 ps
CPU time 539.25 seconds
Started Dec 31 12:27:30 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 231452 kb
Host smart-13106620-4646-40e9-aa6c-9ac90a476f79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117218896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.117218896
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4079393943
Short name T344
Test name
Test status
Simulation time 24356019 ps
CPU time 0.56 seconds
Started Dec 31 12:26:17 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 193904 kb
Host smart-10f32bd9-d1ae-4c7b-9fbd-1a587f905377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079393943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4079393943
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.355298035
Short name T822
Test name
Test status
Simulation time 6664279761 ps
CPU time 59.37 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:27:55 PM PST 23
Peak memory 231376 kb
Host smart-ddea4e70-1be9-4462-b7d8-2f36d4f157a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355298035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.355298035
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.121315538
Short name T38
Test name
Test status
Simulation time 2096786683 ps
CPU time 43.66 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 198536 kb
Host smart-44779851-ebd1-4b60-b849-4961529d30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121315538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.121315538
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2539606368
Short name T215
Test name
Test status
Simulation time 373879189 ps
CPU time 9.54 seconds
Started Dec 31 12:27:42 PM PST 23
Finished Dec 31 12:27:52 PM PST 23
Peak memory 198492 kb
Host smart-f00ee4bd-1c70-4814-bede-2d23a55a2721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539606368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2539606368
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2778771685
Short name T423
Test name
Test status
Simulation time 31350410856 ps
CPU time 92.15 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:28:55 PM PST 23
Peak memory 198700 kb
Host smart-0dfb45db-55f2-4bfa-a72f-52d54f375d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778771685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2778771685
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4005047721
Short name T400
Test name
Test status
Simulation time 17593324486 ps
CPU time 84.42 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:29:12 PM PST 23
Peak memory 198680 kb
Host smart-f12b97b2-a9a9-4caa-a92a-3295f1e9eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005047721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4005047721
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3302503875
Short name T519
Test name
Test status
Simulation time 28596669 ps
CPU time 0.85 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:15 PM PST 23
Peak memory 194804 kb
Host smart-655dd2c2-f424-4d00-b7af-5259336a1e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302503875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3302503875
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3682563696
Short name T316
Test name
Test status
Simulation time 53308619584 ps
CPU time 686.85 seconds
Started Dec 31 12:28:50 PM PST 23
Finished Dec 31 12:40:23 PM PST 23
Peak memory 206420 kb
Host smart-0ab74113-7e70-4d2d-9811-cc26b53027e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682563696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3682563696
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.189401937
Short name T395
Test name
Test status
Simulation time 159182469330 ps
CPU time 1938.26 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:59:05 PM PST 23
Peak memory 257256 kb
Host smart-57b50abc-2e86-404f-8d83-f6384577acdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189401937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.189401937
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3569580237
Short name T453
Test name
Test status
Simulation time 112741419 ps
CPU time 1.11 seconds
Started Dec 31 12:29:02 PM PST 23
Finished Dec 31 12:29:11 PM PST 23
Peak memory 197036 kb
Host smart-b3efeced-8ec6-4281-bbe6-fa49ae77f63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569580237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3569580237
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3639255210
Short name T122
Test name
Test status
Simulation time 54208051219 ps
CPU time 443.45 seconds
Started Dec 31 12:26:12 PM PST 23
Finished Dec 31 12:33:39 PM PST 23
Peak memory 199072 kb
Host smart-078ccf06-d838-4a86-9264-d2ac33f3cdf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639255210 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3639255210
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3950484550
Short name T463
Test name
Test status
Simulation time 2222087034 ps
CPU time 71.28 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:29:02 PM PST 23
Peak memory 198532 kb
Host smart-57e475aa-fb5c-42cf-ad2e-8921b15344d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950484550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3950484550
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2458713214
Short name T647
Test name
Test status
Simulation time 20303120810 ps
CPU time 267.44 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:31:35 PM PST 23
Peak memory 198680 kb
Host smart-7e18bba7-87fb-434a-b82d-cd14e4f4ea37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458713214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2458713214
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.2191532143
Short name T308
Test name
Test status
Simulation time 513651959525 ps
CPU time 3985.23 seconds
Started Dec 31 12:28:25 PM PST 23
Finished Dec 31 01:34:53 PM PST 23
Peak memory 252776 kb
Host smart-e3057007-41a0-4070-9eb1-4e76c9f1f036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191532143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.2191532143
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.417472937
Short name T118
Test name
Test status
Simulation time 171668586978 ps
CPU time 813.23 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:40:53 PM PST 23
Peak memory 229712 kb
Host smart-11f8bcfb-e1f8-4a03-b6cf-fab9c866326c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417472937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.417472937
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3987152140
Short name T54
Test name
Test status
Simulation time 334017144418 ps
CPU time 2508.21 seconds
Started Dec 31 12:27:30 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 215124 kb
Host smart-99d6094d-9826-4fee-ba95-c5114927fa87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987152140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3987152140
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.350271707
Short name T480
Test name
Test status
Simulation time 242266245458 ps
CPU time 899.34 seconds
Started Dec 31 12:27:57 PM PST 23
Finished Dec 31 12:43:02 PM PST 23
Peak memory 239804 kb
Host smart-b38496bc-fd25-442e-ae77-b7db54b475c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350271707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.350271707
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.2902837695
Short name T506
Test name
Test status
Simulation time 66035646731 ps
CPU time 821.18 seconds
Started Dec 31 12:28:11 PM PST 23
Finished Dec 31 12:41:54 PM PST 23
Peak memory 230608 kb
Host smart-19469b4c-710b-4a75-803c-8900832eb45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902837695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.2902837695
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.766413125
Short name T303
Test name
Test status
Simulation time 241576705242 ps
CPU time 1593.35 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 229036 kb
Host smart-3301b80a-38a7-4d70-ab57-b29470d42177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766413125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.766413125
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.607902645
Short name T548
Test name
Test status
Simulation time 196550819036 ps
CPU time 1237.18 seconds
Started Dec 31 12:27:42 PM PST 23
Finished Dec 31 12:48:20 PM PST 23
Peak memory 215712 kb
Host smart-0fb0573b-0fcb-4586-a5df-bd495ba28bc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607902645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.607902645
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.490519295
Short name T139
Test name
Test status
Simulation time 40828759457 ps
CPU time 1961.88 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 01:00:22 PM PST 23
Peak memory 246288 kb
Host smart-5654db05-3a1f-426e-ba06-729c0ca6f487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490519295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.490519295
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3231402459
Short name T795
Test name
Test status
Simulation time 29685323 ps
CPU time 0.56 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:27:41 PM PST 23
Peak memory 192844 kb
Host smart-149c6186-09e2-4227-9ed8-8c5e3777510d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231402459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3231402459
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.725600372
Short name T520
Test name
Test status
Simulation time 918368524 ps
CPU time 25.35 seconds
Started Dec 31 12:28:22 PM PST 23
Finished Dec 31 12:28:49 PM PST 23
Peak memory 206748 kb
Host smart-5471d38e-4c69-48c9-8609-a065b3f65171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725600372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.725600372
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.687929158
Short name T653
Test name
Test status
Simulation time 923052827 ps
CPU time 39.71 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:46 PM PST 23
Peak memory 198604 kb
Host smart-5b62eb8f-afd6-4706-97f6-68d1478a6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687929158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.687929158
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.449388678
Short name T731
Test name
Test status
Simulation time 21259367715 ps
CPU time 116.1 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 12:28:27 PM PST 23
Peak memory 198656 kb
Host smart-092642ec-44a1-4a7b-bd30-f29793cc579c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449388678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.449388678
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.785452169
Short name T317
Test name
Test status
Simulation time 1857528062 ps
CPU time 86.88 seconds
Started Dec 31 12:26:07 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198552 kb
Host smart-70be7f66-e75d-474c-999c-119758885a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785452169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.785452169
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3611310869
Short name T225
Test name
Test status
Simulation time 2588389529 ps
CPU time 38.84 seconds
Started Dec 31 12:26:39 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 198600 kb
Host smart-bc294d8c-3d15-495e-bea4-6682a330b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611310869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3611310869
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.127622791
Short name T391
Test name
Test status
Simulation time 242930825 ps
CPU time 3.6 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 198852 kb
Host smart-48f3b018-efed-4eae-a439-b56b8f47b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127622791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.127622791
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1837959868
Short name T134
Test name
Test status
Simulation time 36698091509 ps
CPU time 1674.78 seconds
Started Dec 31 12:28:18 PM PST 23
Finished Dec 31 12:56:14 PM PST 23
Peak memory 228356 kb
Host smart-a9908b0a-dbfd-4d25-bfad-ff5ad61b99b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837959868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1837959868
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2809071374
Short name T703
Test name
Test status
Simulation time 379521691615 ps
CPU time 2682.62 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 275740 kb
Host smart-532f33cd-774a-4291-aecc-cdae6dcdc837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809071374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2809071374
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2961722482
Short name T663
Test name
Test status
Simulation time 270639620 ps
CPU time 1.08 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 196684 kb
Host smart-8056f4d7-abdd-4e18-9209-2828e055b15c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961722482 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2961722482
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3935267610
Short name T644
Test name
Test status
Simulation time 8239357832 ps
CPU time 390.89 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 198340 kb
Host smart-1425ff8c-93dc-4cbf-a3c8-feab14d4944c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935267610 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.3935267610
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4240656634
Short name T522
Test name
Test status
Simulation time 735123452 ps
CPU time 31.58 seconds
Started Dec 31 12:28:14 PM PST 23
Finished Dec 31 12:28:47 PM PST 23
Peak memory 198540 kb
Host smart-55362f57-afb2-45ec-9f2b-7d0b097e5b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240656634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4240656634
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.1635691060
Short name T600
Test name
Test status
Simulation time 192781854331 ps
CPU time 4122.35 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 01:36:50 PM PST 23
Peak memory 263812 kb
Host smart-4f4b598d-6d1a-4b6d-84e8-5e4814ecff15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635691060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.1635691060
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.136415444
Short name T640
Test name
Test status
Simulation time 14316624402 ps
CPU time 457.23 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:35:39 PM PST 23
Peak memory 198672 kb
Host smart-4b8a7966-3c17-4b44-ab91-1d48a4e30acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136415444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.136415444
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.411907003
Short name T403
Test name
Test status
Simulation time 5004946858 ps
CPU time 9.95 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:28:31 PM PST 23
Peak memory 198724 kb
Host smart-244f2211-fb92-4fac-8564-f7a37223bdbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411907003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.411907003
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1548883307
Short name T717
Test name
Test status
Simulation time 82032324297 ps
CPU time 1499.39 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:52:46 PM PST 23
Peak memory 258052 kb
Host smart-4d7a8864-d3f7-416d-b710-3b9ea9ef9f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548883307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1548883307
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.1934408313
Short name T288
Test name
Test status
Simulation time 33491812390 ps
CPU time 146.25 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:30:33 PM PST 23
Peak memory 215128 kb
Host smart-206afe84-f270-4c19-9d40-59a7c8c726f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934408313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.1934408313
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3310397837
Short name T722
Test name
Test status
Simulation time 15470670661 ps
CPU time 144.52 seconds
Started Dec 31 12:28:26 PM PST 23
Finished Dec 31 12:30:53 PM PST 23
Peak memory 198832 kb
Host smart-601f0c78-d9a5-4321-9c12-62ba59c28577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310397837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3310397837
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.2313746681
Short name T328
Test name
Test status
Simulation time 132068743463 ps
CPU time 2353.02 seconds
Started Dec 31 12:29:42 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 258892 kb
Host smart-901d18a8-0372-4056-a107-1da7b4836dbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313746681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.2313746681
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.341572121
Short name T343
Test name
Test status
Simulation time 117900756414 ps
CPU time 1709.93 seconds
Started Dec 31 12:28:32 PM PST 23
Finished Dec 31 12:57:10 PM PST 23
Peak memory 256116 kb
Host smart-0bed9850-5c87-485d-a437-ad7099f7354a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341572121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.341572121
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2044612810
Short name T239
Test name
Test status
Simulation time 14937570 ps
CPU time 0.55 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 192868 kb
Host smart-f578f2d9-e0bc-47c4-b3b7-dd246e72b86d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044612810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2044612810
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2758049724
Short name T772
Test name
Test status
Simulation time 1427861269 ps
CPU time 9.38 seconds
Started Dec 31 12:25:57 PM PST 23
Finished Dec 31 12:26:13 PM PST 23
Peak memory 214460 kb
Host smart-4f1e28e1-5b78-4c50-ac88-c65c2774d32c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758049724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2758049724
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3073139294
Short name T843
Test name
Test status
Simulation time 11106013485 ps
CPU time 39.38 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:27:25 PM PST 23
Peak memory 198692 kb
Host smart-099a2630-f59e-4556-983b-94126d90f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073139294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3073139294
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3295195173
Short name T599
Test name
Test status
Simulation time 1625738346 ps
CPU time 42.51 seconds
Started Dec 31 12:26:05 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 198448 kb
Host smart-38114853-f781-4198-b6b1-8df6faaf79a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295195173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3295195173
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.32277138
Short name T459
Test name
Test status
Simulation time 8179170670 ps
CPU time 92.58 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:27:59 PM PST 23
Peak memory 198576 kb
Host smart-b1ebc89a-324a-4828-b3b6-f773feab3aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32277138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.32277138
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3101724471
Short name T382
Test name
Test status
Simulation time 2927811428 ps
CPU time 33.49 seconds
Started Dec 31 12:28:36 PM PST 23
Finished Dec 31 12:29:18 PM PST 23
Peak memory 199060 kb
Host smart-06c2246c-817b-4f5a-af66-398f7f96bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101724471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3101724471
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2387960602
Short name T462
Test name
Test status
Simulation time 577090473 ps
CPU time 3.21 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 198616 kb
Host smart-e0deff41-0c47-4d65-ad6f-e5e24d0fea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387960602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2387960602
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2175726117
Short name T762
Test name
Test status
Simulation time 48325741101 ps
CPU time 1113.28 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 246936 kb
Host smart-03cda209-0b08-4fc9-93d3-5280f74db81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175726117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2175726117
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.1536456576
Short name T364
Test name
Test status
Simulation time 589970268939 ps
CPU time 2534.51 seconds
Started Dec 31 12:27:24 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 256124 kb
Host smart-12111980-a67c-4808-9ab9-d257866fc2c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536456576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.1536456576
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1023878235
Short name T3
Test name
Test status
Simulation time 145999116 ps
CPU time 1.18 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:23 PM PST 23
Peak memory 197204 kb
Host smart-bc208cb1-41ac-4e64-b213-4a283141136a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023878235 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1023878235
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2970748286
Short name T481
Test name
Test status
Simulation time 130071647691 ps
CPU time 376.17 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:32:41 PM PST 23
Peak memory 198552 kb
Host smart-8469a778-18f4-4757-9edd-4757e959de1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970748286 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.2970748286
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2929960229
Short name T544
Test name
Test status
Simulation time 3662548723 ps
CPU time 14.78 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 198616 kb
Host smart-e4349380-a432-423d-a322-283c3d8d8e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929960229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2929960229
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.4005358365
Short name T357
Test name
Test status
Simulation time 136758235152 ps
CPU time 5338.53 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 01:56:38 PM PST 23
Peak memory 272712 kb
Host smart-ed28c22e-965a-481a-8078-1db837372815
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005358365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.4005358365
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.620718395
Short name T695
Test name
Test status
Simulation time 1168103391566 ps
CPU time 1927.57 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 01:00:23 PM PST 23
Peak memory 240752 kb
Host smart-fe8ee6ee-4431-4ead-b5b7-8dd1c2be1c7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620718395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.620718395
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.772374150
Short name T581
Test name
Test status
Simulation time 702156019349 ps
CPU time 697.52 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:39:26 PM PST 23
Peak memory 249392 kb
Host smart-f49b91e9-988f-4d2c-8555-1a45a55c83dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772374150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.772374150
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.2573161759
Short name T610
Test name
Test status
Simulation time 25165479677 ps
CPU time 916.26 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:43:04 PM PST 23
Peak memory 206960 kb
Host smart-a83f5265-dfa9-4626-b469-3acecddea147
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573161759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.2573161759
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3263469618
Short name T435
Test name
Test status
Simulation time 173319872091 ps
CPU time 1574.02 seconds
Started Dec 31 12:27:31 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 247912 kb
Host smart-6900167d-3925-4d53-b092-4901eb07b364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263469618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.3263469618
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.474058470
Short name T794
Test name
Test status
Simulation time 55419078700 ps
CPU time 973.75 seconds
Started Dec 31 12:28:25 PM PST 23
Finished Dec 31 12:44:42 PM PST 23
Peak memory 226140 kb
Host smart-e45f7c75-81aa-4393-a894-fc39726ca395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474058470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.474058470
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.749211549
Short name T804
Test name
Test status
Simulation time 275434210272 ps
CPU time 2531.05 seconds
Started Dec 31 12:28:34 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 255496 kb
Host smart-8b63c7c8-7a89-441e-bc78-814a12ac15e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749211549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.749211549
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.2544106274
Short name T779
Test name
Test status
Simulation time 44171262399 ps
CPU time 737.87 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:40:27 PM PST 23
Peak memory 215060 kb
Host smart-e5d5b875-fb92-4ea3-aa23-106f3d32ea0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544106274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.2544106274
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.3856594260
Short name T349
Test name
Test status
Simulation time 375092622066 ps
CPU time 1611.24 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 242104 kb
Host smart-622fbf94-e45a-4d52-a057-4d66516fb5d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856594260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.3856594260
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1593051769
Short name T44
Test name
Test status
Simulation time 54036102247 ps
CPU time 2696.76 seconds
Started Dec 31 12:28:27 PM PST 23
Finished Dec 31 01:13:30 PM PST 23
Peak memory 224592 kb
Host smart-045e9046-1e2e-4184-a701-ded1923bb000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593051769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1593051769
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3168298059
Short name T575
Test name
Test status
Simulation time 11663398 ps
CPU time 0.55 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:28:21 PM PST 23
Peak memory 192928 kb
Host smart-f2540d9b-d72b-4164-a6cc-c7e15853ccfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168298059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3168298059
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1543332648
Short name T656
Test name
Test status
Simulation time 6654930140 ps
CPU time 48.94 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:29:10 PM PST 23
Peak memory 217064 kb
Host smart-7f80f3d5-b393-418c-90e4-eff58df314a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543332648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1543332648
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3059478732
Short name T363
Test name
Test status
Simulation time 1016919722 ps
CPU time 44.17 seconds
Started Dec 31 12:28:13 PM PST 23
Finished Dec 31 12:29:04 PM PST 23
Peak memory 198540 kb
Host smart-09af57f1-0e9b-4d37-a7eb-1c6e803e6d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059478732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3059478732
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.195022565
Short name T594
Test name
Test status
Simulation time 6049224907 ps
CPU time 73.49 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 12:27:44 PM PST 23
Peak memory 198576 kb
Host smart-e1da5a81-9897-4150-9c26-33bc909211d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195022565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.195022565
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3859675707
Short name T507
Test name
Test status
Simulation time 17989016919 ps
CPU time 48.28 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:27:36 PM PST 23
Peak memory 198400 kb
Host smart-ca1426c6-29af-4a64-a5c7-6dcd89e2843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859675707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3859675707
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.533317781
Short name T856
Test name
Test status
Simulation time 8444752828 ps
CPU time 36.41 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 12:28:46 PM PST 23
Peak memory 198680 kb
Host smart-99c52ac8-76ec-4ab2-b7de-03cf373aca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533317781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.533317781
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3503391483
Short name T336
Test name
Test status
Simulation time 1152947474 ps
CPU time 2.25 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 12:28:18 PM PST 23
Peak memory 198500 kb
Host smart-d32e0afc-3fc0-4443-bc1c-53602fefda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503391483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3503391483
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2609380759
Short name T262
Test name
Test status
Simulation time 82162592473 ps
CPU time 947.4 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:43:12 PM PST 23
Peak memory 207100 kb
Host smart-9a75828c-8b2f-4385-aec9-6da2d65f34e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609380759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2609380759
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.3610313912
Short name T140
Test name
Test status
Simulation time 265492873355 ps
CPU time 1672.8 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:54:25 PM PST 23
Peak memory 242744 kb
Host smart-28b66970-49c1-48df-98f2-04d2dcb4a1bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610313912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.3610313912
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3376347270
Short name T534
Test name
Test status
Simulation time 30241734 ps
CPU time 1.03 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 196048 kb
Host smart-6ab97c92-a899-4d66-b048-b3711b3af157
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376347270 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3376347270
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1389979035
Short name T438
Test name
Test status
Simulation time 8314195486 ps
CPU time 356.57 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:33:13 PM PST 23
Peak memory 198680 kb
Host smart-a6b9ab21-2b99-4371-8969-c9eea70a7ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389979035 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.1389979035
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3683474906
Short name T842
Test name
Test status
Simulation time 2375804266 ps
CPU time 40.9 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:28:44 PM PST 23
Peak memory 198644 kb
Host smart-cab5efe1-2e41-4b91-8ae0-a4592597959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683474906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3683474906
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.2742259143
Short name T131
Test name
Test status
Simulation time 517492092139 ps
CPU time 6329.9 seconds
Started Dec 31 12:28:33 PM PST 23
Finished Dec 31 02:14:12 PM PST 23
Peak memory 272532 kb
Host smart-387cbd37-9f93-4a99-9211-ea3aa0b873a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742259143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.2742259143
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1788129511
Short name T814
Test name
Test status
Simulation time 60482441059 ps
CPU time 199.85 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:31:08 PM PST 23
Peak memory 215152 kb
Host smart-7d1f518c-106c-469e-bf06-1b796263c7dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788129511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.1788129511
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.857660192
Short name T859
Test name
Test status
Simulation time 24069926174 ps
CPU time 460.62 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:35:42 PM PST 23
Peak memory 215068 kb
Host smart-3a96af57-6177-4eb0-a7aa-9d1a32044f4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857660192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.857660192
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.4189793120
Short name T734
Test name
Test status
Simulation time 129671029229 ps
CPU time 1903.29 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:59:24 PM PST 23
Peak memory 239804 kb
Host smart-34e77c31-4a40-4ab4-8629-5ba8c4f0df8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189793120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.4189793120
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.3056030862
Short name T238
Test name
Test status
Simulation time 17953368872 ps
CPU time 275.84 seconds
Started Dec 31 12:28:28 PM PST 23
Finished Dec 31 12:33:13 PM PST 23
Peak memory 207040 kb
Host smart-0234c989-8665-4cb4-b0d9-8a26b7aef3b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056030862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.3056030862
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.300680500
Short name T127
Test name
Test status
Simulation time 90644445080 ps
CPU time 1935.32 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 01:00:55 PM PST 23
Peak memory 223368 kb
Host smart-a5465f93-866c-4b7a-97a9-5aa66fbc43b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300680500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.300680500
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.4272310703
Short name T637
Test name
Test status
Simulation time 191251987158 ps
CPU time 882.57 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:42:28 PM PST 23
Peak memory 223336 kb
Host smart-ca407d3e-3469-4ea2-bbb9-bd4cf60360cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272310703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.4272310703
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1793779802
Short name T730
Test name
Test status
Simulation time 48942277524 ps
CPU time 911.2 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:43:01 PM PST 23
Peak memory 256072 kb
Host smart-5d27649f-3398-43a1-851f-079ef54b919b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793779802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1793779802
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3008093555
Short name T808
Test name
Test status
Simulation time 31865567228 ps
CPU time 262.15 seconds
Started Dec 31 12:29:44 PM PST 23
Finished Dec 31 12:34:09 PM PST 23
Peak memory 232576 kb
Host smart-081d756f-9d31-435b-b871-392cb94b1ac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008093555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3008093555
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1562656661
Short name T309
Test name
Test status
Simulation time 54242118 ps
CPU time 0.53 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 192912 kb
Host smart-c428782c-6908-4d2a-ae31-473f6ba229fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562656661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1562656661
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3632221425
Short name T334
Test name
Test status
Simulation time 1794386700 ps
CPU time 28.93 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:27:01 PM PST 23
Peak memory 231240 kb
Host smart-ffd3f1f3-f85d-4643-9bed-f80b42bec67f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632221425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3632221425
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1723723084
Short name T815
Test name
Test status
Simulation time 12028032613 ps
CPU time 34.02 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:27:02 PM PST 23
Peak memory 198580 kb
Host smart-592ab7e6-dd1c-4e55-9b71-f6db77dd3950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723723084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1723723084
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3709874648
Short name T627
Test name
Test status
Simulation time 11177971273 ps
CPU time 139.72 seconds
Started Dec 31 12:26:33 PM PST 23
Finished Dec 31 12:28:56 PM PST 23
Peak memory 198652 kb
Host smart-774cafd7-bf84-4f82-b55e-7b77e683a2c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709874648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3709874648
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.916128199
Short name T623
Test name
Test status
Simulation time 3177645994 ps
CPU time 43.2 seconds
Started Dec 31 12:26:14 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198660 kb
Host smart-cf5faeb0-ce0f-41b9-a563-55b780dd923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916128199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.916128199
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3768103049
Short name T455
Test name
Test status
Simulation time 1969945176 ps
CPU time 36.78 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:28:39 PM PST 23
Peak memory 198548 kb
Host smart-cddbe8fe-5d89-4599-8f00-2a10c234fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768103049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3768103049
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1567043310
Short name T484
Test name
Test status
Simulation time 427279213 ps
CPU time 2.47 seconds
Started Dec 31 12:27:07 PM PST 23
Finished Dec 31 12:27:11 PM PST 23
Peak memory 198376 kb
Host smart-2f3dfff5-b93d-4cbd-bf41-1a0d81c83898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567043310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1567043310
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1991121054
Short name T525
Test name
Test status
Simulation time 14639123673 ps
CPU time 683.79 seconds
Started Dec 31 12:28:30 PM PST 23
Finished Dec 31 12:40:04 PM PST 23
Peak memory 206920 kb
Host smart-5fed7279-9e6b-471f-bde9-4a769a97571e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991121054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1991121054
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.2961898827
Short name T107
Test name
Test status
Simulation time 85746325882 ps
CPU time 1246.75 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 243492 kb
Host smart-e5566a62-0de7-4115-8aa5-1b6f397b35dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961898827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.2961898827
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.614590946
Short name T327
Test name
Test status
Simulation time 136281669 ps
CPU time 0.84 seconds
Started Dec 31 12:29:50 PM PST 23
Finished Dec 31 12:29:53 PM PST 23
Peak memory 195452 kb
Host smart-b1113512-81aa-4c35-9527-d4ee8a85e607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614590946 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.614590946
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3925706162
Short name T607
Test name
Test status
Simulation time 4732881545 ps
CPU time 37.82 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 198740 kb
Host smart-deea3c5a-a8f7-4a09-abff-cfc8de5369af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925706162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3925706162
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1305606505
Short name T626
Test name
Test status
Simulation time 80766678897 ps
CPU time 303.4 seconds
Started Dec 31 12:28:24 PM PST 23
Finished Dec 31 12:33:30 PM PST 23
Peak memory 241064 kb
Host smart-0e4ca06e-2258-4fd3-ae42-79637bc23d24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305606505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.1305606505
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.4176947093
Short name T279
Test name
Test status
Simulation time 71984073961 ps
CPU time 1412.31 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:51:04 PM PST 23
Peak memory 224660 kb
Host smart-27cf6df6-7624-44f4-af60-b83ed972cc5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176947093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.4176947093
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.3958684555
Short name T112
Test name
Test status
Simulation time 89687691337 ps
CPU time 252.53 seconds
Started Dec 31 12:27:27 PM PST 23
Finished Dec 31 12:31:40 PM PST 23
Peak memory 223300 kb
Host smart-aa5cbda2-2c49-42c0-b47c-93cfb6e82f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958684555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.3958684555
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.3147876630
Short name T550
Test name
Test status
Simulation time 376327745856 ps
CPU time 1642.55 seconds
Started Dec 31 12:28:09 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 264384 kb
Host smart-f075d07a-c373-4d80-95d8-2c4053c3cfb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147876630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.3147876630
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.3636328533
Short name T124
Test name
Test status
Simulation time 19341301718 ps
CPU time 319.19 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:32:59 PM PST 23
Peak memory 233156 kb
Host smart-57c70e3b-07f1-4486-8340-588455df82c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636328533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.3636328533
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.147066220
Short name T791
Test name
Test status
Simulation time 160909977745 ps
CPU time 1326.92 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 231500 kb
Host smart-7867fa3e-0e98-4f92-bfd7-1bcf7d1e2cc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147066220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.147066220
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.1038889035
Short name T763
Test name
Test status
Simulation time 25918563838 ps
CPU time 184.13 seconds
Started Dec 31 12:28:22 PM PST 23
Finished Dec 31 12:31:27 PM PST 23
Peak memory 214660 kb
Host smart-46018fcb-7eb8-48ab-9f4c-64507dfb86bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038889035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.1038889035
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.1363213346
Short name T6
Test name
Test status
Simulation time 110048780411 ps
CPU time 349.66 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:33:52 PM PST 23
Peak memory 206840 kb
Host smart-0488669e-270a-4711-9cb8-73349ad2a6e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363213346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.1363213346
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.4045950364
Short name T146
Test name
Test status
Simulation time 189039566481 ps
CPU time 1286.42 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 228440 kb
Host smart-0f8951a2-6e5a-4d98-a8ff-8a6bdc0ee458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045950364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.4045950364
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.726694743
Short name T576
Test name
Test status
Simulation time 288599324887 ps
CPU time 1584.2 seconds
Started Dec 31 12:28:18 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 223348 kb
Host smart-3a166267-e826-42b0-875a-19e0150e10af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726694743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.726694743
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2993937122
Short name T549
Test name
Test status
Simulation time 14649317 ps
CPU time 0.56 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 193956 kb
Host smart-04d52948-34cd-433b-87e8-d332adee268f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993937122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2993937122
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4137372443
Short name T608
Test name
Test status
Simulation time 6019475237 ps
CPU time 42.15 seconds
Started Dec 31 12:26:09 PM PST 23
Finished Dec 31 12:26:56 PM PST 23
Peak memory 214700 kb
Host smart-c838a410-17e1-4a24-a134-86f44d4d9b91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137372443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4137372443
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1029093802
Short name T444
Test name
Test status
Simulation time 1333806780 ps
CPU time 16.53 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:34 PM PST 23
Peak memory 198512 kb
Host smart-bf0beab5-74c3-48d6-bb91-9b3b5c4b727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029093802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1029093802
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4162438976
Short name T587
Test name
Test status
Simulation time 1063299585 ps
CPU time 50.66 seconds
Started Dec 31 12:28:23 PM PST 23
Finished Dec 31 12:29:15 PM PST 23
Peak memory 198532 kb
Host smart-0b733d3e-8712-4b80-840e-d930a81995ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162438976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4162438976
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3918293585
Short name T352
Test name
Test status
Simulation time 4825012570 ps
CPU time 57.88 seconds
Started Dec 31 12:27:52 PM PST 23
Finished Dec 31 12:28:55 PM PST 23
Peak memory 198592 kb
Host smart-021eddcf-299a-4eff-95b0-0a18ebd94b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918293585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3918293585
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3187456487
Short name T619
Test name
Test status
Simulation time 38837269094 ps
CPU time 105.48 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:28:28 PM PST 23
Peak memory 198632 kb
Host smart-a00cd6a9-c60f-4f71-9042-2345cbd6b44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187456487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3187456487
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.269952169
Short name T552
Test name
Test status
Simulation time 86741097 ps
CPU time 1 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 197108 kb
Host smart-37eecaa2-ca6f-4f5b-8234-eafa91cd46de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269952169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.269952169
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.887687228
Short name T612
Test name
Test status
Simulation time 63044919670 ps
CPU time 1263.68 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 223300 kb
Host smart-bde19043-a3ca-4b01-89c5-7da1f0e29fcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887687228 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.887687228
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3298664917
Short name T472
Test name
Test status
Simulation time 170164589 ps
CPU time 0.84 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:27:47 PM PST 23
Peak memory 195652 kb
Host smart-acd1edc6-a156-4c42-b3cf-75efa20c3526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298664917 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3298664917
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.643730431
Short name T699
Test name
Test status
Simulation time 365049735 ps
CPU time 17.5 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 198556 kb
Host smart-ee2e9511-e640-4125-b8ec-a411577d4afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643730431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.643730431
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3585367117
Short name T411
Test name
Test status
Simulation time 408657173324 ps
CPU time 2997.98 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 01:17:17 PM PST 23
Peak memory 264060 kb
Host smart-fa29a9f6-99ba-417a-9dbe-ae5af10d6db1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585367117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3585367117
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.2475798500
Short name T243
Test name
Test status
Simulation time 428635423924 ps
CPU time 1163.58 seconds
Started Dec 31 12:28:08 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 225928 kb
Host smart-8512afaf-5bb3-4488-81f4-c2254bb062e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475798500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.2475798500
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.2555584535
Short name T412
Test name
Test status
Simulation time 25215152754 ps
CPU time 472.5 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:36:14 PM PST 23
Peak memory 244920 kb
Host smart-7a5f8170-31e6-4e7f-b2da-ea0f55e2008a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555584535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.2555584535
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.3426245576
Short name T416
Test name
Test status
Simulation time 1820395520478 ps
CPU time 1975.54 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 01:00:10 PM PST 23
Peak memory 250952 kb
Host smart-efefaa45-eb11-457e-bf21-239875426a61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426245576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.3426245576
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.968238906
Short name T563
Test name
Test status
Simulation time 76915144354 ps
CPU time 727.98 seconds
Started Dec 31 12:28:39 PM PST 23
Finished Dec 31 12:40:56 PM PST 23
Peak memory 215148 kb
Host smart-3d96f3dc-8910-41e7-906d-2e8ece08c6c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968238906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.968238906
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.3972253945
Short name T589
Test name
Test status
Simulation time 15535905315 ps
CPU time 216.98 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:31:39 PM PST 23
Peak memory 206852 kb
Host smart-33b7ca18-9bc3-4fae-b0e1-402f8d3d7502
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972253945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.3972253945
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2815210943
Short name T388
Test name
Test status
Simulation time 144996474319 ps
CPU time 1230.57 seconds
Started Dec 31 12:28:48 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 245432 kb
Host smart-d085e2d0-faf0-45ec-9bcf-627fd2adf965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815210943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2815210943
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.179007530
Short name T616
Test name
Test status
Simulation time 72792414580 ps
CPU time 1026.59 seconds
Started Dec 31 12:28:32 PM PST 23
Finished Dec 31 12:45:47 PM PST 23
Peak memory 243220 kb
Host smart-05d0b388-065a-4579-a78a-dc3f129b26f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179007530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.179007530
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3692474941
Short name T409
Test name
Test status
Simulation time 14497023 ps
CPU time 0.53 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:28:09 PM PST 23
Peak memory 193000 kb
Host smart-ddcb814e-4b5f-4fec-bc46-dc0bd300e2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692474941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3692474941
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1557455507
Short name T827
Test name
Test status
Simulation time 1024087387 ps
CPU time 16.34 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:27:56 PM PST 23
Peak memory 214960 kb
Host smart-597f1a7b-ca21-4152-8821-d14cfc7a7ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557455507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1557455507
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1773806183
Short name T777
Test name
Test status
Simulation time 105471893 ps
CPU time 1.32 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 198520 kb
Host smart-f5efbe72-ab81-4128-80de-f03f0a0ee4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773806183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1773806183
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3150113378
Short name T527
Test name
Test status
Simulation time 6044549756 ps
CPU time 69.91 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:27:33 PM PST 23
Peak memory 198616 kb
Host smart-3df2aeb2-1124-4e3c-bb8f-43ef8d698b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150113378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3150113378
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.735457118
Short name T636
Test name
Test status
Simulation time 6362486033 ps
CPU time 49.14 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:54 PM PST 23
Peak memory 198640 kb
Host smart-805f1d0f-86cc-4621-a7f3-85902a2777e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735457118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.735457118
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1283375046
Short name T590
Test name
Test status
Simulation time 3258495308 ps
CPU time 46.78 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:28:06 PM PST 23
Peak memory 198676 kb
Host smart-ff26bbad-17a9-4002-98fb-5ba09177be34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283375046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1283375046
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2291783899
Short name T685
Test name
Test status
Simulation time 379216068 ps
CPU time 1.15 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:02 PM PST 23
Peak memory 198084 kb
Host smart-7e3854eb-fce0-4eea-a844-c0c4891a884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291783899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2291783899
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2543701095
Short name T645
Test name
Test status
Simulation time 52342250246 ps
CPU time 865.84 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:41:36 PM PST 23
Peak memory 231040 kb
Host smart-71c718aa-bffc-42cc-84f0-8dda6d4f0be9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543701095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2543701095
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.448865721
Short name T108
Test name
Test status
Simulation time 118937629034 ps
CPU time 3883.92 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 01:32:46 PM PST 23
Peak memory 272488 kb
Host smart-75053a28-9613-4da8-85eb-2434bf27db36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448865721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.448865721
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1629454332
Short name T396
Test name
Test status
Simulation time 133484290 ps
CPU time 1.14 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:27:48 PM PST 23
Peak memory 196516 kb
Host smart-2d85fc28-a542-4089-8840-0c78df709cf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629454332 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1629454332
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2124418912
Short name T541
Test name
Test status
Simulation time 32159134257 ps
CPU time 396.11 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:33:52 PM PST 23
Peak memory 198684 kb
Host smart-2caafe8d-d16b-4958-8440-5dd0da182dba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124418912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.2124418912
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1371767539
Short name T757
Test name
Test status
Simulation time 1053017589 ps
CPU time 30.44 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198616 kb
Host smart-636e2837-1e9b-48cf-915b-942b616a6d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371767539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1371767539
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.3203919379
Short name T329
Test name
Test status
Simulation time 350082339644 ps
CPU time 1583.96 seconds
Started Dec 31 12:27:20 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 240112 kb
Host smart-c1a66520-59b7-44d4-ac90-d99278658f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203919379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.3203919379
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3394511041
Short name T574
Test name
Test status
Simulation time 59235187731 ps
CPU time 691.64 seconds
Started Dec 31 12:30:02 PM PST 23
Finished Dec 31 12:41:38 PM PST 23
Peak memory 214624 kb
Host smart-6e74fcdd-922c-4603-a533-ff8bb6eb6728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394511041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.3394511041
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.416497740
Short name T673
Test name
Test status
Simulation time 220567953648 ps
CPU time 1495.78 seconds
Started Dec 31 12:30:12 PM PST 23
Finished Dec 31 12:55:12 PM PST 23
Peak memory 256168 kb
Host smart-ebc36feb-ab18-48e9-8e8e-708db5010483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416497740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.416497740
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.721909724
Short name T319
Test name
Test status
Simulation time 58914927043 ps
CPU time 1923.71 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:59:33 PM PST 23
Peak memory 255868 kb
Host smart-a991bff7-8fe6-4398-9329-be6ca19d1394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721909724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.721909724
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.1743515369
Short name T740
Test name
Test status
Simulation time 93494064701 ps
CPU time 830.44 seconds
Started Dec 31 12:28:17 PM PST 23
Finished Dec 31 12:42:09 PM PST 23
Peak memory 230304 kb
Host smart-f53cb10f-0516-4cbf-b395-a2c0b7db7fd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743515369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.1743515369
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.1915914707
Short name T737
Test name
Test status
Simulation time 10367492185 ps
CPU time 151.26 seconds
Started Dec 31 12:30:29 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 229512 kb
Host smart-05a55c43-ca64-4aae-9b77-c4ade9f7cf08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915914707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.1915914707
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.299945384
Short name T106
Test name
Test status
Simulation time 128006784029 ps
CPU time 566.51 seconds
Started Dec 31 12:28:03 PM PST 23
Finished Dec 31 12:37:35 PM PST 23
Peak memory 224388 kb
Host smart-6012c600-765f-4900-942b-fff1337b307d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299945384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.299945384
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.1367262620
Short name T277
Test name
Test status
Simulation time 497383973446 ps
CPU time 1712.96 seconds
Started Dec 31 12:29:14 PM PST 23
Finished Dec 31 12:57:52 PM PST 23
Peak memory 260088 kb
Host smart-f26b8ac5-7b56-4e6c-b6a2-f09c6ee26796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367262620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.1367262620
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.3036944561
Short name T494
Test name
Test status
Simulation time 127753267622 ps
CPU time 1816.1 seconds
Started Dec 31 12:28:40 PM PST 23
Finished Dec 31 12:59:05 PM PST 23
Peak memory 214600 kb
Host smart-fc41ea31-5f18-4780-954d-15f8f396f8cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036944561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.3036944561
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.994490166
Short name T691
Test name
Test status
Simulation time 14459115 ps
CPU time 0.54 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 192880 kb
Host smart-462d8ad4-4359-4014-afb1-3a04b1cba21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994490166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.994490166
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2551581602
Short name T543
Test name
Test status
Simulation time 1667452203 ps
CPU time 10.94 seconds
Started Dec 31 12:27:51 PM PST 23
Finished Dec 31 12:28:04 PM PST 23
Peak memory 206728 kb
Host smart-2178adf1-28e6-4570-98c3-8cd19e00af72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2551581602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2551581602
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1040610038
Short name T711
Test name
Test status
Simulation time 1285589540 ps
CPU time 17.74 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:49 PM PST 23
Peak memory 198500 kb
Host smart-6da4970f-4103-45df-890d-ea9626657e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040610038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1040610038
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3741197705
Short name T564
Test name
Test status
Simulation time 2515806270 ps
CPU time 60.06 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:29:10 PM PST 23
Peak memory 198700 kb
Host smart-0f31c24c-3350-401a-9204-57171f018d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741197705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3741197705
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1902490090
Short name T505
Test name
Test status
Simulation time 10688973330 ps
CPU time 141.92 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:30:08 PM PST 23
Peak memory 198740 kb
Host smart-4e578c53-d602-4dd1-9b38-a55976366b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902490090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1902490090
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3016710734
Short name T825
Test name
Test status
Simulation time 22385104575 ps
CPU time 76.38 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:28:29 PM PST 23
Peak memory 198744 kb
Host smart-17e0a679-e07c-45aa-a642-051f4acdc784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016710734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3016710734
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3604377680
Short name T845
Test name
Test status
Simulation time 42156386 ps
CPU time 0.86 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:26:32 PM PST 23
Peak memory 195568 kb
Host smart-b953ef48-4164-494e-939f-0b01ebb5850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604377680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3604377680
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2837417386
Short name T341
Test name
Test status
Simulation time 742888680 ps
CPU time 9.21 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 198504 kb
Host smart-ded86581-b0db-40a5-91fa-d16a838931f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837417386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2837417386
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.549740322
Short name T774
Test name
Test status
Simulation time 60397282 ps
CPU time 1.14 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 12:28:50 PM PST 23
Peak memory 196908 kb
Host smart-9f68559e-4c19-450f-9506-671284918eac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549740322 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.549740322
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3699162732
Short name T770
Test name
Test status
Simulation time 108780280899 ps
CPU time 402.59 seconds
Started Dec 31 12:27:20 PM PST 23
Finished Dec 31 12:34:04 PM PST 23
Peak memory 198688 kb
Host smart-c3a8678a-e497-4c49-ac31-e3fa7cb1aaf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699162732 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.3699162732
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1748897188
Short name T123
Test name
Test status
Simulation time 636880418 ps
CPU time 5.97 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 198532 kb
Host smart-e9df7ea9-4a30-4112-9858-f57487a4298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748897188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1748897188
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3443140630
Short name T418
Test name
Test status
Simulation time 53179956178 ps
CPU time 225.92 seconds
Started Dec 31 12:28:37 PM PST 23
Finished Dec 31 12:32:32 PM PST 23
Peak memory 214464 kb
Host smart-0f152855-fb7a-419f-abeb-e554fc03adce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443140630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3443140630
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3868445037
Short name T810
Test name
Test status
Simulation time 97301678615 ps
CPU time 1207.29 seconds
Started Dec 31 12:29:58 PM PST 23
Finished Dec 31 12:50:07 PM PST 23
Peak memory 247916 kb
Host smart-4bea76e7-e94b-48b4-8b44-c3851e5992e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868445037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.3868445037
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.1494095939
Short name T236
Test name
Test status
Simulation time 15649978738 ps
CPU time 225.01 seconds
Started Dec 31 12:28:12 PM PST 23
Finished Dec 31 12:31:59 PM PST 23
Peak memory 214144 kb
Host smart-6863a814-0e4f-4fa0-866d-ca899cef4102
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494095939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.1494095939
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.2375686765
Short name T657
Test name
Test status
Simulation time 82167865441 ps
CPU time 1146.27 seconds
Started Dec 31 12:28:31 PM PST 23
Finished Dec 31 12:47:46 PM PST 23
Peak memory 256184 kb
Host smart-1c450e82-98ab-48b2-9fab-449851977943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375686765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.2375686765
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.1707734930
Short name T642
Test name
Test status
Simulation time 72650381220 ps
CPU time 1045.96 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:45:15 PM PST 23
Peak memory 241660 kb
Host smart-fa5a40c2-9e6d-47d8-bcd0-fdb402d8de2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707734930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.1707734930
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.1318123411
Short name T280
Test name
Test status
Simulation time 64140269411 ps
CPU time 1146.02 seconds
Started Dec 31 12:28:20 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 215136 kb
Host smart-7c90b3ef-a31e-4a25-9e7c-b43a45ef2378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318123411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.1318123411
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.1564222049
Short name T461
Test name
Test status
Simulation time 82287660916 ps
CPU time 2336.53 seconds
Started Dec 31 12:28:55 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 256168 kb
Host smart-3351ec3e-6294-447e-8a15-19dc7d9cd5ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564222049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.1564222049
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.950695720
Short name T5
Test name
Test status
Simulation time 78334524862 ps
CPU time 1422.1 seconds
Started Dec 31 12:28:13 PM PST 23
Finished Dec 31 12:51:57 PM PST 23
Peak memory 241812 kb
Host smart-1ea0bdef-68b9-4730-9ea6-2379ea3370e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950695720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.950695720
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3116765581
Short name T142
Test name
Test status
Simulation time 76939443908 ps
CPU time 2856.21 seconds
Started Dec 31 12:28:11 PM PST 23
Finished Dec 31 01:15:50 PM PST 23
Peak memory 257604 kb
Host smart-9e9d0dd2-6bac-48c9-887d-f872f159c488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116765581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3116765581
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.1885997932
Short name T660
Test name
Test status
Simulation time 61808931469 ps
CPU time 581 seconds
Started Dec 31 12:27:51 PM PST 23
Finished Dec 31 12:37:34 PM PST 23
Peak memory 207184 kb
Host smart-a334e8ff-17eb-4298-9102-d89f73e433d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885997932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.1885997932
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.875188105
Short name T535
Test name
Test status
Simulation time 21121649 ps
CPU time 0.57 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:24 PM PST 23
Peak memory 192980 kb
Host smart-53175116-2e83-437f-a0e5-01bb41f2d6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875188105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.875188105
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3402749728
Short name T655
Test name
Test status
Simulation time 743388062 ps
CPU time 12.85 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:45 PM PST 23
Peak memory 198464 kb
Host smart-70b5ddc9-3eb1-4f08-be8b-ebb64fe9e73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402749728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3402749728
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2355735401
Short name T725
Test name
Test status
Simulation time 6982561349 ps
CPU time 69.82 seconds
Started Dec 31 12:25:18 PM PST 23
Finished Dec 31 12:26:32 PM PST 23
Peak memory 198616 kb
Host smart-8e8ca758-549e-45dc-81de-ecd4e7b1ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355735401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2355735401
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1309161026
Short name T33
Test name
Test status
Simulation time 19596869096 ps
CPU time 135.17 seconds
Started Dec 31 12:22:33 PM PST 23
Finished Dec 31 12:24:50 PM PST 23
Peak memory 199024 kb
Host smart-2a6c658b-4a62-41aa-972a-9e4685e52881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309161026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1309161026
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2464330281
Short name T457
Test name
Test status
Simulation time 51106890582 ps
CPU time 146.49 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:27:46 PM PST 23
Peak memory 198600 kb
Host smart-6a87b05d-d304-4741-9565-c92930ff5332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464330281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2464330281
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2235510231
Short name T792
Test name
Test status
Simulation time 4931187617 ps
CPU time 58.77 seconds
Started Dec 31 12:25:23 PM PST 23
Finished Dec 31 12:26:27 PM PST 23
Peak memory 198340 kb
Host smart-3e31b1c9-faa7-4b48-990e-676317474412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235510231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2235510231
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.3720608445
Short name T306
Test name
Test status
Simulation time 357258684 ps
CPU time 2.13 seconds
Started Dec 31 12:26:56 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198332 kb
Host smart-10bbe171-4c56-404d-a92c-8fc2c5e8e20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720608445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3720608445
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2070653639
Short name T325
Test name
Test status
Simulation time 22483672898 ps
CPU time 259.88 seconds
Started Dec 31 12:22:18 PM PST 23
Finished Dec 31 12:26:39 PM PST 23
Peak memory 215148 kb
Host smart-05b57da0-e0de-4471-9547-622632bf3489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070653639 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2070653639
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2017021109
Short name T664
Test name
Test status
Simulation time 85946985426 ps
CPU time 390.61 seconds
Started Dec 31 12:24:47 PM PST 23
Finished Dec 31 12:31:24 PM PST 23
Peak memory 225840 kb
Host smart-3b7e8062-6f4f-4c55-80f7-a995471472f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017021109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2017021109
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2992309212
Short name T781
Test name
Test status
Simulation time 79980683 ps
CPU time 0.91 seconds
Started Dec 31 12:26:33 PM PST 23
Finished Dec 31 12:26:36 PM PST 23
Peak memory 195616 kb
Host smart-c1369895-2371-4578-90ca-06d87a62afaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992309212 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2992309212
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2264711803
Short name T512
Test name
Test status
Simulation time 25359246834 ps
CPU time 387.17 seconds
Started Dec 31 12:24:29 PM PST 23
Finished Dec 31 12:30:59 PM PST 23
Peak memory 198656 kb
Host smart-0ec97ace-49f8-4cb9-a1f6-673f078c012f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264711803 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.2264711803
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2399845559
Short name T216
Test name
Test status
Simulation time 10797043328 ps
CPU time 28.41 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:35 PM PST 23
Peak memory 198544 kb
Host smart-c7754749-8dc6-4e0b-a068-b3288da2cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399845559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2399845559
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.841729350
Short name T706
Test name
Test status
Simulation time 15460373 ps
CPU time 0.56 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 192876 kb
Host smart-e66de955-1db7-4754-bcd1-767ebc6b251a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841729350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.841729350
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2209541028
Short name T783
Test name
Test status
Simulation time 227760975 ps
CPU time 6.27 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 206700 kb
Host smart-149fae17-8216-4f04-8c7d-0ad5d54c0ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209541028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2209541028
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2102031294
Short name T750
Test name
Test status
Simulation time 287850461 ps
CPU time 2.81 seconds
Started Dec 31 12:27:31 PM PST 23
Finished Dec 31 12:27:35 PM PST 23
Peak memory 198472 kb
Host smart-487df6ef-e385-4510-b1eb-950665c6598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102031294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2102031294
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2086449647
Short name T443
Test name
Test status
Simulation time 1132958390 ps
CPU time 54.27 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:27:27 PM PST 23
Peak memory 198520 kb
Host smart-eb172c59-b65e-47d0-8c6c-93f286c0ddfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086449647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2086449647
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2696120052
Short name T495
Test name
Test status
Simulation time 18220063604 ps
CPU time 111.84 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:28:39 PM PST 23
Peak memory 198696 kb
Host smart-769949ef-96d4-46fb-87e7-366bca3ee9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696120052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2696120052
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1789350510
Short name T654
Test name
Test status
Simulation time 4282694309 ps
CPU time 47.74 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 12:29:04 PM PST 23
Peak memory 198744 kb
Host smart-e598aa3d-eda5-4bf4-b3cc-31d26d39b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789350510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1789350510
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3924625378
Short name T11
Test name
Test status
Simulation time 165947164 ps
CPU time 2.17 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 198480 kb
Host smart-27cb88a9-c1b7-405c-bcaf-22b91eeff69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924625378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3924625378
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2405009502
Short name T620
Test name
Test status
Simulation time 360845761379 ps
CPU time 1077.3 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:44:45 PM PST 23
Peak memory 198668 kb
Host smart-6c1acfa4-3b32-4b6e-b34e-7204c4647804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405009502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2405009502
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1208514257
Short name T381
Test name
Test status
Simulation time 157556625173 ps
CPU time 127.73 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:28:46 PM PST 23
Peak memory 215068 kb
Host smart-11cfed8b-ea9b-4cb2-8547-fe17c90c46be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208514257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1208514257
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2133627540
Short name T475
Test name
Test status
Simulation time 44844505 ps
CPU time 0.91 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 195704 kb
Host smart-b4f0df04-1d7e-4d3b-b82a-8914f3d01964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133627540 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2133627540
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3788217635
Short name T760
Test name
Test status
Simulation time 15797400957 ps
CPU time 365.54 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:34:49 PM PST 23
Peak memory 198616 kb
Host smart-ea1c9786-296a-4a31-8ea5-0516a4494283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788217635 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3788217635
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1594670682
Short name T700
Test name
Test status
Simulation time 1572392029 ps
CPU time 58.31 seconds
Started Dec 31 12:26:57 PM PST 23
Finished Dec 31 12:27:56 PM PST 23
Peak memory 198512 kb
Host smart-70fe64df-7969-41da-8fdf-b75339055e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594670682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1594670682
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2051343424
Short name T789
Test name
Test status
Simulation time 27980308 ps
CPU time 0.55 seconds
Started Dec 31 12:30:06 PM PST 23
Finished Dec 31 12:30:09 PM PST 23
Peak memory 192800 kb
Host smart-395cd129-c16a-4336-8f2e-078993787bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051343424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2051343424
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4029284023
Short name T841
Test name
Test status
Simulation time 12547032204 ps
CPU time 36.74 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:27:24 PM PST 23
Peak memory 206908 kb
Host smart-7dd7ad49-b675-4c42-a10f-3807b60c3a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029284023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4029284023
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2453428954
Short name T305
Test name
Test status
Simulation time 325327819 ps
CPU time 1.85 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 198464 kb
Host smart-b5330e9c-7e73-4e4c-9c89-982bf6c9c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453428954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2453428954
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1513941358
Short name T121
Test name
Test status
Simulation time 2637836332 ps
CPU time 86.13 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:28:39 PM PST 23
Peak memory 198624 kb
Host smart-53aebb76-35e8-4051-be8b-9a35a04569ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513941358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1513941358
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3451765801
Short name T554
Test name
Test status
Simulation time 70620994906 ps
CPU time 107.59 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:28:21 PM PST 23
Peak memory 198552 kb
Host smart-b3311cee-31bd-49c1-9d77-05597c5f22c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451765801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3451765801
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1506047451
Short name T721
Test name
Test status
Simulation time 2048939940 ps
CPU time 25.74 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:28:05 PM PST 23
Peak memory 198544 kb
Host smart-6845bc7e-5a1c-4674-9598-f52683189676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506047451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1506047451
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.934004280
Short name T420
Test name
Test status
Simulation time 2737764083 ps
CPU time 3.9 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 198608 kb
Host smart-2f1a2ee3-c3e8-47b4-a347-b53b1968487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934004280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.934004280
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1770967193
Short name T128
Test name
Test status
Simulation time 57894582423 ps
CPU time 627.71 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 228816 kb
Host smart-2700f113-c671-4fae-b8ce-c3b7d6bd9780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770967193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1770967193
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.1608437159
Short name T249
Test name
Test status
Simulation time 115206999095 ps
CPU time 4646.21 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 01:44:02 PM PST 23
Peak memory 264292 kb
Host smart-c645154a-8b26-43e4-a76c-a1be6456136f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608437159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.1608437159
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.4189929387
Short name T312
Test name
Test status
Simulation time 62932141 ps
CPU time 1.03 seconds
Started Dec 31 12:26:29 PM PST 23
Finished Dec 31 12:26:32 PM PST 23
Peak memory 196156 kb
Host smart-61d05888-e4b8-4fc5-9045-62b92e013198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189929387 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.4189929387
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3252070058
Short name T747
Test name
Test status
Simulation time 45047106667 ps
CPU time 492.8 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:34:47 PM PST 23
Peak memory 198568 kb
Host smart-6a12db1e-f0c0-4646-a8c3-9e719871dda4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252070058 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3252070058
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2715913842
Short name T406
Test name
Test status
Simulation time 4168413884 ps
CPU time 23.85 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:28:02 PM PST 23
Peak memory 198632 kb
Host smart-8e2e6194-6886-4ab8-b616-488c1f40a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715913842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2715913842
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.321962335
Short name T348
Test name
Test status
Simulation time 40756148 ps
CPU time 0.55 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:24 PM PST 23
Peak memory 192920 kb
Host smart-786c28fa-1b55-4fd1-9fe1-4a1903fb664c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321962335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.321962335
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.975850266
Short name T780
Test name
Test status
Simulation time 487242842 ps
CPU time 6.49 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 214604 kb
Host smart-aab7562f-9f3b-4dd1-97af-b779e6f7a362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975850266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.975850266
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3464483883
Short name T624
Test name
Test status
Simulation time 2903846666 ps
CPU time 61.52 seconds
Started Dec 31 12:26:49 PM PST 23
Finished Dec 31 12:27:52 PM PST 23
Peak memory 198620 kb
Host smart-90cf2766-7b19-427b-8b38-8f7126f8b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464483883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3464483883
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1795609661
Short name T510
Test name
Test status
Simulation time 9410468750 ps
CPU time 117.59 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:29:05 PM PST 23
Peak memory 198708 kb
Host smart-829f536f-bf91-40cd-8d6f-1680c8718650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795609661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1795609661
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.982803039
Short name T514
Test name
Test status
Simulation time 398162408 ps
CPU time 18.43 seconds
Started Dec 31 12:28:54 PM PST 23
Finished Dec 31 12:29:18 PM PST 23
Peak memory 197804 kb
Host smart-62eeaeec-eec1-4067-aa7d-2f7684bb2f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982803039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.982803039
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1784150895
Short name T311
Test name
Test status
Simulation time 3032518820 ps
CPU time 13.05 seconds
Started Dec 31 12:26:49 PM PST 23
Finished Dec 31 12:27:04 PM PST 23
Peak memory 198680 kb
Host smart-7f45c1de-35e3-4171-8299-49c3a9557bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784150895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1784150895
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1144019809
Short name T496
Test name
Test status
Simulation time 15769736 ps
CPU time 0.68 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:25 PM PST 23
Peak memory 194316 kb
Host smart-17f424ef-f90f-450e-b46d-ecbad7ed179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144019809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1144019809
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3206429623
Short name T464
Test name
Test status
Simulation time 108993455729 ps
CPU time 1102.22 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:45:23 PM PST 23
Peak memory 214656 kb
Host smart-15c8b054-390d-4ee9-9e23-d91bfbd10fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206429623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3206429623
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.933740738
Short name T556
Test name
Test status
Simulation time 20577241031 ps
CPU time 473.35 seconds
Started Dec 31 12:26:38 PM PST 23
Finished Dec 31 12:34:33 PM PST 23
Peak memory 244828 kb
Host smart-fde5ce82-0cee-4804-b6f7-254783678a8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933740738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.933740738
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3337049072
Short name T300
Test name
Test status
Simulation time 480669575 ps
CPU time 1.1 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 196956 kb
Host smart-592841dd-7242-49d8-a7d6-ffb0320eeb94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337049072 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3337049072
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1198905855
Short name T568
Test name
Test status
Simulation time 7991786221 ps
CPU time 359.15 seconds
Started Dec 31 12:29:08 PM PST 23
Finished Dec 31 12:35:21 PM PST 23
Peak memory 198848 kb
Host smart-51b6de96-64c8-465c-9531-29fc538237e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198905855 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.1198905855
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1197125946
Short name T861
Test name
Test status
Simulation time 8912979783 ps
CPU time 70.27 seconds
Started Dec 31 12:28:54 PM PST 23
Finished Dec 31 12:30:10 PM PST 23
Peak memory 198172 kb
Host smart-1cd3e94c-54ad-48fd-ac8b-850737147571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197125946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1197125946
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1839919187
Short name T436
Test name
Test status
Simulation time 16956529 ps
CPU time 0.55 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:26:59 PM PST 23
Peak memory 192924 kb
Host smart-b751109f-8804-45d2-a870-dad8b3336765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839919187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1839919187
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.186675480
Short name T246
Test name
Test status
Simulation time 1250673837 ps
CPU time 33.04 seconds
Started Dec 31 12:29:38 PM PST 23
Finished Dec 31 12:30:13 PM PST 23
Peak memory 231000 kb
Host smart-6b3931cf-7384-4ac2-b2f7-60904cfea01c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186675480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.186675480
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1600032736
Short name T267
Test name
Test status
Simulation time 3868458853 ps
CPU time 33.77 seconds
Started Dec 31 12:28:33 PM PST 23
Finished Dec 31 12:29:15 PM PST 23
Peak memory 198660 kb
Host smart-bf831c9b-51fb-4db0-b819-2ff4c498deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600032736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1600032736
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.935128648
Short name T839
Test name
Test status
Simulation time 864281664 ps
CPU time 10.86 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:42 PM PST 23
Peak memory 198456 kb
Host smart-1ad1978b-3ce1-4dca-85d5-6a0518780e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935128648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.935128648
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2315886111
Short name T410
Test name
Test status
Simulation time 2342467508 ps
CPU time 9.46 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:27:55 PM PST 23
Peak memory 198636 kb
Host smart-1a274c0d-0fa1-4ea0-9d93-cc09e94a95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315886111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2315886111
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3736990728
Short name T10
Test name
Test status
Simulation time 15568056414 ps
CPU time 10.99 seconds
Started Dec 31 12:28:22 PM PST 23
Finished Dec 31 12:28:35 PM PST 23
Peak memory 198600 kb
Host smart-ce4a40f1-df3f-4420-8c09-c72b75178025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736990728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3736990728
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3022695231
Short name T367
Test name
Test status
Simulation time 625947166 ps
CPU time 3.62 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 198624 kb
Host smart-61bba9ba-5a44-4593-b77b-d882ef01013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022695231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3022695231
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3302553021
Short name T489
Test name
Test status
Simulation time 157133710307 ps
CPU time 421.87 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:33:18 PM PST 23
Peak memory 206816 kb
Host smart-0c80337b-69d0-4a60-aa8d-e9c3be2f02a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302553021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3302553021
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.862707573
Short name T95
Test name
Test status
Simulation time 152088106995 ps
CPU time 1655.17 seconds
Started Dec 31 12:30:09 PM PST 23
Finished Dec 31 12:57:48 PM PST 23
Peak memory 255880 kb
Host smart-43cbd546-448e-4290-b363-f53e7598a3d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862707573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.862707573
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2581296499
Short name T806
Test name
Test status
Simulation time 219686137 ps
CPU time 1.02 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:04 PM PST 23
Peak memory 196416 kb
Host smart-66bb8c39-d40f-4847-8a55-ee6c8e413601
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581296499 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2581296499
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.715711644
Short name T787
Test name
Test status
Simulation time 7500830343 ps
CPU time 362.93 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:32:59 PM PST 23
Peak memory 198648 kb
Host smart-8741c77f-8b57-4dc1-979f-497b774ebdc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715711644 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.hmac_test_sha_vectors.715711644
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3299197688
Short name T771
Test name
Test status
Simulation time 3062553510 ps
CPU time 26.99 seconds
Started Dec 31 12:27:59 PM PST 23
Finished Dec 31 12:28:32 PM PST 23
Peak memory 198636 kb
Host smart-dd36b702-4b1b-440c-826f-1c9bd71f0285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299197688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3299197688
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3454668541
Short name T595
Test name
Test status
Simulation time 17993585 ps
CPU time 0.58 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:27:41 PM PST 23
Peak memory 193940 kb
Host smart-97e50f9f-b857-4019-bbf9-73b23e52019b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454668541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3454668541
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3068759221
Short name T41
Test name
Test status
Simulation time 1646436000 ps
CPU time 18.07 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:28:27 PM PST 23
Peak memory 206740 kb
Host smart-243cef01-d02c-4654-985e-5d97e9f71190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068759221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3068759221
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4120865646
Short name T265
Test name
Test status
Simulation time 7899054373 ps
CPU time 25.39 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:28:05 PM PST 23
Peak memory 198720 kb
Host smart-0faee0bc-7901-4985-9143-f5b56b8a884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120865646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4120865646
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.290522759
Short name T529
Test name
Test status
Simulation time 4403947371 ps
CPU time 29.39 seconds
Started Dec 31 12:27:43 PM PST 23
Finished Dec 31 12:28:13 PM PST 23
Peak memory 198624 kb
Host smart-a20ee314-29e2-4223-adfa-fdcca6b85499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290522759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.290522759
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3695223395
Short name T739
Test name
Test status
Simulation time 7899647716 ps
CPU time 121.49 seconds
Started Dec 31 12:30:22 PM PST 23
Finished Dec 31 12:32:27 PM PST 23
Peak memory 198748 kb
Host smart-cf220b2d-87e4-418c-afb6-b97f2cca50e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695223395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3695223395
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2471359764
Short name T617
Test name
Test status
Simulation time 689117509 ps
CPU time 33.69 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:27:28 PM PST 23
Peak memory 198508 kb
Host smart-65490872-74f5-4acc-97ea-51e287e41298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471359764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2471359764
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1070686769
Short name T208
Test name
Test status
Simulation time 94014599 ps
CPU time 1.53 seconds
Started Dec 31 12:28:33 PM PST 23
Finished Dec 31 12:28:42 PM PST 23
Peak memory 198452 kb
Host smart-2cc5a79a-57c9-491d-9ec0-852110b47b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070686769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1070686769
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3174864001
Short name T318
Test name
Test status
Simulation time 17552851685 ps
CPU time 297.8 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:31:41 PM PST 23
Peak memory 239680 kb
Host smart-4b09da62-3bcf-4042-b2ff-5f9fdd57fa43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174864001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3174864001
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2260587983
Short name T742
Test name
Test status
Simulation time 281180939774 ps
CPU time 2083.34 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 01:02:00 PM PST 23
Peak memory 231404 kb
Host smart-9f3fcf62-abef-4c27-8251-de76a880c255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260587983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2260587983
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.640295017
Short name T720
Test name
Test status
Simulation time 101852428 ps
CPU time 0.88 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 195608 kb
Host smart-7f1f1879-fb13-4c30-8c1e-d736798a95d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640295017 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.640295017
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3142151989
Short name T42
Test name
Test status
Simulation time 94253298840 ps
CPU time 370.73 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:33:53 PM PST 23
Peak memory 198680 kb
Host smart-7b5fb77f-b05c-47f7-86dd-3b97ae8a4072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142151989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.3142151989
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.877923156
Short name T374
Test name
Test status
Simulation time 1126328923 ps
CPU time 13.48 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:28:04 PM PST 23
Peak memory 198492 kb
Host smart-317a5124-31e7-47fc-b685-df5734f74751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877923156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.877923156
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1370771045
Short name T45
Test name
Test status
Simulation time 15795169 ps
CPU time 0.53 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:02 PM PST 23
Peak memory 192928 kb
Host smart-ede47e1e-96ef-4146-92fc-ac8231f437bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370771045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1370771045
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.293094960
Short name T390
Test name
Test status
Simulation time 668271781 ps
CPU time 5.57 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:26:55 PM PST 23
Peak memory 198468 kb
Host smart-c30f3c3f-d1b9-4cdc-8a1c-2f8f03bc9cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293094960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.293094960
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1230978183
Short name T764
Test name
Test status
Simulation time 18932041322 ps
CPU time 49.57 seconds
Started Dec 31 12:27:36 PM PST 23
Finished Dec 31 12:28:27 PM PST 23
Peak memory 198612 kb
Host smart-d25f72b2-79a7-44f6-852f-9f4a672c9e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230978183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1230978183
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1210165852
Short name T283
Test name
Test status
Simulation time 2740076237 ps
CPU time 66.68 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:29:08 PM PST 23
Peak memory 198672 kb
Host smart-118c59a2-9337-4513-b356-35560e8cfce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210165852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1210165852
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2724792510
Short name T694
Test name
Test status
Simulation time 59015763218 ps
CPU time 79.9 seconds
Started Dec 31 12:26:46 PM PST 23
Finished Dec 31 12:28:07 PM PST 23
Peak memory 198688 kb
Host smart-090418fd-796c-4431-936e-d71320544f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724792510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2724792510
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3390145285
Short name T681
Test name
Test status
Simulation time 36498739538 ps
CPU time 63.44 seconds
Started Dec 31 12:26:56 PM PST 23
Finished Dec 31 12:28:01 PM PST 23
Peak memory 198688 kb
Host smart-263696c2-9a7f-4383-a7d5-aea6cef6c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390145285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3390145285
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4215718467
Short name T235
Test name
Test status
Simulation time 230815547 ps
CPU time 3.04 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:26:29 PM PST 23
Peak memory 198364 kb
Host smart-f713f051-7099-4e22-98ac-f4fef58c9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215718467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4215718467
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2597701280
Short name T819
Test name
Test status
Simulation time 32723158553 ps
CPU time 393.6 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:34:09 PM PST 23
Peak memory 231320 kb
Host smart-cbd723f6-c9d4-48d6-b15c-22c02c63d8d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597701280 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2597701280
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.3974511848
Short name T560
Test name
Test status
Simulation time 417455923638 ps
CPU time 1826.56 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:58:38 PM PST 23
Peak memory 244060 kb
Host smart-96ae1f82-0511-4aee-912d-00866a3b0b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974511848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.3974511848
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3008636184
Short name T501
Test name
Test status
Simulation time 180905984 ps
CPU time 0.91 seconds
Started Dec 31 12:27:19 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 196192 kb
Host smart-01d2aca6-3572-4dbc-8c66-6b2ebc6effd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008636184 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3008636184
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3771431174
Short name T458
Test name
Test status
Simulation time 27177986149 ps
CPU time 412.23 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:33:10 PM PST 23
Peak memory 198664 kb
Host smart-96e21971-dcc3-42be-bd3a-0a9a6ae8c363
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771431174 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3771431174
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4066700891
Short name T289
Test name
Test status
Simulation time 3892634057 ps
CPU time 23.35 seconds
Started Dec 31 12:26:21 PM PST 23
Finished Dec 31 12:26:46 PM PST 23
Peak memory 198700 kb
Host smart-8110dd6d-d2b1-4b23-907e-a8430ee33a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066700891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4066700891
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4221822538
Short name T351
Test name
Test status
Simulation time 159770232 ps
CPU time 0.55 seconds
Started Dec 31 12:28:28 PM PST 23
Finished Dec 31 12:28:36 PM PST 23
Peak memory 192984 kb
Host smart-6264b5f8-f1bb-4d65-bb4e-98ffa3e40152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221822538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4221822538
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3577578854
Short name T8
Test name
Test status
Simulation time 995455940 ps
CPU time 31.03 seconds
Started Dec 31 12:27:32 PM PST 23
Finished Dec 31 12:28:04 PM PST 23
Peak memory 222084 kb
Host smart-eebb8a4b-1c6c-41a0-ba24-6fdd8a6426cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577578854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3577578854
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.207187654
Short name T729
Test name
Test status
Simulation time 901358895 ps
CPU time 37.62 seconds
Started Dec 31 12:27:27 PM PST 23
Finished Dec 31 12:28:06 PM PST 23
Peak memory 198508 kb
Host smart-09ed9f03-9ee7-4cba-b4ea-8ec86695d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207187654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.207187654
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2617083339
Short name T426
Test name
Test status
Simulation time 2193187541 ps
CPU time 100.33 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:28:39 PM PST 23
Peak memory 198604 kb
Host smart-29a9fb3a-f7ad-497a-a65f-5d80234ed647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617083339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2617083339
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1865455689
Short name T307
Test name
Test status
Simulation time 11521602758 ps
CPU time 126.44 seconds
Started Dec 31 12:27:27 PM PST 23
Finished Dec 31 12:29:34 PM PST 23
Peak memory 198652 kb
Host smart-4afa4e90-b21f-4fed-bd48-c97986a20830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865455689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1865455689
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3857138720
Short name T678
Test name
Test status
Simulation time 1427859473 ps
CPU time 71.98 seconds
Started Dec 31 12:28:39 PM PST 23
Finished Dec 31 12:30:00 PM PST 23
Peak memory 198572 kb
Host smart-8a51faea-6055-4eba-b7ea-56ce9612d62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857138720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3857138720
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2824026699
Short name T356
Test name
Test status
Simulation time 700709149 ps
CPU time 3.61 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 198332 kb
Host smart-ff29a00c-32b7-49e0-8150-142380cbdfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824026699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2824026699
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3542906453
Short name T263
Test name
Test status
Simulation time 475948768576 ps
CPU time 571.11 seconds
Started Dec 31 12:25:55 PM PST 23
Finished Dec 31 12:35:33 PM PST 23
Peak memory 223208 kb
Host smart-9a4d9c4b-69b5-4117-8106-9bed83bad415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542906453 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3542906453
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3306626850
Short name T129
Test name
Test status
Simulation time 109534243258 ps
CPU time 1891.92 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:58:26 PM PST 23
Peak memory 241880 kb
Host smart-27d96b06-1be2-43f3-90dd-26ede7b0d00e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306626850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3306626850
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1736118985
Short name T716
Test name
Test status
Simulation time 114994007 ps
CPU time 1.06 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 197592 kb
Host smart-b8405ab9-0f33-4586-92ce-8612ba228b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736118985 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1736118985
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3478000575
Short name T371
Test name
Test status
Simulation time 26645245495 ps
CPU time 416.01 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:33:19 PM PST 23
Peak memory 198656 kb
Host smart-608d4c16-277b-4014-80ad-d0990e5413c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478000575 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.3478000575
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3821623569
Short name T60
Test name
Test status
Simulation time 3136634619 ps
CPU time 58.28 seconds
Started Dec 31 12:28:49 PM PST 23
Finished Dec 31 12:29:52 PM PST 23
Peak memory 198688 kb
Host smart-3b64fa65-b763-4c68-990c-e3b55dec9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821623569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3821623569
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1521417325
Short name T383
Test name
Test status
Simulation time 17285771 ps
CPU time 0.54 seconds
Started Dec 31 12:27:00 PM PST 23
Finished Dec 31 12:27:02 PM PST 23
Peak memory 192864 kb
Host smart-74cda5b4-9ddf-4908-a77e-cf3178147caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521417325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1521417325
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.852088257
Short name T429
Test name
Test status
Simulation time 1758367574 ps
CPU time 7.67 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:28:07 PM PST 23
Peak memory 198556 kb
Host smart-fdee2cd0-9b08-4d6f-a9cb-6463c01d70ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852088257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.852088257
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1739056797
Short name T533
Test name
Test status
Simulation time 15158998107 ps
CPU time 43.21 seconds
Started Dec 31 12:27:20 PM PST 23
Finished Dec 31 12:28:04 PM PST 23
Peak memory 198592 kb
Host smart-a7f914e1-7db1-4c05-87b6-a51903e8eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739056797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1739056797
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3362860462
Short name T828
Test name
Test status
Simulation time 921940672 ps
CPU time 45.42 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:54 PM PST 23
Peak memory 198476 kb
Host smart-6a4654fe-82e3-47c1-abea-0ea572cba2d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362860462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3362860462
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1603815699
Short name T710
Test name
Test status
Simulation time 4676661467 ps
CPU time 53.22 seconds
Started Dec 31 12:27:31 PM PST 23
Finished Dec 31 12:28:26 PM PST 23
Peak memory 198708 kb
Host smart-28095f77-c3e7-4764-88cc-7b3e9a377ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603815699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1603815699
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3755608103
Short name T339
Test name
Test status
Simulation time 9504494980 ps
CPU time 59.12 seconds
Started Dec 31 12:27:21 PM PST 23
Finished Dec 31 12:28:24 PM PST 23
Peak memory 198692 kb
Host smart-b51b2920-a80f-4b2f-86d0-1239bfd91480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755608103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3755608103
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2165233944
Short name T285
Test name
Test status
Simulation time 346582847 ps
CPU time 1.46 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:27:50 PM PST 23
Peak memory 198248 kb
Host smart-a8e631f8-efe0-416b-8ee9-d486a4b32d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165233944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2165233944
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.515039985
Short name T606
Test name
Test status
Simulation time 124165714289 ps
CPU time 1441.6 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 198700 kb
Host smart-462acbc1-6c3d-4508-891a-e464c607b1fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515039985 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.515039985
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.2253918773
Short name T609
Test name
Test status
Simulation time 73055812719 ps
CPU time 1330.56 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:50:21 PM PST 23
Peak memory 227852 kb
Host smart-b0fb724a-3239-4c4e-8a93-94af5f8c9ded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253918773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.2253918773
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.4071174301
Short name T738
Test name
Test status
Simulation time 903375590 ps
CPU time 1.2 seconds
Started Dec 31 12:28:09 PM PST 23
Finished Dec 31 12:28:14 PM PST 23
Peak memory 196284 kb
Host smart-213eaf3f-a7db-48f1-b17e-32f8f3b4034c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071174301 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.4071174301
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.212639816
Short name T58
Test name
Test status
Simulation time 46932743677 ps
CPU time 354.17 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:33:41 PM PST 23
Peak memory 198588 kb
Host smart-b6d9b79d-2b34-440e-9dca-4103ab64eccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212639816 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.hmac_test_sha_vectors.212639816
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3100216322
Short name T503
Test name
Test status
Simulation time 14676237833 ps
CPU time 20.9 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 198620 kb
Host smart-b131b0bf-ff19-4e52-9d53-b060f13e2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100216322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3100216322
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1426537132
Short name T442
Test name
Test status
Simulation time 14483494 ps
CPU time 0.55 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 192888 kb
Host smart-d55f2854-3018-4042-8cc5-0b0eb392058f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426537132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1426537132
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1267795903
Short name T847
Test name
Test status
Simulation time 7152243299 ps
CPU time 19.77 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 215056 kb
Host smart-60a757e9-a82a-4c7f-89bd-ba6ead0350ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267795903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1267795903
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1475130634
Short name T256
Test name
Test status
Simulation time 2518592368 ps
CPU time 55.63 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 198628 kb
Host smart-8a6863ae-7ce8-4902-bfd1-b0f82c581c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475130634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1475130634
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3729156562
Short name T377
Test name
Test status
Simulation time 1954046686 ps
CPU time 93.24 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:29:09 PM PST 23
Peak memory 198524 kb
Host smart-50d919db-f96d-48cf-b390-2c56d40f0475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729156562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3729156562
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3723256846
Short name T298
Test name
Test status
Simulation time 10958340624 ps
CPU time 72.21 seconds
Started Dec 31 12:28:31 PM PST 23
Finished Dec 31 12:29:52 PM PST 23
Peak memory 198644 kb
Host smart-adb09d37-894b-488b-a727-9cedc25ce320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723256846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3723256846
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.24789104
Short name T32
Test name
Test status
Simulation time 647553173 ps
CPU time 32.41 seconds
Started Dec 31 12:26:16 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 198564 kb
Host smart-583e5c80-75cc-4d9f-93ac-c38f7c9ea5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24789104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.24789104
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1939556523
Short name T513
Test name
Test status
Simulation time 78576210 ps
CPU time 2.08 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 198312 kb
Host smart-95bab055-4d17-4b37-9d1a-f0335f0fcc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939556523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1939556523
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2596932751
Short name T689
Test name
Test status
Simulation time 20376233589 ps
CPU time 919.26 seconds
Started Dec 31 12:27:42 PM PST 23
Finished Dec 31 12:43:03 PM PST 23
Peak memory 214752 kb
Host smart-fb4386c7-cd01-4b61-8682-9fb525d876bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596932751 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2596932751
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1532139603
Short name T286
Test name
Test status
Simulation time 91466341688 ps
CPU time 2071.2 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 01:03:14 PM PST 23
Peak memory 239688 kb
Host smart-79bdb884-e35e-4032-bec0-ba605300b764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532139603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.1532139603
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.362485576
Short name T221
Test name
Test status
Simulation time 30386663 ps
CPU time 1.09 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:13 PM PST 23
Peak memory 196584 kb
Host smart-907f4bbd-a9da-485c-aa47-43db88988408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362485576 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.362485576
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.741128770
Short name T800
Test name
Test status
Simulation time 118851200245 ps
CPU time 407.63 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:33:29 PM PST 23
Peak memory 198620 kb
Host smart-930eb566-3b01-4bcd-8841-308cd273287d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741128770 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.741128770
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4021563032
Short name T373
Test name
Test status
Simulation time 32771396 ps
CPU time 0.53 seconds
Started Dec 31 12:29:08 PM PST 23
Finished Dec 31 12:29:13 PM PST 23
Peak memory 192904 kb
Host smart-f2e90a44-2675-4985-beb4-4344af998d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021563032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4021563032
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2249722659
Short name T469
Test name
Test status
Simulation time 1708829003 ps
CPU time 10.53 seconds
Started Dec 31 12:28:11 PM PST 23
Finished Dec 31 12:28:24 PM PST 23
Peak memory 198532 kb
Host smart-b7476ce0-656e-4d7d-9d8c-39c79d161938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249722659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2249722659
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4180673876
Short name T497
Test name
Test status
Simulation time 9620465703 ps
CPU time 12.99 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 198588 kb
Host smart-fd01db8c-1730-4995-964d-45d92c14f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180673876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4180673876
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2136055868
Short name T741
Test name
Test status
Simulation time 7474960786 ps
CPU time 88.37 seconds
Started Dec 31 12:28:01 PM PST 23
Finished Dec 31 12:29:35 PM PST 23
Peak memory 198576 kb
Host smart-a6d7edba-36e9-4083-8299-f2427ecdd140
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136055868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2136055868
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.530527730
Short name T476
Test name
Test status
Simulation time 50216859684 ps
CPU time 119.06 seconds
Started Dec 31 12:29:15 PM PST 23
Finished Dec 31 12:31:18 PM PST 23
Peak memory 198624 kb
Host smart-3e476402-a8d7-4784-94ab-b77e0a1a6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530527730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.530527730
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1999784136
Short name T661
Test name
Test status
Simulation time 10678253291 ps
CPU time 89.73 seconds
Started Dec 31 12:28:37 PM PST 23
Finished Dec 31 12:30:16 PM PST 23
Peak memory 198724 kb
Host smart-6cdb2eba-95db-4b12-8214-1fa3aeba8dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999784136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1999784136
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4281089636
Short name T582
Test name
Test status
Simulation time 139421891 ps
CPU time 0.62 seconds
Started Dec 31 12:27:07 PM PST 23
Finished Dec 31 12:27:09 PM PST 23
Peak memory 194168 kb
Host smart-49dd92ab-7beb-4bc8-b9a6-fd20574f2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281089636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4281089636
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2307070063
Short name T293
Test name
Test status
Simulation time 47687297379 ps
CPU time 777.6 seconds
Started Dec 31 12:28:42 PM PST 23
Finished Dec 31 12:41:47 PM PST 23
Peak memory 223344 kb
Host smart-b503ee1a-d7b8-4fa0-b90c-0c5de4063029
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307070063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2307070063
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.1426754447
Short name T109
Test name
Test status
Simulation time 21775881819 ps
CPU time 308.06 seconds
Started Dec 31 12:28:17 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 215124 kb
Host smart-fee89517-31b1-4e59-816b-fa20485c6e3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426754447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.1426754447
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2854143905
Short name T857
Test name
Test status
Simulation time 65124464 ps
CPU time 1.05 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:33 PM PST 23
Peak memory 196108 kb
Host smart-814c84a6-58b1-42b9-a9b1-ec8a03b9bcc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854143905 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2854143905
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2627216944
Short name T686
Test name
Test status
Simulation time 71229797774 ps
CPU time 411.97 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:34:08 PM PST 23
Peak memory 198684 kb
Host smart-5727af6d-f410-4603-844e-0c3366a58dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627216944 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.2627216944
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.441836703
Short name T667
Test name
Test status
Simulation time 5845032791 ps
CPU time 33.48 seconds
Started Dec 31 12:26:52 PM PST 23
Finished Dec 31 12:27:27 PM PST 23
Peak memory 198628 kb
Host smart-e073de3a-8805-488b-99b0-a2bd2de88987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441836703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.441836703
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2528912784
Short name T677
Test name
Test status
Simulation time 20738855 ps
CPU time 0.64 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 191636 kb
Host smart-07ae075a-e2a4-4793-9e67-b3fcff10c835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528912784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2528912784
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3608318131
Short name T431
Test name
Test status
Simulation time 1080337705 ps
CPU time 30.39 seconds
Started Dec 31 12:18:23 PM PST 23
Finished Dec 31 12:18:54 PM PST 23
Peak memory 214876 kb
Host smart-bae429dc-2a54-40bf-a93c-b3a43d0fd30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608318131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3608318131
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3811264735
Short name T223
Test name
Test status
Simulation time 4644134974 ps
CPU time 7.25 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:28 PM PST 23
Peak memory 198676 kb
Host smart-cf546c96-434b-480a-9484-09c1f1228b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811264735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3811264735
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2156416002
Short name T274
Test name
Test status
Simulation time 1349762765 ps
CPU time 12.49 seconds
Started Dec 31 12:30:07 PM PST 23
Finished Dec 31 12:30:24 PM PST 23
Peak memory 198516 kb
Host smart-df7bc18c-5053-4573-8aa2-c34e31ea2b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156416002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2156416002
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2567694291
Short name T207
Test name
Test status
Simulation time 68003670 ps
CPU time 1.02 seconds
Started Dec 31 12:18:24 PM PST 23
Finished Dec 31 12:18:25 PM PST 23
Peak memory 198324 kb
Host smart-9b921c45-cb98-4b18-8316-07c527f37363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567694291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2567694291
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3272980480
Short name T539
Test name
Test status
Simulation time 18867687054 ps
CPU time 83.57 seconds
Started Dec 31 12:23:22 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 198640 kb
Host smart-f8cd1197-bd55-4c77-9bf9-4f01b9ef0d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272980480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3272980480
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.948784093
Short name T52
Test name
Test status
Simulation time 96089965 ps
CPU time 0.94 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 216592 kb
Host smart-e270988f-25a9-42d5-9c1b-4519adebce04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948784093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.948784093
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3880872646
Short name T287
Test name
Test status
Simulation time 211153949 ps
CPU time 1.62 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 198016 kb
Host smart-42855e8f-ad49-4d80-b0bb-05439f509fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880872646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3880872646
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2754845390
Short name T775
Test name
Test status
Simulation time 85324693813 ps
CPU time 1396.88 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 227256 kb
Host smart-f61b6130-2013-41b3-bdbb-2b5abfeecf6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754845390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2754845390
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.395199951
Short name T736
Test name
Test status
Simulation time 161167766564 ps
CPU time 1642.5 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:50:21 PM PST 23
Peak memory 261900 kb
Host smart-4529ba6b-04a6-4415-8a66-fdd27c07841d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395199951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.395199951
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1660284699
Short name T330
Test name
Test status
Simulation time 70047452 ps
CPU time 1.1 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 196632 kb
Host smart-4b27d748-1543-4bd9-9a73-f43c1d1617a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660284699 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1660284699
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2477571363
Short name T669
Test name
Test status
Simulation time 8945296906 ps
CPU time 409.37 seconds
Started Dec 31 12:23:21 PM PST 23
Finished Dec 31 12:30:11 PM PST 23
Peak memory 198628 kb
Host smart-4b3e7f65-8c7b-4c62-a4fe-3dfbb2b35855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477571363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.2477571363
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1368073177
Short name T282
Test name
Test status
Simulation time 1122345154 ps
CPU time 9.5 seconds
Started Dec 31 12:29:43 PM PST 23
Finished Dec 31 12:29:55 PM PST 23
Peak memory 198464 kb
Host smart-683eb325-c5a3-4b58-af97-5fb391271c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368073177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1368073177
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.90187912
Short name T646
Test name
Test status
Simulation time 15292491 ps
CPU time 0.54 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:27:45 PM PST 23
Peak memory 192880 kb
Host smart-6b86c7a9-686f-4db3-bfdf-352e8edf33ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90187912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.90187912
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1384895394
Short name T702
Test name
Test status
Simulation time 502195497 ps
CPU time 14.56 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:23 PM PST 23
Peak memory 206708 kb
Host smart-99481361-e808-4e53-9227-57816f03f532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384895394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1384895394
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3557504284
Short name T613
Test name
Test status
Simulation time 5555351591 ps
CPU time 35.69 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:28:56 PM PST 23
Peak memory 198644 kb
Host smart-b2446d00-e069-46f9-988c-bed9dfd2ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557504284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3557504284
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4036283432
Short name T572
Test name
Test status
Simulation time 215965253 ps
CPU time 4.52 seconds
Started Dec 31 12:28:54 PM PST 23
Finished Dec 31 12:29:04 PM PST 23
Peak memory 197640 kb
Host smart-bc0d1f6f-8a1c-4bf1-b224-504c767661c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036283432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4036283432
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3856068106
Short name T708
Test name
Test status
Simulation time 58472012 ps
CPU time 1.05 seconds
Started Dec 31 12:28:32 PM PST 23
Finished Dec 31 12:28:41 PM PST 23
Peak memory 197880 kb
Host smart-815fc13d-373d-4f0a-88a2-249eb974b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856068106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3856068106
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3950008108
Short name T478
Test name
Test status
Simulation time 88712045658 ps
CPU time 74.82 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:28:05 PM PST 23
Peak memory 198648 kb
Host smart-35c9f7d1-20f0-414d-9c7f-844d1b5959d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950008108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3950008108
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1451256996
Short name T682
Test name
Test status
Simulation time 205123964 ps
CPU time 2.9 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:27:20 PM PST 23
Peak memory 198316 kb
Host smart-c850328f-a299-4ba6-8dad-97a8fb4c0764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451256996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1451256996
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1225457324
Short name T790
Test name
Test status
Simulation time 87125505309 ps
CPU time 1297.83 seconds
Started Dec 31 12:29:03 PM PST 23
Finished Dec 31 12:50:49 PM PST 23
Peak memory 218416 kb
Host smart-e96b8976-65f7-4f55-9503-3c540ba02043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225457324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1225457324
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.930720438
Short name T359
Test name
Test status
Simulation time 86572813797 ps
CPU time 288.37 seconds
Started Dec 31 12:28:18 PM PST 23
Finished Dec 31 12:33:08 PM PST 23
Peak memory 198696 kb
Host smart-fec4271f-73a4-42ac-870d-150909aa33d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930720438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.930720438
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1129606656
Short name T670
Test name
Test status
Simulation time 102719924 ps
CPU time 1.02 seconds
Started Dec 31 12:26:35 PM PST 23
Finished Dec 31 12:26:38 PM PST 23
Peak memory 196120 kb
Host smart-96af0330-795a-4ca1-9dd3-d20d58972990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129606656 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1129606656
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1357470783
Short name T237
Test name
Test status
Simulation time 16851058012 ps
CPU time 381.4 seconds
Started Dec 31 12:27:13 PM PST 23
Finished Dec 31 12:33:35 PM PST 23
Peak memory 198512 kb
Host smart-8fad3671-e23e-4f05-b64e-08735f06d019
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357470783 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1357470783
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2377847753
Short name T816
Test name
Test status
Simulation time 1994503684 ps
CPU time 6.92 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:27:53 PM PST 23
Peak memory 198136 kb
Host smart-8746ab6e-bb39-406a-91dd-cd867283bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377847753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2377847753
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.569762106
Short name T518
Test name
Test status
Simulation time 34189366 ps
CPU time 0.53 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:28:09 PM PST 23
Peak memory 193012 kb
Host smart-8d83b7fa-1d4c-40f9-8fab-4e907ac29698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569762106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.569762106
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3068022636
Short name T569
Test name
Test status
Simulation time 1358544498 ps
CPU time 43.17 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:29:01 PM PST 23
Peak memory 224688 kb
Host smart-5495d5db-9bba-472b-929b-320faf214809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068022636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3068022636
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.925527981
Short name T635
Test name
Test status
Simulation time 1784828412 ps
CPU time 30.72 seconds
Started Dec 31 12:28:34 PM PST 23
Finished Dec 31 12:29:12 PM PST 23
Peak memory 198524 kb
Host smart-12adfbe6-0a31-4f14-b111-c8b0c71d7dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925527981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.925527981
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3987998040
Short name T809
Test name
Test status
Simulation time 2149514537 ps
CPU time 100.68 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:29:01 PM PST 23
Peak memory 198512 kb
Host smart-3925c921-f10e-4159-86a6-5446e1c1503c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987998040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3987998040
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.491432449
Short name T785
Test name
Test status
Simulation time 1006913588 ps
CPU time 23.5 seconds
Started Dec 31 12:28:12 PM PST 23
Finished Dec 31 12:28:37 PM PST 23
Peak memory 198484 kb
Host smart-72d0b651-468d-47a7-a2df-cd3392c91f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491432449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.491432449
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2906771600
Short name T593
Test name
Test status
Simulation time 1764439746 ps
CPU time 20.89 seconds
Started Dec 31 12:27:59 PM PST 23
Finished Dec 31 12:28:27 PM PST 23
Peak memory 198508 kb
Host smart-23a42855-ce3b-414d-91f9-130d3dd609c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906771600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2906771600
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3508553705
Short name T437
Test name
Test status
Simulation time 235169627 ps
CPU time 2.55 seconds
Started Dec 31 12:29:10 PM PST 23
Finished Dec 31 12:29:19 PM PST 23
Peak memory 198512 kb
Host smart-960781d2-7cb6-4dfd-a705-66688167a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508553705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3508553705
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.336773913
Short name T579
Test name
Test status
Simulation time 46618972854 ps
CPU time 735.26 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:39:15 PM PST 23
Peak memory 198608 kb
Host smart-7da1a8e5-62ea-4791-8994-695d762fb289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336773913 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.336773913
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2793848222
Short name T650
Test name
Test status
Simulation time 58815159214 ps
CPU time 1000.03 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 233472 kb
Host smart-62d116db-0611-463b-b1ae-66d0a327825c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793848222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.2793848222
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2095798590
Short name T634
Test name
Test status
Simulation time 126884691 ps
CPU time 1.06 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:26:56 PM PST 23
Peak memory 197480 kb
Host smart-2b9eb26c-bbbf-43c9-8bd7-96922c1682b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095798590 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2095798590
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2240597845
Short name T493
Test name
Test status
Simulation time 59003012477 ps
CPU time 452.71 seconds
Started Dec 31 12:28:47 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 198576 kb
Host smart-1dd10bb8-dacd-4dad-b620-f5d0ee9d4f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240597845 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.2240597845
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3735164449
Short name T735
Test name
Test status
Simulation time 8464808958 ps
CPU time 19.57 seconds
Started Dec 31 12:27:57 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 198732 kb
Host smart-c7812da9-96a0-4aab-9677-086fe2f3ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735164449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3735164449
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1917138218
Short name T532
Test name
Test status
Simulation time 43044094 ps
CPU time 0.54 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:30 PM PST 23
Peak memory 192880 kb
Host smart-cecb681b-98a1-4600-9a7a-bb9568ebe237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917138218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1917138218
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.632571778
Short name T335
Test name
Test status
Simulation time 1628922447 ps
CPU time 8.17 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:27:24 PM PST 23
Peak memory 214620 kb
Host smart-8fc91338-90cc-4457-8c4e-0c34de17c35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632571778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.632571778
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1975578259
Short name T628
Test name
Test status
Simulation time 2434697444 ps
CPU time 8.47 seconds
Started Dec 31 12:28:42 PM PST 23
Finished Dec 31 12:28:57 PM PST 23
Peak memory 198764 kb
Host smart-1e4315d5-823a-413c-99af-47f862e557ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975578259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1975578259
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2641668406
Short name T264
Test name
Test status
Simulation time 1066485964 ps
CPU time 55.77 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:28:06 PM PST 23
Peak memory 198528 kb
Host smart-02bdd316-2d26-404b-b6a5-ffd64ba91e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641668406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2641668406
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2441372111
Short name T715
Test name
Test status
Simulation time 8307927889 ps
CPU time 22.66 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:34 PM PST 23
Peak memory 198696 kb
Host smart-637219e2-4ee0-4e03-a3af-90229e61fd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441372111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2441372111
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1205223678
Short name T110
Test name
Test status
Simulation time 14137160129 ps
CPU time 42.41 seconds
Started Dec 31 12:28:28 PM PST 23
Finished Dec 31 12:29:19 PM PST 23
Peak memory 198684 kb
Host smart-a5fd3a1e-2059-4d59-8492-1704fdbb8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205223678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1205223678
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1515308318
Short name T639
Test name
Test status
Simulation time 67889647 ps
CPU time 1.13 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 197692 kb
Host smart-fe5eff73-2e8d-461e-894c-5211135701bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515308318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1515308318
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1878752414
Short name T258
Test name
Test status
Simulation time 168166615567 ps
CPU time 1960.57 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 01:00:49 PM PST 23
Peak memory 231776 kb
Host smart-f1d7e2e0-6da3-4f0c-b665-d25317a23436
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878752414 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1878752414
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.2163515337
Short name T583
Test name
Test status
Simulation time 419716106772 ps
CPU time 1396.38 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:51:18 PM PST 23
Peak memory 249828 kb
Host smart-28c9cbfc-c8e2-4df7-a770-dcd971014bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163515337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.2163515337
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4006056005
Short name T836
Test name
Test status
Simulation time 100604416 ps
CPU time 0.88 seconds
Started Dec 31 12:29:13 PM PST 23
Finished Dec 31 12:29:19 PM PST 23
Peak memory 196832 kb
Host smart-d7bbbfc8-d6bf-40a1-bdb6-c873c5186883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006056005 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.4006056005
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1293769380
Short name T322
Test name
Test status
Simulation time 75506917627 ps
CPU time 402.38 seconds
Started Dec 31 12:28:23 PM PST 23
Finished Dec 31 12:35:07 PM PST 23
Peak memory 198672 kb
Host smart-66cef104-90ac-416c-964a-16e586029d55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293769380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.1293769380
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1493652282
Short name T817
Test name
Test status
Simulation time 4683541720 ps
CPU time 43.17 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:27:25 PM PST 23
Peak memory 198624 kb
Host smart-f2b570be-84b7-49d7-b234-bdc6dd4e91be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493652282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1493652282
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.755435054
Short name T508
Test name
Test status
Simulation time 47147799 ps
CPU time 0.6 seconds
Started Dec 31 12:28:03 PM PST 23
Finished Dec 31 12:28:09 PM PST 23
Peak memory 194044 kb
Host smart-67f178ef-a67c-4ae7-ab6a-fd2f2047347e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755435054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.755435054
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.382452214
Short name T697
Test name
Test status
Simulation time 133960053 ps
CPU time 3.81 seconds
Started Dec 31 12:27:13 PM PST 23
Finished Dec 31 12:27:18 PM PST 23
Peak memory 198488 kb
Host smart-c3f20f15-8ead-4912-b53c-e43aa891317d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382452214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.382452214
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1141476322
Short name T784
Test name
Test status
Simulation time 1218644716 ps
CPU time 26 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 198560 kb
Host smart-e4715910-c0da-4f68-943c-8639fac1ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141476322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1141476322
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.615498247
Short name T219
Test name
Test status
Simulation time 4521106996 ps
CPU time 51.19 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:27:42 PM PST 23
Peak memory 198652 kb
Host smart-cf36184b-d2a5-4d8b-80d2-ed51a8c44374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615498247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.615498247
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2925901650
Short name T498
Test name
Test status
Simulation time 8371351289 ps
CPU time 92.99 seconds
Started Dec 31 12:28:43 PM PST 23
Finished Dec 31 12:30:23 PM PST 23
Peak memory 198696 kb
Host smart-4da6b14c-fd7d-4998-9136-00f3432d25b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925901650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2925901650
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3259173517
Short name T449
Test name
Test status
Simulation time 16807225894 ps
CPU time 74.52 seconds
Started Dec 31 12:26:23 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198636 kb
Host smart-0423df39-7abc-4a8c-a257-3d978afe3617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259173517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3259173517
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2773407639
Short name T767
Test name
Test status
Simulation time 364696206 ps
CPU time 3.61 seconds
Started Dec 31 12:28:26 PM PST 23
Finished Dec 31 12:28:32 PM PST 23
Peak memory 198556 kb
Host smart-ea04d4e3-4496-46e1-ae00-23fa54999999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773407639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2773407639
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2268713592
Short name T755
Test name
Test status
Simulation time 162473246023 ps
CPU time 945.33 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:43:34 PM PST 23
Peak memory 239704 kb
Host smart-c22a3985-e489-4041-ab22-af865dc31c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268713592 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2268713592
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.3622893982
Short name T407
Test name
Test status
Simulation time 134741258892 ps
CPU time 1020.63 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:43:45 PM PST 23
Peak memory 251968 kb
Host smart-5274bef2-c6b6-45d1-9f31-3cea7965d618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622893982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.3622893982
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2468482771
Short name T212
Test name
Test status
Simulation time 397792094 ps
CPU time 0.86 seconds
Started Dec 31 12:28:06 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 195868 kb
Host smart-ab7d002d-81ee-4a1e-bd32-89bc2f24b3d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468482771 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2468482771
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.600184862
Short name T229
Test name
Test status
Simulation time 30848638005 ps
CPU time 361.09 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:33:46 PM PST 23
Peak memory 198652 kb
Host smart-f1f6b9eb-4064-44cc-ae13-caf59e36127d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600184862 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.hmac_test_sha_vectors.600184862
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.778884345
Short name T855
Test name
Test status
Simulation time 8345135471 ps
CPU time 63.48 seconds
Started Dec 31 12:27:56 PM PST 23
Finished Dec 31 12:29:05 PM PST 23
Peak memory 198704 kb
Host smart-0e155951-daab-4f3a-a517-1449c6426718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778884345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.778884345
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.610124321
Short name T758
Test name
Test status
Simulation time 33618122 ps
CPU time 0.54 seconds
Started Dec 31 12:27:50 PM PST 23
Finished Dec 31 12:27:52 PM PST 23
Peak memory 192908 kb
Host smart-b87a44c9-d5b4-40f8-97dc-5ad62a1b77b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610124321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.610124321
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3556048024
Short name T115
Test name
Test status
Simulation time 3092160676 ps
CPU time 22.86 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 206844 kb
Host smart-84e283c6-d0fa-4630-99ff-f78d99066971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556048024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3556048024
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.743304634
Short name T778
Test name
Test status
Simulation time 2723394456 ps
CPU time 8.42 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 198664 kb
Host smart-54ca51c3-97d6-4935-b607-ffc3bb27bf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743304634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.743304634
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2820059848
Short name T546
Test name
Test status
Simulation time 2780453157 ps
CPU time 141.35 seconds
Started Dec 31 12:26:25 PM PST 23
Finished Dec 31 12:28:47 PM PST 23
Peak memory 198684 kb
Host smart-e9fc47c1-55a3-40e3-ac08-a19736917d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820059848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2820059848
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2995098593
Short name T811
Test name
Test status
Simulation time 2513305997 ps
CPU time 109.32 seconds
Started Dec 31 12:27:12 PM PST 23
Finished Dec 31 12:29:03 PM PST 23
Peak memory 198680 kb
Host smart-76280f9c-b8b6-4829-a861-f06c6da26b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995098593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2995098593
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2780242432
Short name T272
Test name
Test status
Simulation time 9110552819 ps
CPU time 54.88 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:28:31 PM PST 23
Peak memory 198692 kb
Host smart-b35b5a3e-a30c-4a67-bff0-20b1572db2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780242432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2780242432
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4232102611
Short name T651
Test name
Test status
Simulation time 105170707 ps
CPU time 1.06 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:27:46 PM PST 23
Peak memory 197284 kb
Host smart-13d5e4a6-fb49-489f-9c70-f1efa7e5e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232102611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4232102611
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.983839234
Short name T245
Test name
Test status
Simulation time 34479498607 ps
CPU time 143.61 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:29:34 PM PST 23
Peak memory 198712 kb
Host smart-39f7520d-feb4-497c-8a69-536627399b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983839234 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.983839234
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.493820788
Short name T719
Test name
Test status
Simulation time 31776401693 ps
CPU time 1059.97 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 241820 kb
Host smart-cdb68639-a9fa-4617-9228-1baef0ffbfff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493820788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.493820788
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.76594110
Short name T57
Test name
Test status
Simulation time 51189241 ps
CPU time 1.05 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 196056 kb
Host smart-2497e0f7-96f4-4108-b0ee-bb7ade6931b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76594110 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_hmac_vectors.76594110
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.317205882
Short name T408
Test name
Test status
Simulation time 40937491163 ps
CPU time 482.09 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:34:36 PM PST 23
Peak memory 198680 kb
Host smart-44f48ef8-3a41-458b-8439-8583d0cd20d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317205882 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.317205882
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1435279211
Short name T252
Test name
Test status
Simulation time 11943475766 ps
CPU time 51.37 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:27:41 PM PST 23
Peak memory 198700 kb
Host smart-67f926be-fbfd-4830-a978-394b89913cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435279211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1435279211
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1362860089
Short name T421
Test name
Test status
Simulation time 32137248 ps
CPU time 0.52 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 192956 kb
Host smart-6c493eb5-c01f-4c87-90c6-abfa83573c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362860089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1362860089
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.751106604
Short name T788
Test name
Test status
Simulation time 1524755984 ps
CPU time 45.12 seconds
Started Dec 31 12:26:57 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 218996 kb
Host smart-cf4fdd24-154c-46ea-9884-1c74f22a4234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751106604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.751106604
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3038670023
Short name T698
Test name
Test status
Simulation time 905677410 ps
CPU time 17.17 seconds
Started Dec 31 12:26:30 PM PST 23
Finished Dec 31 12:26:49 PM PST 23
Peak memory 198652 kb
Host smart-3f3c52f0-ff02-481d-a070-befbe6ee768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038670023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3038670023
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.933411491
Short name T251
Test name
Test status
Simulation time 1193605037 ps
CPU time 52.85 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:54 PM PST 23
Peak memory 198532 kb
Host smart-36acb6e3-612f-4dc4-af89-6d55e56450c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933411491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.933411491
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3007393890
Short name T536
Test name
Test status
Simulation time 18562041283 ps
CPU time 56.28 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 198620 kb
Host smart-0468a4f8-c15c-4290-ae90-a6a2569e1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007393890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3007393890
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3685906779
Short name T596
Test name
Test status
Simulation time 9391230493 ps
CPU time 39.26 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:27:39 PM PST 23
Peak memory 198584 kb
Host smart-28a9859a-cedf-439d-92ca-0ae13672d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685906779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3685906779
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3904753583
Short name T59
Test name
Test status
Simulation time 172553867 ps
CPU time 0.76 seconds
Started Dec 31 12:26:51 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 194380 kb
Host smart-62e74274-36d6-4080-9100-43c2b3cac60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904753583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3904753583
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3948642780
Short name T679
Test name
Test status
Simulation time 135530289338 ps
CPU time 324.79 seconds
Started Dec 31 12:27:01 PM PST 23
Finished Dec 31 12:32:29 PM PST 23
Peak memory 223244 kb
Host smart-909966e0-0c6d-43cb-afd1-de98583fb9a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948642780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3948642780
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1670053650
Short name T690
Test name
Test status
Simulation time 92313379384 ps
CPU time 1443.37 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:51:23 PM PST 23
Peak memory 257372 kb
Host smart-1034354f-cf66-431c-ac18-70ffb3fcd16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670053650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.1670053650
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2881430873
Short name T266
Test name
Test status
Simulation time 93237587 ps
CPU time 1.05 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 196976 kb
Host smart-9bc8d79c-e13d-420d-b500-f7ba993d07d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881430873 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2881430873
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3885889541
Short name T430
Test name
Test status
Simulation time 30366106654 ps
CPU time 384.93 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:33:07 PM PST 23
Peak memory 198772 kb
Host smart-7f85c659-9a51-4d23-a3ef-4d67ae1435bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885889541 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3885889541
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3148163353
Short name T555
Test name
Test status
Simulation time 4548978243 ps
CPU time 19 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:27:59 PM PST 23
Peak memory 198540 kb
Host smart-72149322-d706-4b3f-9a31-45a4e068281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148163353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3148163353
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2215644128
Short name T39
Test name
Test status
Simulation time 13437232 ps
CPU time 0.56 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 192984 kb
Host smart-fb537554-3fa9-4c4e-b515-53c2e06440b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215644128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2215644128
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1260115596
Short name T440
Test name
Test status
Simulation time 2415548859 ps
CPU time 36.59 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:42 PM PST 23
Peak memory 215032 kb
Host smart-9b97d181-f4ac-4297-9f06-8a4fae7133b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260115596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1260115596
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1160430999
Short name T796
Test name
Test status
Simulation time 824188039 ps
CPU time 34.2 seconds
Started Dec 31 12:27:40 PM PST 23
Finished Dec 31 12:28:20 PM PST 23
Peak memory 198460 kb
Host smart-1a710129-382c-4155-98bf-880014057823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160430999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1160430999
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.97388978
Short name T7
Test name
Test status
Simulation time 2877561214 ps
CPU time 33.49 seconds
Started Dec 31 12:27:26 PM PST 23
Finished Dec 31 12:28:00 PM PST 23
Peak memory 198588 kb
Host smart-75afa6d6-320f-4b2e-8e6f-3d50375345f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97388978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.97388978
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3769964778
Short name T450
Test name
Test status
Simulation time 10408990904 ps
CPU time 123.93 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:29:40 PM PST 23
Peak memory 198568 kb
Host smart-e9e43b3a-c7a9-4487-b725-fcaab7e9ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769964778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3769964778
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.717390157
Short name T415
Test name
Test status
Simulation time 3208272742 ps
CPU time 32.22 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:28:24 PM PST 23
Peak memory 198760 kb
Host smart-32050bca-4583-488c-b6a7-65ab8cafccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717390157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.717390157
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2202544201
Short name T310
Test name
Test status
Simulation time 114224409 ps
CPU time 1.76 seconds
Started Dec 31 12:27:24 PM PST 23
Finished Dec 31 12:27:27 PM PST 23
Peak memory 198392 kb
Host smart-6504935c-db47-4cf4-809a-f26d6ca78084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202544201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2202544201
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3033792924
Short name T754
Test name
Test status
Simulation time 68652844448 ps
CPU time 1083.81 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:45:50 PM PST 23
Peak memory 198684 kb
Host smart-e53dfb94-713a-4ec1-add7-bcaf30ad5c2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033792924 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3033792924
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.4018718096
Short name T468
Test name
Test status
Simulation time 97828551722 ps
CPU time 1540.17 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:52:52 PM PST 23
Peak memory 264152 kb
Host smart-9f7e1573-84b4-4273-bd7b-6c8f1db1735a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018718096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.4018718096
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.588804270
Short name T509
Test name
Test status
Simulation time 31712432 ps
CPU time 1.06 seconds
Started Dec 31 12:26:28 PM PST 23
Finished Dec 31 12:26:31 PM PST 23
Peak memory 197556 kb
Host smart-17ad1f87-aaa9-4ec2-9db2-ab95862b178a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588804270 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.588804270
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2373419079
Short name T675
Test name
Test status
Simulation time 24195856561 ps
CPU time 355.07 seconds
Started Dec 31 12:27:51 PM PST 23
Finished Dec 31 12:34:01 PM PST 23
Peak memory 198604 kb
Host smart-0262cc6c-3aa0-4d68-b6ce-a86c7f695dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373419079 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.2373419079
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2753455991
Short name T228
Test name
Test status
Simulation time 2340452729 ps
CPU time 30.08 seconds
Started Dec 31 12:27:50 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 198664 kb
Host smart-30e228e2-0289-4d67-9e7f-02c2503052a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753455991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2753455991
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.928132200
Short name T746
Test name
Test status
Simulation time 12026914 ps
CPU time 0.54 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:27:13 PM PST 23
Peak memory 192884 kb
Host smart-bdb2acfb-4654-4b3d-b6c9-dd7723ae7c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928132200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.928132200
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.376333770
Short name T850
Test name
Test status
Simulation time 3082297527 ps
CPU time 24.61 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:28:42 PM PST 23
Peak memory 198644 kb
Host smart-3835c15d-8aeb-47fc-8c56-fa0ebdc210cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376333770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.376333770
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1387959388
Short name T346
Test name
Test status
Simulation time 2611435724 ps
CPU time 58.83 seconds
Started Dec 31 12:27:34 PM PST 23
Finished Dec 31 12:28:35 PM PST 23
Peak memory 198736 kb
Host smart-662de9f7-9f49-452f-8c5b-405b1efadeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387959388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1387959388
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3690195382
Short name T768
Test name
Test status
Simulation time 1922124119 ps
CPU time 67.26 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:28:19 PM PST 23
Peak memory 198180 kb
Host smart-a4acba7c-b990-42d8-9892-f3551a7af583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690195382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3690195382
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4096459412
Short name T683
Test name
Test status
Simulation time 80537401202 ps
CPU time 93.58 seconds
Started Dec 31 12:27:07 PM PST 23
Finished Dec 31 12:28:43 PM PST 23
Peak memory 198688 kb
Host smart-3a38c3d4-6aa8-4d07-9598-38f60c8226ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096459412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4096459412
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2485910091
Short name T773
Test name
Test status
Simulation time 14418670834 ps
CPU time 51.08 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 198628 kb
Host smart-f9ec40be-001a-4144-b353-8cbfce8f4e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485910091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2485910091
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.668004232
Short name T571
Test name
Test status
Simulation time 168673109 ps
CPU time 1.18 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 198148 kb
Host smart-6eb83fbc-945b-42ad-89fd-052db120705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668004232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.668004232
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3258517130
Short name T611
Test name
Test status
Simulation time 45964800277 ps
CPU time 508.24 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 198580 kb
Host smart-76886d13-4692-4c61-a1c9-862a095b488c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258517130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3258517130
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.1277687305
Short name T709
Test name
Test status
Simulation time 57259230244 ps
CPU time 995.2 seconds
Started Dec 31 12:28:03 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 215072 kb
Host smart-58d520b2-2afc-4c9d-ae04-4c116e701c95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277687305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.1277687305
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2236841346
Short name T333
Test name
Test status
Simulation time 168602263 ps
CPU time 0.87 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:27:37 PM PST 23
Peak memory 195824 kb
Host smart-44324d45-a38d-4d8f-8e53-31898cda6904
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236841346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2236841346
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2495897465
Short name T399
Test name
Test status
Simulation time 181392534297 ps
CPU time 451.33 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 12:35:47 PM PST 23
Peak memory 198708 kb
Host smart-5bf60280-28eb-4978-8261-33e61bafaa55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495897465 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.2495897465
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3704197641
Short name T592
Test name
Test status
Simulation time 1879146046 ps
CPU time 19.18 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:28:21 PM PST 23
Peak memory 198504 kb
Host smart-8f723ec2-b278-46e9-a5af-79eb82a7a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704197641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3704197641
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.293763571
Short name T253
Test name
Test status
Simulation time 40371456 ps
CPU time 0.54 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 192932 kb
Host smart-ec96b412-86b0-4e22-a817-bd50060e801e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293763571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.293763571
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1552707808
Short name T530
Test name
Test status
Simulation time 4707392664 ps
CPU time 34.58 seconds
Started Dec 31 12:28:20 PM PST 23
Finished Dec 31 12:28:57 PM PST 23
Peak memory 206852 kb
Host smart-5f43cd8d-6fb9-4dfb-9ed0-fefb784a9bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552707808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1552707808
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3736618009
Short name T452
Test name
Test status
Simulation time 1379715176 ps
CPU time 60.95 seconds
Started Dec 31 12:26:57 PM PST 23
Finished Dec 31 12:27:59 PM PST 23
Peak memory 198536 kb
Host smart-e0a8a63e-1876-4f40-a308-55e689226d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736618009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3736618009
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1980268174
Short name T224
Test name
Test status
Simulation time 2325900546 ps
CPU time 25.05 seconds
Started Dec 31 12:27:50 PM PST 23
Finished Dec 31 12:28:24 PM PST 23
Peak memory 198616 kb
Host smart-3bcfe206-83eb-44cb-966c-511d69df5e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980268174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1980268174
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2723301509
Short name T448
Test name
Test status
Simulation time 355181019 ps
CPU time 6.37 seconds
Started Dec 31 12:27:59 PM PST 23
Finished Dec 31 12:28:13 PM PST 23
Peak memory 198512 kb
Host smart-ff5a4e8e-00df-440a-9f04-d514305cbae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723301509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2723301509
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.547532898
Short name T848
Test name
Test status
Simulation time 31723413523 ps
CPU time 96.06 seconds
Started Dec 31 12:28:13 PM PST 23
Finished Dec 31 12:29:50 PM PST 23
Peak memory 198680 kb
Host smart-e54c4542-579e-4542-b47f-be6331e11071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547532898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.547532898
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.504712177
Short name T629
Test name
Test status
Simulation time 167896472 ps
CPU time 1.28 seconds
Started Dec 31 12:27:20 PM PST 23
Finished Dec 31 12:27:22 PM PST 23
Peak memory 198120 kb
Host smart-240ed68d-c83f-4e6c-b9cf-3a4d200f6b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504712177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.504712177
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.998865594
Short name T433
Test name
Test status
Simulation time 232659558100 ps
CPU time 1100.93 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:46:28 PM PST 23
Peak memory 214964 kb
Host smart-48480919-e3cc-4c90-9863-6aa89f99c630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998865594 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.998865594
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.743607403
Short name T652
Test name
Test status
Simulation time 367418988622 ps
CPU time 3786.1 seconds
Started Dec 31 12:27:33 PM PST 23
Finished Dec 31 01:30:40 PM PST 23
Peak memory 246292 kb
Host smart-155c17ef-5bfb-4c70-8f3b-49d994d0d372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743607403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.743607403
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.162221725
Short name T769
Test name
Test status
Simulation time 177044982 ps
CPU time 0.89 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 196124 kb
Host smart-885462aa-c48f-41ae-a170-c2839d8d75b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162221725 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.162221725
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3971197373
Short name T585
Test name
Test status
Simulation time 61933196041 ps
CPU time 375.42 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:34:00 PM PST 23
Peak memory 198612 kb
Host smart-93382204-a6fd-4443-8864-61c551ca7db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971197373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.3971197373
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2505293966
Short name T392
Test name
Test status
Simulation time 6742001396 ps
CPU time 34.94 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:27:20 PM PST 23
Peak memory 198580 kb
Host smart-a536a3e6-92b3-47b0-8a3f-011272ec3ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505293966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2505293966
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.826650646
Short name T835
Test name
Test status
Simulation time 21649830 ps
CPU time 0.54 seconds
Started Dec 31 12:28:53 PM PST 23
Finished Dec 31 12:28:59 PM PST 23
Peak memory 193036 kb
Host smart-debab008-0514-40d1-ac06-2670f6c3f1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826650646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.826650646
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2822108118
Short name T829
Test name
Test status
Simulation time 2389806155 ps
CPU time 31.01 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:49 PM PST 23
Peak memory 206820 kb
Host smart-ba05f8f7-8add-4ec6-a36e-27d7f668a740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822108118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2822108118
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1869139472
Short name T261
Test name
Test status
Simulation time 2474033913 ps
CPU time 17.81 seconds
Started Dec 31 12:30:07 PM PST 23
Finished Dec 31 12:30:29 PM PST 23
Peak memory 198640 kb
Host smart-21b23b96-822d-4835-9767-f21ff258f0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869139472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1869139472
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3008438707
Short name T638
Test name
Test status
Simulation time 978163446 ps
CPU time 44.93 seconds
Started Dec 31 12:28:08 PM PST 23
Finished Dec 31 12:28:56 PM PST 23
Peak memory 198416 kb
Host smart-6f808a2d-1157-4ddc-a943-5d34ab295a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008438707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3008438707
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4162799204
Short name T630
Test name
Test status
Simulation time 52296103952 ps
CPU time 148.32 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:29:48 PM PST 23
Peak memory 198716 kb
Host smart-4bcbac84-348d-4517-92d7-cce6777af0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162799204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4162799204
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2263259171
Short name T299
Test name
Test status
Simulation time 2349216341 ps
CPU time 56.98 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 198632 kb
Host smart-2e52bd32-0c27-4ac6-8356-093a97c45853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263259171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2263259171
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.520430547
Short name T830
Test name
Test status
Simulation time 115664608 ps
CPU time 1.07 seconds
Started Dec 31 12:27:08 PM PST 23
Finished Dec 31 12:27:11 PM PST 23
Peak memory 198508 kb
Host smart-3dfc5763-1e60-40f9-a0cb-9abcf9ada145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520430547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.520430547
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2133923131
Short name T566
Test name
Test status
Simulation time 182603107810 ps
CPU time 1741.99 seconds
Started Dec 31 12:28:45 PM PST 23
Finished Dec 31 12:57:53 PM PST 23
Peak memory 198680 kb
Host smart-d3aaee7b-8648-4925-8003-c982ebd22679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133923131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2133923131
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.1521636008
Short name T147
Test name
Test status
Simulation time 320988406615 ps
CPU time 2966.02 seconds
Started Dec 31 12:27:56 PM PST 23
Finished Dec 31 01:17:28 PM PST 23
Peak memory 263636 kb
Host smart-39ac2287-cc00-451f-95d7-b502131b683c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521636008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.1521636008
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2292722460
Short name T268
Test name
Test status
Simulation time 105066637 ps
CPU time 1.09 seconds
Started Dec 31 12:27:20 PM PST 23
Finished Dec 31 12:27:22 PM PST 23
Peak memory 196632 kb
Host smart-4e2c1617-f38a-4780-98ad-21f90ca52217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292722460 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2292722460
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1039016544
Short name T743
Test name
Test status
Simulation time 8726771230 ps
CPU time 405.47 seconds
Started Dec 31 12:28:32 PM PST 23
Finished Dec 31 12:35:26 PM PST 23
Peak memory 198616 kb
Host smart-e033bcbc-3a01-4191-ae5a-e224e0ef0ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039016544 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.1039016544
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1246119021
Short name T227
Test name
Test status
Simulation time 18509860186 ps
CPU time 83.3 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 12:30:02 PM PST 23
Peak memory 198628 kb
Host smart-75cb1bfe-faef-4ca8-bb0f-e1e23c9326f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246119021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1246119021
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3267166684
Short name T614
Test name
Test status
Simulation time 13774447 ps
CPU time 0.58 seconds
Started Dec 31 12:19:57 PM PST 23
Finished Dec 31 12:19:58 PM PST 23
Peak memory 192932 kb
Host smart-025bc47f-852a-4dce-928d-bd3ec973aee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267166684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3267166684
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2527025884
Short name T860
Test name
Test status
Simulation time 1408792122 ps
CPU time 39.52 seconds
Started Dec 31 12:20:16 PM PST 23
Finished Dec 31 12:20:56 PM PST 23
Peak memory 206800 kb
Host smart-c7e976f3-29ce-4631-afee-22ffa0e221a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527025884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2527025884
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.207069901
Short name T485
Test name
Test status
Simulation time 7086018963 ps
CPU time 22.2 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 198656 kb
Host smart-b10c09a9-255a-4625-8d47-a5b29f50e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207069901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.207069901
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.452804397
Short name T40
Test name
Test status
Simulation time 4759974945 ps
CPU time 37.5 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:26:26 PM PST 23
Peak memory 198604 kb
Host smart-55875f06-eccc-4de8-b531-36c320b9a8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452804397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.452804397
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1621859039
Short name T368
Test name
Test status
Simulation time 4802944546 ps
CPU time 116.46 seconds
Started Dec 31 12:23:27 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 198400 kb
Host smart-5aef8d08-91b6-49b4-a578-7117e33af405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621859039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1621859039
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1779447205
Short name T483
Test name
Test status
Simulation time 4914598517 ps
CPU time 57.44 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 198364 kb
Host smart-de32dd7b-6a6b-4304-9110-195face78041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779447205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1779447205
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2265229454
Short name T50
Test name
Test status
Simulation time 92202706 ps
CPU time 0.95 seconds
Started Dec 31 12:23:38 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 216792 kb
Host smart-fec19e96-71e0-47ad-a745-2807bb76d6a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265229454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2265229454
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1030705540
Short name T492
Test name
Test status
Simulation time 250683306 ps
CPU time 3.81 seconds
Started Dec 31 12:26:20 PM PST 23
Finished Dec 31 12:26:25 PM PST 23
Peak memory 198396 kb
Host smart-c376b629-e1e8-4b05-9026-a085c4c44ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030705540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1030705540
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2245435609
Short name T132
Test name
Test status
Simulation time 811894127068 ps
CPU time 1192.31 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:44:12 PM PST 23
Peak memory 207864 kb
Host smart-c202fda0-c71f-4f46-97fd-205f774613db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245435609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2245435609
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.204733045
Short name T724
Test name
Test status
Simulation time 79048847348 ps
CPU time 2017.07 seconds
Started Dec 31 12:20:39 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 233920 kb
Host smart-464511fc-b4bb-47e3-821f-8117c789e2bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204733045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.204733045
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2228144048
Short name T846
Test name
Test status
Simulation time 52129766 ps
CPU time 0.93 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 195780 kb
Host smart-b5d09d86-3677-42a7-b34c-faaa82846f2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228144048 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2228144048
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2249477667
Short name T744
Test name
Test status
Simulation time 28368447869 ps
CPU time 415.87 seconds
Started Dec 31 12:27:48 PM PST 23
Finished Dec 31 12:34:46 PM PST 23
Peak memory 198592 kb
Host smart-c7ab689d-17ed-4508-b2fc-49442cf13110
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249477667 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.2249477667
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2213696574
Short name T340
Test name
Test status
Simulation time 437370196 ps
CPU time 10.42 seconds
Started Dec 31 12:24:21 PM PST 23
Finished Dec 31 12:24:34 PM PST 23
Peak memory 198532 kb
Host smart-01a38efd-e77b-4536-9832-cbf8c665abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213696574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2213696574
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2441016882
Short name T665
Test name
Test status
Simulation time 22565598 ps
CPU time 0.55 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:02 PM PST 23
Peak memory 193916 kb
Host smart-353cc307-698a-4347-b49c-f9a6199c5bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441016882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2441016882
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.870554777
Short name T622
Test name
Test status
Simulation time 316065228 ps
CPU time 4 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:26:59 PM PST 23
Peak memory 198468 kb
Host smart-b4593b5c-40cb-4a83-bd7f-4d6c251fab7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870554777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.870554777
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1584586024
Short name T218
Test name
Test status
Simulation time 2688845554 ps
CPU time 12.31 seconds
Started Dec 31 12:29:40 PM PST 23
Finished Dec 31 12:30:00 PM PST 23
Peak memory 198616 kb
Host smart-19d14217-8feb-45b9-8e9b-0b84444368f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584586024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1584586024
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1603113522
Short name T756
Test name
Test status
Simulation time 7975835572 ps
CPU time 94.27 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:29:04 PM PST 23
Peak memory 198652 kb
Host smart-2da08d62-1705-4d49-b877-954d6bac4a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603113522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1603113522
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.56983076
Short name T666
Test name
Test status
Simulation time 9981292906 ps
CPU time 120.71 seconds
Started Dec 31 12:27:43 PM PST 23
Finished Dec 31 12:29:44 PM PST 23
Peak memory 198564 kb
Host smart-51fdf3b2-59d8-4014-a268-968d3dd96906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56983076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.56983076
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3622506537
Short name T713
Test name
Test status
Simulation time 1707179513 ps
CPU time 60.97 seconds
Started Dec 31 12:29:58 PM PST 23
Finished Dec 31 12:31:07 PM PST 23
Peak memory 198496 kb
Host smart-6e5a25f1-5020-4aef-b2d5-1e38668c8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622506537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3622506537
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.981824432
Short name T53
Test name
Test status
Simulation time 254378897 ps
CPU time 2.87 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:04 PM PST 23
Peak memory 198504 kb
Host smart-276ca99a-9809-43f8-ad1c-9cdd9d0295e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981824432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.981824432
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1403279664
Short name T326
Test name
Test status
Simulation time 153976005394 ps
CPU time 2346.16 seconds
Started Dec 31 12:27:25 PM PST 23
Finished Dec 31 01:06:32 PM PST 23
Peak memory 198664 kb
Host smart-70a61906-e646-4338-9fb1-0e199b879c92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403279664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1403279664
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.2308424338
Short name T838
Test name
Test status
Simulation time 62232590446 ps
CPU time 771.05 seconds
Started Dec 31 12:28:23 PM PST 23
Finished Dec 31 12:41:16 PM PST 23
Peak memory 239720 kb
Host smart-9a063c73-b7be-4b90-93c3-f3afaff76bfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308424338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.2308424338
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1474192200
Short name T315
Test name
Test status
Simulation time 48446295 ps
CPU time 0.97 seconds
Started Dec 31 12:28:13 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 195636 kb
Host smart-ebb56c2b-ea41-4949-a53a-649272162241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474192200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1474192200
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.862387057
Short name T375
Test name
Test status
Simulation time 114337164943 ps
CPU time 389.13 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:33:52 PM PST 23
Peak memory 198520 kb
Host smart-98c59216-081c-48b4-b6fd-24ecaba1da8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862387057 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_sha_vectors.862387057
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3232246654
Short name T250
Test name
Test status
Simulation time 16416734152 ps
CPU time 21.8 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 198680 kb
Host smart-4cb39685-0bff-4d88-b292-c00cd6c8ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232246654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3232246654
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.250447305
Short name T674
Test name
Test status
Simulation time 104095781 ps
CPU time 0.55 seconds
Started Dec 31 12:28:10 PM PST 23
Finished Dec 31 12:28:13 PM PST 23
Peak memory 192924 kb
Host smart-2b8d196a-425c-4bba-a2fa-c060c467004a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250447305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.250447305
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.306797874
Short name T401
Test name
Test status
Simulation time 1349418070 ps
CPU time 10.67 seconds
Started Dec 31 12:28:09 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 214120 kb
Host smart-1de91d95-b87f-4364-8b19-8f1c7e1077b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306797874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.306797874
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1417564864
Short name T217
Test name
Test status
Simulation time 2006477444 ps
CPU time 42.95 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:29:04 PM PST 23
Peak memory 198584 kb
Host smart-03fd84a3-8987-4183-8b72-3e83f090f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417564864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1417564864
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1215423884
Short name T818
Test name
Test status
Simulation time 5159182645 ps
CPU time 65.82 seconds
Started Dec 31 12:28:30 PM PST 23
Finished Dec 31 12:29:46 PM PST 23
Peak memory 198696 kb
Host smart-9d0ec40b-747d-4731-a08d-c263735ca638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215423884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1215423884
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.312887228
Short name T386
Test name
Test status
Simulation time 9823225702 ps
CPU time 114.99 seconds
Started Dec 31 12:28:12 PM PST 23
Finished Dec 31 12:30:09 PM PST 23
Peak memory 198652 kb
Host smart-0122d709-5047-4f5e-aac5-d6a603402a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312887228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.312887228
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3239130964
Short name T141
Test name
Test status
Simulation time 8238123401 ps
CPU time 96.59 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:28:36 PM PST 23
Peak memory 198588 kb
Host smart-e449bde1-c179-447d-a8cc-48bceb56a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239130964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3239130964
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.282362398
Short name T233
Test name
Test status
Simulation time 245960108 ps
CPU time 0.89 seconds
Started Dec 31 12:28:23 PM PST 23
Finished Dec 31 12:28:26 PM PST 23
Peak memory 196696 kb
Host smart-b18dbfcf-0bc3-4795-9d07-158eebeb4954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282362398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.282362398
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4290328607
Short name T365
Test name
Test status
Simulation time 157575361892 ps
CPU time 1868.77 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:58:17 PM PST 23
Peak memory 223644 kb
Host smart-048d43f4-9cb8-4e03-9725-c903f6cbc5f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290328607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4290328607
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.284879193
Short name T93
Test name
Test status
Simulation time 124307878526 ps
CPU time 430.23 seconds
Started Dec 31 12:27:57 PM PST 23
Finished Dec 31 12:35:12 PM PST 23
Peak memory 207416 kb
Host smart-1776a2c0-6f2f-48b5-83e4-0bab35b4ee10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284879193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.284879193
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.846020848
Short name T213
Test name
Test status
Simulation time 55896778 ps
CPU time 1.15 seconds
Started Dec 31 12:27:23 PM PST 23
Finished Dec 31 12:27:25 PM PST 23
Peak memory 196636 kb
Host smart-38ed8cf2-a7f2-4d9e-9934-3746449aed07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846020848 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.846020848
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3579607440
Short name T56
Test name
Test status
Simulation time 10552408791 ps
CPU time 370.59 seconds
Started Dec 31 12:27:26 PM PST 23
Finished Dec 31 12:33:37 PM PST 23
Peak memory 198592 kb
Host smart-c5e7f924-3b35-4880-a709-5fcc88162c06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579607440 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.3579607440
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.396666331
Short name T776
Test name
Test status
Simulation time 508055088 ps
CPU time 13.2 seconds
Started Dec 31 12:27:36 PM PST 23
Finished Dec 31 12:27:50 PM PST 23
Peak memory 198484 kb
Host smart-d1f5dbbd-8a95-4e8e-9e4f-33a5f6c0a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396666331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.396666331
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.111869853
Short name T46
Test name
Test status
Simulation time 16887786 ps
CPU time 0.54 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:32 PM PST 23
Peak memory 192848 kb
Host smart-5c963e3a-5b9d-4cb5-9baf-c9744e67ac40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111869853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.111869853
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2790448833
Short name T398
Test name
Test status
Simulation time 4005681769 ps
CPU time 34.57 seconds
Started Dec 31 12:27:37 PM PST 23
Finished Dec 31 12:28:12 PM PST 23
Peak memory 220216 kb
Host smart-3f431e05-4462-4130-8063-3e7685f06974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790448833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2790448833
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1111204989
Short name T290
Test name
Test status
Simulation time 4905781454 ps
CPU time 30.79 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:32 PM PST 23
Peak memory 198672 kb
Host smart-1a80c204-0668-4747-9505-ce9146be622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111204989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1111204989
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3823645006
Short name T511
Test name
Test status
Simulation time 1005563562 ps
CPU time 46.72 seconds
Started Dec 31 12:29:02 PM PST 23
Finished Dec 31 12:29:58 PM PST 23
Peak memory 197216 kb
Host smart-a17e4f12-8057-4df2-b613-71f3015bff8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823645006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3823645006
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1264243720
Short name T586
Test name
Test status
Simulation time 1399228913 ps
CPU time 66.15 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 198576 kb
Host smart-9d8044a1-dd09-4440-b796-805405f96e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264243720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1264243720
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3175478974
Short name T405
Test name
Test status
Simulation time 6651322066 ps
CPU time 48.8 seconds
Started Dec 31 12:27:26 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 198732 kb
Host smart-f75f7d4f-dce9-4140-a1a1-d0fc47eb08bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175478974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3175478974
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3094913738
Short name T270
Test name
Test status
Simulation time 163640509 ps
CPU time 1.9 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:27:46 PM PST 23
Peak memory 198528 kb
Host smart-a4bff7a0-5b70-46a8-a718-db3f38070b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094913738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3094913738
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2653610552
Short name T284
Test name
Test status
Simulation time 74898621819 ps
CPU time 839.31 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:41:05 PM PST 23
Peak memory 233372 kb
Host smart-0eac172f-19e0-49d2-83f9-d5569df7e4ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653610552 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2653610552
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.4168939306
Short name T385
Test name
Test status
Simulation time 26482218250 ps
CPU time 101.8 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:29:51 PM PST 23
Peak memory 247972 kb
Host smart-1dc36248-4140-4180-ba5a-7a6aadaf2cfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168939306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.4168939306
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.110710557
Short name T521
Test name
Test status
Simulation time 26660998 ps
CPU time 0.86 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:53 PM PST 23
Peak memory 196216 kb
Host smart-04f1bc0b-4af6-4883-9205-fb04d6e8c661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110710557 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.110710557
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1846314909
Short name T320
Test name
Test status
Simulation time 8466867845 ps
CPU time 398.43 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:33:58 PM PST 23
Peak memory 198740 kb
Host smart-5d3ee26d-ae9d-47b7-a42b-5f8316125996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846314909 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.1846314909
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2284993783
Short name T295
Test name
Test status
Simulation time 14983964561 ps
CPU time 47.55 seconds
Started Dec 31 12:28:20 PM PST 23
Finished Dec 31 12:29:09 PM PST 23
Peak memory 198668 kb
Host smart-ec75de37-3dd7-486e-b4cb-b5468a482383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284993783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2284993783
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1372920373
Short name T854
Test name
Test status
Simulation time 72616772 ps
CPU time 0.53 seconds
Started Dec 31 12:28:11 PM PST 23
Finished Dec 31 12:28:14 PM PST 23
Peak memory 192896 kb
Host smart-a982f07a-abab-4c25-9ab2-0eea53400834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372920373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1372920373
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2826519537
Short name T658
Test name
Test status
Simulation time 620579894 ps
CPU time 18.43 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:27:55 PM PST 23
Peak memory 223092 kb
Host smart-164b7a0a-082e-4642-8c28-c5571e2ca5c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826519537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2826519537
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2293286160
Short name T226
Test name
Test status
Simulation time 5153705249 ps
CPU time 10.66 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 198708 kb
Host smart-1a277cf2-4f91-43cd-82e6-3f1787f05aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293286160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2293286160
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.817506034
Short name T222
Test name
Test status
Simulation time 4481432227 ps
CPU time 56.67 seconds
Started Dec 31 12:28:39 PM PST 23
Finished Dec 31 12:29:44 PM PST 23
Peak memory 198680 kb
Host smart-71c988ff-a40b-48a3-a91e-ac470ed5e8e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817506034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.817506034
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.853186589
Short name T547
Test name
Test status
Simulation time 799290799 ps
CPU time 8.68 seconds
Started Dec 31 12:27:09 PM PST 23
Finished Dec 31 12:27:20 PM PST 23
Peak memory 198540 kb
Host smart-6630cd71-aade-4ba9-9194-950f7c4cac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853186589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.853186589
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2454300704
Short name T413
Test name
Test status
Simulation time 7044976415 ps
CPU time 91.15 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:28:43 PM PST 23
Peak memory 198652 kb
Host smart-94b882e9-a464-4023-8f80-e870d273ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454300704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2454300704
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3992709530
Short name T427
Test name
Test status
Simulation time 27772992 ps
CPU time 0.95 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 197764 kb
Host smart-329657fc-7b81-4d32-bdf1-42deb93b3427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992709530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3992709530
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2926175800
Short name T837
Test name
Test status
Simulation time 94120576578 ps
CPU time 301.01 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 232372 kb
Host smart-b9bbd586-6f2c-42ad-8d89-e14ef0025779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926175800 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2926175800
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.908329911
Short name T116
Test name
Test status
Simulation time 716820532230 ps
CPU time 1346.38 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 12:51:15 PM PST 23
Peak memory 262196 kb
Host smart-8d48ca02-f675-4284-9101-50eaa450218b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908329911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.908329911
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1053701900
Short name T820
Test name
Test status
Simulation time 232066332 ps
CPU time 1.03 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 12:28:41 PM PST 23
Peak memory 197136 kb
Host smart-5f8e9068-57b1-4cb7-a400-e1ddbb4f538a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053701900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1053701900
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.28751873
Short name T849
Test name
Test status
Simulation time 29540419961 ps
CPU time 376.32 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:34:31 PM PST 23
Peak memory 198728 kb
Host smart-1c934575-5529-464d-96c6-e986cb75fdb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751873 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.hmac_test_sha_vectors.28751873
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2486233738
Short name T499
Test name
Test status
Simulation time 45044157898 ps
CPU time 39.01 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:28:38 PM PST 23
Peak memory 198724 kb
Host smart-e8425e97-1521-466c-b6cc-83c13d9f8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486233738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2486233738
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1345074760
Short name T487
Test name
Test status
Simulation time 18921449 ps
CPU time 0.55 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 12:28:40 PM PST 23
Peak memory 192896 kb
Host smart-0a2ddd3d-1bca-4315-85ef-2d43074197aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345074760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1345074760
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.586383675
Short name T35
Test name
Test status
Simulation time 836715429 ps
CPU time 30.87 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:27:47 PM PST 23
Peak memory 231244 kb
Host smart-ab6c44a5-abb5-4637-b004-ca20d30923f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586383675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.586383675
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1355737339
Short name T297
Test name
Test status
Simulation time 1495304924 ps
CPU time 20.11 seconds
Started Dec 31 12:28:43 PM PST 23
Finished Dec 31 12:29:09 PM PST 23
Peak memory 198584 kb
Host smart-9f7f34d6-c073-4a51-8a0b-5147edc3f2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355737339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1355737339
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.26901213
Short name T531
Test name
Test status
Simulation time 812437141 ps
CPU time 39.72 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:28:18 PM PST 23
Peak memory 198436 kb
Host smart-6ee5c768-3935-417a-a364-2031bdbd4365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26901213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.26901213
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.572929210
Short name T618
Test name
Test status
Simulation time 208405432 ps
CPU time 9.91 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 12:28:25 PM PST 23
Peak memory 198468 kb
Host smart-9e90753a-564e-4e0c-8f0e-65e9e626ffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572929210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.572929210
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.342034695
Short name T439
Test name
Test status
Simulation time 5477254130 ps
CPU time 71.82 seconds
Started Dec 31 12:28:14 PM PST 23
Finished Dec 31 12:29:27 PM PST 23
Peak memory 198720 kb
Host smart-8cd8e8b4-c6ec-4abe-9d8d-bc2e1ef6679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342034695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.342034695
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.905392709
Short name T220
Test name
Test status
Simulation time 1012574346 ps
CPU time 2.6 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:27:17 PM PST 23
Peak memory 198408 kb
Host smart-e069b419-df61-4a03-85cf-b22153a16111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905392709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.905392709
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1629707333
Short name T451
Test name
Test status
Simulation time 80631586838 ps
CPU time 712.2 seconds
Started Dec 31 12:27:51 PM PST 23
Finished Dec 31 12:39:46 PM PST 23
Peak memory 198592 kb
Host smart-4f1239e6-5656-4347-af8a-3952d110708d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629707333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1629707333
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3787600345
Short name T276
Test name
Test status
Simulation time 65623043356 ps
CPU time 1464.31 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:53:07 PM PST 23
Peak memory 216324 kb
Host smart-22f35729-e3b5-4c41-9ac0-f5f53b35b37b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787600345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.3787600345
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2169534307
Short name T824
Test name
Test status
Simulation time 119954680 ps
CPU time 1 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 197324 kb
Host smart-49a6b3ff-1d0b-4550-acaa-cda92fbd4b73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169534307 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2169534307
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.12226764
Short name T294
Test name
Test status
Simulation time 87207897232 ps
CPU time 342.73 seconds
Started Dec 31 12:27:03 PM PST 23
Finished Dec 31 12:32:48 PM PST 23
Peak memory 198656 kb
Host smart-80bff4b9-7c31-41d3-931f-b1df60bd76d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226764 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.hmac_test_sha_vectors.12226764
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.286212262
Short name T380
Test name
Test status
Simulation time 3375653834 ps
CPU time 14.58 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 198508 kb
Host smart-52e03352-09a4-421d-9893-56bc42b5ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286212262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.286212262
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3677766799
Short name T269
Test name
Test status
Simulation time 54777653 ps
CPU time 0.57 seconds
Started Dec 31 12:28:20 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 194024 kb
Host smart-caf2aec3-4e6c-4888-a86c-fcf51d7c5407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677766799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3677766799
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3814176746
Short name T479
Test name
Test status
Simulation time 388798820 ps
CPU time 11.9 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 206648 kb
Host smart-4ade167d-7298-4544-86e1-f66de53211e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814176746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3814176746
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.795425302
Short name T643
Test name
Test status
Simulation time 3745210442 ps
CPU time 46.45 seconds
Started Dec 31 12:27:57 PM PST 23
Finished Dec 31 12:28:49 PM PST 23
Peak memory 198684 kb
Host smart-291bf61d-7e9c-41e7-848f-6a9135cde47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795425302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.795425302
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.195336640
Short name T526
Test name
Test status
Simulation time 2720133209 ps
CPU time 56.21 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:29:13 PM PST 23
Peak memory 198604 kb
Host smart-3fe9b721-7135-4e4e-806e-50ddc21f489b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195336640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.195336640
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2429687592
Short name T598
Test name
Test status
Simulation time 35387339812 ps
CPU time 112.2 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:29:40 PM PST 23
Peak memory 198708 kb
Host smart-77c8f485-302a-4c1d-9d40-9c6e8925a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429687592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2429687592
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1895856001
Short name T823
Test name
Test status
Simulation time 5452686207 ps
CPU time 87.22 seconds
Started Dec 31 12:27:23 PM PST 23
Finished Dec 31 12:28:51 PM PST 23
Peak memory 198656 kb
Host smart-5111f54b-b6a1-4b57-96a1-56af993b9039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895856001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1895856001
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3615111222
Short name T362
Test name
Test status
Simulation time 531433685 ps
CPU time 1.61 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:12 PM PST 23
Peak memory 197980 kb
Host smart-c2482955-25cd-4454-a1ee-3786eef0de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615111222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3615111222
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1428542310
Short name T210
Test name
Test status
Simulation time 256924520 ps
CPU time 1.67 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:27:44 PM PST 23
Peak memory 198624 kb
Host smart-7274b1d3-c096-4d44-9d93-28fc2c19f46d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428542310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1428542310
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.2831189676
Short name T542
Test name
Test status
Simulation time 44190099089 ps
CPU time 796.04 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:42:00 PM PST 23
Peak memory 247856 kb
Host smart-ee0fbe8a-3ecd-4038-96fb-b3c1c878f7ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831189676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.2831189676
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3266654213
Short name T500
Test name
Test status
Simulation time 53276486 ps
CPU time 0.95 seconds
Started Dec 31 12:28:58 PM PST 23
Finished Dec 31 12:29:03 PM PST 23
Peak memory 196304 kb
Host smart-413f0e3c-dad4-4970-b54a-1cdf97face93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266654213 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3266654213
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1839508857
Short name T55
Test name
Test status
Simulation time 69673784521 ps
CPU time 380.13 seconds
Started Dec 31 12:28:56 PM PST 23
Finished Dec 31 12:35:21 PM PST 23
Peak memory 198716 kb
Host smart-0794435a-0f38-470f-9611-7a06e5a42245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839508857 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.1839508857
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1533806693
Short name T718
Test name
Test status
Simulation time 541299143 ps
CPU time 10.82 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:28:31 PM PST 23
Peak memory 198444 kb
Host smart-43f80562-d07b-4436-90e2-742369617943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533806693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1533806693
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3053486695
Short name T257
Test name
Test status
Simulation time 54626618 ps
CPU time 0.57 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 192892 kb
Host smart-e404aecb-0949-48b9-8f7a-e016d9136d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053486695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3053486695
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.496192953
Short name T471
Test name
Test status
Simulation time 775543717 ps
CPU time 7.3 seconds
Started Dec 31 12:28:20 PM PST 23
Finished Dec 31 12:28:29 PM PST 23
Peak memory 223120 kb
Host smart-1360fcc3-1637-4193-8d31-99779cbb1a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496192953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.496192953
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.214932906
Short name T588
Test name
Test status
Simulation time 539005766 ps
CPU time 22.9 seconds
Started Dec 31 12:27:10 PM PST 23
Finished Dec 31 12:27:35 PM PST 23
Peak memory 198500 kb
Host smart-d11ddd9b-b8cc-4c7e-a646-96157b7289a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214932906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.214932906
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2653713133
Short name T331
Test name
Test status
Simulation time 3648812351 ps
CPU time 31.1 seconds
Started Dec 31 12:28:37 PM PST 23
Finished Dec 31 12:29:17 PM PST 23
Peak memory 198724 kb
Host smart-da2ae5fb-f9be-4407-bc6d-84081841c568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653713133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2653713133
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2333025991
Short name T376
Test name
Test status
Simulation time 14013159520 ps
CPU time 131.76 seconds
Started Dec 31 12:28:09 PM PST 23
Finished Dec 31 12:30:28 PM PST 23
Peak memory 198652 kb
Host smart-659978b3-d8be-4a64-9529-c0979d6fb615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333025991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2333025991
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.559375318
Short name T432
Test name
Test status
Simulation time 2116054483 ps
CPU time 28.69 seconds
Started Dec 31 12:26:43 PM PST 23
Finished Dec 31 12:27:18 PM PST 23
Peak memory 198584 kb
Host smart-cf9d2339-0cf1-4719-9960-831dfebd3991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559375318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.559375318
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1850034237
Short name T419
Test name
Test status
Simulation time 67670894 ps
CPU time 1.53 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:12 PM PST 23
Peak memory 198608 kb
Host smart-f7e2e7e7-da8c-4f20-bc0d-9e6500ef0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850034237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1850034237
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2136822912
Short name T851
Test name
Test status
Simulation time 47744420049 ps
CPU time 149.52 seconds
Started Dec 31 12:26:54 PM PST 23
Finished Dec 31 12:29:25 PM PST 23
Peak memory 198668 kb
Host smart-dce12fa2-5452-4b70-948c-76d0b625a3a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136822912 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2136822912
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.1026149560
Short name T241
Test name
Test status
Simulation time 83094322745 ps
CPU time 273 seconds
Started Dec 31 12:29:45 PM PST 23
Finished Dec 31 12:34:21 PM PST 23
Peak memory 214480 kb
Host smart-6cf19b28-c97e-4eac-afaa-7f137b0178e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026149560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.1026149560
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4110863025
Short name T832
Test name
Test status
Simulation time 189368761 ps
CPU time 1.04 seconds
Started Dec 31 12:29:38 PM PST 23
Finished Dec 31 12:29:41 PM PST 23
Peak memory 196888 kb
Host smart-fcf1f7d2-1c95-48f9-9f39-b4c2b93e9056
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110863025 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4110863025
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1703476798
Short name T668
Test name
Test status
Simulation time 28185282034 ps
CPU time 426.78 seconds
Started Dec 31 12:28:39 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 198712 kb
Host smart-ba3ca639-26ea-494e-b724-5f6376b6e92e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703476798 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1703476798
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3651608806
Short name T671
Test name
Test status
Simulation time 2242042957 ps
CPU time 19.49 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:28:22 PM PST 23
Peak memory 198592 kb
Host smart-d00232a5-72db-4deb-85c8-19f839bfb5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651608806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3651608806
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2296106092
Short name T247
Test name
Test status
Simulation time 20979646 ps
CPU time 0.55 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 192932 kb
Host smart-dbe7f8d9-fc40-4dbd-9d1b-1c62278ba064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296106092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2296106092
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.371577906
Short name T314
Test name
Test status
Simulation time 3140734724 ps
CPU time 17.25 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:27:56 PM PST 23
Peak memory 214596 kb
Host smart-f1361186-53ca-4cdf-9fbc-401fe2ab6967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371577906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.371577906
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.417044081
Short name T248
Test name
Test status
Simulation time 4185153191 ps
CPU time 36.96 seconds
Started Dec 31 12:28:03 PM PST 23
Finished Dec 31 12:28:45 PM PST 23
Peak memory 198648 kb
Host smart-4d31a5ca-dbb5-4353-842c-9b6582b626b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417044081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.417044081
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1415172741
Short name T119
Test name
Test status
Simulation time 5398822408 ps
CPU time 63.76 seconds
Started Dec 31 12:30:09 PM PST 23
Finished Dec 31 12:31:17 PM PST 23
Peak memory 198584 kb
Host smart-2a472f8c-875c-4d14-a630-113ca8f2fd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415172741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1415172741
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3651384795
Short name T254
Test name
Test status
Simulation time 36258451 ps
CPU time 0.58 seconds
Started Dec 31 12:29:02 PM PST 23
Finished Dec 31 12:29:12 PM PST 23
Peak memory 191568 kb
Host smart-d0029cfb-982c-4aa5-8f4b-8ff02333b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651384795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3651384795
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4107766586
Short name T659
Test name
Test status
Simulation time 1256430445 ps
CPU time 6.39 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 12:28:46 PM PST 23
Peak memory 198508 kb
Host smart-6eda490e-8765-4040-8613-c6c40ea70af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107766586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4107766586
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2670376571
Short name T570
Test name
Test status
Simulation time 54646534 ps
CPU time 0.68 seconds
Started Dec 31 12:28:37 PM PST 23
Finished Dec 31 12:28:46 PM PST 23
Peak memory 194284 kb
Host smart-8f82c657-5084-47b3-873f-df1a94760dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670376571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2670376571
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1171188850
Short name T528
Test name
Test status
Simulation time 2120873812 ps
CPU time 34.73 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 12:28:44 PM PST 23
Peak memory 198528 kb
Host smart-7d88ff3c-55ef-4ba0-bf6b-8d2ccadcb4fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171188850 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1171188850
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.3849361736
Short name T803
Test name
Test status
Simulation time 16853747286 ps
CPU time 294.16 seconds
Started Dec 31 12:27:11 PM PST 23
Finished Dec 31 12:32:07 PM PST 23
Peak memory 198812 kb
Host smart-b8b2c463-7d23-44bb-9875-52d6144f4c6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849361736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.3849361736
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3698527444
Short name T467
Test name
Test status
Simulation time 271842339 ps
CPU time 0.92 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:28:44 PM PST 23
Peak memory 195692 kb
Host smart-29786d75-9d0c-4244-9f16-cacf16a5c83a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698527444 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3698527444
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1654060663
Short name T355
Test name
Test status
Simulation time 28149317968 ps
CPU time 327.77 seconds
Started Dec 31 12:27:38 PM PST 23
Finished Dec 31 12:33:06 PM PST 23
Peak memory 198664 kb
Host smart-fbf5f19a-e755-46d8-8655-0ab9b91c5d2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654060663 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.1654060663
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2749506669
Short name T470
Test name
Test status
Simulation time 495531665 ps
CPU time 23.95 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:36 PM PST 23
Peak memory 198520 kb
Host smart-0945ea99-58da-4fcd-a000-c45f189a604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749506669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2749506669
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3451016077
Short name T360
Test name
Test status
Simulation time 27910671 ps
CPU time 0.55 seconds
Started Dec 31 12:28:02 PM PST 23
Finished Dec 31 12:28:08 PM PST 23
Peak memory 192924 kb
Host smart-bf2e3e65-1093-4ce9-8a91-d91e382ffdeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451016077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3451016077
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.772437871
Short name T43
Test name
Test status
Simulation time 841113573 ps
CPU time 12.14 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:28:14 PM PST 23
Peak memory 198484 kb
Host smart-031edb72-16ff-4fad-baee-8884c6e42f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772437871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.772437871
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2422536484
Short name T723
Test name
Test status
Simulation time 2029692271 ps
CPU time 33.11 seconds
Started Dec 31 12:28:25 PM PST 23
Finished Dec 31 12:29:00 PM PST 23
Peak memory 198512 kb
Host smart-697cb0f3-8dfc-4c28-9bdc-4c54406cf7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422536484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2422536484
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3380169671
Short name T231
Test name
Test status
Simulation time 1491425229 ps
CPU time 36.12 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 12:28:57 PM PST 23
Peak memory 198576 kb
Host smart-a4251493-e836-4344-aa92-ec3e88f6b4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380169671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3380169671
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3031564780
Short name T232
Test name
Test status
Simulation time 13109910792 ps
CPU time 41.27 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:28:29 PM PST 23
Peak memory 198648 kb
Host smart-b7749663-efcf-46d3-ba2b-d1e251aa91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031564780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3031564780
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3537250561
Short name T332
Test name
Test status
Simulation time 7989806988 ps
CPU time 100.07 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:29:39 PM PST 23
Peak memory 198624 kb
Host smart-d5534262-4e61-4236-a7f9-7b705a4f7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537250561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3537250561
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3315874997
Short name T662
Test name
Test status
Simulation time 1594789340 ps
CPU time 1.51 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 198232 kb
Host smart-7ef7e177-8399-4bcf-b254-2ed22af37f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315874997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3315874997
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3220058302
Short name T324
Test name
Test status
Simulation time 64237328208 ps
CPU time 796.76 seconds
Started Dec 31 12:29:55 PM PST 23
Finished Dec 31 12:43:14 PM PST 23
Peak memory 239608 kb
Host smart-3e842f03-d3b2-4de9-a4ab-83643f883366
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220058302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3220058302
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.4046056260
Short name T211
Test name
Test status
Simulation time 86141159745 ps
CPU time 1186.32 seconds
Started Dec 31 12:28:37 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 246704 kb
Host smart-28b4ecef-91b5-424b-8e90-f5e41998b002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046056260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.4046056260
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3766714238
Short name T603
Test name
Test status
Simulation time 114614216 ps
CPU time 1.07 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:27:24 PM PST 23
Peak memory 196960 kb
Host smart-821b2c0e-5520-48d2-bea9-eaa15582ef7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766714238 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3766714238
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.398536511
Short name T573
Test name
Test status
Simulation time 49549322234 ps
CPU time 384.85 seconds
Started Dec 31 12:28:15 PM PST 23
Finished Dec 31 12:34:42 PM PST 23
Peak memory 198632 kb
Host smart-8b56d946-5446-4897-bdf0-d27192e393db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398536511 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_sha_vectors.398536511
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3013333619
Short name T13
Test name
Test status
Simulation time 6947511515 ps
CPU time 76.42 seconds
Started Dec 31 12:27:39 PM PST 23
Finished Dec 31 12:28:56 PM PST 23
Peak memory 198736 kb
Host smart-8410d93d-7fb7-40a9-a49a-1357aed366d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013333619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3013333619
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.578270359
Short name T473
Test name
Test status
Simulation time 47691579 ps
CPU time 0.56 seconds
Started Dec 31 12:28:49 PM PST 23
Finished Dec 31 12:28:55 PM PST 23
Peak memory 192984 kb
Host smart-b216df6f-7698-4842-9dcb-9000b1775ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578270359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.578270359
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.889701239
Short name T9
Test name
Test status
Simulation time 849993471 ps
CPU time 6.33 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:27:54 PM PST 23
Peak memory 206920 kb
Host smart-3146ffc2-1ea2-4c3c-a202-1a12340e7de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889701239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.889701239
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1419935309
Short name T454
Test name
Test status
Simulation time 631841285 ps
CPU time 6.72 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:27:57 PM PST 23
Peak memory 198476 kb
Host smart-3c052999-3b6a-406b-a950-a895d32b3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419935309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1419935309
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3577241346
Short name T537
Test name
Test status
Simulation time 524340525 ps
CPU time 26.73 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:57 PM PST 23
Peak memory 198476 kb
Host smart-f39793e7-e250-4d8b-978b-4cd0e4f7195e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577241346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3577241346
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3408120111
Short name T799
Test name
Test status
Simulation time 1616027594 ps
CPU time 24.48 seconds
Started Dec 31 12:27:59 PM PST 23
Finished Dec 31 12:28:30 PM PST 23
Peak memory 198524 kb
Host smart-920a6a8d-ab0c-472b-b935-4bcbb03abf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408120111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3408120111
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.171664585
Short name T502
Test name
Test status
Simulation time 71872926 ps
CPU time 3.41 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:28:05 PM PST 23
Peak memory 198484 kb
Host smart-f22b3324-9946-43ae-a078-a3b63f9f85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171664585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.171664585
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3810972214
Short name T404
Test name
Test status
Simulation time 1188107597 ps
CPU time 4.03 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:15 PM PST 23
Peak memory 198340 kb
Host smart-1a17d70e-da24-4b77-ac23-abd8539790dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810972214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3810972214
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3352417785
Short name T605
Test name
Test status
Simulation time 144566378192 ps
CPU time 1588.17 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 214448 kb
Host smart-24146a1c-175a-4da6-b278-ac004ec37dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352417785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3352417785
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.359773769
Short name T858
Test name
Test status
Simulation time 28961641288 ps
CPU time 1312.52 seconds
Started Dec 31 12:27:42 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 247016 kb
Host smart-04246284-0a53-45ac-a056-b8658d9a1c74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359773769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.359773769
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.886957251
Short name T209
Test name
Test status
Simulation time 48141431 ps
CPU time 0.88 seconds
Started Dec 31 12:27:58 PM PST 23
Finished Dec 31 12:28:03 PM PST 23
Peak memory 195456 kb
Host smart-16a07414-8340-4894-9393-e719e010f2a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886957251 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.886957251
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.954860647
Short name T422
Test name
Test status
Simulation time 141770617783 ps
CPU time 406.33 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:34:09 PM PST 23
Peak memory 198616 kb
Host smart-2def7bb9-68db-4bcf-b65d-bdf69236fc5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954860647 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_test_sha_vectors.954860647
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1472363154
Short name T516
Test name
Test status
Simulation time 4506716524 ps
CPU time 57.71 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:27:54 PM PST 23
Peak memory 198524 kb
Host smart-036082ba-f752-4d24-a457-7afd1d63fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472363154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1472363154
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1841487962
Short name T523
Test name
Test status
Simulation time 46952907 ps
CPU time 0.57 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 12:28:49 PM PST 23
Peak memory 193952 kb
Host smart-de70f271-be4c-4124-9f25-f25b58e713f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841487962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1841487962
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3327560595
Short name T538
Test name
Test status
Simulation time 1338818810 ps
CPU time 9.52 seconds
Started Dec 31 12:26:53 PM PST 23
Finished Dec 31 12:27:05 PM PST 23
Peak memory 198620 kb
Host smart-ab045186-aca5-4bd7-b899-88fe87cec755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327560595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3327560595
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.392793983
Short name T393
Test name
Test status
Simulation time 1073900292 ps
CPU time 47.5 seconds
Started Dec 31 12:26:04 PM PST 23
Finished Dec 31 12:26:57 PM PST 23
Peak memory 198552 kb
Host smart-75abc039-a904-4649-ac39-2314e8bdd474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392793983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.392793983
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2953260440
Short name T302
Test name
Test status
Simulation time 9280115999 ps
CPU time 66.3 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:28:34 PM PST 23
Peak memory 198668 kb
Host smart-2d74b3c5-90f9-4b2f-96a1-b1c43dd90b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953260440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2953260440
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.626435188
Short name T676
Test name
Test status
Simulation time 2608591516 ps
CPU time 29.44 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:58 PM PST 23
Peak memory 198572 kb
Host smart-66232ae5-e2eb-47b7-8c4f-17312e9da0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626435188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.626435188
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4149401244
Short name T296
Test name
Test status
Simulation time 11375492934 ps
CPU time 69.61 seconds
Started Dec 31 12:27:43 PM PST 23
Finished Dec 31 12:28:54 PM PST 23
Peak memory 198716 kb
Host smart-1de7c435-b812-44e8-aba7-de671a7d6cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149401244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4149401244
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2384449051
Short name T482
Test name
Test status
Simulation time 122585032 ps
CPU time 2.88 seconds
Started Dec 31 12:23:37 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 198268 kb
Host smart-545493e8-afd9-47dc-9cb0-19d68b32a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384449051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2384449051
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2825911890
Short name T394
Test name
Test status
Simulation time 938364286450 ps
CPU time 922.63 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:42:29 PM PST 23
Peak memory 215012 kb
Host smart-d87038fa-12f7-4293-a63e-467c57cdde4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825911890 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2825911890
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3803625104
Short name T553
Test name
Test status
Simulation time 1124266034619 ps
CPU time 1571.15 seconds
Started Dec 31 12:27:23 PM PST 23
Finished Dec 31 12:53:35 PM PST 23
Peak memory 238668 kb
Host smart-412c2b48-6811-44ef-88d9-1990c895b968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803625104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3803625104
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3483471265
Short name T761
Test name
Test status
Simulation time 27093715 ps
CPU time 0.93 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 196284 kb
Host smart-58ff5e8b-f68b-4e6e-9bd7-5a36c3e79556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483471265 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3483471265
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1516599552
Short name T805
Test name
Test status
Simulation time 7207720784 ps
CPU time 346.65 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:33:19 PM PST 23
Peak memory 198680 kb
Host smart-0a67ceaa-f9ec-47cc-85b3-7810e857e5e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516599552 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.1516599552
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2552399391
Short name T759
Test name
Test status
Simulation time 20112057372 ps
CPU time 69.46 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:27:58 PM PST 23
Peak memory 198680 kb
Host smart-c922692f-ca35-47b3-9aa7-15a0439064c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552399391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2552399391
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1897464627
Short name T727
Test name
Test status
Simulation time 440035890468 ps
CPU time 722.58 seconds
Started Dec 31 12:28:47 PM PST 23
Finished Dec 31 12:40:55 PM PST 23
Peak memory 231584 kb
Host smart-42a6ce1e-1670-4aee-901e-54ff251c3fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897464627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1897464627
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.2452250105
Short name T259
Test name
Test status
Simulation time 52330503906 ps
CPU time 1652.81 seconds
Started Dec 31 12:27:24 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 239580 kb
Host smart-69761946-e5f4-40b7-9665-30bb2c9cb0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452250105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.2452250105
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.3649287807
Short name T145
Test name
Test status
Simulation time 107907522530 ps
CPU time 2215.5 seconds
Started Dec 31 12:27:21 PM PST 23
Finished Dec 31 01:04:18 PM PST 23
Peak memory 245968 kb
Host smart-b93ff89a-db16-4658-a3eb-a1041a2cf03a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649287807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.3649287807
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3174558456
Short name T797
Test name
Test status
Simulation time 144640987513 ps
CPU time 2050.86 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 01:01:47 PM PST 23
Peak memory 253056 kb
Host smart-16b59546-8314-4307-89b8-5cf6f82357f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174558456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.3174558456
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.4104386969
Short name T602
Test name
Test status
Simulation time 247480262046 ps
CPU time 930.65 seconds
Started Dec 31 12:28:35 PM PST 23
Finished Dec 31 12:44:12 PM PST 23
Peak memory 215104 kb
Host smart-f3f4b5a4-49a4-4911-8bd8-43050c9f7909
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104386969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.4104386969
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.302747042
Short name T798
Test name
Test status
Simulation time 17624732219 ps
CPU time 206.72 seconds
Started Dec 31 12:28:58 PM PST 23
Finished Dec 31 12:32:29 PM PST 23
Peak memory 198788 kb
Host smart-72346242-28b5-4e7a-9f44-66eac6247f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302747042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.302747042
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3213630847
Short name T833
Test name
Test status
Simulation time 55079183008 ps
CPU time 359.24 seconds
Started Dec 31 12:27:54 PM PST 23
Finished Dec 31 12:34:01 PM PST 23
Peak memory 227572 kb
Host smart-5f941c16-4ac2-467c-8ddc-744e994c6f13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213630847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.3213630847
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.1565419444
Short name T137
Test name
Test status
Simulation time 152656908334 ps
CPU time 3066.95 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 01:19:56 PM PST 23
Peak memory 223360 kb
Host smart-e90d5925-bd17-4574-b2c2-9247c4fcc1d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565419444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.1565419444
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.262573448
Short name T801
Test name
Test status
Simulation time 288974375599 ps
CPU time 1044.15 seconds
Started Dec 31 12:27:30 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 258316 kb
Host smart-a8c823d3-cf6a-401b-9785-fe7e01fa63bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262573448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.262573448
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.1063312732
Short name T136
Test name
Test status
Simulation time 52744057224 ps
CPU time 1458.51 seconds
Started Dec 31 12:27:13 PM PST 23
Finished Dec 31 12:51:35 PM PST 23
Peak memory 247044 kb
Host smart-a56e24f6-c452-4b44-890f-bc9681e8343c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063312732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.1063312732
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4286381325
Short name T545
Test name
Test status
Simulation time 34981453 ps
CPU time 0.55 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:20 PM PST 23
Peak memory 192980 kb
Host smart-21126288-e977-406f-9ab0-157d1252f344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286381325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4286381325
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.383036739
Short name T601
Test name
Test status
Simulation time 469947415 ps
CPU time 7.2 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:54 PM PST 23
Peak memory 206796 kb
Host smart-2451bffa-ab4f-40a4-81b9-7dc5a469a860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383036739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.383036739
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4166012633
Short name T802
Test name
Test status
Simulation time 1868244603 ps
CPU time 40.58 seconds
Started Dec 31 12:27:03 PM PST 23
Finished Dec 31 12:27:46 PM PST 23
Peak memory 198480 kb
Host smart-b43c6d85-095e-46c6-8da3-02e430d4cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166012633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4166012633
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2012749110
Short name T834
Test name
Test status
Simulation time 2426506198 ps
CPU time 63.33 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:27:00 PM PST 23
Peak memory 198564 kb
Host smart-d6335b03-2f8f-4a40-81f9-4990d41211f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012749110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2012749110
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1087370693
Short name T844
Test name
Test status
Simulation time 5530199952 ps
CPU time 45.35 seconds
Started Dec 31 12:26:32 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 198724 kb
Host smart-e4133b32-12cf-457e-8ea9-591b34f62f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087370693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1087370693
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.547432185
Short name T389
Test name
Test status
Simulation time 947159769 ps
CPU time 23.19 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 198584 kb
Host smart-caf0de07-f2ec-444c-b6b0-1a6dd2ac251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547432185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.547432185
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3472020954
Short name T345
Test name
Test status
Simulation time 659836347 ps
CPU time 2.11 seconds
Started Dec 31 12:28:41 PM PST 23
Finished Dec 31 12:28:51 PM PST 23
Peak memory 197756 kb
Host smart-4ccb802c-12af-43b7-b73e-d5ac83448c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472020954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3472020954
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3093145121
Short name T130
Test name
Test status
Simulation time 174387079090 ps
CPU time 1341.05 seconds
Started Dec 31 12:26:35 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 215112 kb
Host smart-a4df2071-580d-4ca9-9ed7-aefeda07e288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093145121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3093145121
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.572739329
Short name T135
Test name
Test status
Simulation time 59262541858 ps
CPU time 1106.63 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 12:45:43 PM PST 23
Peak memory 247312 kb
Host smart-3ab94a8c-3fc6-4223-97da-91391d60a20a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572739329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.572739329
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.119307630
Short name T692
Test name
Test status
Simulation time 50758387 ps
CPU time 0.9 seconds
Started Dec 31 12:25:56 PM PST 23
Finished Dec 31 12:26:04 PM PST 23
Peak memory 195704 kb
Host smart-2c90aadd-0b8c-47f9-adab-61bb773a941c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119307630 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.119307630
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3280575274
Short name T551
Test name
Test status
Simulation time 43318414045 ps
CPU time 494.2 seconds
Started Dec 31 12:27:30 PM PST 23
Finished Dec 31 12:35:46 PM PST 23
Peak memory 199048 kb
Host smart-f3fec237-5b3d-426d-8298-92188c3da07e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280575274 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3280575274
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.13696932
Short name T230
Test name
Test status
Simulation time 1436969636 ps
CPU time 46.14 seconds
Started Dec 31 12:25:42 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 198532 kb
Host smart-d74172fc-08d0-439b-870c-9eee32f80a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13696932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.13696932
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1435693376
Short name T648
Test name
Test status
Simulation time 123908013641 ps
CPU time 1171.45 seconds
Started Dec 31 12:29:15 PM PST 23
Finished Dec 31 12:48:51 PM PST 23
Peak memory 247336 kb
Host smart-0944492d-9aed-4d98-a1af-3fc4fb51b8ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435693376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.1435693376
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.1517171248
Short name T732
Test name
Test status
Simulation time 80752775124 ps
CPU time 1296.34 seconds
Started Dec 31 12:28:14 PM PST 23
Finished Dec 31 12:49:51 PM PST 23
Peak memory 241880 kb
Host smart-36eb2c8e-536a-4bb8-993d-821c12ed7c55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517171248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.1517171248
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.3377156848
Short name T144
Test name
Test status
Simulation time 517562316166 ps
CPU time 2300.41 seconds
Started Dec 31 12:27:16 PM PST 23
Finished Dec 31 01:05:38 PM PST 23
Peak memory 262776 kb
Host smart-ffd06551-5135-4c15-ba89-51593c26b6d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377156848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.3377156848
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3135157284
Short name T366
Test name
Test status
Simulation time 77979646412 ps
CPU time 421.55 seconds
Started Dec 31 12:27:45 PM PST 23
Finished Dec 31 12:34:48 PM PST 23
Peak memory 231156 kb
Host smart-c4611ace-ea9b-470f-a0e1-25fb435e69e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135157284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.3135157284
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2098563355
Short name T812
Test name
Test status
Simulation time 330174452438 ps
CPU time 1228.66 seconds
Started Dec 31 12:27:52 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 215164 kb
Host smart-3a19093f-ce79-491e-bd0c-4f1c5892d9f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098563355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2098563355
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.2653073711
Short name T580
Test name
Test status
Simulation time 177263829136 ps
CPU time 1972.17 seconds
Started Dec 31 12:28:29 PM PST 23
Finished Dec 31 01:01:31 PM PST 23
Peak memory 246976 kb
Host smart-91e433cb-fdec-4c8f-9e9c-a5afe580ddbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653073711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.2653073711
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.533643650
Short name T597
Test name
Test status
Simulation time 125553878139 ps
CPU time 1641.24 seconds
Started Dec 31 12:28:38 PM PST 23
Finished Dec 31 12:56:08 PM PST 23
Peak memory 253040 kb
Host smart-21be105c-5e3a-4931-86a7-041183cd072a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533643650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.533643650
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.746261282
Short name T291
Test name
Test status
Simulation time 10537994224 ps
CPU time 144.1 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:30:06 PM PST 23
Peak memory 213856 kb
Host smart-8eaaf2e2-f763-4b5a-9455-719b2cff3876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746261282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.746261282
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.1282413989
Short name T31
Test name
Test status
Simulation time 292555711344 ps
CPU time 406.12 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 12:34:28 PM PST 23
Peak memory 244952 kb
Host smart-104ee309-fadf-4f36-8db4-52d8ac0f5ffd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282413989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.1282413989
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.1288532813
Short name T562
Test name
Test status
Simulation time 165285684308 ps
CPU time 1943.17 seconds
Started Dec 31 12:28:17 PM PST 23
Finished Dec 31 01:00:42 PM PST 23
Peak memory 239764 kb
Host smart-cfbfcdcb-8aa1-45ba-b75c-a00b5feaa4e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288532813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.1288532813
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4132686309
Short name T273
Test name
Test status
Simulation time 12623288 ps
CPU time 0.55 seconds
Started Dec 31 12:26:06 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 193920 kb
Host smart-94233848-a3f1-4309-8ecd-4393ddffc84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132686309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4132686309
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2330895
Short name T337
Test name
Test status
Simulation time 1219749598 ps
CPU time 36.75 seconds
Started Dec 31 12:27:19 PM PST 23
Finished Dec 31 12:27:57 PM PST 23
Peak memory 218608 kb
Host smart-9727e745-b350-4e49-8e98-d8ad36daf39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2330895
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4230256636
Short name T765
Test name
Test status
Simulation time 1534467446 ps
CPU time 22.23 seconds
Started Dec 31 12:27:31 PM PST 23
Finished Dec 31 12:27:54 PM PST 23
Peak memory 198556 kb
Host smart-2d25ee4a-a77f-43ae-b1bb-2b102685ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230256636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4230256636
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.489639218
Short name T733
Test name
Test status
Simulation time 1807595578 ps
CPU time 41.89 seconds
Started Dec 31 12:27:49 PM PST 23
Finished Dec 31 12:28:33 PM PST 23
Peak memory 198484 kb
Host smart-369f549b-63d2-4047-bce5-761737fdbe9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489639218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.489639218
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2125034461
Short name T515
Test name
Test status
Simulation time 51308566643 ps
CPU time 132.6 seconds
Started Dec 31 12:29:28 PM PST 23
Finished Dec 31 12:31:44 PM PST 23
Peak memory 198624 kb
Host smart-0715d0b8-3a37-450b-b32f-d2d49aaf9c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125034461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2125034461
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2638998349
Short name T441
Test name
Test status
Simulation time 12276444785 ps
CPU time 23.85 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:59 PM PST 23
Peak memory 198720 kb
Host smart-4afb4b7b-e333-4ec4-b253-3683c91ae02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638998349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2638998349
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.551220511
Short name T271
Test name
Test status
Simulation time 117703313 ps
CPU time 2.61 seconds
Started Dec 31 12:27:22 PM PST 23
Finished Dec 31 12:27:26 PM PST 23
Peak memory 198444 kb
Host smart-5f71de52-b63b-4194-9723-26d4d98ea513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551220511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.551220511
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.861990147
Short name T625
Test name
Test status
Simulation time 25155845238 ps
CPU time 696.93 seconds
Started Dec 31 12:27:08 PM PST 23
Finished Dec 31 12:38:46 PM PST 23
Peak memory 198728 kb
Host smart-0ddd0523-c412-47c4-a0a2-b238bd71bb97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861990147 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.861990147
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2531193152
Short name T96
Test name
Test status
Simulation time 364070521591 ps
CPU time 1626.88 seconds
Started Dec 31 12:27:56 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 242880 kb
Host smart-d107bcea-c9dc-48a3-bf37-c969bd9174ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531193152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2531193152
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2430236809
Short name T214
Test name
Test status
Simulation time 45943493 ps
CPU time 0.84 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:26:43 PM PST 23
Peak memory 195624 kb
Host smart-00b0200e-a644-44a2-9f1e-56d166c4439e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430236809 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2430236809
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.595219752
Short name T558
Test name
Test status
Simulation time 180868808536 ps
CPU time 434.46 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:34:30 PM PST 23
Peak memory 198680 kb
Host smart-1d41eb22-5eb1-4229-a1c4-320d267a26ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595219752 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.595219752
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1930653690
Short name T347
Test name
Test status
Simulation time 1347750687 ps
CPU time 24.57 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:39 PM PST 23
Peak memory 198580 kb
Host smart-b5db1aa3-bed4-4c9e-8ca0-f0e0ea73d42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930653690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1930653690
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2217841350
Short name T379
Test name
Test status
Simulation time 58784941939 ps
CPU time 720.6 seconds
Started Dec 31 12:27:23 PM PST 23
Finished Dec 31 12:39:24 PM PST 23
Peak memory 215096 kb
Host smart-426043f6-bd2e-46b0-9169-9cd9a87dd752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217841350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2217841350
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.238594923
Short name T260
Test name
Test status
Simulation time 51668096845 ps
CPU time 736.8 seconds
Started Dec 31 12:27:47 PM PST 23
Finished Dec 31 12:40:05 PM PST 23
Peak memory 215176 kb
Host smart-e1dd8839-f5c0-4c86-b076-9aefe33d17cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238594923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.238594923
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.660470726
Short name T120
Test name
Test status
Simulation time 23338303859 ps
CPU time 1150.54 seconds
Started Dec 31 12:27:21 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 240396 kb
Host smart-d5fcebba-d51a-4b74-a1c1-96e6d15d33a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660470726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.660470726
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.4199464178
Short name T559
Test name
Test status
Simulation time 79853832506 ps
CPU time 3402.05 seconds
Started Dec 31 12:27:41 PM PST 23
Finished Dec 31 01:24:24 PM PST 23
Peak memory 260436 kb
Host smart-b9c90716-b333-4738-92b4-6f3e337b1369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199464178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.4199464178
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.314951323
Short name T649
Test name
Test status
Simulation time 97529405343 ps
CPU time 1606.45 seconds
Started Dec 31 12:28:55 PM PST 23
Finished Dec 31 12:55:46 PM PST 23
Peak memory 256056 kb
Host smart-8d2176ef-c9c1-4d90-a9d6-8ee81d4462d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314951323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.314951323
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.3792964989
Short name T751
Test name
Test status
Simulation time 25769303473 ps
CPU time 382.78 seconds
Started Dec 31 12:28:27 PM PST 23
Finished Dec 31 12:34:55 PM PST 23
Peak memory 231552 kb
Host smart-d6654365-fe5e-40c1-adfb-306f285798d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792964989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.3792964989
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.2015281448
Short name T853
Test name
Test status
Simulation time 339441288943 ps
CPU time 3017.34 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 01:18:27 PM PST 23
Peak memory 226304 kb
Host smart-c96475c2-a808-4c77-9fc0-dc287dadda07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015281448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.2015281448
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3355554832
Short name T301
Test name
Test status
Simulation time 113267545825 ps
CPU time 595.16 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:38:03 PM PST 23
Peak memory 210200 kb
Host smart-4437a736-54bc-4dc8-b381-71a1f1b59ebf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355554832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3355554832
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.865687577
Short name T447
Test name
Test status
Simulation time 11160326912 ps
CPU time 216.6 seconds
Started Dec 31 12:28:00 PM PST 23
Finished Dec 31 12:31:43 PM PST 23
Peak memory 214428 kb
Host smart-e1b9e051-5147-4d7c-9d23-9e3fbe1e7616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865687577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.865687577
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.2865983280
Short name T255
Test name
Test status
Simulation time 40447363085 ps
CPU time 1096.68 seconds
Started Dec 31 12:28:44 PM PST 23
Finished Dec 31 12:47:07 PM PST 23
Peak memory 255644 kb
Host smart-841db066-799b-497f-8080-0a53032ba9dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865983280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.2865983280
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.337857135
Short name T633
Test name
Test status
Simulation time 15938057 ps
CPU time 0.57 seconds
Started Dec 31 12:26:50 PM PST 23
Finished Dec 31 12:26:52 PM PST 23
Peak memory 192940 kb
Host smart-732e30f9-f443-496d-82c4-ce6157fb0b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337857135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.337857135
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3289773746
Short name T244
Test name
Test status
Simulation time 2094790373 ps
CPU time 28.63 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:37 PM PST 23
Peak memory 206712 kb
Host smart-ce98d33e-587c-4e15-af30-2cb4cea1429d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289773746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3289773746
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1838200920
Short name T852
Test name
Test status
Simulation time 246096226 ps
CPU time 8.24 seconds
Started Dec 31 12:27:01 PM PST 23
Finished Dec 31 12:27:12 PM PST 23
Peak memory 198548 kb
Host smart-e3553fdb-9c65-4ca8-b6a6-6c21babca3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838200920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1838200920
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.19849803
Short name T567
Test name
Test status
Simulation time 1610187408 ps
CPU time 79.04 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 198492 kb
Host smart-52632b41-08b6-4853-9de8-bba9d5e9e3dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19849803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.19849803
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2165912743
Short name T641
Test name
Test status
Simulation time 7008505244 ps
CPU time 53.88 seconds
Started Dec 31 12:26:40 PM PST 23
Finished Dec 31 12:27:35 PM PST 23
Peak memory 198736 kb
Host smart-653a7ce9-0179-4e48-b2b4-4029657b82c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165912743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2165912743
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1061249371
Short name T813
Test name
Test status
Simulation time 1655976736 ps
CPU time 80.62 seconds
Started Dec 31 12:27:24 PM PST 23
Finished Dec 31 12:28:45 PM PST 23
Peak memory 198572 kb
Host smart-d6fc3c41-cab0-4f99-89f2-80b2846a04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061249371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1061249371
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2690389239
Short name T712
Test name
Test status
Simulation time 836316733 ps
CPU time 2.42 seconds
Started Dec 31 12:27:15 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 197848 kb
Host smart-14a4f104-104b-4bd9-8ce3-9d7abedd72c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690389239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2690389239
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.577421526
Short name T465
Test name
Test status
Simulation time 171553413950 ps
CPU time 2074.7 seconds
Started Dec 31 12:27:31 PM PST 23
Finished Dec 31 01:02:07 PM PST 23
Peak memory 214984 kb
Host smart-6cfc7e81-e41b-4121-b5c1-4165d4e6bc39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577421526 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.577421526
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1747524232
Short name T397
Test name
Test status
Simulation time 270301688514 ps
CPU time 313.53 seconds
Started Dec 31 12:26:15 PM PST 23
Finished Dec 31 12:31:31 PM PST 23
Peak memory 223352 kb
Host smart-cd1ebccc-0635-440c-adac-a862b5330837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747524232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1747524232
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2146465200
Short name T701
Test name
Test status
Simulation time 109124883 ps
CPU time 1.03 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:31 PM PST 23
Peak memory 197888 kb
Host smart-a16a45f2-1c81-46e8-8724-70db289bfbda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146465200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2146465200
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1750825696
Short name T370
Test name
Test status
Simulation time 17279797294 ps
CPU time 403.11 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:33:31 PM PST 23
Peak memory 198624 kb
Host smart-795a75d5-97bf-4d5c-b9e3-0af3777b5c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750825696 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.1750825696
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1624828103
Short name T752
Test name
Test status
Simulation time 16078328 ps
CPU time 0.61 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:42 PM PST 23
Peak memory 193160 kb
Host smart-560a3f4a-06ea-4c8f-b4c7-5322c205bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624828103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1624828103
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1846799363
Short name T133
Test name
Test status
Simulation time 60361107423 ps
CPU time 1802.87 seconds
Started Dec 31 12:27:44 PM PST 23
Finished Dec 31 12:57:50 PM PST 23
Peak memory 255688 kb
Host smart-105c53eb-40e4-4aef-b9f5-bb1ef86ba6b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846799363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.1846799363
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.2889358265
Short name T428
Test name
Test status
Simulation time 44974275759 ps
CPU time 652.59 seconds
Started Dec 31 12:27:52 PM PST 23
Finished Dec 31 12:38:52 PM PST 23
Peak memory 208080 kb
Host smart-98662c29-0678-48a2-a6c7-d3cde1a65357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889358265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.2889358265
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.1296486959
Short name T466
Test name
Test status
Simulation time 65092250509 ps
CPU time 1121.34 seconds
Started Dec 31 12:29:58 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 233436 kb
Host smart-ea99549e-1158-4beb-ab5b-c05d87a014de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296486959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.1296486959
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2862297917
Short name T323
Test name
Test status
Simulation time 47626292208 ps
CPU time 675.54 seconds
Started Dec 31 12:29:51 PM PST 23
Finished Dec 31 12:41:08 PM PST 23
Peak memory 223220 kb
Host smart-961d2d01-354a-4cf3-b1c9-0b594eb0a03c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862297917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.2862297917
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1202144657
Short name T402
Test name
Test status
Simulation time 107443659998 ps
CPU time 430.35 seconds
Started Dec 31 12:28:34 PM PST 23
Finished Dec 31 12:35:51 PM PST 23
Peak memory 224396 kb
Host smart-2b1e4c60-1f6b-4bcf-a96e-4479322b308f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202144657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.1202144657
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2068767770
Short name T557
Test name
Test status
Simulation time 413285758313 ps
CPU time 1419.34 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:51:27 PM PST 23
Peak memory 223280 kb
Host smart-8d2f61cf-12cf-46b1-aeb6-123f04633643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068767770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.2068767770
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.2293209293
Short name T105
Test name
Test status
Simulation time 61442532987 ps
CPU time 1088.88 seconds
Started Dec 31 12:28:38 PM PST 23
Finished Dec 31 12:46:56 PM PST 23
Peak memory 227924 kb
Host smart-2a8d1016-c319-4aaa-a55c-fcad83e2a214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293209293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.2293209293
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1198553039
Short name T486
Test name
Test status
Simulation time 15954392465 ps
CPU time 236.44 seconds
Started Dec 31 12:27:46 PM PST 23
Finished Dec 31 12:31:44 PM PST 23
Peak memory 207120 kb
Host smart-fa5f075f-4c47-490f-9f31-64d0e0065308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198553039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.1198553039
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.2522090978
Short name T36
Test name
Test status
Simulation time 158761502122 ps
CPU time 1837.35 seconds
Started Dec 31 12:30:20 PM PST 23
Finished Dec 31 01:01:03 PM PST 23
Peak memory 255068 kb
Host smart-3555206d-85c3-4c10-9753-fe9204c569e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522090978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.2522090978
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.275987054
Short name T242
Test name
Test status
Simulation time 142263568146 ps
CPU time 1530.91 seconds
Started Dec 31 12:28:21 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 243876 kb
Host smart-66183dd1-30bf-47ca-807c-a4438de2c43a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275987054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.275987054
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3793727759
Short name T446
Test name
Test status
Simulation time 53192772 ps
CPU time 0.53 seconds
Started Dec 31 12:27:48 PM PST 23
Finished Dec 31 12:27:50 PM PST 23
Peak memory 192832 kb
Host smart-fef0d957-cd2f-47d4-8c91-f542db6a899a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793727759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3793727759
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1617872610
Short name T696
Test name
Test status
Simulation time 2517652993 ps
CPU time 20.7 seconds
Started Dec 31 12:26:26 PM PST 23
Finished Dec 31 12:26:48 PM PST 23
Peak memory 211044 kb
Host smart-c38c3edb-ceaf-4aa4-b4da-938c078505b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617872610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1617872610
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3766849734
Short name T369
Test name
Test status
Simulation time 1252970224 ps
CPU time 53.74 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:28:00 PM PST 23
Peak memory 198504 kb
Host smart-6ff2f28d-727d-4efd-8715-02e1034dae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766849734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3766849734
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.204765920
Short name T749
Test name
Test status
Simulation time 1973754630 ps
CPU time 91.4 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:28:17 PM PST 23
Peak memory 198556 kb
Host smart-bc1e441d-2d37-4e93-bd2d-d1d9b5366f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204765920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.204765920
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1026053708
Short name T12
Test name
Test status
Simulation time 30781573277 ps
CPU time 66.1 seconds
Started Dec 31 12:27:55 PM PST 23
Finished Dec 31 12:29:08 PM PST 23
Peak memory 198648 kb
Host smart-0fea7bb1-603e-47ae-8b3d-a63266be9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026053708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1026053708
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.4034091990
Short name T748
Test name
Test status
Simulation time 11385931101 ps
CPU time 53.2 seconds
Started Dec 31 12:26:48 PM PST 23
Finished Dec 31 12:27:43 PM PST 23
Peak memory 198640 kb
Host smart-d502545b-03d3-48b1-9627-3af3b859e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034091990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.4034091990
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2532568021
Short name T621
Test name
Test status
Simulation time 520475374 ps
CPU time 1.27 seconds
Started Dec 31 12:26:44 PM PST 23
Finished Dec 31 12:26:47 PM PST 23
Peak memory 198104 kb
Host smart-ab866750-2f61-4574-baee-742635986a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532568021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2532568021
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1542567364
Short name T693
Test name
Test status
Simulation time 15978890333 ps
CPU time 532.32 seconds
Started Dec 31 12:28:04 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 198756 kb
Host smart-d69c81f4-400d-4e87-953a-33f87ac634f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542567364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1542567364
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.566958483
Short name T687
Test name
Test status
Simulation time 511151241698 ps
CPU time 2347.96 seconds
Started Dec 31 12:27:56 PM PST 23
Finished Dec 31 01:07:10 PM PST 23
Peak memory 242108 kb
Host smart-f49b7ac7-0fe8-4c07-a41f-7d36e616277e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566958483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.566958483
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2007359708
Short name T591
Test name
Test status
Simulation time 164173578 ps
CPU time 0.95 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 12:27:10 PM PST 23
Peak memory 196584 kb
Host smart-36b9416d-9261-4617-aba3-fc7630b9b402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007359708 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2007359708
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3425792199
Short name T424
Test name
Test status
Simulation time 4252474662 ps
CPU time 40.24 seconds
Started Dec 31 12:27:07 PM PST 23
Finished Dec 31 12:27:49 PM PST 23
Peak memory 198708 kb
Host smart-83f6b518-3152-4c66-b87d-83b24a80534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425792199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3425792199
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2500060201
Short name T417
Test name
Test status
Simulation time 15079769802 ps
CPU time 223.34 seconds
Started Dec 31 12:27:30 PM PST 23
Finished Dec 31 12:31:15 PM PST 23
Peak memory 215208 kb
Host smart-6e836bc2-6194-4ee8-baba-29f51574dc33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500060201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.2500060201
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3275656842
Short name T826
Test name
Test status
Simulation time 91727716087 ps
CPU time 868.37 seconds
Started Dec 31 12:28:05 PM PST 23
Finished Dec 31 12:42:37 PM PST 23
Peak memory 245748 kb
Host smart-6837579c-00d5-469a-9433-54d29853f328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275656842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.3275656842
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1471867952
Short name T578
Test name
Test status
Simulation time 44042482932 ps
CPU time 683.22 seconds
Started Dec 31 12:29:45 PM PST 23
Finished Dec 31 12:41:11 PM PST 23
Peak memory 242260 kb
Host smart-681d6786-dad5-496e-89e4-e8ba211d6bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471867952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.1471867952
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1738967549
Short name T517
Test name
Test status
Simulation time 292395797381 ps
CPU time 1915.08 seconds
Started Dec 31 12:28:01 PM PST 23
Finished Dec 31 01:00:02 PM PST 23
Peak memory 251032 kb
Host smart-18c80fc6-2018-4964-8aec-fe150bcea100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738967549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.1738967549
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3952983782
Short name T361
Test name
Test status
Simulation time 77362351695 ps
CPU time 283.49 seconds
Started Dec 31 12:27:12 PM PST 23
Finished Dec 31 12:31:57 PM PST 23
Peak memory 214360 kb
Host smart-47c0e797-54e3-4621-ae0e-f331cdf0f19f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952983782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3952983782
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2192611333
Short name T705
Test name
Test status
Simulation time 106200561181 ps
CPU time 1934.03 seconds
Started Dec 31 12:28:19 PM PST 23
Finished Dec 31 01:00:35 PM PST 23
Peak memory 256160 kb
Host smart-0493c40a-4415-4b7c-8977-9b1ed5740145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192611333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.2192611333
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.2036521877
Short name T338
Test name
Test status
Simulation time 124962712113 ps
CPU time 1500.73 seconds
Started Dec 31 12:27:53 PM PST 23
Finished Dec 31 12:53:00 PM PST 23
Peak memory 222660 kb
Host smart-8baab623-cac2-4954-ac9f-1209ae7f20bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036521877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.2036521877
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.4294061802
Short name T862
Test name
Test status
Simulation time 134307215606 ps
CPU time 3174.53 seconds
Started Dec 31 12:27:25 PM PST 23
Finished Dec 31 01:20:21 PM PST 23
Peak memory 240612 kb
Host smart-ffeade5a-767b-45db-bbc5-5200134a6a2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294061802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.4294061802
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.931566348
Short name T632
Test name
Test status
Simulation time 206429987556 ps
CPU time 1016.56 seconds
Started Dec 31 12:28:16 PM PST 23
Finished Dec 31 12:45:14 PM PST 23
Peak memory 256100 kb
Host smart-5ab92d64-33f9-4c67-8f61-4559fb346e1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931566348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.931566348
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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