Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	44419039	1			T17	8		T18	1		T21	5
all_values[1]	44419039	1			T17	8		T18	1		T21	5
all_values[2]	44419039	1			T17	8		T18	1		T21	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141797

1

T17

10

T18

3

T21

12

auto[1]

133115320

1

T17

14

T21

3

T24

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96641180

1

T17

9

T18

3

T21

9

auto[1]

36615937

1

T17

15

T21

6

T24

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	51474	1			T17	3		T18	1		T21	3
all_values[0]	auto[0]	auto[1]	1349	1			T17	3		T21	2		T24	1
all_values[0]	auto[1]	auto[0]	44187854	1			T24	6		T48	4		T47	2
all_values[0]	auto[1]	auto[1]	178362	1			T17	2		T24	2		T47	3
all_values[1]	auto[0]	auto[0]	21759	1			T17	2		T18	1		T21	2
all_values[1]	auto[0]	auto[1]	17215	1			T21	3		T24	2		T47	4
all_values[1]	auto[1]	auto[0]	25264549	1			T17	3		T24	2		T48	1
all_values[1]	auto[1]	auto[1]	19115516	1			T17	3		T24	5		T48	2
all_values[2]	auto[0]	auto[0]	34604	1			T18	1		T21	1		T22	1
all_values[2]	auto[0]	auto[1]	15396	1			T17	2		T21	1		T24	3
all_values[2]	auto[1]	auto[0]	27080940	1			T17	1		T21	3		T24	2
all_values[2]	auto[1]	auto[1]	17288099	1			T17	5		T24	4		T47	1