Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.58 100.00 100.00 99.76 99.49 100.00


Total tests in report: 909
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
49.77 49.77 39.53 39.53 32.90 32.90 56.78 56.78 100.00 100.00 25.41 25.41 80.30 80.30 13.48 13.48 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4101296332
85.01 35.24 97.67 58.13 79.67 46.78 61.31 4.52 100.00 0.00 94.35 68.94 94.70 14.39 67.40 53.92 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2927467392
94.76 9.75 98.29 0.62 92.68 13.01 98.74 37.44 100.00 0.00 97.18 2.82 95.96 1.26 80.47 13.07 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4075291577
96.77 2.01 99.07 0.78 95.41 2.73 99.50 0.75 100.00 0.00 98.59 1.41 95.96 0.00 88.86 8.39 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3281433252
97.60 0.83 99.46 0.39 97.70 2.30 99.50 0.00 100.00 0.00 99.06 0.47 96.72 0.76 90.78 1.93 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.278979652
98.11 0.51 99.46 0.00 97.70 0.00 99.50 0.00 100.00 0.00 99.06 0.00 96.72 0.00 94.36 3.58 /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.1965556465
98.33 0.22 99.46 0.00 97.70 0.00 99.50 0.00 100.00 0.00 99.06 0.00 98.23 1.52 94.36 0.00 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.435887710
98.54 0.21 99.46 0.00 97.92 0.22 100.00 0.50 100.00 0.00 99.29 0.24 98.48 0.25 94.64 0.28 /workspace/coverage/default/3.hmac_sec_cm.31343679
98.70 0.16 99.46 0.00 97.92 0.00 100.00 0.00 100.00 0.00 99.29 0.00 98.48 0.00 95.74 1.10 /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.3411557185
98.80 0.10 99.46 0.00 97.92 0.00 100.00 0.00 100.00 0.00 99.29 0.00 98.48 0.00 96.42 0.69 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.791966501
98.90 0.10 99.46 0.00 97.92 0.00 100.00 0.00 100.00 0.00 99.29 0.00 98.48 0.00 97.11 0.69 /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.3258429706
98.99 0.09 99.53 0.08 98.03 0.11 100.00 0.00 100.00 0.00 99.76 0.47 98.48 0.00 97.11 0.00 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1871687363
99.07 0.08 99.53 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 97.66 0.55 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2183028569
99.15 0.08 99.53 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 98.21 0.55 /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.338278856
99.23 0.08 99.53 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 98.76 0.55 /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.3925931930
99.28 0.06 99.53 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.41 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3687526849
99.32 0.04 99.53 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.28 /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2192959807
99.35 0.03 99.53 0.00 98.25 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.00 /workspace/coverage/default/11.hmac_alert_test.2567072095
99.39 0.03 99.53 0.00 98.47 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.00 /workspace/coverage/default/12.hmac_error.1646105690
99.41 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2191785910
99.43 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.2030455830
99.45 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3669942024
99.46 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 100.00 0.14 /workspace/coverage/default/37.hmac_wipe_secret.344699886
99.48 0.02 99.53 0.00 98.58 0.11 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 100.00 0.00 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3305295438

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2690400523
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.289191742
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.485687428
/workspace/coverage/cover_reg_top/0.hmac_intr_test.4044491472
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.3632311794
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2107059410
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.984998926
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1498934025
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.98254109
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.2100540625
/workspace/coverage/cover_reg_top/1.hmac_intr_test.2856963267
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1436801210
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.988448951
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.199985167
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3356618049
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.669996652
/workspace/coverage/cover_reg_top/10.hmac_intr_test.2145208402
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1045769114
/workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3838612840
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.95256650
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.1898121478
/workspace/coverage/cover_reg_top/11.hmac_intr_test.459959110
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4138241066
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.2482346748
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1045159198
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.285237547
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.2493858461
/workspace/coverage/cover_reg_top/12.hmac_intr_test.1517652644
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2717784251
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.1612002113
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.207777354
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.1821376140
/workspace/coverage/cover_reg_top/13.hmac_intr_test.1726716578
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1799575612
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.3289388112
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3474684738
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.863408399
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.574540687
/workspace/coverage/cover_reg_top/14.hmac_intr_test.399638633
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.736357588
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.2480017833
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2189986578
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.222379045
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.2142626883
/workspace/coverage/cover_reg_top/15.hmac_intr_test.790583747
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2573126748
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.3988842808
/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4244093128
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3448842041
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.4036486983
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3959009478
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.582270486
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.445338388
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3471254304
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1797004361
/workspace/coverage/cover_reg_top/17.hmac_intr_test.2189957379
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3908019205
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.3514203205
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2155894930
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2608777759
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.59584000
/workspace/coverage/cover_reg_top/18.hmac_intr_test.3677146595
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455645897
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.4206744505
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2314580681
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3221823688
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.2909424295
/workspace/coverage/cover_reg_top/19.hmac_intr_test.1985287345
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1737080321
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.123043730
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3614791641
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1985210758
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3864014909
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.226536638
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.592464307
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.1279056817
/workspace/coverage/cover_reg_top/2.hmac_intr_test.2390547570
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1053067414
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.3234127550
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1187537839
/workspace/coverage/cover_reg_top/20.hmac_intr_test.3081625327
/workspace/coverage/cover_reg_top/21.hmac_intr_test.3107718202
/workspace/coverage/cover_reg_top/22.hmac_intr_test.3754132677
/workspace/coverage/cover_reg_top/23.hmac_intr_test.370111010
/workspace/coverage/cover_reg_top/24.hmac_intr_test.1034331970
/workspace/coverage/cover_reg_top/25.hmac_intr_test.49615641
/workspace/coverage/cover_reg_top/26.hmac_intr_test.706118322
/workspace/coverage/cover_reg_top/27.hmac_intr_test.369179214
/workspace/coverage/cover_reg_top/28.hmac_intr_test.320405007
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2928291432
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.480695064
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3486845184
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4291667955
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3293326327
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.3394862079
/workspace/coverage/cover_reg_top/3.hmac_intr_test.2551944034
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3134876894
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.141087389
/workspace/coverage/cover_reg_top/30.hmac_intr_test.1044098015
/workspace/coverage/cover_reg_top/31.hmac_intr_test.995581311
/workspace/coverage/cover_reg_top/32.hmac_intr_test.142042304
/workspace/coverage/cover_reg_top/33.hmac_intr_test.1947477518
/workspace/coverage/cover_reg_top/34.hmac_intr_test.2845784870
/workspace/coverage/cover_reg_top/35.hmac_intr_test.307422757
/workspace/coverage/cover_reg_top/36.hmac_intr_test.2708698795
/workspace/coverage/cover_reg_top/37.hmac_intr_test.2273105516
/workspace/coverage/cover_reg_top/38.hmac_intr_test.4122370340
/workspace/coverage/cover_reg_top/39.hmac_intr_test.155852414
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4111290579
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1328623422
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3956613060
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1673688665
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.3100652189
/workspace/coverage/cover_reg_top/4.hmac_intr_test.974603503
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1612857863
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.17740677
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2848032982
/workspace/coverage/cover_reg_top/40.hmac_intr_test.226150033
/workspace/coverage/cover_reg_top/41.hmac_intr_test.1513349559
/workspace/coverage/cover_reg_top/42.hmac_intr_test.2651005996
/workspace/coverage/cover_reg_top/43.hmac_intr_test.1366597308
/workspace/coverage/cover_reg_top/44.hmac_intr_test.579431936
/workspace/coverage/cover_reg_top/45.hmac_intr_test.2636874526
/workspace/coverage/cover_reg_top/46.hmac_intr_test.3042473683
/workspace/coverage/cover_reg_top/47.hmac_intr_test.3021039823
/workspace/coverage/cover_reg_top/48.hmac_intr_test.554371269
/workspace/coverage/cover_reg_top/49.hmac_intr_test.3277641584
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3374380158
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.825686659
/workspace/coverage/cover_reg_top/5.hmac_intr_test.2516793016
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3524750029
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.2030321577
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2614165639
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3747816166
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.2201614096
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3650494390
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.2720892330
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.475522733
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3460795934
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2798752649
/workspace/coverage/cover_reg_top/7.hmac_intr_test.3672134930
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3076428528
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.3436612977
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1566774710
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3527668283
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.269597248
/workspace/coverage/cover_reg_top/8.hmac_intr_test.309950485
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2183733040
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.1864120668
/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2530143634
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1608276961
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.3928427785
/workspace/coverage/cover_reg_top/9.hmac_intr_test.2481970329
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.843654166
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.3703977333
/workspace/coverage/default/0.hmac_alert_test.1115299115
/workspace/coverage/default/0.hmac_back_pressure.2309361861
/workspace/coverage/default/0.hmac_burst_wr.2482468739
/workspace/coverage/default/0.hmac_datapath_stress.721753896
/workspace/coverage/default/0.hmac_error.1693349451
/workspace/coverage/default/0.hmac_long_msg.1994342618
/workspace/coverage/default/0.hmac_sec_cm.1858428300
/workspace/coverage/default/0.hmac_smoke.1087338862
/workspace/coverage/default/0.hmac_stress_all.2017182721
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.905345613
/workspace/coverage/default/0.hmac_test_hmac_vectors.1537143788
/workspace/coverage/default/0.hmac_test_sha_vectors.1307628235
/workspace/coverage/default/0.hmac_wipe_secret.3874361062
/workspace/coverage/default/1.hmac_alert_test.2583370211
/workspace/coverage/default/1.hmac_back_pressure.1426946559
/workspace/coverage/default/1.hmac_burst_wr.446344682
/workspace/coverage/default/1.hmac_datapath_stress.831088834
/workspace/coverage/default/1.hmac_error.627821711
/workspace/coverage/default/1.hmac_long_msg.4221407307
/workspace/coverage/default/1.hmac_sec_cm.545884882
/workspace/coverage/default/1.hmac_smoke.3030929041
/workspace/coverage/default/1.hmac_stress_all.3636560796
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1377097520
/workspace/coverage/default/1.hmac_test_hmac_vectors.1173061676
/workspace/coverage/default/1.hmac_test_sha_vectors.3672096540
/workspace/coverage/default/1.hmac_wipe_secret.2559962110
/workspace/coverage/default/10.hmac_alert_test.2677640994
/workspace/coverage/default/10.hmac_back_pressure.85322248
/workspace/coverage/default/10.hmac_burst_wr.2644964107
/workspace/coverage/default/10.hmac_datapath_stress.4094539898
/workspace/coverage/default/10.hmac_error.1750727662
/workspace/coverage/default/10.hmac_long_msg.2291563211
/workspace/coverage/default/10.hmac_smoke.1244085087
/workspace/coverage/default/10.hmac_stress_all.3405115716
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1927047422
/workspace/coverage/default/10.hmac_test_hmac_vectors.859167831
/workspace/coverage/default/10.hmac_test_sha_vectors.1653357177
/workspace/coverage/default/10.hmac_wipe_secret.4216861400
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2012373195
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.393684950
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2877459178
/workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3986338999
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.2360103023
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1094345691
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2396059172
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.4240341216
/workspace/coverage/default/11.hmac_back_pressure.293230216
/workspace/coverage/default/11.hmac_burst_wr.1433521654
/workspace/coverage/default/11.hmac_datapath_stress.10529274
/workspace/coverage/default/11.hmac_error.2550790444
/workspace/coverage/default/11.hmac_long_msg.996411766
/workspace/coverage/default/11.hmac_smoke.3551360568
/workspace/coverage/default/11.hmac_stress_all.4284670689
/workspace/coverage/default/11.hmac_stress_all_with_rand_reset.344873665
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/workspace/coverage/default/78.hmac_stress_all_with_rand_reset.3035913338
/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.697875432
/workspace/coverage/default/8.hmac_alert_test.1799414809
/workspace/coverage/default/8.hmac_back_pressure.2632135704
/workspace/coverage/default/8.hmac_burst_wr.2702301955
/workspace/coverage/default/8.hmac_datapath_stress.3511233435
/workspace/coverage/default/8.hmac_error.3441527139
/workspace/coverage/default/8.hmac_long_msg.722654654
/workspace/coverage/default/8.hmac_smoke.709396369
/workspace/coverage/default/8.hmac_stress_all.2651502149
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4061559708
/workspace/coverage/default/8.hmac_test_hmac_vectors.3850910761
/workspace/coverage/default/8.hmac_test_sha_vectors.3448841409
/workspace/coverage/default/8.hmac_wipe_secret.3075782547
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1360635823
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4037262256
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.2101334701
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.330587703
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1415306588
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.290448001
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.3140391328
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1054948649
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3025022016
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.435158800
/workspace/coverage/default/9.hmac_alert_test.3328051157
/workspace/coverage/default/9.hmac_back_pressure.2564154856
/workspace/coverage/default/9.hmac_burst_wr.3741071290
/workspace/coverage/default/9.hmac_datapath_stress.3989195437
/workspace/coverage/default/9.hmac_error.3270846293
/workspace/coverage/default/9.hmac_long_msg.302002258
/workspace/coverage/default/9.hmac_smoke.1097849349
/workspace/coverage/default/9.hmac_stress_all.3336298652
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1483634947
/workspace/coverage/default/9.hmac_test_hmac_vectors.391069929
/workspace/coverage/default/9.hmac_test_sha_vectors.2426901100
/workspace/coverage/default/9.hmac_wipe_secret.3187902250
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.4067281434
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3472572422
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.3933382063
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1544192
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.4290717714
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3789262627
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3615512772
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1054624145
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.4175215960
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.678417836



Total test records in report: 909
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T13 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4101296332 Jan 03 12:50:00 PM PST 24 Jan 03 12:50:26 PM PST 24 85017994 ps
T14 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3486845184 Jan 03 12:50:01 PM PST 24 Jan 03 12:50:37 PM PST 24 1002067439 ps
T15 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3134876894 Jan 03 12:49:48 PM PST 24 Jan 03 12:50:02 PM PST 24 378241794 ps
T16 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1799575612 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:49 PM PST 24 17907211 ps
T17 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3677146595 Jan 03 12:50:21 PM PST 24 Jan 03 12:50:51 PM PST 24 22475090 ps
T18 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3703977333 Jan 03 12:50:00 PM PST 24 Jan 03 12:50:26 PM PST 24 32232228 ps
T19 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1053067414 Jan 03 12:50:16 PM PST 24 Jan 03 12:50:40 PM PST 24 1074647386 ps
T20 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4075291577 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:35 PM PST 24 111947245 ps
T21 /workspace/coverage/cover_reg_top/39.hmac_intr_test.155852414 Jan 03 12:50:16 PM PST 24 Jan 03 12:50:39 PM PST 24 16509657 ps
T22 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3289388112 Jan 03 12:50:27 PM PST 24 Jan 03 12:50:52 PM PST 24 283904815 ps
T24 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3281433252 Jan 03 12:50:32 PM PST 24 Jan 03 12:50:56 PM PST 24 13240150 ps
T32 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2107059410 Jan 03 12:49:50 PM PST 24 Jan 03 12:50:06 PM PST 24 1066226011 ps
T33 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1985210758 Jan 03 12:49:50 PM PST 24 Jan 03 12:50:05 PM PST 24 94437661 ps
T34 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.445338388 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:40 PM PST 24 295031687 ps
T23 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.278979652 Jan 03 12:50:18 PM PST 24 Jan 03 12:50:43 PM PST 24 156820896 ps
T48 /workspace/coverage/cover_reg_top/27.hmac_intr_test.369179214 Jan 03 12:49:58 PM PST 24 Jan 03 12:50:21 PM PST 24 13611499 ps
T47 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3754132677 Jan 03 12:49:58 PM PST 24 Jan 03 12:50:21 PM PST 24 41731471 ps
T68 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.226536638 Jan 03 12:50:13 PM PST 24 Jan 03 12:50:36 PM PST 24 18315264 ps
T25 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2030321577 Jan 03 12:50:41 PM PST 24 Jan 03 12:51:07 PM PST 24 328873075 ps
T73 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1612857863 Jan 03 12:50:32 PM PST 24 Jan 03 12:50:57 PM PST 24 138945859 ps
T87 /workspace/coverage/cover_reg_top/23.hmac_intr_test.370111010 Jan 03 12:50:43 PM PST 24 Jan 03 12:51:07 PM PST 24 106751243 ps
T69 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2183733040 Jan 03 12:50:14 PM PST 24 Jan 03 12:50:38 PM PST 24 58404146 ps
T26 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3988842808 Jan 03 12:50:33 PM PST 24 Jan 03 12:50:59 PM PST 24 149340808 ps
T62 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1566774710 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:43 PM PST 24 167774596 ps
T27 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.582270486 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:56 PM PST 24 359677057 ps
T70 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4291667955 Jan 03 12:50:30 PM PST 24 Jan 03 12:50:54 PM PST 24 43407816 ps
T28 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.285237547 Jan 03 12:50:17 PM PST 24 Jan 03 12:50:41 PM PST 24 41199374 ps
T29 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3374380158 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:39 PM PST 24 44681964 ps
T64 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1187537839 Jan 03 12:50:26 PM PST 24 Jan 03 12:50:52 PM PST 24 100063671 ps
T65 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3524750029 Jan 03 12:50:50 PM PST 24 Jan 03 12:51:13 PM PST 24 52699553 ps
T66 /workspace/coverage/cover_reg_top/35.hmac_intr_test.307422757 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:31 PM PST 24 54057502 ps
T67 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3687526849 Jan 03 12:50:02 PM PST 24 Jan 03 12:50:28 PM PST 24 223810771 ps
T71 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1436801210 Jan 03 12:50:48 PM PST 24 Jan 03 12:51:12 PM PST 24 291416094 ps
T30 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.123043730 Jan 03 12:50:37 PM PST 24 Jan 03 12:51:04 PM PST 24 119518041 ps
T72 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3076428528 Jan 03 12:50:37 PM PST 24 Jan 03 12:51:03 PM PST 24 115326797 ps
T137 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2708698795 Jan 03 12:50:23 PM PST 24 Jan 03 12:50:46 PM PST 24 45677408 ps
T31 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.98254109 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 35527712 ps
T138 /workspace/coverage/cover_reg_top/40.hmac_intr_test.226150033 Jan 03 12:50:28 PM PST 24 Jan 03 12:50:52 PM PST 24 45471745 ps
T139 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3021039823 Jan 03 12:50:26 PM PST 24 Jan 03 12:50:50 PM PST 24 22667833 ps
T86 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.207777354 Jan 03 12:50:37 PM PST 24 Jan 03 12:51:03 PM PST 24 22468235 ps
T140 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3081625327 Jan 03 12:49:53 PM PST 24 Jan 03 12:50:10 PM PST 24 15601310 ps
T63 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3305295438 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:39 PM PST 24 158209129 ps
T85 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4138241066 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:43 PM PST 24 59952991 ps
T141 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1737080321 Jan 03 12:50:19 PM PST 24 Jan 03 12:50:41 PM PST 24 50159595 ps
T142 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2551944034 Jan 03 12:50:28 PM PST 24 Jan 03 12:50:52 PM PST 24 35858660 ps
T143 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3614791641 Jan 03 12:50:09 PM PST 24 Jan 03 12:50:34 PM PST 24 236482705 ps
T74 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1797004361 Jan 03 12:50:38 PM PST 24 Jan 03 12:51:03 PM PST 24 47033865 ps
T75 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1279056817 Jan 03 12:50:30 PM PST 24 Jan 03 12:50:54 PM PST 24 12585669 ps
T144 /workspace/coverage/cover_reg_top/11.hmac_intr_test.459959110 Jan 03 12:50:27 PM PST 24 Jan 03 12:50:51 PM PST 24 45957414 ps
T135 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.863408399 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:51 PM PST 24 31514421 ps
T145 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2183028569 Jan 03 12:50:12 PM PST 24 Jan 03 12:50:36 PM PST 24 21330645 ps
T146 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2481970329 Jan 03 12:50:42 PM PST 24 Jan 03 12:51:07 PM PST 24 12830651 ps
T147 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.825686659 Jan 03 12:49:58 PM PST 24 Jan 03 12:50:21 PM PST 24 13596906 ps
T148 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2909424295 Jan 03 12:50:09 PM PST 24 Jan 03 12:50:33 PM PST 24 62312448 ps
T149 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.289191742 Jan 03 12:50:11 PM PST 24 Jan 03 12:50:40 PM PST 24 1811586010 ps
T76 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.269597248 Jan 03 12:50:27 PM PST 24 Jan 03 12:50:51 PM PST 24 14116107 ps
T150 /workspace/coverage/cover_reg_top/28.hmac_intr_test.320405007 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:52 PM PST 24 22923187 ps
T77 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.59584000 Jan 03 12:50:26 PM PST 24 Jan 03 12:50:50 PM PST 24 21731393 ps
T136 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3356618049 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:32 PM PST 24 23066628 ps
T151 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3514203205 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:49 PM PST 24 78570072 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2848032982 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 84072141 ps
T152 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455645897 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:44 PM PST 24 71591765 ps
T153 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3864014909 Jan 03 12:49:42 PM PST 24 Jan 03 12:50:04 PM PST 24 1001623575 ps
T154 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3277641584 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:42 PM PST 24 36590445 ps
T155 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3221823688 Jan 03 12:51:00 PM PST 24 Jan 03 01:03:52 PM PST 24 86294537842 ps
T156 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2928291432 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 29106474 ps
T157 /workspace/coverage/cover_reg_top/25.hmac_intr_test.49615641 Jan 03 12:49:56 PM PST 24 Jan 03 12:50:17 PM PST 24 13180797 ps
T94 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2189986578 Jan 03 12:50:19 PM PST 24 Jan 03 12:50:43 PM PST 24 47704513 ps
T158 /workspace/coverage/cover_reg_top/48.hmac_intr_test.554371269 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:54 PM PST 24 63885205 ps
T159 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2189957379 Jan 03 12:50:41 PM PST 24 Jan 03 12:51:06 PM PST 24 18954163 ps
T160 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3471254304 Jan 03 12:50:47 PM PST 24 Jan 03 12:51:11 PM PST 24 21155235 ps
T161 /workspace/coverage/cover_reg_top/0.hmac_intr_test.4044491472 Jan 03 12:49:59 PM PST 24 Jan 03 12:50:22 PM PST 24 17340339 ps
T162 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3474684738 Jan 03 12:50:33 PM PST 24 Jan 03 12:50:58 PM PST 24 189374489 ps
T163 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3632311794 Jan 03 12:49:41 PM PST 24 Jan 03 12:49:57 PM PST 24 184087467 ps
T164 /workspace/coverage/cover_reg_top/32.hmac_intr_test.142042304 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:43 PM PST 24 20452640 ps
T165 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2720892330 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:39 PM PST 24 49960865 ps
T166 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1726716578 Jan 03 12:50:11 PM PST 24 Jan 03 12:50:35 PM PST 24 45942118 ps
T167 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1513349559 Jan 03 12:50:38 PM PST 24 Jan 03 12:51:02 PM PST 24 125636634 ps
T168 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1947477518 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:31 PM PST 24 125646794 ps
T169 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.843654166 Jan 03 12:49:59 PM PST 24 Jan 03 12:50:24 PM PST 24 44072788 ps
T170 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1864120668 Jan 03 12:50:11 PM PST 24 Jan 03 12:50:38 PM PST 24 222840336 ps
T171 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1871687363 Jan 03 12:49:57 PM PST 24 Jan 03 12:50:19 PM PST 24 32533298 ps
T172 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2614165639 Jan 03 12:50:04 PM PST 24 Jan 03 12:50:30 PM PST 24 380635950 ps
T173 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.736357588 Jan 03 12:50:22 PM PST 24 Jan 03 12:50:46 PM PST 24 211092722 ps
T174 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2651005996 Jan 03 12:50:36 PM PST 24 Jan 03 12:51:00 PM PST 24 109225027 ps
T175 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.984998926 Jan 03 12:51:15 PM PST 24 Jan 03 12:51:38 PM PST 24 2259888023 ps
T176 /workspace/coverage/cover_reg_top/15.hmac_intr_test.790583747 Jan 03 12:50:38 PM PST 24 Jan 03 12:51:03 PM PST 24 14744604 ps
T177 /workspace/coverage/cover_reg_top/14.hmac_intr_test.399638633 Jan 03 12:50:45 PM PST 24 Jan 03 12:51:09 PM PST 24 12763412 ps
T178 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3650494390 Jan 03 12:50:35 PM PST 24 Jan 03 12:51:00 PM PST 24 51092043 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.791966501 Jan 03 12:49:44 PM PST 24 Jan 03 12:49:58 PM PST 24 170548589 ps
T179 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.222379045 Jan 03 12:50:17 PM PST 24 Jan 03 12:50:41 PM PST 24 40176500 ps
T90 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2314580681 Jan 03 12:50:21 PM PST 24 Jan 03 12:50:44 PM PST 24 48124624 ps
T180 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4206744505 Jan 03 12:50:36 PM PST 24 Jan 03 12:51:01 PM PST 24 55539015 ps
T181 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1034331970 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:48 PM PST 24 44531623 ps
T93 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2155894930 Jan 03 12:50:38 PM PST 24 Jan 03 12:51:04 PM PST 24 44125464 ps
T182 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3394862079 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:38 PM PST 24 24299913 ps
T183 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2493858461 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:54 PM PST 24 50081991 ps
T184 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2273105516 Jan 03 12:50:26 PM PST 24 Jan 03 12:50:50 PM PST 24 51939907 ps
T185 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3956613060 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:53 PM PST 24 67854855 ps
T186 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3959009478 Jan 03 12:50:33 PM PST 24 Jan 03 12:50:58 PM PST 24 51017479 ps
T187 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1045159198 Jan 03 12:50:17 PM PST 24 Jan 03 12:50:41 PM PST 24 82495650 ps
T188 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1673688665 Jan 03 12:49:56 PM PST 24 Jan 03 12:50:19 PM PST 24 68103787 ps
T189 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2798752649 Jan 03 12:50:07 PM PST 24 Jan 03 12:50:32 PM PST 24 37073799 ps
T78 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.435887710 Jan 03 12:49:45 PM PST 24 Jan 03 12:49:58 PM PST 24 70078973 ps
T79 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1821376140 Jan 03 12:50:37 PM PST 24 Jan 03 12:51:02 PM PST 24 26545251 ps
T190 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1608276961 Jan 03 12:50:20 PM PST 24 Jan 03 12:50:44 PM PST 24 314704996 ps
T191 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4036486983 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:48 PM PST 24 12759908 ps
T192 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2516793016 Jan 03 12:50:19 PM PST 24 Jan 03 12:50:42 PM PST 24 31848125 ps
T193 /workspace/coverage/cover_reg_top/44.hmac_intr_test.579431936 Jan 03 12:50:32 PM PST 24 Jan 03 12:50:56 PM PST 24 18423515 ps
T1 /workspace/coverage/default/23.hmac_stress_all.72520183 Jan 03 01:04:50 PM PST 24 Jan 03 01:08:14 PM PST 24 8500052279 ps
T2 /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.3231559821 Jan 03 01:05:58 PM PST 24 Jan 03 01:13:06 PM PST 24 49360951095 ps
T3 /workspace/coverage/default/20.hmac_smoke.2072375840 Jan 03 01:04:42 PM PST 24 Jan 03 01:06:14 PM PST 24 224421434 ps
T4 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2927467392 Jan 03 01:05:56 PM PST 24 Jan 03 01:51:58 PM PST 24 60754164347 ps
T6 /workspace/coverage/default/47.hmac_back_pressure.3156163110 Jan 03 01:05:14 PM PST 24 Jan 03 01:06:56 PM PST 24 269471308 ps
T8 /workspace/coverage/default/37.hmac_alert_test.1944657574 Jan 03 01:05:42 PM PST 24 Jan 03 01:07:02 PM PST 24 51712625 ps
T9 /workspace/coverage/default/3.hmac_alert_test.3270970606 Jan 03 01:04:37 PM PST 24 Jan 03 01:05:58 PM PST 24 12966608 ps
T7 /workspace/coverage/default/46.hmac_back_pressure.2497565627 Jan 03 01:05:23 PM PST 24 Jan 03 01:07:31 PM PST 24 1455479550 ps
T10 /workspace/coverage/default/40.hmac_stress_all.518214302 Jan 03 01:05:48 PM PST 24 Jan 03 01:35:08 PM PST 24 434720938084 ps
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