Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22319572

1

T1

10197

T2

8146

T3

129

auto[1]

10162250

1

T1

7934

T2

6873

T3

61

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10347656

1

T1

7893

T2

6378

T3

70

auto[1]

22134166

1

T1

10238

T2

8641

T3

120

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19541588

1

T1

3090

T2

8294

T3

107

auto[1]

12940234

1

T1

15041

T2

6725

T3

83

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	17853011	1			T1	16437		T2	13458		T3	117
fifo_depth[1]	1662223	1			T1	960		T2	622		T3	12
fifo_depth[2]	1526364	1			T1	486		T2	428		T3	5
fifo_depth[3]	1310023	1			T1	168		T2	169		T3	5
fifo_depth[4]	1263535	1			T1	62		T2	243		T3	9
fifo_depth[5]	1083008	1			T1	16		T2	55		T3	6
fifo_depth[6]	1108788	1			T1	2		T2	36		T3	6
fifo_depth[7]	945690	1			T2	6		T3	8		T4	8700
fifo_depth[8]	1117872	1			T2	2		T3	6		T4	10553
fifo_depth[9]	653289	1			T3	9		T4	6038		T6	1
fifo_depth[10]	664747	1			T3	2		T4	6137		T6	1
fifo_depth[11]	404401	1			T3	3		T4	3853		T7	2
fifo_depth[12]	683728	1			T3	1		T4	5404		T7	7
fifo_depth[13]	299649	1			T3	1		T4	2687		T6	1
fifo_depth[14]	488854	1			T4	3587		T7	5		T35	9
fifo_depth[15]	270529	1			T4	2336		T7	3		T42	6
fifo_depth[16]	1146111	1			T4	7903		T6	2		T7	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14628811

1

T1

1694

T2

1561

T3

73

auto[1]

17853011

1

T1

16437

T2

13458

T3

117

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31335711

1

T1

18131

T2

15019

T3

190

auto[1]

1146111

1

T4

7903

T6

2

T7

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1110588

1

T1

52

T2

291

T4

7107

auto[0]

auto[0]

auto[0]

auto[1]

1098779

1

T1

71

T2

139

T4

7309

auto[0]

auto[0]

auto[1]

auto[0]

4175614

1

T1

96

T2

179

T4

46701

auto[0]

auto[0]

auto[1]

auto[1]

1086363

1

T1

54

T2

188

T4

9807

auto[0]

auto[1]

auto[0]

auto[0]

1799042

1

T1

384

T2

217

T3

16

auto[0]

auto[1]

auto[0]

auto[1]

1748620

1

T1

241

T2

121

T3

13

auto[0]

auto[1]

auto[1]

auto[0]

1823250

1

T1

431

T2

248

T3

37

auto[0]

auto[1]

auto[1]

auto[1]

1786555

1

T1

365

T2

178

T3

7

auto[1]

auto[0]

auto[0]

auto[0]

853345

1

T1

588

T2

2161

T3

25

auto[1]

auto[0]

auto[0]

auto[1]

833457

1

T1

735

T2

950

T3

12

auto[1]

auto[0]

auto[1]

auto[0]

9591643

1

T1

923

T2

2022

T3

45

auto[1]

auto[0]

auto[1]

auto[1]

791799

1

T1

571

T2

2364

T3

25

auto[1]

auto[1]

auto[0]

auto[0]

1490391

1

T1

3520

T2

1485

T3

1

auto[1]

auto[1]

auto[0]

auto[1]

1413434

1

T1

2302

T2

1014

T3

3

auto[1]

auto[1]

auto[1]

auto[0]

1475699

1

T1

4203

T2

1543

T3

5

auto[1]

auto[1]

auto[1]

auto[1]

1403243

1

T1

3595

T2

1919

T3

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1819997

1

T1

640

T2

2452

T3

25

auto[0]

auto[0]

auto[0]

auto[1]

1782845

1

T1

806

T2

1089

T3

12

auto[0]

auto[0]

auto[1]

auto[0]

13639377

1

T1

1019

T2

2201

T3

45

auto[0]

auto[0]

auto[1]

auto[1]

1736601

1

T1

625

T2

2552

T3

25

auto[0]

auto[1]

auto[0]

auto[0]

3142205

1

T1

3904

T2

1702

T3

17

auto[0]

auto[1]

auto[0]

auto[1]

3027412

1

T1

2543

T2

1135

T3

16

auto[0]

auto[1]

auto[1]

auto[0]

3145203

1

T1

4634

T2

1791

T3

42

auto[0]

auto[1]

auto[1]

auto[1]

3042071

1

T1

3960

T2

2097

T3

8

auto[1]

auto[0]

auto[0]

auto[0]

143936

1

T4

1296

T7

2

T36

1154

auto[1]

auto[0]

auto[0]

auto[1]

149391

1

T4

950

T36

1749

T133

309

auto[1]

auto[0]

auto[1]

auto[0]

127880

1

T4

730

T6

2

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

141561

1

T4

592

T7

2

T36

653

auto[1]

auto[1]

auto[0]

auto[0]

147228

1

T4

938

T7

1

T42

1

auto[1]

auto[1]

auto[0]

auto[1]

134642

1

T4

2074

T44

1

T36

1508

auto[1]

auto[1]

auto[1]

auto[0]

153746

1

T4

1196

T36

2818

T37

331

auto[1]

auto[1]

auto[1]

auto[1]

147727

1

T4

127

T42

1

T44

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	853345	1			T1	588		T2	2161		T3	25
fifo_depth[0]	auto[0]	auto[0]	auto[1]	833457	1			T1	735		T2	950		T3	12
fifo_depth[0]	auto[0]	auto[1]	auto[0]	9591643	1			T1	923		T2	2022		T3	45
fifo_depth[0]	auto[0]	auto[1]	auto[1]	791799	1			T1	571		T2	2364		T3	25
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1490391	1			T1	3520		T2	1485		T3	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1413434	1			T1	2302		T2	1014		T3	3
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1475699	1			T1	4203		T2	1543		T3	5
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1403243	1			T1	3595		T2	1919		T3	1
fifo_depth[1]	auto[0]	auto[0]	auto[0]	82167	1			T1	34		T2	102		T4	325
fifo_depth[1]	auto[0]	auto[0]	auto[1]	79733	1			T1	44		T2	57		T4	582
fifo_depth[1]	auto[0]	auto[1]	auto[0]	749351	1			T1	55		T2	103		T4	7676
fifo_depth[1]	auto[0]	auto[1]	auto[1]	76723	1			T1	28		T2	88		T4	777
fifo_depth[1]	auto[1]	auto[0]	auto[0]	172226	1			T1	214		T2	52		T3	5
fifo_depth[1]	auto[1]	auto[0]	auto[1]	165311	1			T1	134		T2	58		T3	2
fifo_depth[1]	auto[1]	auto[1]	auto[0]	172386	1			T1	247		T2	87		T3	4
fifo_depth[1]	auto[1]	auto[1]	auto[1]	164326	1			T1	204		T2	75		T3	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	78089	1			T1	13		T2	60		T4	313
fifo_depth[2]	auto[0]	auto[0]	auto[1]	77451	1			T1	18		T2	36		T4	654
fifo_depth[2]	auto[0]	auto[1]	auto[0]	659878	1			T1	29		T2	37		T4	7554
fifo_depth[2]	auto[0]	auto[1]	auto[1]	75249	1			T1	15		T2	46		T4	930
fifo_depth[2]	auto[1]	auto[0]	auto[0]	162526	1			T1	108		T2	96		T4	838
fifo_depth[2]	auto[1]	auto[0]	auto[1]	156108	1			T1	65		T2	23		T3	2
fifo_depth[2]	auto[1]	auto[1]	auto[0]	162151	1			T1	123		T2	64		T3	2
fifo_depth[2]	auto[1]	auto[1]	auto[1]	154912	1			T1	115		T2	66		T3	1
fifo_depth[3]	auto[0]	auto[0]	auto[0]	69555	1			T1	4		T2	39		T4	361
fifo_depth[3]	auto[0]	auto[0]	auto[1]	68446	1			T1	5		T2	22		T4	496
fifo_depth[3]	auto[0]	auto[1]	auto[0]	534800	1			T1	9		T2	7		T4	6367
fifo_depth[3]	auto[0]	auto[1]	auto[1]	66055	1			T1	8		T2	19		T4	902
fifo_depth[3]	auto[1]	auto[0]	auto[0]	145455	1			T1	40		T2	18		T3	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	140409	1			T1	27		T2	14		T3	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	146168	1			T1	40		T2	39		T3	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	139135	1			T1	35		T2	11		T4	1048
fifo_depth[4]	auto[0]	auto[0]	auto[0]	81029	1			T1	1		T2	61		T4	512
fifo_depth[4]	auto[0]	auto[0]	auto[1]	78337	1			T1	4		T2	13		T4	647
fifo_depth[4]	auto[0]	auto[1]	auto[0]	422478	1			T1	2		T2	30		T4	5252
fifo_depth[4]	auto[0]	auto[1]	auto[1]	78449	1			T1	2		T2	24		T4	886
fifo_depth[4]	auto[1]	auto[0]	auto[0]	151065	1			T1	16		T2	38		T3	2
fifo_depth[4]	auto[1]	auto[0]	auto[1]	148762	1			T1	11		T2	11		T3	2
fifo_depth[4]	auto[1]	auto[1]	auto[0]	154892	1			T1	15		T2	43		T3	4
fifo_depth[4]	auto[1]	auto[1]	auto[1]	148523	1			T1	11		T2	23		T3	1
fifo_depth[5]	auto[0]	auto[0]	auto[0]	65353	1			T2	20		T4	411		T10	8
fifo_depth[5]	auto[0]	auto[0]	auto[1]	65026	1			T2	5		T4	432		T10	9
fifo_depth[5]	auto[0]	auto[1]	auto[0]	350488	1			T1	1		T4	4570		T10	77
fifo_depth[5]	auto[0]	auto[1]	auto[1]	64344	1			T1	1		T2	7		T4	859
fifo_depth[5]	auto[1]	auto[0]	auto[0]	136090	1			T1	4		T2	6		T3	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	132916	1			T1	4		T2	6		T3	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	137996	1			T1	6		T2	10		T3	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	130795	1			T2	1		T3	1		T4	1111
fifo_depth[6]	auto[0]	auto[0]	auto[0]	74896	1			T2	8		T4	451		T10	6
fifo_depth[6]	auto[0]	auto[0]	auto[1]	73479	1			T2	5		T4	582		T10	4
fifo_depth[6]	auto[0]	auto[1]	auto[0]	313650	1			T2	1		T4	4019		T10	20
fifo_depth[6]	auto[0]	auto[1]	auto[1]	75122	1			T2	2		T4	933		T10	14
fifo_depth[6]	auto[1]	auto[0]	auto[0]	144248	1			T1	2		T2	6		T3	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	140831	1			T2	8		T3	1		T4	1030
fifo_depth[6]	auto[1]	auto[1]	auto[0]	146188	1			T2	4		T3	3		T4	1526
fifo_depth[6]	auto[1]	auto[1]	auto[1]	140374	1			T2	2		T3	1		T4	1096
fifo_depth[7]	auto[0]	auto[0]	auto[0]	62477	1			T2	1		T4	357		T7	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	63634	1			T2	1		T4	402		T5	6
fifo_depth[7]	auto[0]	auto[1]	auto[0]	250748	1			T4	3115		T7	1		T10	4
fifo_depth[7]	auto[0]	auto[1]	auto[1]	62724	1			T2	1		T4	780		T10	6
fifo_depth[7]	auto[1]	auto[0]	auto[0]	128179	1			T2	1		T3	1		T4	871
fifo_depth[7]	auto[1]	auto[0]	auto[1]	124932	1			T2	1		T3	1		T4	861
fifo_depth[7]	auto[1]	auto[1]	auto[0]	129735	1			T2	1		T3	5		T4	1277
fifo_depth[7]	auto[1]	auto[1]	auto[1]	123261	1			T3	1		T4	1037		T10	7
fifo_depth[8]	auto[0]	auto[0]	auto[0]	97128	1			T4	754		T7	1		T10	1
fifo_depth[8]	auto[0]	auto[0]	auto[1]	99534	1			T4	737		T7	1		T10	1
fifo_depth[8]	auto[0]	auto[1]	auto[0]	226564	1			T2	1		T4	2400		T5	13
fifo_depth[8]	auto[0]	auto[1]	auto[1]	93658	1			T2	1		T4	845		T10	8
fifo_depth[8]	auto[1]	auto[0]	auto[0]	146552	1			T3	2		T4	854		T5	2
fifo_depth[8]	auto[1]	auto[0]	auto[1]	149379	1			T3	1		T4	2210		T10	3
fifo_depth[8]	auto[1]	auto[1]	auto[0]	151894	1			T3	3		T4	1756		T10	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	153163	1			T4	997		T7	1		T10	4
fifo_depth[9]	auto[0]	auto[0]	auto[0]	48431	1			T4	258		T6	1		T7	3
fifo_depth[9]	auto[0]	auto[0]	auto[1]	50775	1			T4	256		T5	3		T97	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	139076	1			T4	1559		T41	1		T97	3
fifo_depth[9]	auto[0]	auto[1]	auto[1]	50330	1			T4	618		T97	5		T43	2
fifo_depth[9]	auto[1]	auto[0]	auto[0]	90237	1			T4	688		T97	3		T42	180
fifo_depth[9]	auto[1]	auto[0]	auto[1]	89269	1			T4	642		T5	1		T41	8
fifo_depth[9]	auto[1]	auto[1]	auto[0]	93932	1			T3	9		T4	1233		T5	2
fifo_depth[9]	auto[1]	auto[1]	auto[1]	91239	1			T4	784		T10	2		T41	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	61191	1			T4	412		T7	1		T97	5
fifo_depth[10]	auto[0]	auto[0]	auto[1]	59125	1			T4	542		T7	1		T5	7
fifo_depth[10]	auto[0]	auto[1]	auto[0]	113932	1			T4	1185		T35	218		T43	2
fifo_depth[10]	auto[0]	auto[1]	auto[1]	64409	1			T4	500		T10	2		T43	3
fifo_depth[10]	auto[1]	auto[0]	auto[0]	89384	1			T4	490		T7	1		T97	9
fifo_depth[10]	auto[1]	auto[0]	auto[1]	88863	1			T3	1		T4	880		T7	1
fifo_depth[10]	auto[1]	auto[1]	auto[0]	92467	1			T4	1429		T7	1		T5	3
fifo_depth[10]	auto[1]	auto[1]	auto[1]	95376	1			T3	1		T4	699		T6	1
fifo_depth[11]	auto[0]	auto[0]	auto[0]	37727	1			T4	246		T36	452		T134	13
fifo_depth[11]	auto[0]	auto[0]	auto[1]	38123	1			T4	167		T36	323		T133	117
fifo_depth[11]	auto[0]	auto[1]	auto[0]	68343	1			T4	745		T7	1		T97	1
fifo_depth[11]	auto[0]	auto[1]	auto[1]	39828	1			T4	307		T36	352		T37	203
fifo_depth[11]	auto[1]	auto[0]	auto[0]	54600	1			T3	2		T4	419		T42	66
fifo_depth[11]	auto[1]	auto[0]	auto[1]	53636	1			T3	1		T4	498		T41	2
fifo_depth[11]	auto[1]	auto[1]	auto[0]	56994	1			T4	997		T11	2		T41	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	55150	1			T4	474		T7	1		T97	2
fifo_depth[12]	auto[0]	auto[0]	auto[0]	82485	1			T4	541		T36	1787		T134	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	77144	1			T4	417		T7	1		T97	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	85970	1			T4	579		T7	2		T97	1
fifo_depth[12]	auto[0]	auto[1]	auto[1]	76519	1			T4	290		T36	634		T37	658
fifo_depth[12]	auto[1]	auto[0]	auto[0]	90969	1			T4	433		T42	26		T44	41
fifo_depth[12]	auto[1]	auto[0]	auto[1]	91068	1			T4	1681		T42	12		T44	47
fifo_depth[12]	auto[1]	auto[1]	auto[0]	86177	1			T3	1		T4	1097		T7	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	93396	1			T4	366		T7	3		T42	21
fifo_depth[13]	auto[0]	auto[0]	auto[0]	34412	1			T4	188		T7	1		T36	274
fifo_depth[13]	auto[0]	auto[0]	auto[1]	32732	1			T4	78		T6	1		T36	152
fifo_depth[13]	auto[0]	auto[1]	auto[0]	39616	1			T4	381		T7	1		T35	29
fifo_depth[13]	auto[0]	auto[1]	auto[1]	33800	1			T4	212		T36	119		T37	149
fifo_depth[13]	auto[1]	auto[0]	auto[0]	40212	1			T4	365		T7	1		T42	21
fifo_depth[13]	auto[1]	auto[0]	auto[1]	37576	1			T4	433		T42	2		T44	16
fifo_depth[13]	auto[1]	auto[1]	auto[0]	39944	1			T3	1		T4	763		T41	1
fifo_depth[13]	auto[1]	auto[1]	auto[1]	41357	1			T4	267		T7	1		T10	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	59724	1			T4	421		T7	1		T36	679
fifo_depth[14]	auto[0]	auto[0]	auto[1]	54292	1			T4	316		T36	163		T133	135
fifo_depth[14]	auto[0]	auto[1]	auto[0]	58823	1			T4	323		T35	9		T36	600
fifo_depth[14]	auto[0]	auto[1]	auto[1]	57773	1			T4	233		T7	2		T36	450
fifo_depth[14]	auto[1]	auto[0]	auto[0]	64810	1			T4	505		T42	7		T44	3
fifo_depth[14]	auto[1]	auto[0]	auto[1]	62023	1			T4	653		T42	1		T44	9
fifo_depth[14]	auto[1]	auto[1]	auto[0]	62027	1			T4	902		T7	1		T42	10
fifo_depth[14]	auto[1]	auto[1]	auto[1]	69382	1			T4	234		T7	1		T42	5
fifo_depth[15]	auto[0]	auto[0]	auto[0]	31988	1			T4	261		T36	202		T37	236
fifo_depth[15]	auto[0]	auto[0]	auto[1]	31557	1			T4	51		T7	1		T36	100
fifo_depth[15]	auto[0]	auto[1]	auto[0]	34017	1			T4	246		T7	1		T36	334
fifo_depth[15]	auto[0]	auto[1]	auto[1]	29819	1			T4	143		T7	1		T36	41
fifo_depth[15]	auto[1]	auto[0]	auto[0]	35261	1			T4	463		T42	2		T44	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	32895	1			T4	432		T44	5		T36	338
fifo_depth[15]	auto[1]	auto[1]	auto[0]	36553	1			T4	598		T42	2		T36	774
fifo_depth[15]	auto[1]	auto[1]	auto[1]	38439	1			T4	142		T42	2		T44	4
fifo_depth[16]	auto[0]	auto[0]	auto[0]	143936	1			T4	1296		T7	2		T36	1154
fifo_depth[16]	auto[0]	auto[0]	auto[1]	149391	1			T4	950		T36	1749		T133	309
fifo_depth[16]	auto[0]	auto[1]	auto[0]	127880	1			T4	730		T6	2		T35	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	141561	1			T4	592		T7	2		T36	653
fifo_depth[16]	auto[1]	auto[0]	auto[0]	147228	1			T4	938		T7	1		T42	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	134642	1			T4	2074		T44	1		T36	1508
fifo_depth[16]	auto[1]	auto[1]	auto[0]	153746	1			T4	1196		T36	2818		T37	331
fifo_depth[16]	auto[1]	auto[1]	auto[1]	147727	1			T4	127		T42	1		T44	3