Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	44419039	1			T17	8		T18	1		T21	5
all_pins[1]	44419039	1			T17	8		T18	1		T21	5
all_pins[2]	44419039	1			T17	8		T18	1		T21	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	96417320	1			T17	14		T18	3		T21	15
values[0x1]	36839797	1			T17	10		T24	11		T48	2
transitions[0x0=>0x1]	32312841	1			T17	6		T24	6		T48	2
transitions[0x1=>0x0]	32312878	1			T17	6		T24	6		T48	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	44236556	1			T17	6		T18	1		T21	5
all_pins[0]	values[0x1]	182483	1			T17	2		T24	2		T47	3
all_pins[0]	transitions[0x0=>0x1]	182252	1			T17	1		T24	1		T47	3
all_pins[0]	transitions[0x1=>0x0]	17287905	1			T17	4		T24	3		T47	1
all_pins[1]	values[0x0]	25049824	1			T17	5		T18	1		T21	5
all_pins[1]	values[0x1]	19369215	1			T17	3		T24	5		T48	2
all_pins[1]	transitions[0x0=>0x1]	19226296	1			T17	1		T24	4		T48	2
all_pins[1]	transitions[0x1=>0x0]	39564	1			T24	1		T47	3		T87	1
all_pins[2]	values[0x0]	27130940	1			T17	3		T18	1		T21	5
all_pins[2]	values[0x1]	17288099	1			T17	5		T24	4		T47	1
all_pins[2]	transitions[0x0=>0x1]	12904293	1			T17	4		T24	1		T87	3
all_pins[2]	transitions[0x1=>0x0]	14985409	1			T17	2		T24	2		T48	2