Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4032 1 T17 7 T21 4 T24 10
all_values[1] 4032 1 T17 7 T21 4 T24 10
all_values[2] 4032 1 T17 7 T21 4 T24 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5798 1 T17 9 T21 11 T24 18
auto[1] 6298 1 T17 12 T21 1 T24 12


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4458 1 T17 4 T21 4 T24 8
auto[1] 7638 1 T17 17 T21 8 T24 22


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6862 1 T17 8 T21 8 T24 18
auto[1] 5234 1 T17 13 T21 4 T24 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 716 1 T17 2 T21 1 T24 4
all_values[0] auto[0] auto[0] auto[1] 416 1 T17 1 T21 2 T24 2
all_values[0] auto[0] auto[1] auto[0] 781 1 T24 2 T48 2 T47 1
all_values[0] auto[0] auto[1] auto[1] 381 1 T17 1 T24 1 T47 1
all_values[0] auto[1] auto[0] auto[1] 820 1 T17 1 T21 1 T48 1
all_values[0] auto[1] auto[1] auto[1] 918 1 T17 2 T24 1 T47 2
all_values[1] auto[0] auto[0] auto[0] 743 1 T17 1 T21 1 T24 2
all_values[1] auto[0] auto[0] auto[1] 388 1 T21 2 T24 1 T47 2
all_values[1] auto[0] auto[1] auto[0] 735 1 T17 1 T87 1 T66 1
all_values[1] auto[0] auto[1] auto[1] 421 1 T24 4 T48 1 T66 1
all_values[1] auto[1] auto[0] auto[1] 818 1 T21 1 T24 2 T48 1
all_values[1] auto[1] auto[1] auto[1] 927 1 T17 5 T24 1 T48 1
all_values[2] auto[0] auto[0] auto[0] 675 1 T21 1 T47 2 T87 2
all_values[2] auto[0] auto[0] auto[1] 391 1 T17 1 T24 1 T48 1
all_values[2] auto[0] auto[1] auto[0] 808 1 T21 1 T48 1 T47 1
all_values[2] auto[0] auto[1] auto[1] 407 1 T17 1 T24 1 T87 1
all_values[2] auto[1] auto[0] auto[1] 831 1 T17 3 T21 2 T24 6
all_values[2] auto[1] auto[1] auto[1] 920 1 T17 2 T24 2 T47 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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