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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.58 100.00 100.00 99.76 99.49 100.00


Total test records in report: 909
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T758 /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.2978396513 Jan 03 01:05:29 PM PST 24 Jan 03 01:19:47 PM PST 24 68027200324 ps
T759 /workspace/coverage/default/35.hmac_long_msg.1689491676 Jan 03 01:05:22 PM PST 24 Jan 03 01:06:56 PM PST 24 7524065334 ps
T760 /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.697875432 Jan 03 01:05:47 PM PST 24 Jan 03 01:10:13 PM PST 24 10660639437 ps
T761 /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.3709729128 Jan 03 01:05:30 PM PST 24 Jan 03 01:28:55 PM PST 24 73328742574 ps
T762 /workspace/coverage/default/10.hmac_back_pressure.85322248 Jan 03 01:04:56 PM PST 24 Jan 03 01:06:49 PM PST 24 5399886499 ps
T763 /workspace/coverage/default/14.hmac_burst_wr.2384555776 Jan 03 01:04:45 PM PST 24 Jan 03 01:06:15 PM PST 24 1337042820 ps
T764 /workspace/coverage/default/43.hmac_error.3221909076 Jan 03 01:05:27 PM PST 24 Jan 03 01:09:57 PM PST 24 24110962230 ps
T765 /workspace/coverage/default/35.hmac_test_hmac_vectors.1639476717 Jan 03 01:05:10 PM PST 24 Jan 03 01:06:46 PM PST 24 96394093 ps
T766 /workspace/coverage/default/33.hmac_smoke.2118963294 Jan 03 01:05:00 PM PST 24 Jan 03 01:06:23 PM PST 24 921827778 ps
T767 /workspace/coverage/default/29.hmac_datapath_stress.1494427430 Jan 03 01:04:58 PM PST 24 Jan 03 01:07:53 PM PST 24 2018906642 ps
T768 /workspace/coverage/default/34.hmac_back_pressure.1405997162 Jan 03 01:05:07 PM PST 24 Jan 03 01:07:18 PM PST 24 1276088685 ps
T769 /workspace/coverage/default/3.hmac_datapath_stress.3640065296 Jan 03 01:04:26 PM PST 24 Jan 03 01:07:28 PM PST 24 8259300335 ps
T770 /workspace/coverage/default/40.hmac_smoke.61848988 Jan 03 01:05:30 PM PST 24 Jan 03 01:06:50 PM PST 24 325460510 ps
T771 /workspace/coverage/default/31.hmac_smoke.3996479796 Jan 03 01:05:51 PM PST 24 Jan 03 01:07:14 PM PST 24 84295518 ps
T772 /workspace/coverage/default/10.hmac_stress_all.3405115716 Jan 03 01:05:20 PM PST 24 Jan 03 01:28:43 PM PST 24 25084570537 ps
T773 /workspace/coverage/default/39.hmac_smoke.2339726373 Jan 03 01:05:56 PM PST 24 Jan 03 01:07:20 PM PST 24 74669196 ps
T774 /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.691561143 Jan 03 01:05:38 PM PST 24 Jan 03 01:23:47 PM PST 24 548082576567 ps
T775 /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.7884260 Jan 03 01:05:47 PM PST 24 Jan 03 01:41:28 PM PST 24 46412615580 ps
T776 /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.1015324178 Jan 03 01:05:27 PM PST 24 Jan 03 01:21:28 PM PST 24 140301890156 ps
T777 /workspace/coverage/default/31.hmac_wipe_secret.429323919 Jan 03 01:05:10 PM PST 24 Jan 03 01:06:42 PM PST 24 650267429 ps
T778 /workspace/coverage/default/6.hmac_alert_test.357863602 Jan 03 01:04:24 PM PST 24 Jan 03 01:05:43 PM PST 24 14690839 ps
T779 /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.2587510073 Jan 03 01:06:03 PM PST 24 Jan 03 02:06:05 PM PST 24 181105934109 ps
T780 /workspace/coverage/default/13.hmac_smoke.1429641912 Jan 03 01:04:47 PM PST 24 Jan 03 01:06:10 PM PST 24 73624925 ps
T781 /workspace/coverage/default/42.hmac_smoke.1592476214 Jan 03 01:05:31 PM PST 24 Jan 03 01:06:52 PM PST 24 406157732 ps
T782 /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.1224229521 Jan 03 01:05:43 PM PST 24 Jan 03 02:03:02 PM PST 24 80821768352 ps
T783 /workspace/coverage/default/22.hmac_test_sha_vectors.3015792834 Jan 03 01:05:12 PM PST 24 Jan 03 01:12:59 PM PST 24 41628335642 ps
T784 /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.3678448426 Jan 03 01:05:49 PM PST 24 Jan 03 01:17:55 PM PST 24 36610023750 ps
T785 /workspace/coverage/default/36.hmac_alert_test.2004145648 Jan 03 01:05:31 PM PST 24 Jan 03 01:06:50 PM PST 24 116139624 ps
T786 /workspace/coverage/default/43.hmac_long_msg.781413239 Jan 03 01:05:19 PM PST 24 Jan 03 01:07:53 PM PST 24 2966799622 ps
T787 /workspace/coverage/default/44.hmac_error.1569846342 Jan 03 01:05:25 PM PST 24 Jan 03 01:07:05 PM PST 24 320960006 ps
T788 /workspace/coverage/default/21.hmac_alert_test.1336066699 Jan 03 01:05:22 PM PST 24 Jan 03 01:06:39 PM PST 24 43295576 ps
T789 /workspace/coverage/default/0.hmac_long_msg.1994342618 Jan 03 01:04:30 PM PST 24 Jan 03 01:07:31 PM PST 24 15750226663 ps
T790 /workspace/coverage/default/24.hmac_stress_all.2887231 Jan 03 01:05:01 PM PST 24 Jan 03 01:25:25 PM PST 24 69478393045 ps
T791 /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.167223906 Jan 03 01:05:31 PM PST 24 Jan 03 01:15:33 PM PST 24 55254563525 ps
T792 /workspace/coverage/default/39.hmac_back_pressure.1704804019 Jan 03 01:05:27 PM PST 24 Jan 03 01:06:59 PM PST 24 510538071 ps
T114 /workspace/coverage/default/38.hmac_stress_all.3739904289 Jan 03 01:05:05 PM PST 24 Jan 03 01:20:22 PM PST 24 107573550096 ps
T793 /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.4220648155 Jan 03 01:05:16 PM PST 24 Jan 03 01:17:36 PM PST 24 386040480424 ps
T794 /workspace/coverage/default/13.hmac_stress_all.2669941718 Jan 03 01:05:04 PM PST 24 Jan 03 01:43:56 PM PST 24 193694005668 ps
T795 /workspace/coverage/default/45.hmac_stress_all.1416546357 Jan 03 01:05:27 PM PST 24 Jan 03 01:11:08 PM PST 24 6660161143 ps
T796 /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3030785720 Jan 03 01:05:47 PM PST 24 Jan 03 02:05:36 PM PST 24 306799401311 ps
T797 /workspace/coverage/default/19.hmac_test_hmac_vectors.2524434195 Jan 03 01:04:45 PM PST 24 Jan 03 01:06:05 PM PST 24 143638364 ps
T798 /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1214800606 Jan 03 01:05:50 PM PST 24 Jan 03 01:29:52 PM PST 24 666102739851 ps
T799 /workspace/coverage/default/1.hmac_test_hmac_vectors.1173061676 Jan 03 01:04:04 PM PST 24 Jan 03 01:05:10 PM PST 24 183526499 ps
T800 /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.1309860342 Jan 03 01:05:44 PM PST 24 Jan 03 01:21:18 PM PST 24 131546986519 ps
T801 /workspace/coverage/default/2.hmac_error.3616755985 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:37 PM PST 24 323924714 ps
T802 /workspace/coverage/default/21.hmac_test_hmac_vectors.4003834773 Jan 03 01:04:56 PM PST 24 Jan 03 01:06:18 PM PST 24 105563184 ps
T803 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1222434210 Jan 03 01:06:01 PM PST 24 Jan 03 01:30:43 PM PST 24 212461980346 ps
T804 /workspace/coverage/default/9.hmac_datapath_stress.3989195437 Jan 03 01:05:10 PM PST 24 Jan 03 01:08:49 PM PST 24 9722701730 ps
T805 /workspace/coverage/default/10.hmac_alert_test.2677640994 Jan 03 01:04:36 PM PST 24 Jan 03 01:06:05 PM PST 24 13371516 ps
T806 /workspace/coverage/default/36.hmac_datapath_stress.4131824164 Jan 03 01:05:23 PM PST 24 Jan 03 01:07:20 PM PST 24 3111020426 ps
T807 /workspace/coverage/default/26.hmac_test_sha_vectors.2111691013 Jan 03 01:04:57 PM PST 24 Jan 03 01:12:47 PM PST 24 33839782040 ps
T808 /workspace/coverage/default/4.hmac_burst_wr.304324920 Jan 03 01:04:43 PM PST 24 Jan 03 01:06:45 PM PST 24 3431772673 ps
T809 /workspace/coverage/default/0.hmac_alert_test.1115299115 Jan 03 01:04:19 PM PST 24 Jan 03 01:05:36 PM PST 24 26931992 ps
T810 /workspace/coverage/default/20.hmac_long_msg.407894204 Jan 03 01:04:44 PM PST 24 Jan 03 01:07:09 PM PST 24 1179618967 ps
T811 /workspace/coverage/default/8.hmac_back_pressure.2632135704 Jan 03 01:04:54 PM PST 24 Jan 03 01:06:27 PM PST 24 422400816 ps
T812 /workspace/coverage/default/4.hmac_stress_all.1558604866 Jan 03 01:05:05 PM PST 24 Jan 03 01:15:16 PM PST 24 15635429280 ps
T813 /workspace/coverage/default/13.hmac_error.1843115869 Jan 03 01:04:53 PM PST 24 Jan 03 01:07:07 PM PST 24 2255352759 ps
T814 /workspace/coverage/default/19.hmac_burst_wr.269395053 Jan 03 01:05:19 PM PST 24 Jan 03 01:07:25 PM PST 24 4039965307 ps
T815 /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.4232206942 Jan 03 01:05:56 PM PST 24 Jan 03 01:10:47 PM PST 24 289505419157 ps
T816 /workspace/coverage/default/45.hmac_burst_wr.2811952430 Jan 03 01:05:30 PM PST 24 Jan 03 01:06:53 PM PST 24 778237238 ps
T817 /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1914007124 Jan 03 01:05:58 PM PST 24 Jan 03 01:13:42 PM PST 24 158859971481 ps
T818 /workspace/coverage/default/24.hmac_error.26952004 Jan 03 01:05:41 PM PST 24 Jan 03 01:07:44 PM PST 24 2951451359 ps
T819 /workspace/coverage/default/18.hmac_datapath_stress.3328556854 Jan 03 01:05:12 PM PST 24 Jan 03 01:07:09 PM PST 24 3312448854 ps
T820 /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3986338999 Jan 03 01:05:33 PM PST 24 Jan 03 01:43:20 PM PST 24 151630236198 ps
T821 /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.358789996 Jan 03 01:06:03 PM PST 24 Jan 03 01:17:56 PM PST 24 12670250261 ps
T822 /workspace/coverage/default/32.hmac_error.4030554260 Jan 03 01:04:55 PM PST 24 Jan 03 01:08:44 PM PST 24 13503066690 ps
T823 /workspace/coverage/default/21.hmac_datapath_stress.4056561600 Jan 03 01:05:05 PM PST 24 Jan 03 01:06:46 PM PST 24 429977986 ps
T824 /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.2953962981 Jan 03 01:05:22 PM PST 24 Jan 03 01:12:24 PM PST 24 97651963710 ps
T825 /workspace/coverage/default/39.hmac_test_sha_vectors.1690303794 Jan 03 01:06:00 PM PST 24 Jan 03 01:14:39 PM PST 24 68380315201 ps
T826 /workspace/coverage/default/2.hmac_stress_all.3788134731 Jan 03 01:04:46 PM PST 24 Jan 03 01:16:47 PM PST 24 13194931922 ps
T827 /workspace/coverage/default/17.hmac_datapath_stress.3183321083 Jan 03 01:05:07 PM PST 24 Jan 03 01:07:48 PM PST 24 1598749785 ps
T828 /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.2148126750 Jan 03 01:05:51 PM PST 24 Jan 03 01:22:32 PM PST 24 31417599343 ps
T829 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.31143091 Jan 03 01:05:55 PM PST 24 Jan 03 02:20:32 PM PST 24 195421579397 ps
T830 /workspace/coverage/default/25.hmac_datapath_stress.1577982998 Jan 03 01:04:56 PM PST 24 Jan 03 01:07:38 PM PST 24 3196130911 ps
T831 /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.784199330 Jan 03 01:05:23 PM PST 24 Jan 03 02:03:40 PM PST 24 76899333202 ps
T832 /workspace/coverage/default/28.hmac_error.1349823941 Jan 03 01:05:19 PM PST 24 Jan 03 01:07:35 PM PST 24 4861312530 ps
T833 /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2236141213 Jan 03 01:05:51 PM PST 24 Jan 03 01:30:03 PM PST 24 29685058717 ps
T834 /workspace/coverage/default/32.hmac_wipe_secret.1827464436 Jan 03 01:05:33 PM PST 24 Jan 03 01:07:38 PM PST 24 2908200180 ps
T835 /workspace/coverage/default/12.hmac_burst_wr.296802629 Jan 03 01:04:55 PM PST 24 Jan 03 01:06:33 PM PST 24 4036910602 ps
T836 /workspace/coverage/default/22.hmac_wipe_secret.1113194301 Jan 03 01:05:16 PM PST 24 Jan 03 01:07:16 PM PST 24 6260735571 ps
T837 /workspace/coverage/default/16.hmac_smoke.3508925564 Jan 03 01:04:48 PM PST 24 Jan 03 01:06:08 PM PST 24 86251065 ps
T838 /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3681591081 Jan 03 01:05:54 PM PST 24 Jan 03 01:33:08 PM PST 24 60931950708 ps
T839 /workspace/coverage/default/18.hmac_test_sha_vectors.613109754 Jan 03 01:05:11 PM PST 24 Jan 03 01:13:41 PM PST 24 40950947184 ps
T840 /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.330587703 Jan 03 01:06:01 PM PST 24 Jan 03 01:22:16 PM PST 24 86149874921 ps
T841 /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1792001546 Jan 03 01:05:34 PM PST 24 Jan 03 01:20:34 PM PST 24 113164398650 ps
T842 /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.1528683967 Jan 03 01:05:05 PM PST 24 Jan 03 02:16:52 PM PST 24 363565642772 ps
T843 /workspace/coverage/default/7.hmac_back_pressure.2972951468 Jan 03 01:04:30 PM PST 24 Jan 03 01:06:17 PM PST 24 786521949 ps
T844 /workspace/coverage/default/37.hmac_smoke.578867378 Jan 03 01:05:26 PM PST 24 Jan 03 01:06:47 PM PST 24 846086612 ps
T845 /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.1604982571 Jan 03 01:05:54 PM PST 24 Jan 03 01:25:35 PM PST 24 103588306817 ps
T846 /workspace/coverage/default/14.hmac_back_pressure.1082104883 Jan 03 01:04:53 PM PST 24 Jan 03 01:06:23 PM PST 24 997993296 ps
T847 /workspace/coverage/default/15.hmac_stress_all.555775090 Jan 03 01:04:46 PM PST 24 Jan 03 01:19:10 PM PST 24 48060244569 ps
T848 /workspace/coverage/default/33.hmac_test_hmac_vectors.2049781064 Jan 03 01:05:10 PM PST 24 Jan 03 01:06:41 PM PST 24 581605304 ps
T849 /workspace/coverage/default/15.hmac_back_pressure.147691467 Jan 03 01:04:55 PM PST 24 Jan 03 01:07:05 PM PST 24 1591731561 ps
T850 /workspace/coverage/default/25.hmac_test_sha_vectors.78288854 Jan 03 01:05:16 PM PST 24 Jan 03 01:12:49 PM PST 24 32422739085 ps
T851 /workspace/coverage/default/16.hmac_burst_wr.2973617354 Jan 03 01:04:48 PM PST 24 Jan 03 01:06:17 PM PST 24 633511058 ps
T852 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3764446108 Jan 03 01:05:38 PM PST 24 Jan 03 01:28:48 PM PST 24 374883524017 ps
T853 /workspace/coverage/default/25.hmac_wipe_secret.67843496 Jan 03 01:05:04 PM PST 24 Jan 03 01:07:06 PM PST 24 26067345223 ps
T854 /workspace/coverage/default/33.hmac_stress_all.2320451793 Jan 03 01:05:04 PM PST 24 Jan 03 01:09:47 PM PST 24 11641766445 ps
T855 /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.1793320003 Jan 03 01:05:48 PM PST 24 Jan 03 01:38:16 PM PST 24 231050663472 ps
T856 /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.1386496458 Jan 03 01:05:43 PM PST 24 Jan 03 02:04:15 PM PST 24 298741590831 ps
T857 /workspace/coverage/default/48.hmac_test_sha_vectors.1505737541 Jan 03 01:05:13 PM PST 24 Jan 03 01:13:40 PM PST 24 156614258957 ps
T858 /workspace/coverage/default/24.hmac_alert_test.886893364 Jan 03 01:05:22 PM PST 24 Jan 03 01:06:40 PM PST 24 24807093 ps
T859 /workspace/coverage/default/11.hmac_test_hmac_vectors.1589665090 Jan 03 01:04:48 PM PST 24 Jan 03 01:06:08 PM PST 24 150699683 ps
T860 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2201614096 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:48 PM PST 24 53591887 ps
T861 /workspace/coverage/cover_reg_top/8.hmac_intr_test.309950485 Jan 03 12:50:40 PM PST 24 Jan 03 12:51:05 PM PST 24 16285807 ps
T862 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2390547570 Jan 03 12:49:51 PM PST 24 Jan 03 12:50:07 PM PST 24 24445375 ps
T863 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3747816166 Jan 03 12:50:39 PM PST 24 Jan 03 12:51:05 PM PST 24 70028323 ps
T864 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3293326327 Jan 03 12:50:31 PM PST 24 Jan 03 12:50:56 PM PST 24 24159925 ps
T80 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2100540625 Jan 03 12:51:11 PM PST 24 Jan 03 12:51:29 PM PST 24 71732439 ps
T81 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2142626883 Jan 03 12:50:13 PM PST 24 Jan 03 12:50:37 PM PST 24 50269008 ps
T865 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3928427785 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:34 PM PST 24 52660936 ps
T866 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1498934025 Jan 03 12:50:30 PM PST 24 Jan 03 12:50:54 PM PST 24 15247273 ps
T867 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2845784870 Jan 03 12:49:52 PM PST 24 Jan 03 12:50:08 PM PST 24 16269458 ps
T868 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3908019205 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:54 PM PST 24 40098409 ps
T869 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2636874526 Jan 03 12:50:38 PM PST 24 Jan 03 12:51:03 PM PST 24 45176942 ps
T870 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2145208402 Jan 03 12:50:41 PM PST 24 Jan 03 12:51:06 PM PST 24 53560029 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.199985167 Jan 03 12:50:23 PM PST 24 Jan 03 12:50:48 PM PST 24 149385003 ps
T871 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1328623422 Jan 03 12:50:19 PM PST 24 Jan 03 12:50:50 PM PST 24 1019127112 ps
T872 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.141087389 Jan 03 12:49:58 PM PST 24 Jan 03 12:50:23 PM PST 24 293058787 ps
T873 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1366597308 Jan 03 12:50:25 PM PST 24 Jan 03 12:50:48 PM PST 24 17849771 ps
T874 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1898121478 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 17529337 ps
T875 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2482346748 Jan 03 12:50:07 PM PST 24 Jan 03 12:50:36 PM PST 24 50909074 ps
T876 /workspace/coverage/cover_reg_top/4.hmac_intr_test.974603503 Jan 03 12:50:18 PM PST 24 Jan 03 12:50:41 PM PST 24 42531098 ps
T877 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.592464307 Jan 03 12:49:38 PM PST 24 Jan 03 12:49:53 PM PST 24 26861813 ps
T88 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2530143634 Jan 03 12:50:16 PM PST 24 Jan 03 12:50:40 PM PST 24 401059652 ps
T878 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.988448951 Jan 03 12:49:57 PM PST 24 Jan 03 12:50:19 PM PST 24 665248475 ps
T879 /workspace/coverage/cover_reg_top/26.hmac_intr_test.706118322 Jan 03 12:50:42 PM PST 24 Jan 03 12:51:07 PM PST 24 13574655 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3838612840 Jan 03 12:50:18 PM PST 24 Jan 03 12:50:46 PM PST 24 2921440808 ps
T880 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1517652644 Jan 03 12:49:59 PM PST 24 Jan 03 12:50:22 PM PST 24 77633482 ps
T881 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.17740677 Jan 03 12:50:18 PM PST 24 Jan 03 12:50:42 PM PST 24 59817263 ps
T882 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3436612977 Jan 03 12:50:33 PM PST 24 Jan 03 12:50:59 PM PST 24 354681466 ps
T883 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3234127550 Jan 03 12:50:14 PM PST 24 Jan 03 12:50:39 PM PST 24 293021289 ps
T884 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3460795934 Jan 03 12:50:08 PM PST 24 Jan 03 12:50:33 PM PST 24 40773879 ps
T885 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2608777759 Jan 03 12:50:17 PM PST 24 Jan 03 12:50:41 PM PST 24 66010010 ps
T886 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1044098015 Jan 03 12:50:23 PM PST 24 Jan 03 12:50:46 PM PST 24 55696249 ps
T887 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1045769114 Jan 03 12:50:00 PM PST 24 Jan 03 12:50:25 PM PST 24 28058662 ps
T888 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2690400523 Jan 03 12:49:46 PM PST 24 Jan 03 12:50:00 PM PST 24 188788967 ps
T889 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2480017833 Jan 03 12:50:21 PM PST 24 Jan 03 12:50:46 PM PST 24 547999551 ps
T890 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3042473683 Jan 03 12:50:12 PM PST 24 Jan 03 12:50:35 PM PST 24 16727004 ps
T89 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4244093128 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:39 PM PST 24 249535763 ps
T891 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2573126748 Jan 03 12:50:52 PM PST 24 Jan 03 12:51:16 PM PST 24 51669457 ps
T892 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2856963267 Jan 03 12:51:05 PM PST 24 Jan 03 12:51:25 PM PST 24 228668499 ps
T893 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1612002113 Jan 03 12:50:09 PM PST 24 Jan 03 12:50:35 PM PST 24 133078748 ps
T894 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.480695064 Jan 03 12:50:11 PM PST 24 Jan 03 12:50:39 PM PST 24 70828039 ps
T895 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4122370340 Jan 03 12:50:09 PM PST 24 Jan 03 12:50:33 PM PST 24 13966188 ps
T896 /workspace/coverage/cover_reg_top/31.hmac_intr_test.995581311 Jan 03 12:50:12 PM PST 24 Jan 03 12:50:36 PM PST 24 45294803 ps
T897 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1985287345 Jan 03 12:50:11 PM PST 24 Jan 03 12:50:34 PM PST 24 19893571 ps
T898 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3100652189 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 29919956 ps
T899 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.485687428 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:38 PM PST 24 90356216 ps
T900 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.475522733 Jan 03 12:50:10 PM PST 24 Jan 03 12:50:34 PM PST 24 222222194 ps
T901 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4111290579 Jan 03 12:50:14 PM PST 24 Jan 03 12:50:38 PM PST 24 39545182 ps
T902 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3107718202 Jan 03 12:50:15 PM PST 24 Jan 03 12:50:38 PM PST 24 22754255 ps
T903 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.574540687 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:31 PM PST 24 188220799 ps
T904 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.95256650 Jan 03 12:50:06 PM PST 24 Jan 03 12:50:31 PM PST 24 23118571 ps
T905 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3448842041 Jan 03 12:50:14 PM PST 24 Jan 03 12:50:38 PM PST 24 25111224 ps
T906 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2717784251 Jan 03 12:50:29 PM PST 24 Jan 03 12:50:54 PM PST 24 49937059 ps
T907 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3672134930 Jan 03 12:50:45 PM PST 24 Jan 03 12:51:09 PM PST 24 18465128 ps
T908 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3527668283 Jan 03 12:49:57 PM PST 24 Jan 03 12:50:20 PM PST 24 29006765 ps
T909 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.669996652 Jan 03 12:50:00 PM PST 24 Jan 03 12:50:25 PM PST 24 78665196 ps

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4101296332
Short name T13
Test name
Test status
Simulation time 85017994 ps
CPU time 1.38 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 192396 kb
Host smart-f649485b-3b58-425e-b41c-c2c864961df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101296332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4101296332
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2927467392
Short name T4
Test name
Test status
Simulation time 60754164347 ps
CPU time 2678.73 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:51:58 PM PST 24
Peak memory 248112 kb
Host smart-d8d1b8a5-a4dc-4095-8c6e-67a214df1e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927467392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.2927467392
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4075291577
Short name T20
Test name
Test status
Simulation time 111947245 ps
CPU time 1.71 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 198136 kb
Host smart-17fc4888-ba93-4f1b-bb17-90528d27f4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075291577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4075291577
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3281433252
Short name T24
Test name
Test status
Simulation time 13240150 ps
CPU time 0.58 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 183748 kb
Host smart-ce1faebd-2f0b-4fe1-b683-186a66439798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281433252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3281433252
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.278979652
Short name T23
Test name
Test status
Simulation time 156820896 ps
CPU time 2.81 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 198488 kb
Host smart-64120a54-fa5d-4e52-8960-232b10f4cafb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278979652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.278979652
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.1965556465
Short name T37
Test name
Test status
Simulation time 171962323898 ps
CPU time 3159.55 seconds
Started Jan 03 01:06:27 PM PST 24
Finished Jan 03 02:00:19 PM PST 24
Peak memory 224808 kb
Host smart-2e093b79-c023-47f4-8836-87e30276d3ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965556465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.1965556465
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.435887710
Short name T78
Test name
Test status
Simulation time 70078973 ps
CPU time 0.66 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:49:58 PM PST 24
Peak memory 194080 kb
Host smart-acc76984-3981-46bc-bb10-8f61fc527ee4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435887710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.435887710
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.31343679
Short name T49
Test name
Test status
Simulation time 229949370 ps
CPU time 0.82 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 215884 kb
Host smart-ac69e5b8-51b3-4d7d-af68-3868a0d36de7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.31343679
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.3411557185
Short name T101
Test name
Test status
Simulation time 253507346940 ps
CPU time 5597.9 seconds
Started Jan 03 01:06:02 PM PST 24
Finished Jan 03 02:40:50 PM PST 24
Peak memory 277348 kb
Host smart-c784450d-9809-41b3-88bf-8e7d9832bcc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411557185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.3411557185
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.791966501
Short name T95
Test name
Test status
Simulation time 170548589 ps
CPU time 2.39 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:49:58 PM PST 24
Peak memory 198276 kb
Host smart-ce3aba30-8838-4863-b02c-6edbe5bccb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791966501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.791966501
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.3258429706
Short name T99
Test name
Test status
Simulation time 303341862165 ps
CPU time 2761.59 seconds
Started Jan 03 01:06:10 PM PST 24
Finished Jan 03 01:53:31 PM PST 24
Peak memory 256248 kb
Host smart-1b828172-b285-43e9-af0a-42f5a48fd94b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258429706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.3258429706
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1871687363
Short name T171
Test name
Test status
Simulation time 32533298 ps
CPU time 1.12 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 198232 kb
Host smart-27f36b2b-5c5d-4932-be43-32f350062017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871687363 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1871687363
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2183028569
Short name T145
Test name
Test status
Simulation time 21330645 ps
CPU time 0.59 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 183664 kb
Host smart-4bef2792-5bd1-4334-8d6b-0f8fd5ce8ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183028569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2183028569
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.338278856
Short name T370
Test name
Test status
Simulation time 176390809371 ps
CPU time 4481.72 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 02:21:51 PM PST 24
Peak memory 261884 kb
Host smart-b60cb5ca-0555-4e3e-94f6-41d406c0d89c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338278856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.338278856
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.3925931930
Short name T129
Test name
Test status
Simulation time 43691644849 ps
CPU time 2060.51 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:41:30 PM PST 24
Peak memory 248104 kb
Host smart-669b8420-fc28-44e6-8cd3-0f647ddb4264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925931930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.3925931930
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3687526849
Short name T67
Test name
Test status
Simulation time 223810771 ps
CPU time 1.69 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 198164 kb
Host smart-8ca3d0ec-d638-429c-b3cc-d3e7dee7a3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687526849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3687526849
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2192959807
Short name T126
Test name
Test status
Simulation time 125254894239 ps
CPU time 1019.48 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:24:10 PM PST 24
Peak memory 241860 kb
Host smart-83cb45d4-c568-4075-9cdc-2e5047e1eab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192959807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.2192959807
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2567072095
Short name T244
Test name
Test status
Simulation time 14990058 ps
CPU time 0.56 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:06:20 PM PST 24
Peak memory 193132 kb
Host smart-7347d84f-2c2d-4b02-b8f8-883756d38f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567072095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2567072095
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_error.1646105690
Short name T198
Test name
Test status
Simulation time 37868538144 ps
CPU time 100.43 seconds
Started Jan 03 01:04:46 PM PST 24
Finished Jan 03 01:07:49 PM PST 24
Peak memory 198876 kb
Host smart-e0ca7d3c-4cd8-4d01-9bfe-670aa6d46596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646105690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1646105690
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2191785910
Short name T113
Test name
Test status
Simulation time 100073390441 ps
CPU time 2268.2 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:44:54 PM PST 24
Peak memory 231500 kb
Host smart-5ac2871b-f507-43c6-81e1-2643115fad0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191785910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.2191785910
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.2030455830
Short name T130
Test name
Test status
Simulation time 160355494450 ps
CPU time 1098.17 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:25:30 PM PST 24
Peak memory 223580 kb
Host smart-95ceecc2-7c41-4b33-9566-f9cf9a438b6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030455830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.2030455830
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3669942024
Short name T128
Test name
Test status
Simulation time 669769434923 ps
CPU time 2085.51 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:41:58 PM PST 24
Peak memory 247596 kb
Host smart-267cc5ec-c496-471c-a57a-a495cfe435e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669942024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.3669942024
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.344699886
Short name T120
Test name
Test status
Simulation time 1826693606 ps
CPU time 33.03 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198716 kb
Host smart-19ba45a5-aab8-4113-98ee-7b17ee237395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344699886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.344699886
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3305295438
Short name T63
Test name
Test status
Simulation time 158209129 ps
CPU time 2.35 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 198324 kb
Host smart-85d4d375-d16f-4aa4-817c-44d4b15de467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305295438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3305295438
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2690400523
Short name T888
Test name
Test status
Simulation time 188788967 ps
CPU time 1.79 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 192164 kb
Host smart-d72c1ac7-600d-4166-a66a-42676ad4f5c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690400523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2690400523
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.289191742
Short name T149
Test name
Test status
Simulation time 1811586010 ps
CPU time 5.8 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 195832 kb
Host smart-496858a9-16fc-455e-9ea0-d882a1f1cda5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289191742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.289191742
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.485687428
Short name T899
Test name
Test status
Simulation time 90356216 ps
CPU time 0.64 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 193948 kb
Host smart-000d1ced-d910-404c-bf9b-6f0ce6f92650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485687428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.485687428
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.4044491472
Short name T161
Test name
Test status
Simulation time 17340339 ps
CPU time 0.62 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 183612 kb
Host smart-ad1ebf92-295d-4173-9f15-10e5a6368b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044491472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.4044491472
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3632311794
Short name T163
Test name
Test status
Simulation time 184087467 ps
CPU time 3.04 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 198604 kb
Host smart-811cd968-32ee-447f-bff4-3a38ce4a77f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632311794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3632311794
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2107059410
Short name T32
Test name
Test status
Simulation time 1066226011 ps
CPU time 2.55 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 191952 kb
Host smart-e4c3ccd8-8a41-4b78-ac46-d0de59a9c89f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107059410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2107059410
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.984998926
Short name T175
Test name
Test status
Simulation time 2259888023 ps
CPU time 6.22 seconds
Started Jan 03 12:51:15 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 191952 kb
Host smart-ef1f1e01-4980-4bf0-acd2-c3e4d2391b8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984998926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.984998926
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1498934025
Short name T866
Test name
Test status
Simulation time 15247273 ps
CPU time 0.66 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 193336 kb
Host smart-84327b78-f7ff-42ac-b10e-bb8ec0ce8719
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498934025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1498934025
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.98254109
Short name T31
Test name
Test status
Simulation time 35527712 ps
CPU time 0.78 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 198360 kb
Host smart-f361ed2e-4ff0-45a5-8263-20f206524703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98254109 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.98254109
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2100540625
Short name T80
Test name
Test status
Simulation time 71732439 ps
CPU time 0.69 seconds
Started Jan 03 12:51:11 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 194472 kb
Host smart-aa9484b7-bb00-428b-96bf-56adf505ac20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100540625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2100540625
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2856963267
Short name T892
Test name
Test status
Simulation time 228668499 ps
CPU time 0.53 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:51:25 PM PST 24
Peak memory 183448 kb
Host smart-1ca4e47a-9a30-4f19-b1a3-5f93d68a7dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856963267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2856963267
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1436801210
Short name T71
Test name
Test status
Simulation time 291416094 ps
CPU time 1.02 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 191824 kb
Host smart-c99ceae6-5e94-48da-b444-54405827a724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436801210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1436801210
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.988448951
Short name T878
Test name
Test status
Simulation time 665248475 ps
CPU time 1.72 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 198452 kb
Host smart-dc3c0b21-6346-4490-9357-b18aed61c82d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988448951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.988448951
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.199985167
Short name T96
Test name
Test status
Simulation time 149385003 ps
CPU time 2.2 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 197988 kb
Host smart-004b1e18-e6db-419b-a06b-2fe0cd111409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199985167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.199985167
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3356618049
Short name T136
Test name
Test status
Simulation time 23066628 ps
CPU time 1.62 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 198520 kb
Host smart-7484fe61-cbf3-449f-90fd-9fb82024b510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356618049 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3356618049
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.669996652
Short name T909
Test name
Test status
Simulation time 78665196 ps
CPU time 0.72 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:25 PM PST 24
Peak memory 194552 kb
Host smart-38b5d9bb-a53e-45b5-b3e9-41f856d16e47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669996652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.669996652
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2145208402
Short name T870
Test name
Test status
Simulation time 53560029 ps
CPU time 0.53 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 183720 kb
Host smart-f81014dc-af8f-4f5c-ada5-b52a266bf7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145208402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2145208402
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1045769114
Short name T887
Test name
Test status
Simulation time 28058662 ps
CPU time 0.76 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:25 PM PST 24
Peak memory 191908 kb
Host smart-72e6185c-b95d-4ee5-93a6-085223caf792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045769114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1045769114
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3838612840
Short name T91
Test name
Test status
Simulation time 2921440808 ps
CPU time 3.08 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 198604 kb
Host smart-b08a0aeb-34c8-451f-89e0-fe43b19faa38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838612840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3838612840
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.95256650
Short name T904
Test name
Test status
Simulation time 23118571 ps
CPU time 1.01 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 198392 kb
Host smart-f6483571-9f8f-48f1-9a88-2b6c8f053701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95256650 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.95256650
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1898121478
Short name T874
Test name
Test status
Simulation time 17529337 ps
CPU time 0.61 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 193724 kb
Host smart-170244d5-4552-44c3-9e3c-a0efd2895199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898121478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1898121478
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.459959110
Short name T144
Test name
Test status
Simulation time 45957414 ps
CPU time 0.61 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 183604 kb
Host smart-fb281d63-59b0-430b-a1ef-16c0ff045278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459959110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.459959110
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4138241066
Short name T85
Test name
Test status
Simulation time 59952991 ps
CPU time 0.78 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 195136 kb
Host smart-2550705d-5a41-4dd1-9327-4aea61a470ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138241066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4138241066
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2482346748
Short name T875
Test name
Test status
Simulation time 50909074 ps
CPU time 2.74 seconds
Started Jan 03 12:50:07 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 198540 kb
Host smart-277d37f9-fdb8-464b-b33f-19b7981d9846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482346748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2482346748
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1045159198
Short name T187
Test name
Test status
Simulation time 82495650 ps
CPU time 1.7 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 198264 kb
Host smart-a5c87cad-3d59-4da8-ac24-5adf00850147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045159198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1045159198
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.285237547
Short name T28
Test name
Test status
Simulation time 41199374 ps
CPU time 1.14 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 198256 kb
Host smart-c2566e67-36a9-404c-b84c-8dbdd1feaeeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285237547 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.285237547
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2493858461
Short name T183
Test name
Test status
Simulation time 50081991 ps
CPU time 0.64 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 194088 kb
Host smart-652fd780-3a52-436f-a131-6b78e45ab3bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493858461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2493858461
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1517652644
Short name T880
Test name
Test status
Simulation time 77633482 ps
CPU time 0.57 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 183680 kb
Host smart-2c5eed8a-8a62-43fa-8848-939862631d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517652644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1517652644
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2717784251
Short name T906
Test name
Test status
Simulation time 49937059 ps
CPU time 0.98 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 191980 kb
Host smart-bc40f7aa-1f1d-4bfb-a78e-c05bd2764d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717784251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2717784251
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1612002113
Short name T893
Test name
Test status
Simulation time 133078748 ps
CPU time 2.91 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 198504 kb
Host smart-284533e8-53f5-4d74-9db6-29a8db396d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612002113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1612002113
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.207777354
Short name T86
Test name
Test status
Simulation time 22468235 ps
CPU time 1.37 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 198428 kb
Host smart-a25fa7e9-3090-4813-8569-41a9141ae0f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207777354 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.207777354
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1821376140
Short name T79
Test name
Test status
Simulation time 26545251 ps
CPU time 0.67 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 194380 kb
Host smart-fcf7b171-4928-4206-952d-509a25e9fba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821376140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1821376140
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1726716578
Short name T166
Test name
Test status
Simulation time 45942118 ps
CPU time 0.57 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 183620 kb
Host smart-05b4b564-5ed5-4df2-a44e-3f2d52529870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726716578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1726716578
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1799575612
Short name T16
Test name
Test status
Simulation time 17907211 ps
CPU time 0.78 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 191932 kb
Host smart-7dae79a5-6c44-4e52-aae4-3c32b60e4993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799575612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1799575612
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3289388112
Short name T22
Test name
Test status
Simulation time 283904815 ps
CPU time 1.51 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 198548 kb
Host smart-1c9ffb87-07d4-408d-b39a-2ea4f2ab0146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289388112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3289388112
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3474684738
Short name T162
Test name
Test status
Simulation time 189374489 ps
CPU time 1.75 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:58 PM PST 24
Peak memory 198104 kb
Host smart-8530ce74-703d-4031-8e53-c9c91302fa86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474684738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3474684738
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.863408399
Short name T135
Test name
Test status
Simulation time 31514421 ps
CPU time 2.41 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 198572 kb
Host smart-e17cf1ed-d215-4372-8835-c3cb01324e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863408399 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.863408399
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.574540687
Short name T903
Test name
Test status
Simulation time 188220799 ps
CPU time 0.73 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 194776 kb
Host smart-5c933397-d8ed-4da2-915c-512e54e580df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574540687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.574540687
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.399638633
Short name T177
Test name
Test status
Simulation time 12763412 ps
CPU time 0.58 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:09 PM PST 24
Peak memory 183656 kb
Host smart-8b9366d8-1f0b-4b6d-934f-5b1f2a5b3b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399638633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.399638633
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.736357588
Short name T173
Test name
Test status
Simulation time 211092722 ps
CPU time 1.03 seconds
Started Jan 03 12:50:22 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 192156 kb
Host smart-34bfdcfe-f3fb-42c4-9dc6-b7a3abbdb0e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736357588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.736357588
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2480017833
Short name T889
Test name
Test status
Simulation time 547999551 ps
CPU time 3.11 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 198516 kb
Host smart-a518473e-66b2-40cd-9357-bdbdeacdaa50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480017833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2480017833
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2189986578
Short name T94
Test name
Test status
Simulation time 47704513 ps
CPU time 1.09 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 197580 kb
Host smart-90dc2608-34ec-41c2-97ac-caf7effdd0d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189986578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2189986578
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.222379045
Short name T179
Test name
Test status
Simulation time 40176500 ps
CPU time 1.72 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 198412 kb
Host smart-b93b6d19-2eb7-4d9a-91e2-faeba880dbad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222379045 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.222379045
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2142626883
Short name T81
Test name
Test status
Simulation time 50269008 ps
CPU time 0.59 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 193756 kb
Host smart-f4b6b061-2ec4-4142-b731-f0f482b57675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142626883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2142626883
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.790583747
Short name T176
Test name
Test status
Simulation time 14744604 ps
CPU time 0.56 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 183732 kb
Host smart-f4e3589f-bbdc-4966-a42b-80f9e662af7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790583747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.790583747
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2573126748
Short name T891
Test name
Test status
Simulation time 51669457 ps
CPU time 1.1 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 196844 kb
Host smart-0853d6ee-8178-434b-93f4-6098b6096490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573126748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2573126748
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3988842808
Short name T26
Test name
Test status
Simulation time 149340808 ps
CPU time 2.64 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 198512 kb
Host smart-3830c959-fd1f-4180-a0c8-94d13f8b6d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988842808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3988842808
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4244093128
Short name T89
Test name
Test status
Simulation time 249535763 ps
CPU time 1.18 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 197860 kb
Host smart-8d0463ea-25ad-48dc-9e1c-e96d021dcdf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244093128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4244093128
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3448842041
Short name T905
Test name
Test status
Simulation time 25111224 ps
CPU time 1.53 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 198524 kb
Host smart-bbc010dd-d9d9-471c-83b1-c08ab881b392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448842041 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3448842041
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4036486983
Short name T191
Test name
Test status
Simulation time 12759908 ps
CPU time 0.58 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 193872 kb
Host smart-9721efe0-d1bc-460b-a7e1-dc86175806e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036486983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4036486983
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3959009478
Short name T186
Test name
Test status
Simulation time 51017479 ps
CPU time 1.05 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:58 PM PST 24
Peak memory 192068 kb
Host smart-ee09b88a-bde6-40ca-9c69-d43307f3a315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959009478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3959009478
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.582270486
Short name T27
Test name
Test status
Simulation time 359677057 ps
CPU time 3.39 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 198484 kb
Host smart-35855bee-06d2-4d6e-8547-79a6c3b8ebff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582270486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.582270486
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.445338388
Short name T34
Test name
Test status
Simulation time 295031687 ps
CPU time 1.85 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 198252 kb
Host smart-c7c38e9a-9015-461b-ba34-b7374b1b8306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445338388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.445338388
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3471254304
Short name T160
Test name
Test status
Simulation time 21155235 ps
CPU time 1.24 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 198500 kb
Host smart-8687ab9b-0003-441a-84c4-b8e17dac6e11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471254304 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3471254304
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1797004361
Short name T74
Test name
Test status
Simulation time 47033865 ps
CPU time 0.73 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 194628 kb
Host smart-8c33cecb-1276-4d06-b699-cc8a51587b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797004361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1797004361
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2189957379
Short name T159
Test name
Test status
Simulation time 18954163 ps
CPU time 0.53 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 183676 kb
Host smart-31b4161e-dd16-47b2-ad88-78cd779e13c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189957379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2189957379
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3908019205
Short name T868
Test name
Test status
Simulation time 40098409 ps
CPU time 1.31 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 196232 kb
Host smart-1378efb0-3522-4e5e-a962-30eaad364d07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908019205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3908019205
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3514203205
Short name T151
Test name
Test status
Simulation time 78570072 ps
CPU time 1.27 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 198516 kb
Host smart-a8a16d4f-4429-40bb-ab8b-a1d8909d37c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514203205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3514203205
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2155894930
Short name T93
Test name
Test status
Simulation time 44125464 ps
CPU time 1.13 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 197968 kb
Host smart-19b762ef-6343-4109-a23e-2ebf52198d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155894930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2155894930
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2608777759
Short name T885
Test name
Test status
Simulation time 66010010 ps
CPU time 1.55 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 198488 kb
Host smart-928cd182-82fa-4b78-b06e-198b8dd009ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608777759 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2608777759
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.59584000
Short name T77
Test name
Test status
Simulation time 21731393 ps
CPU time 0.8 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 194160 kb
Host smart-00aa2bc2-0dc8-4a58-86b9-feeb92de96ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59584000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.59584000
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3677146595
Short name T17
Test name
Test status
Simulation time 22475090 ps
CPU time 0.59 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 183664 kb
Host smart-5f0333c5-95d6-4e69-af41-0f32c0c29fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677146595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3677146595
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455645897
Short name T152
Test name
Test status
Simulation time 71591765 ps
CPU time 1.33 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 192124 kb
Host smart-eeb28efa-5ddc-4f53-8959-9243bdb838d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455645897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2455645897
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4206744505
Short name T180
Test name
Test status
Simulation time 55539015 ps
CPU time 1.25 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:01 PM PST 24
Peak memory 198512 kb
Host smart-8a03d7c0-b1ed-41aa-bf73-50cf45464251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206744505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4206744505
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2314580681
Short name T90
Test name
Test status
Simulation time 48124624 ps
CPU time 1.14 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 197844 kb
Host smart-9dae1f4e-cb85-4909-aa00-4510b6d74484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314580681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2314580681
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3221823688
Short name T155
Test name
Test status
Simulation time 86294537842 ps
CPU time 751.63 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 208116 kb
Host smart-de505779-9b42-43c9-b6cb-3891805902f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221823688 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3221823688
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2909424295
Short name T148
Test name
Test status
Simulation time 62312448 ps
CPU time 0.71 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 194356 kb
Host smart-1633af9d-68ad-4c37-ae0b-54fd3738df26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909424295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2909424295
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1985287345
Short name T897
Test name
Test status
Simulation time 19893571 ps
CPU time 0.57 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 183652 kb
Host smart-b9700fdb-72f8-4caf-8fa2-57d7d4e0031d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985287345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1985287345
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1737080321
Short name T141
Test name
Test status
Simulation time 50159595 ps
CPU time 0.77 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 191744 kb
Host smart-d2ff4b9a-aff5-4cd8-844c-27385e685817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737080321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1737080321
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.123043730
Short name T30
Test name
Test status
Simulation time 119518041 ps
CPU time 2.58 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 198648 kb
Host smart-50a091a7-7614-4e28-87f2-77c0b900cacd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123043730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.123043730
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3614791641
Short name T143
Test name
Test status
Simulation time 236482705 ps
CPU time 1.73 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 198180 kb
Host smart-ae856f3f-a324-4b75-806b-43a09ef77c75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614791641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3614791641
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1985210758
Short name T33
Test name
Test status
Simulation time 94437661 ps
CPU time 1.75 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 192108 kb
Host smart-aac2da3c-7656-4ab0-b1a6-cfcae789471d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985210758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1985210758
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3864014909
Short name T153
Test name
Test status
Simulation time 1001623575 ps
CPU time 9.37 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:04 PM PST 24
Peak memory 192068 kb
Host smart-47afdd18-45c2-4bf2-9882-17a34e90c845
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864014909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3864014909
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.226536638
Short name T68
Test name
Test status
Simulation time 18315264 ps
CPU time 0.69 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 194064 kb
Host smart-cb4739ee-9fb2-4f47-a319-61d8283074ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226536638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.226536638
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.592464307
Short name T877
Test name
Test status
Simulation time 26861813 ps
CPU time 1.42 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 198396 kb
Host smart-da39fc2c-7523-451f-b724-2b85a2982348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592464307 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.592464307
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1279056817
Short name T75
Test name
Test status
Simulation time 12585669 ps
CPU time 0.65 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 193804 kb
Host smart-5ffc46e1-5b12-45cc-874b-b0ec43eebb97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279056817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1279056817
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2390547570
Short name T862
Test name
Test status
Simulation time 24445375 ps
CPU time 0.52 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 183600 kb
Host smart-b4759c36-48d2-49df-9f82-dafd0fe5f3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390547570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2390547570
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1053067414
Short name T19
Test name
Test status
Simulation time 1074647386 ps
CPU time 1.3 seconds
Started Jan 03 12:50:16 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 196604 kb
Host smart-15b5b218-b5c5-4051-bff8-5182577cd650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053067414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1053067414
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3234127550
Short name T883
Test name
Test status
Simulation time 293021289 ps
CPU time 2.81 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 198456 kb
Host smart-f0604584-06ad-4282-af2c-12a48f03dd10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234127550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3234127550
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1187537839
Short name T64
Test name
Test status
Simulation time 100063671 ps
CPU time 1.1 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 196320 kb
Host smart-3548c09f-36e6-490d-9e4e-8e45f22ea215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187537839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1187537839
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3081625327
Short name T140
Test name
Test status
Simulation time 15601310 ps
CPU time 0.54 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 183744 kb
Host smart-0b02f318-a87b-4569-a5ab-8338476939ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081625327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3081625327
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3107718202
Short name T902
Test name
Test status
Simulation time 22754255 ps
CPU time 0.55 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 183748 kb
Host smart-6c0e12cb-a689-4b38-abdb-d671c6e4513f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107718202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3107718202
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3754132677
Short name T47
Test name
Test status
Simulation time 41731471 ps
CPU time 0.55 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 183636 kb
Host smart-f4213dcb-cc03-4904-a94b-225267b1dd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754132677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3754132677
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.370111010
Short name T87
Test name
Test status
Simulation time 106751243 ps
CPU time 0.57 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 183744 kb
Host smart-93c823ac-2f69-4a7d-bdc6-87ab0c7c85a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370111010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.370111010
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1034331970
Short name T181
Test name
Test status
Simulation time 44531623 ps
CPU time 0.57 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 183732 kb
Host smart-d5fdbfb5-b1ec-4843-a135-d688ac0bd131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034331970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1034331970
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.49615641
Short name T157
Test name
Test status
Simulation time 13180797 ps
CPU time 0.6 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:50:17 PM PST 24
Peak memory 183676 kb
Host smart-e385ab40-9872-4ab7-abc3-cb7df5a8f31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49615641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.49615641
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.706118322
Short name T879
Test name
Test status
Simulation time 13574655 ps
CPU time 0.55 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 183744 kb
Host smart-1c76db4c-e458-4393-8d2e-89c55fefc13f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706118322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.706118322
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.369179214
Short name T48
Test name
Test status
Simulation time 13611499 ps
CPU time 0.55 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 183800 kb
Host smart-c6ca8820-b938-4cc4-a5e3-d239c9c49a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369179214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.369179214
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.320405007
Short name T150
Test name
Test status
Simulation time 22923187 ps
CPU time 0.55 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 183636 kb
Host smart-58d188f2-387b-476b-ab25-02e3f4dfa72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320405007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.320405007
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2928291432
Short name T156
Test name
Test status
Simulation time 29106474 ps
CPU time 0.53 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 183604 kb
Host smart-0347bac7-2712-433b-ae23-96d5ea15ca9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928291432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2928291432
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.480695064
Short name T894
Test name
Test status
Simulation time 70828039 ps
CPU time 1.67 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 183816 kb
Host smart-dd519020-bb31-4e8d-8bbf-97b83621ae95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480695064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.480695064
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3486845184
Short name T14
Test name
Test status
Simulation time 1002067439 ps
CPU time 9.35 seconds
Started Jan 03 12:50:01 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 192056 kb
Host smart-b4425e46-b639-4809-ab69-8768f7779232
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486845184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3486845184
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4291667955
Short name T70
Test name
Test status
Simulation time 43407816 ps
CPU time 0.61 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 193128 kb
Host smart-ebd99c37-3116-4578-921a-2fc9a503a1f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291667955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4291667955
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3293326327
Short name T864
Test name
Test status
Simulation time 24159925 ps
CPU time 0.86 seconds
Started Jan 03 12:50:31 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 198264 kb
Host smart-7b3693ae-f73e-4a79-b603-cb270737fc76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293326327 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3293326327
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3394862079
Short name T182
Test name
Test status
Simulation time 24299913 ps
CPU time 0.71 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 194368 kb
Host smart-6951bf90-bc33-480f-8252-45cf56f09d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394862079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3394862079
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2551944034
Short name T142
Test name
Test status
Simulation time 35858660 ps
CPU time 0.55 seconds
Started Jan 03 12:50:28 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 183592 kb
Host smart-f258caf1-f705-42f3-bcfc-97c0337bf0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551944034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2551944034
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3134876894
Short name T15
Test name
Test status
Simulation time 378241794 ps
CPU time 1.02 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:50:02 PM PST 24
Peak memory 196784 kb
Host smart-1ebd350e-e1a9-4a22-8a2e-a770696c1d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134876894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3134876894
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.141087389
Short name T872
Test name
Test status
Simulation time 293058787 ps
CPU time 2.24 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 198448 kb
Host smart-40c3ddac-d4f6-4e48-9aff-ef8054fea201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141087389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.141087389
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1044098015
Short name T886
Test name
Test status
Simulation time 55696249 ps
CPU time 0.54 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 183588 kb
Host smart-41bd9f72-31c2-4a69-bb66-95e27ea5905b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044098015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1044098015
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.995581311
Short name T896
Test name
Test status
Simulation time 45294803 ps
CPU time 0.56 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 183552 kb
Host smart-58e5bc77-7019-460f-9826-61f3c5fe918e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995581311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.995581311
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.142042304
Short name T164
Test name
Test status
Simulation time 20452640 ps
CPU time 0.56 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 183744 kb
Host smart-c3816ba5-ce5d-4dfd-8f15-dd385400f6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142042304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.142042304
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1947477518
Short name T168
Test name
Test status
Simulation time 125646794 ps
CPU time 0.58 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 183736 kb
Host smart-c83b3ba9-1dbb-4add-a218-1e5e22755b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947477518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1947477518
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2845784870
Short name T867
Test name
Test status
Simulation time 16269458 ps
CPU time 0.58 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 183668 kb
Host smart-14e483a1-1445-42c4-a0a1-73a184f2f1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845784870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2845784870
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.307422757
Short name T66
Test name
Test status
Simulation time 54057502 ps
CPU time 0.56 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 183648 kb
Host smart-230d0a91-87c4-4d7a-a049-23731005c130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307422757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.307422757
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2708698795
Short name T137
Test name
Test status
Simulation time 45677408 ps
CPU time 0.59 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 183608 kb
Host smart-884e9d59-0700-42b8-b326-c5713ec16bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708698795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2708698795
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2273105516
Short name T184
Test name
Test status
Simulation time 51939907 ps
CPU time 0.58 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 183748 kb
Host smart-1767d6bc-053d-4661-901a-6007220fa13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273105516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2273105516
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4122370340
Short name T895
Test name
Test status
Simulation time 13966188 ps
CPU time 0.53 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 183744 kb
Host smart-e9d0e61b-4d9e-4ea9-802d-78bc97b30b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122370340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4122370340
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.155852414
Short name T21
Test name
Test status
Simulation time 16509657 ps
CPU time 0.54 seconds
Started Jan 03 12:50:16 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 183660 kb
Host smart-34c3f4ba-9027-49b7-a6e1-403373a9b044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155852414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.155852414
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4111290579
Short name T901
Test name
Test status
Simulation time 39545182 ps
CPU time 1.73 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 192052 kb
Host smart-20c7d25a-fea4-4dd5-ac58-72c21b243042
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111290579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4111290579
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1328623422
Short name T871
Test name
Test status
Simulation time 1019127112 ps
CPU time 9.01 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 192108 kb
Host smart-4754e6cc-e929-46ee-891c-1d4ed0099b14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328623422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1328623422
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3956613060
Short name T185
Test name
Test status
Simulation time 67854855 ps
CPU time 0.66 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:53 PM PST 24
Peak memory 193928 kb
Host smart-a0c45d46-5468-4390-929f-1d2a67bae91f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956613060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3956613060
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1673688665
Short name T188
Test name
Test status
Simulation time 68103787 ps
CPU time 1.8 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 198436 kb
Host smart-ba564494-925a-4d1f-a488-9192cbcce351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673688665 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1673688665
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3100652189
Short name T898
Test name
Test status
Simulation time 29919956 ps
CPU time 0.74 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 194684 kb
Host smart-e823b118-4fe9-4901-91e3-7c384788e8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100652189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3100652189
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.974603503
Short name T876
Test name
Test status
Simulation time 42531098 ps
CPU time 0.55 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 183580 kb
Host smart-efd1b893-4ceb-4498-865f-41be953ca015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974603503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.974603503
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1612857863
Short name T73
Test name
Test status
Simulation time 138945859 ps
CPU time 0.82 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 191748 kb
Host smart-2e6f4feb-1d26-403e-8e65-46da673d1a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612857863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1612857863
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.17740677
Short name T881
Test name
Test status
Simulation time 59817263 ps
CPU time 1.58 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 198608 kb
Host smart-bbc0569b-066d-44cd-9e78-56e3aa519472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17740677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.17740677
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2848032982
Short name T92
Test name
Test status
Simulation time 84072141 ps
CPU time 1.13 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 197884 kb
Host smart-f7cfdd30-2f1d-403e-9ff2-4e84593a790a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848032982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2848032982
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.226150033
Short name T138
Test name
Test status
Simulation time 45471745 ps
CPU time 0.55 seconds
Started Jan 03 12:50:28 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 183572 kb
Host smart-e7b16fc8-df64-468f-8f04-7f61fb819383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226150033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.226150033
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1513349559
Short name T167
Test name
Test status
Simulation time 125636634 ps
CPU time 0.59 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 183660 kb
Host smart-3b98e4f9-79bb-4ae3-9203-5f2eeccda2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513349559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1513349559
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2651005996
Short name T174
Test name
Test status
Simulation time 109225027 ps
CPU time 0.6 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 183608 kb
Host smart-61435262-6f13-4daf-a5f0-fdc3c39627ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651005996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2651005996
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1366597308
Short name T873
Test name
Test status
Simulation time 17849771 ps
CPU time 0.58 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 183744 kb
Host smart-3a47a4f0-1429-4993-8c1f-647b55014f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366597308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1366597308
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.579431936
Short name T193
Test name
Test status
Simulation time 18423515 ps
CPU time 0.55 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 183676 kb
Host smart-10e881de-cb77-4623-a4d0-fcc50f97aeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579431936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.579431936
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2636874526
Short name T869
Test name
Test status
Simulation time 45176942 ps
CPU time 0.54 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 183676 kb
Host smart-3105dc88-d7ab-49cc-bbc3-12dacc868264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636874526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2636874526
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3042473683
Short name T890
Test name
Test status
Simulation time 16727004 ps
CPU time 0.58 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 183744 kb
Host smart-cd1b9646-6946-4ab3-8138-21d177971132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042473683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3042473683
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3021039823
Short name T139
Test name
Test status
Simulation time 22667833 ps
CPU time 0.55 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 183644 kb
Host smart-de86830f-bbc6-4daf-b660-cab796aae3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021039823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3021039823
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.554371269
Short name T158
Test name
Test status
Simulation time 63885205 ps
CPU time 0.57 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 183568 kb
Host smart-b2d91b8e-ae46-4a87-9f9a-2e0bdeacd180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554371269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.554371269
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3277641584
Short name T154
Test name
Test status
Simulation time 36590445 ps
CPU time 0.57 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 183724 kb
Host smart-57896dbd-e9a8-4a67-b04f-094fa1415e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277641584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3277641584
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3374380158
Short name T29
Test name
Test status
Simulation time 44681964 ps
CPU time 1.26 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 198432 kb
Host smart-595954db-be0b-4064-a4e8-6c7d80148b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374380158 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3374380158
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.825686659
Short name T147
Test name
Test status
Simulation time 13596906 ps
CPU time 0.62 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 194036 kb
Host smart-daec6e04-9148-43be-8855-5a284461b90c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825686659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.825686659
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2516793016
Short name T192
Test name
Test status
Simulation time 31848125 ps
CPU time 0.53 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 183744 kb
Host smart-d4f994e5-b5db-4842-86ff-bfe73cfaec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516793016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2516793016
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3524750029
Short name T65
Test name
Test status
Simulation time 52699553 ps
CPU time 1.07 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 192080 kb
Host smart-4ab73d46-cf1e-4494-b783-cc9559b6c595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524750029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3524750029
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2030321577
Short name T25
Test name
Test status
Simulation time 328873075 ps
CPU time 1.91 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 198456 kb
Host smart-550a7072-5e8e-4647-b4a3-a1f7b8a07bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030321577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2030321577
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2614165639
Short name T172
Test name
Test status
Simulation time 380635950 ps
CPU time 1.78 seconds
Started Jan 03 12:50:04 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 198264 kb
Host smart-f75a870d-29b6-4259-a173-039303b4c0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614165639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2614165639
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3747816166
Short name T863
Test name
Test status
Simulation time 70028323 ps
CPU time 0.97 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 198340 kb
Host smart-3816836c-a0bb-4dfb-b1be-30894f2f0ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747816166 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3747816166
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2201614096
Short name T860
Test name
Test status
Simulation time 53591887 ps
CPU time 0.72 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 194672 kb
Host smart-35383b03-a77b-4d9e-93d7-858246a37cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201614096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2201614096
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3650494390
Short name T178
Test name
Test status
Simulation time 51092043 ps
CPU time 1.1 seconds
Started Jan 03 12:50:35 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 192056 kb
Host smart-83fb8246-2d6f-49f4-b4af-e64936b34e70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650494390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3650494390
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2720892330
Short name T165
Test name
Test status
Simulation time 49960865 ps
CPU time 1.46 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 198492 kb
Host smart-cfe4459a-c315-464f-9de3-201609fa6bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720892330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2720892330
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.475522733
Short name T900
Test name
Test status
Simulation time 222222194 ps
CPU time 1.21 seconds
Started Jan 03 12:50:10 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 197864 kb
Host smart-f243a462-b774-4308-970b-6dd81094754d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475522733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.475522733
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3460795934
Short name T884
Test name
Test status
Simulation time 40773879 ps
CPU time 1.76 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 198440 kb
Host smart-dfd0679a-019f-49e5-b9bd-b1243e812b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460795934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3460795934
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2798752649
Short name T189
Test name
Test status
Simulation time 37073799 ps
CPU time 0.7 seconds
Started Jan 03 12:50:07 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 194572 kb
Host smart-95eab5cf-e944-49a2-9b15-13d8bab8347a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798752649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2798752649
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3672134930
Short name T907
Test name
Test status
Simulation time 18465128 ps
CPU time 0.58 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:09 PM PST 24
Peak memory 183636 kb
Host smart-3d585fd9-3039-4db0-81a0-3f792c169b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672134930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3672134930
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3076428528
Short name T72
Test name
Test status
Simulation time 115326797 ps
CPU time 1.33 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 192164 kb
Host smart-5f2b463b-06e4-4632-be7d-63223d3ab857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076428528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3076428528
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3436612977
Short name T882
Test name
Test status
Simulation time 354681466 ps
CPU time 2.36 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 198632 kb
Host smart-bfa19f8d-37bd-4782-84a7-6cea1816dd0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436612977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3436612977
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1566774710
Short name T62
Test name
Test status
Simulation time 167774596 ps
CPU time 1.17 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 197720 kb
Host smart-bba28589-e0ce-47e6-8f6f-a8e18b7eaf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566774710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1566774710
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3527668283
Short name T908
Test name
Test status
Simulation time 29006765 ps
CPU time 1.05 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:20 PM PST 24
Peak memory 198244 kb
Host smart-5962abaa-36ad-4c30-ac81-2bed21767f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527668283 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3527668283
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.269597248
Short name T76
Test name
Test status
Simulation time 14116107 ps
CPU time 0.67 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 194356 kb
Host smart-a17a4d98-1093-4ef2-964d-8eadc4fc0f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269597248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.269597248
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.309950485
Short name T861
Test name
Test status
Simulation time 16285807 ps
CPU time 0.6 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 183604 kb
Host smart-516b9e1b-39f5-450c-adc4-2faa6bd92de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309950485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.309950485
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2183733040
Short name T69
Test name
Test status
Simulation time 58404146 ps
CPU time 1.1 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 192068 kb
Host smart-1a9fbbd1-0fbd-4955-86f8-544a8e17d89a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183733040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2183733040
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1864120668
Short name T170
Test name
Test status
Simulation time 222840336 ps
CPU time 3.94 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 198504 kb
Host smart-3d7b4d34-27dc-44e1-8131-6b457a65ba88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864120668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1864120668
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2530143634
Short name T88
Test name
Test status
Simulation time 401059652 ps
CPU time 2.35 seconds
Started Jan 03 12:50:16 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 198120 kb
Host smart-7961ab43-0048-45f3-997e-05e2f1e91f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530143634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2530143634
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1608276961
Short name T190
Test name
Test status
Simulation time 314704996 ps
CPU time 1.51 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 198540 kb
Host smart-21496bfe-300c-4c4f-8576-e1d1c65a93d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608276961 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1608276961
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3928427785
Short name T865
Test name
Test status
Simulation time 52660936 ps
CPU time 0.66 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 194188 kb
Host smart-ea9d9f3b-909d-4c03-a4ac-79327829fcbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928427785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3928427785
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2481970329
Short name T146
Test name
Test status
Simulation time 12830651 ps
CPU time 0.61 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 183752 kb
Host smart-417a4b24-2ab2-495d-959e-0a81df3169bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481970329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2481970329
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.843654166
Short name T169
Test name
Test status
Simulation time 44072788 ps
CPU time 0.71 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:24 PM PST 24
Peak memory 191816 kb
Host smart-02ef846e-d077-4257-beff-904b757a03c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843654166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.843654166
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3703977333
Short name T18
Test name
Test status
Simulation time 32232228 ps
CPU time 1.73 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 198488 kb
Host smart-d6679f33-81ff-4ee2-8491-d12e7e4f3eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703977333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3703977333
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1115299115
Short name T809
Test name
Test status
Simulation time 26931992 ps
CPU time 0.57 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 193056 kb
Host smart-2644089e-151f-485d-bb06-2d5fe8e420b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115299115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1115299115
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2309361861
Short name T647
Test name
Test status
Simulation time 850839118 ps
CPU time 6.13 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:49 PM PST 24
Peak memory 198748 kb
Host smart-daaa6f8e-7169-44cb-b683-9caf769c87f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309361861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2309361861
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2482468739
Short name T688
Test name
Test status
Simulation time 3429796508 ps
CPU time 9.16 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 198824 kb
Host smart-209f6b0b-a1a5-43d0-ab33-bfb3d126c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482468739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2482468739
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.721753896
Short name T749
Test name
Test status
Simulation time 1545758566 ps
CPU time 79.13 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 198688 kb
Host smart-8105af3e-606d-49fd-805a-fafd3d3694d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721753896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.721753896
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1693349451
Short name T624
Test name
Test status
Simulation time 1903008289 ps
CPU time 91.36 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198688 kb
Host smart-885b8c32-787f-4e7f-b9a2-0ee38bcc16a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693349451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1693349451
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1994342618
Short name T789
Test name
Test status
Simulation time 15750226663 ps
CPU time 101.48 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:07:31 PM PST 24
Peak memory 198832 kb
Host smart-26f7bcb2-8cd8-4d96-9120-0d5eff3ca711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994342618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1994342618
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1858428300
Short name T52
Test name
Test status
Simulation time 101430718 ps
CPU time 0.96 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:06 PM PST 24
Peak memory 217124 kb
Host smart-fb6aac91-a53f-459f-a3ff-dc4ff2fcbf9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858428300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1858428300
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1087338862
Short name T596
Test name
Test status
Simulation time 280740678 ps
CPU time 3.05 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 198548 kb
Host smart-a97d50bb-3e62-4311-823d-976ebca4e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087338862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1087338862
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2017182721
Short name T512
Test name
Test status
Simulation time 103752234877 ps
CPU time 1249.71 seconds
Started Jan 03 01:04:36 PM PST 24
Finished Jan 03 01:27:05 PM PST 24
Peak memory 217272 kb
Host smart-c7d11b95-3dd3-4241-981b-d03a8d8a1c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017182721 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2017182721
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.905345613
Short name T690
Test name
Test status
Simulation time 151438816146 ps
CPU time 1017.89 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:22:29 PM PST 24
Peak memory 255904 kb
Host smart-ff9035fe-4c3a-4b89-8c74-721cec750f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905345613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.905345613
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1537143788
Short name T201
Test name
Test status
Simulation time 128342038 ps
CPU time 0.92 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:04 PM PST 24
Peak memory 196304 kb
Host smart-5bf1feab-7be3-40e3-be28-c370a3952f51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537143788 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1537143788
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1307628235
Short name T323
Test name
Test status
Simulation time 28668709061 ps
CPU time 442.84 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:13:10 PM PST 24
Peak memory 198752 kb
Host smart-dfd66b1e-2863-42fa-bdcb-f11e6ab7240c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307628235 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.1307628235
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3874361062
Short name T440
Test name
Test status
Simulation time 77444712276 ps
CPU time 74.13 seconds
Started Jan 03 01:04:29 PM PST 24
Finished Jan 03 01:07:06 PM PST 24
Peak memory 198832 kb
Host smart-4780687c-34aa-40ee-ad66-113fad0068d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874361062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3874361062
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2583370211
Short name T544
Test name
Test status
Simulation time 14550284 ps
CPU time 0.55 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 193112 kb
Host smart-f22805d7-7184-42c0-b4a8-c9120167af7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583370211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2583370211
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1426946559
Short name T629
Test name
Test status
Simulation time 3369314105 ps
CPU time 23.41 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:35 PM PST 24
Peak memory 216244 kb
Host smart-2fbaf51b-0e84-478c-b01b-5537b4abb14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426946559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1426946559
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.446344682
Short name T722
Test name
Test status
Simulation time 1356845257 ps
CPU time 9.46 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:49 PM PST 24
Peak memory 198644 kb
Host smart-f96a1888-2dfe-43e3-8d15-edf14fe9e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446344682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.446344682
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.831088834
Short name T259
Test name
Test status
Simulation time 2082657675 ps
CPU time 18.75 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:06:02 PM PST 24
Peak memory 198772 kb
Host smart-a56d4331-65a6-4a97-a3aa-cf4a38be5941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831088834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.831088834
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.627821711
Short name T12
Test name
Test status
Simulation time 3778515173 ps
CPU time 14.62 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 198800 kb
Host smart-3d213087-75bd-40a9-ac1d-110bf23dace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627821711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.627821711
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4221407307
Short name T628
Test name
Test status
Simulation time 72771456 ps
CPU time 3.64 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 198700 kb
Host smart-701e2e5f-a6d3-4456-a091-8adc156f739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221407307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4221407307
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.545884882
Short name T50
Test name
Test status
Simulation time 125623694 ps
CPU time 0.81 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 217112 kb
Host smart-62bfc644-d59b-4644-993b-6df54f11c962
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545884882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.545884882
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3030929041
Short name T290
Test name
Test status
Simulation time 683567142 ps
CPU time 1.7 seconds
Started Jan 03 01:04:34 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 198484 kb
Host smart-237122bc-acf6-46e2-baac-758ab2665169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030929041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3030929041
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3636560796
Short name T680
Test name
Test status
Simulation time 95897696293 ps
CPU time 1549.53 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:31:01 PM PST 24
Peak memory 231620 kb
Host smart-0ae5b2ad-d566-4b24-80f9-79f5ffd8f426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636560796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3636560796
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1377097520
Short name T335
Test name
Test status
Simulation time 81743600451 ps
CPU time 533.74 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 209016 kb
Host smart-61e6ac00-d65e-4bc6-8ad2-1a84e43d12ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377097520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1377097520
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1173061676
Short name T799
Test name
Test status
Simulation time 183526499 ps
CPU time 0.83 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:10 PM PST 24
Peak memory 195732 kb
Host smart-ac3671cd-9e8b-4a54-86cf-41fc771ea0ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173061676 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1173061676
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3672096540
Short name T213
Test name
Test status
Simulation time 27317521731 ps
CPU time 419.69 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:12:34 PM PST 24
Peak memory 198844 kb
Host smart-d516089b-fbf5-43a1-bc09-9fea16153edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672096540 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.3672096540
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2559962110
Short name T242
Test name
Test status
Simulation time 8939522830 ps
CPU time 36.73 seconds
Started Jan 03 01:04:38 PM PST 24
Finished Jan 03 01:06:37 PM PST 24
Peak memory 198816 kb
Host smart-9faf63e4-6822-4fe7-8b60-cf0f110d6145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559962110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2559962110
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2677640994
Short name T805
Test name
Test status
Simulation time 13371516 ps
CPU time 0.55 seconds
Started Jan 03 01:04:36 PM PST 24
Finished Jan 03 01:06:05 PM PST 24
Peak memory 193096 kb
Host smart-c1cfcada-8fbe-464a-bc7d-3600b039d8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677640994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2677640994
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.85322248
Short name T762
Test name
Test status
Simulation time 5399886499 ps
CPU time 32.94 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 206992 kb
Host smart-42fcdaac-2882-48f2-950d-ab6f7ce66aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85322248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.85322248
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2644964107
Short name T225
Test name
Test status
Simulation time 6776654979 ps
CPU time 34.59 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 01:07:35 PM PST 24
Peak memory 198856 kb
Host smart-fcd38698-7dfa-4086-b9de-fb98e479fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644964107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2644964107
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4094539898
Short name T755
Test name
Test status
Simulation time 13860849718 ps
CPU time 43.56 seconds
Started Jan 03 01:06:02 PM PST 24
Finished Jan 03 01:08:09 PM PST 24
Peak memory 198784 kb
Host smart-bbc81fcd-151f-4acd-bc45-3eca8e93b403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094539898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4094539898
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1750727662
Short name T428
Test name
Test status
Simulation time 1136939306 ps
CPU time 51.57 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:07:21 PM PST 24
Peak memory 198752 kb
Host smart-4a48e1c3-b899-41be-87cf-67fd2c79d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750727662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1750727662
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2291563211
Short name T592
Test name
Test status
Simulation time 5387620765 ps
CPU time 64.9 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:07:45 PM PST 24
Peak memory 198788 kb
Host smart-7b73c9c3-4b95-4cd9-be2a-b29413e5804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291563211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2291563211
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1244085087
Short name T273
Test name
Test status
Simulation time 1626223018 ps
CPU time 4.62 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 198708 kb
Host smart-65db2445-3f03-44af-9136-bcc5189ce53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244085087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1244085087
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3405115716
Short name T772
Test name
Test status
Simulation time 25084570537 ps
CPU time 1326.27 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:28:43 PM PST 24
Peak memory 198784 kb
Host smart-aae8cc5b-aa5b-4011-b1a0-33a177f6e7b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405115716 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3405115716
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1927047422
Short name T425
Test name
Test status
Simulation time 164691985273 ps
CPU time 502.49 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:14:28 PM PST 24
Peak memory 247332 kb
Host smart-80050dfc-4dac-4d39-abff-311b038950e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927047422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.1927047422
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.859167831
Short name T330
Test name
Test status
Simulation time 102554665 ps
CPU time 1.06 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 197120 kb
Host smart-892466c2-0409-44ef-b83e-efed6ac8f6e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859167831 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.859167831
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1653357177
Short name T35
Test name
Test status
Simulation time 7980102458 ps
CPU time 379.76 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 198780 kb
Host smart-70fd5c8a-1fa4-4560-80c0-a91b96d3b4b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653357177 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.1653357177
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4216861400
Short name T584
Test name
Test status
Simulation time 3206648174 ps
CPU time 31.49 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:58 PM PST 24
Peak memory 198828 kb
Host smart-0a3c1194-6ae8-45ff-a9b2-4bd2420ef569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216861400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4216861400
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2012373195
Short name T698
Test name
Test status
Simulation time 157088097067 ps
CPU time 1968.33 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:39:59 PM PST 24
Peak memory 223436 kb
Host smart-8e772cf2-1929-44b3-89e3-c6bc77035994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012373195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.2012373195
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.393684950
Short name T362
Test name
Test status
Simulation time 433488260887 ps
CPU time 3044.33 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:57:49 PM PST 24
Peak memory 261372 kb
Host smart-1750f1dd-0758-4f8e-b0fd-de9b204995a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393684950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.393684950
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2877459178
Short name T211
Test name
Test status
Simulation time 200065641012 ps
CPU time 1246.31 seconds
Started Jan 03 01:05:33 PM PST 24
Finished Jan 03 01:27:38 PM PST 24
Peak memory 215284 kb
Host smart-f7742a02-65ea-43f8-a8e0-5186763007e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877459178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.2877459178
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3986338999
Short name T820
Test name
Test status
Simulation time 151630236198 ps
CPU time 2188.8 seconds
Started Jan 03 01:05:33 PM PST 24
Finished Jan 03 01:43:20 PM PST 24
Peak memory 256208 kb
Host smart-8639331d-e819-4603-a298-8fb6d1cf687f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986338999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.3986338999
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.2360103023
Short name T637
Test name
Test status
Simulation time 57196868480 ps
CPU time 2515.88 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:49:04 PM PST 24
Peak memory 244396 kb
Host smart-428fad4f-cd35-46c1-8880-de038a3d7564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360103023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.2360103023
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1094345691
Short name T377
Test name
Test status
Simulation time 30972585267 ps
CPU time 1350.02 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 240852 kb
Host smart-b247e2a3-c5ff-4ac1-946e-889f80153681
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094345691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.1094345691
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2396059172
Short name T312
Test name
Test status
Simulation time 52251654784 ps
CPU time 181.4 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:09:54 PM PST 24
Peak memory 198944 kb
Host smart-ee498e2f-6d43-42e5-a92f-90b8e75f6e48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396059172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.2396059172
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.4240341216
Short name T580
Test name
Test status
Simulation time 71799035701 ps
CPU time 976.5 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:23:18 PM PST 24
Peak memory 248044 kb
Host smart-82ff62b0-e592-4899-b693-8b77e5f51cdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240341216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.4240341216
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.293230216
Short name T536
Test name
Test status
Simulation time 6292980136 ps
CPU time 41.43 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:47 PM PST 24
Peak memory 231404 kb
Host smart-1e151e8e-1edc-4d31-b8ee-f1ff868cc4f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293230216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.293230216
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1433521654
Short name T727
Test name
Test status
Simulation time 5180224327 ps
CPU time 58.93 seconds
Started Jan 03 01:04:32 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198744 kb
Host smart-aa91f5f3-2d9e-4c47-b05e-be83a91046b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433521654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1433521654
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.10529274
Short name T538
Test name
Test status
Simulation time 6138858298 ps
CPU time 80.88 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198820 kb
Host smart-d1f01b77-2285-4c14-9f91-8afbcf15e865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10529274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.10529274
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2550790444
Short name T395
Test name
Test status
Simulation time 2662209298 ps
CPU time 124.9 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:08:14 PM PST 24
Peak memory 198776 kb
Host smart-c614ca5d-d0c6-422d-9150-1c477a958fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550790444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2550790444
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.996411766
Short name T310
Test name
Test status
Simulation time 10990497616 ps
CPU time 67.73 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 198788 kb
Host smart-950e9f12-7512-4006-9c00-114bfadc9b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996411766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.996411766
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3551360568
Short name T531
Test name
Test status
Simulation time 185800367 ps
CPU time 2.65 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 198788 kb
Host smart-e935cbf4-d7a2-483d-b42a-3b5d50b0d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551360568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3551360568
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4284670689
Short name T392
Test name
Test status
Simulation time 162706139059 ps
CPU time 990.63 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:22:31 PM PST 24
Peak memory 239724 kb
Host smart-871d7a4b-44e2-44f4-95b9-4992826a4592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284670689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4284670689
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.344873665
Short name T743
Test name
Test status
Simulation time 62030464287 ps
CPU time 1652.39 seconds
Started Jan 03 01:04:59 PM PST 24
Finished Jan 03 01:33:55 PM PST 24
Peak memory 215212 kb
Host smart-1c11d911-4ced-4ee2-8060-048f6eda0c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344873665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.344873665
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1589665090
Short name T859
Test name
Test status
Simulation time 150699683 ps
CPU time 0.89 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 196320 kb
Host smart-546b4ba4-01f7-40af-98bc-194033c39126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589665090 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1589665090
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3292990085
Short name T737
Test name
Test status
Simulation time 143125541430 ps
CPU time 438.87 seconds
Started Jan 03 01:04:59 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 198836 kb
Host smart-68f116d7-72e7-4cd0-b62d-ef7beb136546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292990085 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.3292990085
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3480946379
Short name T543
Test name
Test status
Simulation time 3706406723 ps
CPU time 62.74 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 198792 kb
Host smart-72ec9902-d866-4db4-adbd-ab1def0f8245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480946379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3480946379
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.4232206942
Short name T815
Test name
Test status
Simulation time 289505419157 ps
CPU time 207.67 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:10:47 PM PST 24
Peak memory 207120 kb
Host smart-c4be0bf3-ea84-4794-9c35-10352b55e528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232206942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.4232206942
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.632582886
Short name T701
Test name
Test status
Simulation time 68168098974 ps
CPU time 641.37 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:17:54 PM PST 24
Peak memory 234696 kb
Host smart-9bc43ddd-6ecd-4b9c-a190-45dda9d1cadb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632582886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.632582886
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.1000120892
Short name T296
Test name
Test status
Simulation time 54686667488 ps
CPU time 1033.77 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:24:05 PM PST 24
Peak memory 223520 kb
Host smart-fb8b782b-adf0-41eb-9d5d-5df3573d0fff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000120892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.1000120892
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.1118348218
Short name T598
Test name
Test status
Simulation time 39130237799 ps
CPU time 703.76 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:18:48 PM PST 24
Peak memory 214668 kb
Host smart-10510780-8905-47dc-9505-7bddc492afa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118348218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.1118348218
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3424673627
Short name T109
Test name
Test status
Simulation time 76613953118 ps
CPU time 1083.41 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:24:56 PM PST 24
Peak memory 215280 kb
Host smart-2d29bbed-9bff-4b02-8790-dcaa7a7536ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424673627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.3424673627
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1857002415
Short name T474
Test name
Test status
Simulation time 11580617945 ps
CPU time 166.27 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:09:51 PM PST 24
Peak memory 207104 kb
Host smart-10fc0cfe-660b-408f-8dfd-0c927776b08a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857002415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.1857002415
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.7884260
Short name T775
Test name
Test status
Simulation time 46412615580 ps
CPU time 2062.69 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:41:28 PM PST 24
Peak memory 231628 kb
Host smart-eb21ab2a-310a-41b0-881e-de08dc2798f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7884260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.7884260
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.2927219710
Short name T402
Test name
Test status
Simulation time 109360090713 ps
CPU time 3873.72 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 254524 kb
Host smart-dff97327-48f4-4627-8239-fcce605593b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927219710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.2927219710
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.272248363
Short name T448
Test name
Test status
Simulation time 11460177359 ps
CPU time 175.82 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 01:09:57 PM PST 24
Peak memory 231212 kb
Host smart-8eff581c-d433-434b-be9f-088bcf38b8bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272248363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.272248363
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.167223906
Short name T791
Test name
Test status
Simulation time 55254563525 ps
CPU time 524.02 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:15:33 PM PST 24
Peak memory 241892 kb
Host smart-ee668b8c-3aef-4db8-a5b6-3e3fe8a1cab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167223906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.167223906
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2026688731
Short name T311
Test name
Test status
Simulation time 12878528 ps
CPU time 0.57 seconds
Started Jan 03 01:04:51 PM PST 24
Finished Jan 03 01:06:11 PM PST 24
Peak memory 193072 kb
Host smart-494a3f75-4e43-4b14-b73a-645c9151b807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026688731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2026688731
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1484118113
Short name T245
Test name
Test status
Simulation time 494083664 ps
CPU time 14.88 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:24 PM PST 24
Peak memory 206964 kb
Host smart-51aa4a87-34c3-4ee6-ae87-10a1d66b6ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484118113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1484118113
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.296802629
Short name T835
Test name
Test status
Simulation time 4036910602 ps
CPU time 15.02 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 198808 kb
Host smart-059e0e7d-6805-4359-8624-01347c7c1d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296802629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.296802629
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.123871397
Short name T332
Test name
Test status
Simulation time 2152938048 ps
CPU time 111.98 seconds
Started Jan 03 01:04:44 PM PST 24
Finished Jan 03 01:08:06 PM PST 24
Peak memory 198724 kb
Host smart-1e5dfad6-fa77-408c-baed-0a0ad0df4b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123871397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.123871397
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2856683955
Short name T266
Test name
Test status
Simulation time 6149354507 ps
CPU time 38.22 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:07:01 PM PST 24
Peak memory 198828 kb
Host smart-492052dc-eeeb-4073-aec1-fead694b7964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856683955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2856683955
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2223104469
Short name T433
Test name
Test status
Simulation time 113071554 ps
CPU time 1.84 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 198616 kb
Host smart-9f49796d-72f2-4353-8cc2-f1568d89b9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223104469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2223104469
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3010910865
Short name T288
Test name
Test status
Simulation time 41974845855 ps
CPU time 997.75 seconds
Started Jan 03 01:04:54 PM PST 24
Finished Jan 03 01:22:52 PM PST 24
Peak memory 236408 kb
Host smart-db56fb53-1fe3-4cff-8c71-41560b7b3c65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010910865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3010910865
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.668803871
Short name T84
Test name
Test status
Simulation time 169234272881 ps
CPU time 1916.32 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:38:18 PM PST 24
Peak memory 247636 kb
Host smart-fbdb9b31-f049-4612-abe9-0752476825af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668803871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.668803871
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1841112642
Short name T271
Test name
Test status
Simulation time 471443431 ps
CPU time 0.9 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 195536 kb
Host smart-258e56f1-6cb4-42e1-8f50-1e8f84dd70f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841112642 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1841112642
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2985898239
Short name T423
Test name
Test status
Simulation time 27640547747 ps
CPU time 416.34 seconds
Started Jan 03 01:04:44 PM PST 24
Finished Jan 03 01:13:11 PM PST 24
Peak memory 198744 kb
Host smart-3cf47f9a-0dae-41c4-9a73-508279b79199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985898239 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.2985898239
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.291480361
Short name T619
Test name
Test status
Simulation time 2758491481 ps
CPU time 46.69 seconds
Started Jan 03 01:04:54 PM PST 24
Finished Jan 03 01:07:01 PM PST 24
Peak memory 198800 kb
Host smart-8e56a664-7b6d-4dcf-9f8a-8b38053852eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291480361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.291480361
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2985963079
Short name T638
Test name
Test status
Simulation time 32736763081 ps
CPU time 474.09 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:15:09 PM PST 24
Peak memory 245472 kb
Host smart-b3ec2f0e-1ac8-4e45-bb7c-d74dfd53610d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985963079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2985963079
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.1374226645
Short name T236
Test name
Test status
Simulation time 32634835345 ps
CPU time 1437.67 seconds
Started Jan 03 01:05:35 PM PST 24
Finished Jan 03 01:30:51 PM PST 24
Peak memory 199664 kb
Host smart-3c6b1ccf-03a2-46ff-8735-978b503e583e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374226645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.1374226645
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.906337439
Short name T660
Test name
Test status
Simulation time 58257255563 ps
CPU time 2227.4 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:44:13 PM PST 24
Peak memory 229760 kb
Host smart-a4f1e48c-abbc-4304-833d-01c2ba98dcc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906337439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.906337439
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.2235631302
Short name T492
Test name
Test status
Simulation time 1213745551729 ps
CPU time 2368.64 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:46:41 PM PST 24
Peak memory 253108 kb
Host smart-ec09fcae-401b-49c9-b40d-570f09182ea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235631302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.2235631302
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.1386496458
Short name T856
Test name
Test status
Simulation time 298741590831 ps
CPU time 3432.48 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 02:04:15 PM PST 24
Peak memory 256376 kb
Host smart-5af8628e-f252-4ee2-b857-a9c55077bc70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386496458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.1386496458
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.1885587472
Short name T645
Test name
Test status
Simulation time 150872110291 ps
CPU time 718.47 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:19:13 PM PST 24
Peak memory 229624 kb
Host smart-a3721d2d-9280-49a8-97eb-99b30db8e9ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885587472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.1885587472
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.448107203
Short name T753
Test name
Test status
Simulation time 153460971179 ps
CPU time 672.38 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:18:01 PM PST 24
Peak memory 230692 kb
Host smart-81b8e0fd-a802-4b68-bff1-fff8be23f072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448107203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.448107203
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.1224229521
Short name T782
Test name
Test status
Simulation time 80821768352 ps
CPU time 3359.61 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 02:03:02 PM PST 24
Peak memory 244500 kb
Host smart-3924595a-9096-4bbb-a2b0-fd498b7a0bbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224229521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.1224229521
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.691561143
Short name T774
Test name
Test status
Simulation time 548082576567 ps
CPU time 1010.65 seconds
Started Jan 03 01:05:38 PM PST 24
Finished Jan 03 01:23:47 PM PST 24
Peak memory 210408 kb
Host smart-bbc533d9-ad7a-4014-98a9-56d1d27070c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691561143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.691561143
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.3548674536
Short name T381
Test name
Test status
Simulation time 337444268600 ps
CPU time 1180.98 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:26:49 PM PST 24
Peak memory 245516 kb
Host smart-cabb1b81-88fd-4b8e-807e-b26f92c82941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548674536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.3548674536
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4084329093
Short name T745
Test name
Test status
Simulation time 24084681 ps
CPU time 0.55 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:28 PM PST 24
Peak memory 193092 kb
Host smart-caa2d4e9-bd83-4e00-8170-d7450a57d2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084329093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4084329093
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3882964777
Short name T756
Test name
Test status
Simulation time 5015410658 ps
CPU time 26.64 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:10 PM PST 24
Peak memory 239784 kb
Host smart-cad32db0-b9f2-4f89-9c0a-e4a62c94f2ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882964777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3882964777
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.767922803
Short name T587
Test name
Test status
Simulation time 3147977094 ps
CPU time 10.46 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 198792 kb
Host smart-0ce99d99-7ce1-4b95-a566-02bee37122b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767922803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.767922803
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2246896357
Short name T611
Test name
Test status
Simulation time 4669915077 ps
CPU time 60.75 seconds
Started Jan 03 01:04:46 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 198808 kb
Host smart-fffe0375-48a2-45d3-9af3-dc39714bf28f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246896357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2246896357
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1843115869
Short name T813
Test name
Test status
Simulation time 2255352759 ps
CPU time 51.23 seconds
Started Jan 03 01:04:53 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 198764 kb
Host smart-c25fff7a-ccbe-496c-bd6f-7f199d43babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843115869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1843115869
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2955444266
Short name T589
Test name
Test status
Simulation time 1888600830 ps
CPU time 3.98 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 198116 kb
Host smart-42c850e8-2d0b-41ca-9ffd-a13c96a49886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955444266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2955444266
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1429641912
Short name T780
Test name
Test status
Simulation time 73624925 ps
CPU time 1.25 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 198100 kb
Host smart-3410f4cf-1bab-4158-ab29-b52a60e0a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429641912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1429641912
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2669941718
Short name T794
Test name
Test status
Simulation time 193694005668 ps
CPU time 2253.38 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:43:56 PM PST 24
Peak memory 245636 kb
Host smart-d2787a91-8740-4a18-97bf-6c363f10d511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669941718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2669941718
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.1588050878
Short name T234
Test name
Test status
Simulation time 54947552428 ps
CPU time 965.08 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:22:11 PM PST 24
Peak memory 237144 kb
Host smart-3f113448-7460-494f-9b76-005361cb67a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588050878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.1588050878
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3229127975
Short name T223
Test name
Test status
Simulation time 55966219 ps
CPU time 1.14 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 197472 kb
Host smart-9aeecb9a-e124-4236-8bc9-a8ea7e4ba0cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229127975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3229127975
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.716788549
Short name T444
Test name
Test status
Simulation time 7866959948 ps
CPU time 370.9 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:12:29 PM PST 24
Peak memory 198696 kb
Host smart-084a6f8b-3676-458f-b724-a9a230dbb22e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716788549 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_test_sha_vectors.716788549
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2360764772
Short name T546
Test name
Test status
Simulation time 1385969684 ps
CPU time 4.74 seconds
Started Jan 03 01:04:51 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 198696 kb
Host smart-73d41df9-48c3-49b8-abba-6e949da1ad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360764772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2360764772
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.3271917852
Short name T576
Test name
Test status
Simulation time 257697171213 ps
CPU time 1433.49 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:31:03 PM PST 24
Peak memory 226380 kb
Host smart-81072cef-0063-487d-97fc-9812f2d8cbfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271917852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.3271917852
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.1176781752
Short name T256
Test name
Test status
Simulation time 81588588810 ps
CPU time 3588.21 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 02:07:09 PM PST 24
Peak memory 248048 kb
Host smart-8ebab813-1ff4-4e1d-85a6-3fa068b9803a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176781752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.1176781752
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.3851993083
Short name T116
Test name
Test status
Simulation time 43169668864 ps
CPU time 826.58 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:20:59 PM PST 24
Peak memory 233576 kb
Host smart-4e479d34-5997-48ac-8e44-b538e37cefb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851993083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.3851993083
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.1604982571
Short name T845
Test name
Test status
Simulation time 103588306817 ps
CPU time 1099.36 seconds
Started Jan 03 01:05:54 PM PST 24
Finished Jan 03 01:25:35 PM PST 24
Peak memory 231724 kb
Host smart-68e336cd-ffad-4641-9754-a169cbda2816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604982571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.1604982571
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1214800606
Short name T798
Test name
Test status
Simulation time 666102739851 ps
CPU time 1362.03 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:29:52 PM PST 24
Peak memory 223844 kb
Host smart-adfc1751-1e10-4575-8455-ec42caa7de30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214800606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.1214800606
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1476901849
Short name T491
Test name
Test status
Simulation time 511194762589 ps
CPU time 1865.52 seconds
Started Jan 03 01:05:57 PM PST 24
Finished Jan 03 01:38:25 PM PST 24
Peak memory 258196 kb
Host smart-82405412-3d8d-4213-9475-e0d0dd6c16cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476901849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1476901849
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.2414102543
Short name T280
Test name
Test status
Simulation time 498750118049 ps
CPU time 1460.14 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:31:29 PM PST 24
Peak memory 266280 kb
Host smart-be0e536d-ad83-4c38-88bc-eec32cab4211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414102543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.2414102543
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3691166282
Short name T417
Test name
Test status
Simulation time 70728407674 ps
CPU time 1602.47 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:33:52 PM PST 24
Peak memory 230348 kb
Host smart-6e9f3170-ec28-4c08-8062-31d18bd8e3f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691166282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3691166282
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.2849023454
Short name T232
Test name
Test status
Simulation time 70813633491 ps
CPU time 930.03 seconds
Started Jan 03 01:05:54 PM PST 24
Finished Jan 03 01:22:46 PM PST 24
Peak memory 223408 kb
Host smart-e76287b9-a556-4b49-8694-9a60f9e7fa20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849023454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.2849023454
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.237293067
Short name T83
Test name
Test status
Simulation time 205662410774 ps
CPU time 947.39 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:22:56 PM PST 24
Peak memory 223508 kb
Host smart-ebf1c95e-3e16-4564-957f-0c10970128bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237293067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.237293067
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2287730716
Short name T365
Test name
Test status
Simulation time 38916504 ps
CPU time 0.55 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:25 PM PST 24
Peak memory 193088 kb
Host smart-c71ae814-1c76-48f9-bed6-c4d7f1d9a5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287730716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2287730716
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1082104883
Short name T846
Test name
Test status
Simulation time 997993296 ps
CPU time 7.44 seconds
Started Jan 03 01:04:53 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 214248 kb
Host smart-b9f60eb5-f9a1-4b07-95ba-1c4ec3df37b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082104883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1082104883
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2384555776
Short name T763
Test name
Test status
Simulation time 1337042820 ps
CPU time 12.19 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 198532 kb
Host smart-554a5bac-c5db-4fa6-9c34-55916a11b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384555776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2384555776
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3753926181
Short name T235
Test name
Test status
Simulation time 7710249087 ps
CPU time 88.32 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:08:00 PM PST 24
Peak memory 198824 kb
Host smart-48d5beed-6949-43cb-bb73-e4179bb25ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753926181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3753926181
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.291713323
Short name T350
Test name
Test status
Simulation time 12119384234 ps
CPU time 46.03 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:07:26 PM PST 24
Peak memory 198740 kb
Host smart-d5ee0f2b-3aa4-4425-8e3e-045c095c5c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291713323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.291713323
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.573696096
Short name T58
Test name
Test status
Simulation time 2710281630 ps
CPU time 19.21 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 198836 kb
Host smart-393a435e-aed2-4857-8ae8-ccd86f7256e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573696096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.573696096
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4083153693
Short name T447
Test name
Test status
Simulation time 354214195 ps
CPU time 4.37 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:06:19 PM PST 24
Peak memory 198672 kb
Host smart-388032c0-3a54-4bcf-a55b-4b5feb08e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083153693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4083153693
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1968711284
Short name T586
Test name
Test status
Simulation time 23385752375 ps
CPU time 1126.48 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:24:48 PM PST 24
Peak memory 214760 kb
Host smart-f0d9b0ca-b1da-409a-93e3-71e93bf41931
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968711284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1968711284
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.3832223746
Short name T570
Test name
Test status
Simulation time 11182574274 ps
CPU time 204.8 seconds
Started Jan 03 01:04:44 PM PST 24
Finished Jan 03 01:09:28 PM PST 24
Peak memory 214668 kb
Host smart-5124e028-4af4-411d-a151-79dd812a83f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832223746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.3832223746
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3233331547
Short name T716
Test name
Test status
Simulation time 250863064 ps
CPU time 0.99 seconds
Started Jan 03 01:04:53 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 196444 kb
Host smart-ec68edbf-50ab-4aa3-8260-abc983037e02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233331547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3233331547
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.532070391
Short name T415
Test name
Test status
Simulation time 32832073360 ps
CPU time 386.39 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:12:46 PM PST 24
Peak memory 198848 kb
Host smart-e1cd3dc3-f0ea-41a5-88cb-e8f6aaac2490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532070391 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.532070391
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2515980538
Short name T597
Test name
Test status
Simulation time 6688468226 ps
CPU time 47.76 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 198804 kb
Host smart-3559041f-c54e-4268-9b21-17d98e181001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515980538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2515980538
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.1105637423
Short name T696
Test name
Test status
Simulation time 33662104184 ps
CPU time 486.74 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:15:15 PM PST 24
Peak memory 228084 kb
Host smart-05539a32-27b7-4537-a1d0-12a86a6d2d2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105637423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.1105637423
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.2825913378
Short name T121
Test name
Test status
Simulation time 281971417194 ps
CPU time 1919.6 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:39:13 PM PST 24
Peak memory 255556 kb
Host smart-a828c1a3-4bb0-45e6-8904-cb459c4df52e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825913378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.2825913378
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.28435579
Short name T103
Test name
Test status
Simulation time 88388462404 ps
CPU time 2057.67 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:41:26 PM PST 24
Peak memory 255088 kb
Host smart-1843c764-a572-4ca9-ab53-0b7982e1c978
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28435579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.28435579
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.1309860342
Short name T800
Test name
Test status
Simulation time 131546986519 ps
CPU time 852.13 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:21:18 PM PST 24
Peak memory 239752 kb
Host smart-0f48554b-8bcf-49cc-ade0-77ce2f2162c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309860342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.1309860342
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.3228409794
Short name T422
Test name
Test status
Simulation time 1709011443693 ps
CPU time 1569.66 seconds
Started Jan 03 01:05:57 PM PST 24
Finished Jan 03 01:33:28 PM PST 24
Peak memory 245260 kb
Host smart-84b8811e-ee4a-4d73-9a8d-116b4f822e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228409794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.3228409794
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.31143091
Short name T829
Test name
Test status
Simulation time 195421579397 ps
CPU time 4394.35 seconds
Started Jan 03 01:05:55 PM PST 24
Finished Jan 03 02:20:32 PM PST 24
Peak memory 245560 kb
Host smart-86c9e295-02ac-43b7-ab3b-84491bd3ca23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31143091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.31143091
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.1267451628
Short name T496
Test name
Test status
Simulation time 216038975782 ps
CPU time 4522.89 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 02:22:44 PM PST 24
Peak memory 261612 kb
Host smart-791671f3-66b3-429d-b0d8-b719617d28f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267451628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.1267451628
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.4164204265
Short name T421
Test name
Test status
Simulation time 14642826242 ps
CPU time 258.21 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:11:32 PM PST 24
Peak memory 214652 kb
Host smart-7b4bec12-b4dd-4616-96c5-9de6fcd137f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164204265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.4164204265
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.3678448426
Short name T784
Test name
Test status
Simulation time 36610023750 ps
CPU time 644.24 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:17:55 PM PST 24
Peak memory 233728 kb
Host smart-b6829f1e-b502-4b53-915d-eee40afc50ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678448426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.3678448426
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2851336843
Short name T477
Test name
Test status
Simulation time 30017496 ps
CPU time 0.54 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 193104 kb
Host smart-17d1d97f-d46d-478d-be19-422c3d23498d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851336843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2851336843
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.147691467
Short name T849
Test name
Test status
Simulation time 1591731561 ps
CPU time 50.07 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 217912 kb
Host smart-c053b6c4-84f6-41a4-b512-98996c81ba5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147691467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.147691467
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3818828076
Short name T574
Test name
Test status
Simulation time 3480582607 ps
CPU time 14.91 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 198872 kb
Host smart-904ec929-3ccc-4f22-a195-5ff6d249aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818828076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3818828076
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3474186829
Short name T309
Test name
Test status
Simulation time 1716081321 ps
CPU time 19.38 seconds
Started Jan 03 01:04:52 PM PST 24
Finished Jan 03 01:06:30 PM PST 24
Peak memory 198660 kb
Host smart-35010a98-1860-4173-9381-848edb9f9a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474186829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3474186829
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1037345609
Short name T301
Test name
Test status
Simulation time 7056114459 ps
CPU time 21.14 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 198852 kb
Host smart-100ca401-69fc-4c62-be6f-a1f04a127c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037345609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1037345609
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4004570356
Short name T635
Test name
Test status
Simulation time 3509537331 ps
CPU time 30.26 seconds
Started Jan 03 01:04:37 PM PST 24
Finished Jan 03 01:06:28 PM PST 24
Peak memory 198772 kb
Host smart-0f6e4998-5211-4064-aec3-472efa1de7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004570356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4004570356
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3549645
Short name T254
Test name
Test status
Simulation time 44123623 ps
CPU time 0.71 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:07 PM PST 24
Peak memory 194568 kb
Host smart-9197049f-4901-4685-b35f-ea973d652c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3549645
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.555775090
Short name T847
Test name
Test status
Simulation time 48060244569 ps
CPU time 775.42 seconds
Started Jan 03 01:04:46 PM PST 24
Finished Jan 03 01:19:10 PM PST 24
Peak memory 198824 kb
Host smart-5abe75aa-0e6d-4145-b8f0-df89e9412918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555775090 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.555775090
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2276905775
Short name T612
Test name
Test status
Simulation time 58786872763 ps
CPU time 1928.52 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:38:07 PM PST 24
Peak memory 234812 kb
Host smart-a9172838-6b08-4bba-9756-7f89cf0ab9b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276905775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2276905775
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.350831816
Short name T746
Test name
Test status
Simulation time 28331800 ps
CPU time 0.87 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:06:21 PM PST 24
Peak memory 196028 kb
Host smart-f2071f52-8cd9-4e41-a408-4da7963956ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350831816 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.350831816
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3511301496
Short name T403
Test name
Test status
Simulation time 29827421706 ps
CPU time 465.64 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 198792 kb
Host smart-2afc233d-a99a-4a12-8b4d-e046594b45b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511301496 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.3511301496
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2747756639
Short name T568
Test name
Test status
Simulation time 16375629469 ps
CPU time 48.53 seconds
Started Jan 03 01:04:52 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 198824 kb
Host smart-a74e4331-9f22-49e9-83c7-9518ad72b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747756639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2747756639
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.283082118
Short name T529
Test name
Test status
Simulation time 6968720979 ps
CPU time 63.01 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:08:13 PM PST 24
Peak memory 198928 kb
Host smart-00b8d423-139e-476c-a2ab-7f80aa636c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283082118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.283082118
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.2339579282
Short name T687
Test name
Test status
Simulation time 199841652929 ps
CPU time 2263.52 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:44:59 PM PST 24
Peak memory 255660 kb
Host smart-5d049c09-02e9-4bc7-b1e2-5738671b955a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339579282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.2339579282
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.1003108044
Short name T643
Test name
Test status
Simulation time 60821014603 ps
CPU time 932.91 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:22:52 PM PST 24
Peak memory 245376 kb
Host smart-cf266208-a3cb-40e7-8037-36c211ca7b07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003108044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.1003108044
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3443248851
Short name T689
Test name
Test status
Simulation time 299279512477 ps
CPU time 475.12 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:15:05 PM PST 24
Peak memory 206992 kb
Host smart-efe68445-70a5-47df-a384-c6a52aeb5f36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443248851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.3443248851
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2220423738
Short name T486
Test name
Test status
Simulation time 84152664315 ps
CPU time 798.15 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:20:36 PM PST 24
Peak memory 240252 kb
Host smart-f7597006-d04a-47f0-9b46-dd32eff992ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220423738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2220423738
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.694770845
Short name T522
Test name
Test status
Simulation time 214963125476 ps
CPU time 1661.59 seconds
Started Jan 03 01:06:03 PM PST 24
Finished Jan 03 01:35:06 PM PST 24
Peak memory 221288 kb
Host smart-f6026022-806e-4f08-9f32-908d7cc7372d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694770845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.694770845
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.3864721736
Short name T741
Test name
Test status
Simulation time 292287507616 ps
CPU time 2274.98 seconds
Started Jan 03 01:05:59 PM PST 24
Finished Jan 03 01:45:17 PM PST 24
Peak memory 263384 kb
Host smart-bf4ba8e8-31af-49ba-a8b9-a1c714503326
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864721736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.3864721736
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1764763563
Short name T595
Test name
Test status
Simulation time 304163739440 ps
CPU time 1348.82 seconds
Started Jan 03 01:06:06 PM PST 24
Finished Jan 03 01:29:57 PM PST 24
Peak memory 239876 kb
Host smart-53669ef1-ece6-4d92-bf62-39259ae63ef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764763563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1764763563
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2016605653
Short name T585
Test name
Test status
Simulation time 31071693 ps
CPU time 0.54 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:06:22 PM PST 24
Peak memory 193108 kb
Host smart-512c3f32-e373-4188-8b2d-680bc7cbd8fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016605653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2016605653
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.43649875
Short name T251
Test name
Test status
Simulation time 5936983150 ps
CPU time 52.97 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:07:10 PM PST 24
Peak memory 228652 kb
Host smart-81e8d2ad-3389-411f-9ad9-e2d5978adc8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43649875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.43649875
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2973617354
Short name T851
Test name
Test status
Simulation time 633511058 ps
CPU time 10.25 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 198704 kb
Host smart-97e7de07-ca2a-4997-8b23-6d95aa35ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973617354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2973617354
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3545311843
Short name T221
Test name
Test status
Simulation time 1316162628 ps
CPU time 63.63 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:07:10 PM PST 24
Peak memory 198648 kb
Host smart-71885e4e-6281-4798-817a-d5818127edca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545311843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3545311843
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4271995332
Short name T578
Test name
Test status
Simulation time 6553476489 ps
CPU time 147.3 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:08:42 PM PST 24
Peak memory 198908 kb
Host smart-ffb1a14f-13a0-4aca-8700-cf119e04d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271995332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4271995332
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3222075163
Short name T439
Test name
Test status
Simulation time 53911762957 ps
CPU time 74.61 seconds
Started Jan 03 01:04:50 PM PST 24
Finished Jan 03 01:07:27 PM PST 24
Peak memory 198804 kb
Host smart-4355dce8-822c-489d-862a-1d636ef38e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222075163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3222075163
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3508925564
Short name T837
Test name
Test status
Simulation time 86251065 ps
CPU time 1.38 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 198456 kb
Host smart-38e6061b-9c1d-49f1-998d-9fa72cdee349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508925564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3508925564
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2021778111
Short name T710
Test name
Test status
Simulation time 26715054201 ps
CPU time 91.92 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:07:57 PM PST 24
Peak memory 198828 kb
Host smart-9b590218-415d-4c74-a642-97f100c95830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021778111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2021778111
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3707170894
Short name T262
Test name
Test status
Simulation time 108236686 ps
CPU time 0.88 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 196920 kb
Host smart-2ced54c8-60ba-4758-a6c1-a931f38943a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707170894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3707170894
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.799922929
Short name T372
Test name
Test status
Simulation time 50681958904 ps
CPU time 397.54 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:13:07 PM PST 24
Peak memory 198768 kb
Host smart-ce38d1ea-4a80-4a7c-bc35-93dddbe62cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799922929 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_sha_vectors.799922929
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1658955139
Short name T322
Test name
Test status
Simulation time 171426623 ps
CPU time 1.97 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 198744 kb
Host smart-5397211d-6026-4c2d-be7d-134317e0c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658955139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1658955139
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1028657853
Short name T528
Test name
Test status
Simulation time 232752480679 ps
CPU time 3315.63 seconds
Started Jan 03 01:05:59 PM PST 24
Finished Jan 03 02:02:38 PM PST 24
Peak memory 225624 kb
Host smart-84fe768e-14b7-444f-97f6-3c6846f80689
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028657853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.1028657853
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.2905879056
Short name T82
Test name
Test status
Simulation time 145395863880 ps
CPU time 500.19 seconds
Started Jan 03 01:05:55 PM PST 24
Finished Jan 03 01:15:36 PM PST 24
Peak memory 214352 kb
Host smart-8168ef13-40b8-4957-9f9a-b1e01e23c035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905879056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.2905879056
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.358789996
Short name T821
Test name
Test status
Simulation time 12670250261 ps
CPU time 629.9 seconds
Started Jan 03 01:06:03 PM PST 24
Finished Jan 03 01:17:56 PM PST 24
Peak memory 207036 kb
Host smart-9e356303-781e-425e-9a6a-848966e47b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358789996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.358789996
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.40364230
Short name T274
Test name
Test status
Simulation time 171159170704 ps
CPU time 508.3 seconds
Started Jan 03 01:06:00 PM PST 24
Finished Jan 03 01:15:50 PM PST 24
Peak memory 207160 kb
Host smart-e99094ab-5950-4937-9c19-4c55b408a212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40364230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.40364230
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.2148126750
Short name T828
Test name
Test status
Simulation time 31417599343 ps
CPU time 920.21 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:22:32 PM PST 24
Peak memory 245536 kb
Host smart-76aa5e68-6862-4265-8347-a2b471033e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148126750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.2148126750
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1914007124
Short name T817
Test name
Test status
Simulation time 158859971481 ps
CPU time 381.55 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 01:13:42 PM PST 24
Peak memory 214324 kb
Host smart-a102870f-0de6-4129-8157-3deb3380a759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914007124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1914007124
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.1480035902
Short name T418
Test name
Test status
Simulation time 505182470764 ps
CPU time 4760.5 seconds
Started Jan 03 01:05:55 PM PST 24
Finished Jan 03 02:26:39 PM PST 24
Peak memory 272704 kb
Host smart-5c437c18-7482-427f-b118-fa594f1071f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480035902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.1480035902
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1326727229
Short name T634
Test name
Test status
Simulation time 11176100030 ps
CPU time 208.87 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:10:40 PM PST 24
Peak memory 215228 kb
Host smart-efd9fca3-a891-49b2-b936-4bf9cf0339ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326727229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1326727229
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.482394036
Short name T518
Test name
Test status
Simulation time 167960796145 ps
CPU time 565.43 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 01:16:46 PM PST 24
Peak memory 246072 kb
Host smart-1b7e2d72-edea-434a-8615-0cdf976d07e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482394036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.482394036
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.66303356
Short name T489
Test name
Test status
Simulation time 22445291 ps
CPU time 0.57 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 194196 kb
Host smart-d4eb099c-0842-477c-8008-8bdc2212c2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66303356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.66303356
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1458143850
Short name T411
Test name
Test status
Simulation time 12231697841 ps
CPU time 23.48 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:54 PM PST 24
Peak memory 198820 kb
Host smart-3e3b9ad4-eba4-4052-b55a-aa002ca78df1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458143850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1458143850
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1705639898
Short name T358
Test name
Test status
Simulation time 11124569752 ps
CPU time 39.75 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 198856 kb
Host smart-f43a8472-2b6c-4bca-beed-135d8eb3fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705639898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1705639898
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3183321083
Short name T827
Test name
Test status
Simulation time 1598749785 ps
CPU time 81.42 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:07:48 PM PST 24
Peak memory 198680 kb
Host smart-493eeed8-19a2-4552-8093-ec5d4bf59dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183321083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3183321083
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2629591448
Short name T459
Test name
Test status
Simulation time 18771876843 ps
CPU time 104.72 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:08:16 PM PST 24
Peak memory 198832 kb
Host smart-cf1964d7-75f6-458f-b894-9abd037f4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629591448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2629591448
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4139081978
Short name T414
Test name
Test status
Simulation time 5839280045 ps
CPU time 36.54 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198776 kb
Host smart-e8391503-32f9-43fe-9460-c2971d1df253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139081978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4139081978
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1932963075
Short name T548
Test name
Test status
Simulation time 2360505737 ps
CPU time 2.74 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 198840 kb
Host smart-00fba57b-3a16-4876-8124-f4e898925a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932963075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1932963075
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2590105376
Short name T97
Test name
Test status
Simulation time 370809325706 ps
CPU time 817.34 seconds
Started Jan 03 01:07:49 PM PST 24
Finished Jan 03 01:22:39 PM PST 24
Peak memory 198804 kb
Host smart-60dc8234-7d11-4041-891e-8a6cfc143543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590105376 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2590105376
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.3406272030
Short name T313
Test name
Test status
Simulation time 913092594926 ps
CPU time 1134.1 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:25:38 PM PST 24
Peak memory 224452 kb
Host smart-51d70712-4486-499a-97b2-1499602a5599
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406272030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.3406272030
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.4155579963
Short name T641
Test name
Test status
Simulation time 46623096 ps
CPU time 0.91 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:26 PM PST 24
Peak memory 195684 kb
Host smart-bf011b70-aeae-43d5-b2f5-a3422b3e81a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155579963 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.4155579963
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.4072383520
Short name T327
Test name
Test status
Simulation time 41403023036 ps
CPU time 439.16 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 198788 kb
Host smart-dbc6ee95-1ba3-4874-a5c8-80085d3c8ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072383520 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.4072383520
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1397100522
Short name T349
Test name
Test status
Simulation time 348065348 ps
CPU time 16.7 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198636 kb
Host smart-1f5eba12-ed52-4756-9917-680d106859ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397100522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1397100522
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1222434210
Short name T803
Test name
Test status
Simulation time 212461980346 ps
CPU time 1399.61 seconds
Started Jan 03 01:06:01 PM PST 24
Finished Jan 03 01:30:43 PM PST 24
Peak memory 256268 kb
Host smart-53b09cd2-526b-4c85-8890-7a4950cfcdde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222434210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.1222434210
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.3080527115
Short name T700
Test name
Test status
Simulation time 186756903054 ps
CPU time 1163.19 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:26:38 PM PST 24
Peak memory 223440 kb
Host smart-a17d417b-b9c8-4a6e-b62f-713b4a50528a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080527115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.3080527115
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.2604357680
Short name T118
Test name
Test status
Simulation time 306409295614 ps
CPU time 3561.69 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 02:06:34 PM PST 24
Peak memory 264452 kb
Host smart-4978fcb0-6c0e-4eed-9e95-ba4d0f6f7c6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604357680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.2604357680
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.3629205409
Short name T626
Test name
Test status
Simulation time 55888209281 ps
CPU time 807.97 seconds
Started Jan 03 01:06:09 PM PST 24
Finished Jan 03 01:20:58 PM PST 24
Peak memory 240232 kb
Host smart-94d18713-57e0-4457-a460-4b35e2dd4cbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629205409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.3629205409
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.524576213
Short name T127
Test name
Test status
Simulation time 206675829988 ps
CPU time 4458.06 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 02:21:26 PM PST 24
Peak memory 264172 kb
Host smart-94d9e1b1-5f26-441f-95d6-93cf5144c1fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524576213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.524576213
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3681591081
Short name T838
Test name
Test status
Simulation time 60931950708 ps
CPU time 1551.69 seconds
Started Jan 03 01:05:54 PM PST 24
Finished Jan 03 01:33:08 PM PST 24
Peak memory 208532 kb
Host smart-a73c9acd-3705-458f-8a2d-c8fcef8d4784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681591081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.3681591081
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.3231559821
Short name T2
Test name
Test status
Simulation time 49360951095 ps
CPU time 345.61 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 241920 kb
Host smart-d5b9e8f7-62d1-4bdc-b456-cd41227815a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231559821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.3231559821
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.3205017208
Short name T59
Test name
Test status
Simulation time 60257136060 ps
CPU time 894.88 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:22:13 PM PST 24
Peak memory 231700 kb
Host smart-bb564a6b-9f22-4831-9224-a19b50e4cabc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205017208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.3205017208
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2893271077
Short name T291
Test name
Test status
Simulation time 48003733620 ps
CPU time 170.2 seconds
Started Jan 03 01:05:55 PM PST 24
Finished Jan 03 01:10:08 PM PST 24
Peak memory 228728 kb
Host smart-278bea83-9d94-4711-9302-c5bee8061d03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893271077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2893271077
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.968641267
Short name T100
Test name
Test status
Simulation time 61115632473 ps
CPU time 557.04 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:16:26 PM PST 24
Peak memory 215324 kb
Host smart-89a7c0bd-a5d8-4c69-b374-cb15183edcb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968641267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.968641267
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.677220571
Short name T238
Test name
Test status
Simulation time 18613230 ps
CPU time 0.55 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 193088 kb
Host smart-a44f27f1-633c-4a35-988d-e9186007df9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677220571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.677220571
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.21055500
Short name T466
Test name
Test status
Simulation time 13453771738 ps
CPU time 52.99 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:07:30 PM PST 24
Peak memory 232612 kb
Host smart-88505333-cc25-4cbf-9730-ac5f6185497b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21055500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.21055500
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2421102479
Short name T549
Test name
Test status
Simulation time 1320322608 ps
CPU time 6.5 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:36 PM PST 24
Peak memory 198664 kb
Host smart-ef55d3c3-66d0-404c-9a8a-a1abc6aa2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421102479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2421102479
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3328556854
Short name T819
Test name
Test status
Simulation time 3312448854 ps
CPU time 38.54 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 198848 kb
Host smart-41b97f8f-ab68-4435-82a7-c9e7c6c93587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328556854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3328556854
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3255980188
Short name T222
Test name
Test status
Simulation time 13582656891 ps
CPU time 52.61 seconds
Started Jan 03 01:05:26 PM PST 24
Finished Jan 03 01:07:36 PM PST 24
Peak memory 198904 kb
Host smart-1d03b3dc-0630-4f02-a489-5b9780448865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255980188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3255980188
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2534494435
Short name T750
Test name
Test status
Simulation time 1005112966 ps
CPU time 24.67 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 198720 kb
Host smart-19f25c18-71ec-4a80-8fba-80726a6b4f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534494435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2534494435
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2087691231
Short name T671
Test name
Test status
Simulation time 265629225 ps
CPU time 1.78 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:35 PM PST 24
Peak memory 198432 kb
Host smart-ecd8958c-8b3b-47e1-8a31-44d3177dca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087691231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2087691231
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3546804130
Short name T509
Test name
Test status
Simulation time 164291738480 ps
CPU time 1797.46 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:36:19 PM PST 24
Peak memory 198880 kb
Host smart-b878beb9-abdf-4af3-9533-ba9892930a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546804130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3546804130
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.1528683967
Short name T842
Test name
Test status
Simulation time 363565642772 ps
CPU time 4222.98 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 02:16:52 PM PST 24
Peak memory 272636 kb
Host smart-b45eac7b-c6ef-45bd-98cc-7d6f813f420b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528683967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.1528683967
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3564981935
Short name T709
Test name
Test status
Simulation time 146409630 ps
CPU time 1.23 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:27 PM PST 24
Peak memory 197324 kb
Host smart-b3012e30-a0df-48d0-bcab-5a197a0d1478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564981935 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3564981935
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.613109754
Short name T839
Test name
Test status
Simulation time 40950947184 ps
CPU time 432.27 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:13:41 PM PST 24
Peak memory 198888 kb
Host smart-9b17b77e-f065-46b0-a084-c7144fd8e5f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613109754 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.hmac_test_sha_vectors.613109754
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.452788062
Short name T387
Test name
Test status
Simulation time 3313990499 ps
CPU time 56.83 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:07:24 PM PST 24
Peak memory 198740 kb
Host smart-062390b9-dde0-4c86-b437-56e6c6e8cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452788062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.452788062
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.3732357672
Short name T272
Test name
Test status
Simulation time 79962828223 ps
CPU time 4049.01 seconds
Started Jan 03 01:06:10 PM PST 24
Finished Jan 03 02:14:58 PM PST 24
Peak memory 230800 kb
Host smart-f7091c9d-e1e3-4384-9f62-5032c4bd832b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732357672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.3732357672
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.1698102777
Short name T521
Test name
Test status
Simulation time 448464684678 ps
CPU time 2036.46 seconds
Started Jan 03 01:06:06 PM PST 24
Finished Jan 03 01:41:25 PM PST 24
Peak memory 251204 kb
Host smart-ef9a2c12-d8e0-4e32-9db5-09c0f3396815
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698102777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.1698102777
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.3089053504
Short name T564
Test name
Test status
Simulation time 49783495720 ps
CPU time 478.42 seconds
Started Jan 03 01:06:10 PM PST 24
Finished Jan 03 01:15:29 PM PST 24
Peak memory 247880 kb
Host smart-539a4514-84c8-4e56-9f41-c304f70770ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089053504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.3089053504
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.2587510073
Short name T779
Test name
Test status
Simulation time 181105934109 ps
CPU time 3520.47 seconds
Started Jan 03 01:06:03 PM PST 24
Finished Jan 03 02:06:05 PM PST 24
Peak memory 248608 kb
Host smart-b7b878bd-7cc7-48e3-84cc-cdea52205600
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587510073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.2587510073
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.2821624429
Short name T107
Test name
Test status
Simulation time 39856336938 ps
CPU time 500.44 seconds
Started Jan 03 01:06:09 PM PST 24
Finished Jan 03 01:15:50 PM PST 24
Peak memory 247364 kb
Host smart-6dbe43e4-bb8b-4586-944d-cf4b93790f6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821624429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.2821624429
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.4028660104
Short name T467
Test name
Test status
Simulation time 33650660093 ps
CPU time 1643.2 seconds
Started Jan 03 01:06:06 PM PST 24
Finished Jan 03 01:34:51 PM PST 24
Peak memory 245520 kb
Host smart-7a7d6c98-7bb2-4fac-8623-0bf8679f5bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028660104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.4028660104
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.460558283
Short name T308
Test name
Test status
Simulation time 377655596316 ps
CPU time 2597.34 seconds
Started Jan 03 01:06:04 PM PST 24
Finished Jan 03 01:50:42 PM PST 24
Peak memory 257248 kb
Host smart-e1616b9e-dd4e-44dc-a5dd-df48fc6c7c6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460558283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.460558283
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2786103018
Short name T384
Test name
Test status
Simulation time 41487641 ps
CPU time 0.53 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:07 PM PST 24
Peak memory 193096 kb
Host smart-ae69bba4-bc26-44b9-8ed5-381e647c8186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786103018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2786103018
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3382392378
Short name T424
Test name
Test status
Simulation time 2252279391 ps
CPU time 34.39 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:07:06 PM PST 24
Peak memory 225324 kb
Host smart-8032fb7c-84af-4d43-b270-2887742f471e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382392378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3382392378
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.269395053
Short name T814
Test name
Test status
Simulation time 4039965307 ps
CPU time 49.73 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:25 PM PST 24
Peak memory 198784 kb
Host smart-c8679857-39fe-466a-94c7-ca516f752d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269395053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.269395053
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.403033787
Short name T108
Test name
Test status
Simulation time 1214146201 ps
CPU time 61.71 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:07:40 PM PST 24
Peak memory 198740 kb
Host smart-0e5dc92e-044a-4d9e-b73b-bca32c79fd5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403033787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.403033787
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3895517425
Short name T410
Test name
Test status
Simulation time 2066498913 ps
CPU time 99.65 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:08:04 PM PST 24
Peak memory 198668 kb
Host smart-936f53c1-920e-4da8-876f-9e54a66e5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895517425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3895517425
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2458957243
Short name T718
Test name
Test status
Simulation time 147522391 ps
CPU time 2.06 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:06:37 PM PST 24
Peak memory 198656 kb
Host smart-47d9e088-5a07-4455-922f-0704a5bb4660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458957243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2458957243
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1212341051
Short name T373
Test name
Test status
Simulation time 76589050 ps
CPU time 1.35 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198436 kb
Host smart-c77a98e9-ad22-48ff-a341-0730431b2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212341051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1212341051
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1401361849
Short name T224
Test name
Test status
Simulation time 27187200136 ps
CPU time 421.97 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:13:29 PM PST 24
Peak memory 198836 kb
Host smart-784edb91-92c4-4c75-aec9-49c43f6f0139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401361849 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1401361849
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.3209219987
Short name T443
Test name
Test status
Simulation time 15059445547 ps
CPU time 236.72 seconds
Started Jan 03 01:04:58 PM PST 24
Finished Jan 03 01:10:15 PM PST 24
Peak memory 215264 kb
Host smart-6eafd686-99e8-45f0-a26e-c11047d19a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209219987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.3209219987
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2524434195
Short name T797
Test name
Test status
Simulation time 143638364 ps
CPU time 1.02 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:05 PM PST 24
Peak memory 196940 kb
Host smart-0c43ac89-1627-4d79-9b8c-b1a46f4fc1f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524434195 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2524434195
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.4134763554
Short name T630
Test name
Test status
Simulation time 40424445734 ps
CPU time 436.2 seconds
Started Jan 03 01:05:52 PM PST 24
Finished Jan 03 01:14:29 PM PST 24
Peak memory 198832 kb
Host smart-a02a12d8-32af-49d9-98d6-e1e461d40de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134763554 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.4134763554
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3388425593
Short name T319
Test name
Test status
Simulation time 1675962135 ps
CPU time 29.5 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:07:15 PM PST 24
Peak memory 198728 kb
Host smart-8fa4ed99-aa9b-4743-bca8-d625884b707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388425593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3388425593
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3401396464
Short name T404
Test name
Test status
Simulation time 1424686212017 ps
CPU time 1283.64 seconds
Started Jan 03 01:06:06 PM PST 24
Finished Jan 03 01:28:52 PM PST 24
Peak memory 247256 kb
Host smart-ddee07eb-5d4e-4c23-8420-36bd4aff9705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401396464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3401396464
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3398462314
Short name T249
Test name
Test status
Simulation time 68880613258 ps
CPU time 1633.62 seconds
Started Jan 03 01:06:43 PM PST 24
Finished Jan 03 01:35:03 PM PST 24
Peak memory 248056 kb
Host smart-436e30c3-1fc5-4486-879f-f9b51052759d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398462314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.3398462314
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3402693183
Short name T393
Test name
Test status
Simulation time 510463978682 ps
CPU time 2902.11 seconds
Started Jan 03 01:06:08 PM PST 24
Finished Jan 03 01:55:50 PM PST 24
Peak memory 231600 kb
Host smart-3adf116e-659a-446f-8b69-cfaa6118483d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402693183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3402693183
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.495656252
Short name T438
Test name
Test status
Simulation time 137762837963 ps
CPU time 1505.04 seconds
Started Jan 03 01:06:06 PM PST 24
Finished Jan 03 01:32:34 PM PST 24
Peak memory 231648 kb
Host smart-5dd489d0-e45a-4ac8-8f8c-2325e6838858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495656252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.495656252
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.2544377286
Short name T281
Test name
Test status
Simulation time 66450063008 ps
CPU time 3342.83 seconds
Started Jan 03 01:06:51 PM PST 24
Finished Jan 03 02:03:39 PM PST 24
Peak memory 244164 kb
Host smart-4336fca7-228b-404c-ab59-fe03467daeda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544377286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.2544377286
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.2617922064
Short name T550
Test name
Test status
Simulation time 68260950367 ps
CPU time 3346.62 seconds
Started Jan 03 01:06:52 PM PST 24
Finished Jan 03 02:03:44 PM PST 24
Peak memory 247728 kb
Host smart-68cf014b-26dc-46c4-aaca-224bfc1cc481
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617922064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.2617922064
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1391005849
Short name T468
Test name
Test status
Simulation time 11775102 ps
CPU time 0.54 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:06 PM PST 24
Peak memory 193120 kb
Host smart-b4dcb761-02cd-474d-b032-538631ffaea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391005849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1391005849
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.209916098
Short name T502
Test name
Test status
Simulation time 639622371 ps
CPU time 9.84 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:48 PM PST 24
Peak memory 206912 kb
Host smart-7ac4cbe1-deab-4ffe-8245-6db69a124c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209916098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.209916098
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3717935367
Short name T547
Test name
Test status
Simulation time 309818858 ps
CPU time 1.81 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 198692 kb
Host smart-349aa0bc-ee09-474f-90ff-5ef63b7ab6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717935367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3717935367
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4149540181
Short name T42
Test name
Test status
Simulation time 3313343823 ps
CPU time 83.59 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198848 kb
Host smart-ec0bafc1-7221-4c21-9cf4-be492c7e638c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149540181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4149540181
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3616755985
Short name T801
Test name
Test status
Simulation time 323924714 ps
CPU time 5.84 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 198692 kb
Host smart-f94aece6-0253-4eed-b4e9-c8f029298879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616755985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3616755985
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3249460837
Short name T623
Test name
Test status
Simulation time 17811046589 ps
CPU time 24.28 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:29 PM PST 24
Peak memory 198772 kb
Host smart-74ff846a-9ed0-4798-8bc1-bd6663112952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249460837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3249460837
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.233036800
Short name T51
Test name
Test status
Simulation time 60512461 ps
CPU time 0.85 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:48 PM PST 24
Peak memory 217052 kb
Host smart-360f672a-9c0b-4338-8071-109ae2fbdd65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233036800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.233036800
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2953081941
Short name T239
Test name
Test status
Simulation time 1589447432 ps
CPU time 4.39 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 198620 kb
Host smart-a3148a46-97e7-4248-8bad-2deb95f73eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953081941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2953081941
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3788134731
Short name T826
Test name
Test status
Simulation time 13194931922 ps
CPU time 638.35 seconds
Started Jan 03 01:04:46 PM PST 24
Finished Jan 03 01:16:47 PM PST 24
Peak memory 206940 kb
Host smart-dc9f1bb5-c6a5-48c8-a96a-52c1124a2a73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788134731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3788134731
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3316340442
Short name T537
Test name
Test status
Simulation time 95516464975 ps
CPU time 1379.23 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:29:02 PM PST 24
Peak memory 263800 kb
Host smart-cd848c91-8ffe-4cdc-97c5-1c5e820b0b3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316340442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3316340442
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.175631957
Short name T454
Test name
Test status
Simulation time 108159104 ps
CPU time 1.1 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 197856 kb
Host smart-0aa916b5-4d76-4de0-864b-3f1edab95273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175631957 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.175631957
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.4050692839
Short name T218
Test name
Test status
Simulation time 177995265316 ps
CPU time 451.62 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:13:07 PM PST 24
Peak memory 198836 kb
Host smart-8b2cc8db-c375-4f9c-a70a-6e66b3e2092d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050692839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.4050692839
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1295296049
Short name T315
Test name
Test status
Simulation time 3258029968 ps
CPU time 56.81 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:06:35 PM PST 24
Peak memory 198836 kb
Host smart-9b4c6249-399a-45c1-85cc-5afd62252137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295296049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1295296049
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1794768009
Short name T534
Test name
Test status
Simulation time 17928465 ps
CPU time 0.53 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:06:16 PM PST 24
Peak memory 193084 kb
Host smart-e61c3ee8-8f12-4167-987e-76c0c81e5072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794768009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1794768009
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4006444439
Short name T340
Test name
Test status
Simulation time 6264926285 ps
CPU time 21.44 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 215076 kb
Host smart-08f09ff6-75c2-4a07-9aaf-03eed7eaf7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006444439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4006444439
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2355051744
Short name T604
Test name
Test status
Simulation time 229586397 ps
CPU time 4.05 seconds
Started Jan 03 01:04:32 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 198676 kb
Host smart-54ca9e43-8918-43ee-be59-ce2d7d40f30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355051744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2355051744
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1265937875
Short name T430
Test name
Test status
Simulation time 16813170345 ps
CPU time 68.01 seconds
Started Jan 03 01:04:35 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198768 kb
Host smart-1b52bac6-ad66-4ea9-b499-828abff44a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265937875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1265937875
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1941950144
Short name T196
Test name
Test status
Simulation time 1190244274 ps
CPU time 7.05 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 198720 kb
Host smart-4ab9ccd5-1a09-41c0-ae14-e6ad2b396b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941950144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1941950144
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.407894204
Short name T810
Test name
Test status
Simulation time 1179618967 ps
CPU time 54.03 seconds
Started Jan 03 01:04:44 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 198676 kb
Host smart-40bf3fbe-654c-452b-b8bb-58b65023dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407894204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.407894204
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2072375840
Short name T3
Test name
Test status
Simulation time 224421434 ps
CPU time 2.5 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:14 PM PST 24
Peak memory 198652 kb
Host smart-d67388e8-6fb5-4d13-beee-499faac14f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072375840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2072375840
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.33460176
Short name T747
Test name
Test status
Simulation time 21861987650 ps
CPU time 364.65 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:12:31 PM PST 24
Peak memory 214588 kb
Host smart-d8f3ca52-590f-4d25-a4d2-457b863eea5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33460176 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.33460176
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.29029938
Short name T507
Test name
Test status
Simulation time 97663389 ps
CPU time 0.99 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:30 PM PST 24
Peak memory 195804 kb
Host smart-ad936b87-ea3b-4c5b-86bc-28d6bb41dcb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029938 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.hmac_test_hmac_vectors.29029938
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2858985718
Short name T355
Test name
Test status
Simulation time 27663147692 ps
CPU time 439.54 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:13:37 PM PST 24
Peak memory 198792 kb
Host smart-aafbf66c-6dfd-4318-bb1f-1c5e6f50dde0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858985718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.2858985718
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2824190150
Short name T214
Test name
Test status
Simulation time 12245364253 ps
CPU time 39.77 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 198840 kb
Host smart-31b01e58-58d7-428e-8eae-503b5f51038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824190150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2824190150
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1336066699
Short name T788
Test name
Test status
Simulation time 43295576 ps
CPU time 0.54 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 193064 kb
Host smart-411c2c74-de92-46af-b968-a85365426697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336066699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1336066699
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2442874880
Short name T212
Test name
Test status
Simulation time 11018752259 ps
CPU time 48.78 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:07:00 PM PST 24
Peak memory 227252 kb
Host smart-b7ee2813-6dce-4b92-b4bd-0e97252c4724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442874880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2442874880
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2482127245
Short name T199
Test name
Test status
Simulation time 1220728248 ps
CPU time 52.36 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:07:20 PM PST 24
Peak memory 198720 kb
Host smart-ebdd9f71-992b-4843-8cb6-7a4c1083218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482127245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2482127245
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4056561600
Short name T823
Test name
Test status
Simulation time 429977986 ps
CPU time 22.03 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:46 PM PST 24
Peak memory 198708 kb
Host smart-cd3e09d0-0657-443e-a086-c8f03cb94050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056561600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4056561600
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.454139882
Short name T517
Test name
Test status
Simulation time 2142270603 ps
CPU time 9.01 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 198704 kb
Host smart-33eb276f-a289-47a8-a950-e2adf429ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454139882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.454139882
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2245927447
Short name T539
Test name
Test status
Simulation time 21576825730 ps
CPU time 94.64 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:07:42 PM PST 24
Peak memory 198780 kb
Host smart-864a8e84-0052-4718-b51b-5a88c29f3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245927447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2245927447
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3239530290
Short name T294
Test name
Test status
Simulation time 232891856 ps
CPU time 3.18 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:29 PM PST 24
Peak memory 198696 kb
Host smart-078ea599-967f-4a15-b3fe-aed5a110dffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239530290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3239530290
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3961128621
Short name T620
Test name
Test status
Simulation time 46843425830 ps
CPU time 753.18 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:18:57 PM PST 24
Peak memory 198900 kb
Host smart-c089aca3-df64-4f6c-8556-0e048f3bb874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961128621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3961128621
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.3155430560
Short name T711
Test name
Test status
Simulation time 66401473069 ps
CPU time 250.86 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:10:42 PM PST 24
Peak memory 247332 kb
Host smart-ddca2f51-50b0-4d84-bcfc-d48b011bd4e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155430560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.3155430560
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.4003834773
Short name T802
Test name
Test status
Simulation time 105563184 ps
CPU time 1.09 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:18 PM PST 24
Peak memory 197264 kb
Host smart-b6e1793a-a91a-4673-bc35-41fc46b2ee22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003834773 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.4003834773
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1322349681
Short name T704
Test name
Test status
Simulation time 6788068292 ps
CPU time 46.86 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:07:43 PM PST 24
Peak memory 198868 kb
Host smart-b91736f5-025d-410f-a53f-e55cc8e71a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322349681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1322349681
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.580042953
Short name T725
Test name
Test status
Simulation time 41708718 ps
CPU time 0.62 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:06:29 PM PST 24
Peak memory 193104 kb
Host smart-16ef9642-492a-4178-9dd1-6184eb0cdd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580042953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.580042953
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.48703114
Short name T385
Test name
Test status
Simulation time 3748793531 ps
CPU time 29.76 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 214608 kb
Host smart-467347c8-0c20-4c27-ae17-264e5c7eef32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48703114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.48703114
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3319745152
Short name T41
Test name
Test status
Simulation time 1805259974 ps
CPU time 30.91 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 198664 kb
Host smart-09e1d840-1ae6-46a1-b05d-d73593a65f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319745152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3319745152
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.34706007
Short name T581
Test name
Test status
Simulation time 220605418 ps
CPU time 5.11 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 198696 kb
Host smart-2561a14b-5553-449c-8972-36479b009a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34706007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.34706007
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1290040686
Short name T712
Test name
Test status
Simulation time 403868186 ps
CPU time 3.23 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198064 kb
Host smart-1497c0e4-7921-45ef-b747-a9ecb47d549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290040686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1290040686
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3046168734
Short name T590
Test name
Test status
Simulation time 5266657590 ps
CPU time 70.42 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:59 PM PST 24
Peak memory 198804 kb
Host smart-0b52a0b9-d0a3-4bc6-80c4-c6ce753b7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046168734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3046168734
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1107342122
Short name T582
Test name
Test status
Simulation time 554266569 ps
CPU time 2.7 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:28 PM PST 24
Peak memory 198716 kb
Host smart-f187db18-cdc9-42f1-bf2d-a6301d271b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107342122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1107342122
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2939827395
Short name T617
Test name
Test status
Simulation time 8341134930 ps
CPU time 408.23 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:13:09 PM PST 24
Peak memory 198808 kb
Host smart-2273ccd1-e259-4069-93d1-8f10d1e74f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939827395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2939827395
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.613629801
Short name T43
Test name
Test status
Simulation time 66434675695 ps
CPU time 1245.28 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:27:13 PM PST 24
Peak memory 239856 kb
Host smart-e9dae816-7ef9-4469-9bd3-a6632d4de434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613629801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.613629801
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3127685672
Short name T56
Test name
Test status
Simulation time 42593294 ps
CPU time 0.91 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 195728 kb
Host smart-cecd1ff2-f557-4a50-b3f0-5585f93fe948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127685672 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3127685672
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3015792834
Short name T783
Test name
Test status
Simulation time 41628335642 ps
CPU time 390.27 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 198840 kb
Host smart-bce07d7c-4a7c-43c9-ac08-1ed99c87e3d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015792834 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3015792834
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1113194301
Short name T836
Test name
Test status
Simulation time 6260735571 ps
CPU time 43.86 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:07:16 PM PST 24
Peak memory 198860 kb
Host smart-54426ef4-b846-446f-829f-c7aaabe030ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113194301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1113194301
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.95651010
Short name T306
Test name
Test status
Simulation time 37440900 ps
CPU time 0.55 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 193160 kb
Host smart-4eebc8ba-6e84-405a-9042-a2b20f64a3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95651010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.95651010
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3080993259
Short name T396
Test name
Test status
Simulation time 6468270828 ps
CPU time 47.19 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:07:47 PM PST 24
Peak memory 221788 kb
Host smart-f4c053ac-1653-4693-b427-ad7e1397455e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080993259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3080993259
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3575095263
Short name T398
Test name
Test status
Simulation time 3284507309 ps
CPU time 12.51 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:01 PM PST 24
Peak memory 198864 kb
Host smart-400619b9-7ddd-4b9c-8db0-812cb9ecb6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575095263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3575095263
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2438804088
Short name T60
Test name
Test status
Simulation time 7373666541 ps
CPU time 94.79 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:08:20 PM PST 24
Peak memory 198784 kb
Host smart-8eb67250-2dac-40db-b33d-ff7ec8e4cae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438804088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2438804088
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2037185323
Short name T446
Test name
Test status
Simulation time 11588816 ps
CPU time 0.57 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:07:15 PM PST 24
Peak memory 193176 kb
Host smart-670ed912-f29f-41bf-82f1-20261aec83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037185323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2037185323
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.80184766
Short name T341
Test name
Test status
Simulation time 3155826246 ps
CPU time 79.5 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:08:19 PM PST 24
Peak memory 198840 kb
Host smart-5fdac46c-96df-47cf-9bfa-429cf753c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80184766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.80184766
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2758259057
Short name T298
Test name
Test status
Simulation time 704309650 ps
CPU time 2.14 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:36 PM PST 24
Peak memory 198480 kb
Host smart-ca8684c7-4694-481c-8342-397cf4fffced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758259057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2758259057
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.72520183
Short name T1
Test name
Test status
Simulation time 8500052279 ps
CPU time 118.17 seconds
Started Jan 03 01:04:50 PM PST 24
Finished Jan 03 01:08:14 PM PST 24
Peak memory 198792 kb
Host smart-3dcb3d63-393a-46fa-b46a-ebc6ebafa2af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72520183 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.72520183
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.1793320003
Short name T855
Test name
Test status
Simulation time 231050663472 ps
CPU time 1867.48 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 258188 kb
Host smart-43ab43f3-b33f-4715-a382-f597e35a7d4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793320003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.1793320003
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.880155692
Short name T326
Test name
Test status
Simulation time 24981858 ps
CPU time 0.86 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 196488 kb
Host smart-c930d2cf-6060-402a-9d72-800f8b716792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880155692 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.880155692
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.189405017
Short name T388
Test name
Test status
Simulation time 178754338757 ps
CPU time 458.49 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 198764 kb
Host smart-6146196a-e8a8-45a3-9788-ec61b2ca14a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189405017 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.hmac_test_sha_vectors.189405017
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.25393688
Short name T703
Test name
Test status
Simulation time 4937680037 ps
CPU time 84.32 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:08:02 PM PST 24
Peak memory 198808 kb
Host smart-a01eb76f-b029-47e5-8d0d-628e8909abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25393688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.25393688
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.886893364
Short name T858
Test name
Test status
Simulation time 24807093 ps
CPU time 0.6 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:06:40 PM PST 24
Peak memory 193100 kb
Host smart-e9ecaac6-e2ca-4ab3-bd4b-e970156084d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886893364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.886893364
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1628221183
Short name T220
Test name
Test status
Simulation time 11891728060 ps
CPU time 21.74 seconds
Started Jan 03 01:04:52 PM PST 24
Finished Jan 03 01:06:37 PM PST 24
Peak memory 215016 kb
Host smart-b9e8a07b-ba1f-49c5-81cd-784f4b24dda7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628221183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1628221183
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3235011302
Short name T102
Test name
Test status
Simulation time 644216247 ps
CPU time 15.2 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 198668 kb
Host smart-621732bf-352c-4ef4-9a92-9706754ed410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235011302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3235011302
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3232946033
Short name T401
Test name
Test status
Simulation time 2628837256 ps
CPU time 33.3 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 198764 kb
Host smart-e578bc31-ae30-48af-a54f-e2f0b2bd67f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232946033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3232946033
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.26952004
Short name T818
Test name
Test status
Simulation time 2951451359 ps
CPU time 43.31 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:07:44 PM PST 24
Peak memory 198808 kb
Host smart-261ffa5d-f7a5-40dc-a5be-acb01efd4c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26952004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.26952004
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3312599040
Short name T736
Test name
Test status
Simulation time 6840173989 ps
CPU time 105.21 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:08:12 PM PST 24
Peak memory 198804 kb
Host smart-6c5eb98b-0d4b-473d-b7a8-202e14ceab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312599040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3312599040
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1972381179
Short name T678
Test name
Test status
Simulation time 63211242 ps
CPU time 0.86 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:06:13 PM PST 24
Peak memory 196056 kb
Host smart-b85d9f08-205e-42b7-ba23-d0a208c1ed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972381179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1972381179
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2887231
Short name T790
Test name
Test status
Simulation time 69478393045 ps
CPU time 1144.44 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:25:25 PM PST 24
Peak memory 211924 kb
Host smart-00c625ba-ada7-4117-8db0-348cc56608cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887231 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2887231
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2740573524
Short name T495
Test name
Test status
Simulation time 18772896322 ps
CPU time 361.87 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 215300 kb
Host smart-aa811b0e-452b-4baa-9591-be8184f3ead7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740573524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2740573524
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2844076048
Short name T333
Test name
Test status
Simulation time 313752084 ps
CPU time 1.15 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 196892 kb
Host smart-2722fbdb-e320-489f-99b7-8a6a36e3c08c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844076048 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2844076048
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.564896921
Short name T551
Test name
Test status
Simulation time 53423699717 ps
CPU time 417.23 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:13:24 PM PST 24
Peak memory 198788 kb
Host smart-7fa9009f-ccb5-4655-a839-8808c3da7461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564896921 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.hmac_test_sha_vectors.564896921
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1552141236
Short name T713
Test name
Test status
Simulation time 4394490232 ps
CPU time 71.6 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:07:36 PM PST 24
Peak memory 198864 kb
Host smart-e09fa776-f94e-418d-8065-6f18efabc091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552141236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1552141236
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1999829362
Short name T409
Test name
Test status
Simulation time 230261853 ps
CPU time 0.58 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 193060 kb
Host smart-8b3a9ced-2c28-4460-9645-375af2dcf08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999829362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1999829362
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.919198703
Short name T482
Test name
Test status
Simulation time 805345433 ps
CPU time 23.48 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 213888 kb
Host smart-193ccf6d-5b54-40c7-a7e5-2abccd940682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919198703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.919198703
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3254760563
Short name T752
Test name
Test status
Simulation time 2019493192 ps
CPU time 9.11 seconds
Started Jan 03 01:04:59 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 198680 kb
Host smart-2a322036-f1bf-4020-a764-88e21d1a059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254760563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3254760563
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1577982998
Short name T830
Test name
Test status
Simulation time 3196130911 ps
CPU time 81.37 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198820 kb
Host smart-b3b81101-26b5-4c46-ad53-cdd6c76ec40f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577982998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1577982998
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1525550452
Short name T642
Test name
Test status
Simulation time 391359353 ps
CPU time 18.3 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198696 kb
Host smart-91622fbd-9599-4c1d-bee3-aa8dabcf7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525550452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1525550452
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3218708999
Short name T632
Test name
Test status
Simulation time 47821250878 ps
CPU time 85.42 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:08:02 PM PST 24
Peak memory 198820 kb
Host smart-d09cc786-75ce-4485-960a-674ed1413712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218708999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3218708999
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2649510632
Short name T714
Test name
Test status
Simulation time 324981419 ps
CPU time 3.32 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:06:20 PM PST 24
Peak memory 198640 kb
Host smart-a236d477-7de8-4b93-b4cf-b750c8eecef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649510632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2649510632
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.433550130
Short name T300
Test name
Test status
Simulation time 137313078668 ps
CPU time 1606.64 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:33:20 PM PST 24
Peak memory 198856 kb
Host smart-51ebd42e-49e4-4edc-85b5-ad140f105ece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433550130 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.433550130
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.3542143717
Short name T485
Test name
Test status
Simulation time 167596093684 ps
CPU time 1581.25 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:33:10 PM PST 24
Peak memory 223492 kb
Host smart-94efd06f-1650-427f-8c97-d2dc20331204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542143717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.3542143717
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4069724672
Short name T383
Test name
Test status
Simulation time 395952928 ps
CPU time 0.9 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 195952 kb
Host smart-4ace49dc-b424-43b8-a9e0-ac51722fbe47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069724672 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4069724672
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.78288854
Short name T850
Test name
Test status
Simulation time 32422739085 ps
CPU time 375 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 198804 kb
Host smart-b6109c15-4145-47bb-a7bf-05636d71ceec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78288854 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.hmac_test_sha_vectors.78288854
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.67843496
Short name T853
Test name
Test status
Simulation time 26067345223 ps
CPU time 42.77 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:07:06 PM PST 24
Peak memory 198800 kb
Host smart-67fd8cb8-0eb2-4a35-8d8f-ccd4048a164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67843496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.67843496
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1047221776
Short name T558
Test name
Test status
Simulation time 27081507 ps
CPU time 0.57 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:40 PM PST 24
Peak memory 193084 kb
Host smart-90e59fc0-78dc-47f2-998a-70f25949458f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047221776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1047221776
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2920793372
Short name T609
Test name
Test status
Simulation time 5497675894 ps
CPU time 35.9 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:07:10 PM PST 24
Peak memory 207072 kb
Host smart-8e457fb9-1792-47ad-930b-c14a6da00d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920793372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2920793372
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1813664800
Short name T210
Test name
Test status
Simulation time 1903521739 ps
CPU time 20.96 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 198636 kb
Host smart-a4720911-b2c6-48c2-8e4d-527118cd24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813664800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1813664800
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1897373724
Short name T686
Test name
Test status
Simulation time 3126019788 ps
CPU time 30.13 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 198812 kb
Host smart-232be136-c9de-432e-abfd-5b35004a0ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897373724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1897373724
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3987596979
Short name T268
Test name
Test status
Simulation time 39070337829 ps
CPU time 164.09 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:09:23 PM PST 24
Peak memory 198668 kb
Host smart-c378d223-8813-457a-a9a6-e5e3fea9a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987596979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3987596979
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.103274405
Short name T742
Test name
Test status
Simulation time 14986315902 ps
CPU time 94.39 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:08:14 PM PST 24
Peak memory 198840 kb
Host smart-99f34b32-aca5-415b-b262-3e8c556ebc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103274405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.103274405
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3402918801
Short name T682
Test name
Test status
Simulation time 1927972190 ps
CPU time 2.09 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:06:26 PM PST 24
Peak memory 198424 kb
Host smart-faf606c4-d3b0-4220-b5bb-b508d9736cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402918801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3402918801
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2575488846
Short name T514
Test name
Test status
Simulation time 24574877514 ps
CPU time 548.34 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:15:35 PM PST 24
Peak memory 198780 kb
Host smart-7576e63f-6be1-45cf-8f7c-a2d17fba8732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575488846 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2575488846
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3892696587
Short name T684
Test name
Test status
Simulation time 364484093194 ps
CPU time 4176.62 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 02:16:18 PM PST 24
Peak memory 245808 kb
Host smart-0df93b55-d117-4730-ae9d-3898de891392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892696587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3892696587
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2201149537
Short name T739
Test name
Test status
Simulation time 134696713 ps
CPU time 1.13 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 196412 kb
Host smart-7e5b134c-c7f3-4388-88d6-cd69eb22a730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201149537 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2201149537
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2111691013
Short name T807
Test name
Test status
Simulation time 33839782040 ps
CPU time 390.68 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:12:47 PM PST 24
Peak memory 198852 kb
Host smart-cea79436-72ff-4a70-a9db-921354a673e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111691013 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2111691013
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3260778625
Short name T594
Test name
Test status
Simulation time 3828253237 ps
CPU time 30.14 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198884 kb
Host smart-80457162-a257-41af-aaa2-a7ee4c742513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260778625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3260778625
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2265686696
Short name T445
Test name
Test status
Simulation time 20721924 ps
CPU time 0.54 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 193124 kb
Host smart-8fcdc5d6-81ef-4335-b641-d69e00705edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265686696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2265686696
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.748776849
Short name T305
Test name
Test status
Simulation time 4537292970 ps
CPU time 34.86 seconds
Started Jan 03 01:05:32 PM PST 24
Finished Jan 03 01:07:26 PM PST 24
Peak memory 224320 kb
Host smart-f5e4388e-dfea-4fae-b7f8-da6d7f1596b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748776849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.748776849
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3063680483
Short name T374
Test name
Test status
Simulation time 2505715908 ps
CPU time 10.78 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:06:47 PM PST 24
Peak memory 198760 kb
Host smart-552f41cc-a4df-475f-a453-68dbffd4d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063680483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3063680483
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1893513768
Short name T599
Test name
Test status
Simulation time 33640532231 ps
CPU time 137.65 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:09:01 PM PST 24
Peak memory 198832 kb
Host smart-726169e6-3eb6-419a-812b-7fa5f8be8439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893513768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1893513768
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3600633898
Short name T460
Test name
Test status
Simulation time 1237992509 ps
CPU time 15.44 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 198712 kb
Host smart-a8a2af25-19a4-43fd-ae94-ebadbc8841b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600633898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3600633898
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2977039221
Short name T386
Test name
Test status
Simulation time 6612981589 ps
CPU time 91.97 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:08:20 PM PST 24
Peak memory 198800 kb
Host smart-8a86bdd0-5907-4eb5-9837-af2e045fec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977039221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2977039221
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1314321
Short name T400
Test name
Test status
Simulation time 59194932 ps
CPU time 1.04 seconds
Started Jan 03 01:05:25 PM PST 24
Finished Jan 03 01:06:50 PM PST 24
Peak memory 197620 kb
Host smart-91d5f8d4-235e-4007-8aa3-ec5c7fbc4f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1314321
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3826153350
Short name T658
Test name
Test status
Simulation time 24738065 ps
CPU time 0.62 seconds
Started Jan 03 01:05:54 PM PST 24
Finished Jan 03 01:07:19 PM PST 24
Peak memory 193184 kb
Host smart-5479b200-0ece-453d-8fc8-64e6850d76c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826153350 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3826153350
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.1432690079
Short name T697
Test name
Test status
Simulation time 81690098418 ps
CPU time 644.33 seconds
Started Jan 03 01:05:58 PM PST 24
Finished Jan 03 01:18:05 PM PST 24
Peak memory 231500 kb
Host smart-2bf1d81c-70b0-4259-acad-4cb85720699d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432690079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.1432690079
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.4067411735
Short name T284
Test name
Test status
Simulation time 910807665 ps
CPU time 1.04 seconds
Started Jan 03 01:05:29 PM PST 24
Finished Jan 03 01:06:47 PM PST 24
Peak memory 197460 kb
Host smart-bfc2a430-2828-4d8c-b35b-1886df6f1095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067411735 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.4067411735
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1458411477
Short name T662
Test name
Test status
Simulation time 171516739423 ps
CPU time 433.11 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:13:56 PM PST 24
Peak memory 198776 kb
Host smart-4c1054b1-7c8f-4b3c-8912-bca5aa388dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458411477 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1458411477
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.602507461
Short name T610
Test name
Test status
Simulation time 648952339 ps
CPU time 7.84 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 198664 kb
Host smart-19392461-5323-4daa-aa42-5854b172abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602507461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.602507461
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1009678559
Short name T442
Test name
Test status
Simulation time 39190886 ps
CPU time 0.55 seconds
Started Jan 03 01:04:51 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 193088 kb
Host smart-88ae2c0d-4bbc-4c6a-a12b-a6554aa61ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009678559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1009678559
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2049438630
Short name T217
Test name
Test status
Simulation time 1195121539 ps
CPU time 35.42 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:06:58 PM PST 24
Peak memory 210412 kb
Host smart-418e24e5-a111-4def-8e43-36b55b95c597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049438630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2049438630
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1129398306
Short name T685
Test name
Test status
Simulation time 4266356549 ps
CPU time 35.84 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:12 PM PST 24
Peak memory 198620 kb
Host smart-b1836b7c-8625-4faf-a00d-fbd5ac72d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129398306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1129398306
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3244886372
Short name T744
Test name
Test status
Simulation time 5402471184 ps
CPU time 65.96 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:07:35 PM PST 24
Peak memory 198796 kb
Host smart-030450e7-05ce-408b-b929-c84981ecbff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244886372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3244886372
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1349823941
Short name T832
Test name
Test status
Simulation time 4861312530 ps
CPU time 59.41 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:35 PM PST 24
Peak memory 198840 kb
Host smart-26c44c55-1358-4657-a1c7-1f8514ce3c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349823941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1349823941
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1710188856
Short name T449
Test name
Test status
Simulation time 7130230573 ps
CPU time 85.47 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:08:04 PM PST 24
Peak memory 198832 kb
Host smart-b74ab024-81eb-43e2-b43b-5c2baafaea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710188856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1710188856
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1171353581
Short name T481
Test name
Test status
Simulation time 2407043617 ps
CPU time 3.03 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:42 PM PST 24
Peak memory 198840 kb
Host smart-4c41f0a0-96d1-48de-800b-3f62012d5177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171353581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1171353581
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.988642793
Short name T228
Test name
Test status
Simulation time 78101064833 ps
CPU time 279.97 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:11:02 PM PST 24
Peak memory 224388 kb
Host smart-c4e535ae-06cf-41ba-99d3-4778353e2980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988642793 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.988642793
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.2920424315
Short name T122
Test name
Test status
Simulation time 243500257304 ps
CPU time 2026.84 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 01:40:04 PM PST 24
Peak memory 250080 kb
Host smart-d26ab6dd-c456-4c17-8c77-c8e0c4cd61e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920424315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.2920424315
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1057616697
Short name T673
Test name
Test status
Simulation time 53722292 ps
CPU time 1.12 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:42 PM PST 24
Peak memory 196300 kb
Host smart-30b00bfb-f4fd-4ae6-8c0c-4387ca0c49ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057616697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1057616697
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.739793132
Short name T652
Test name
Test status
Simulation time 25075038230 ps
CPU time 397.04 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:13:10 PM PST 24
Peak memory 198784 kb
Host smart-1dfa4b8d-6934-4a8a-8ba9-d59d65e7e16b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739793132 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.739793132
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3391781300
Short name T297
Test name
Test status
Simulation time 12586092498 ps
CPU time 28.8 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:55 PM PST 24
Peak memory 198800 kb
Host smart-2e5e162b-7dca-4913-b71f-3009ff5eac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391781300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3391781300
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1166303155
Short name T375
Test name
Test status
Simulation time 45142902 ps
CPU time 0.55 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 194084 kb
Host smart-aaf820ed-d7e4-4409-9b89-4576833c3ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166303155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1166303155
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1342291301
Short name T279
Test name
Test status
Simulation time 7487527301 ps
CPU time 49.13 seconds
Started Jan 03 01:04:58 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 215264 kb
Host smart-d13810c5-2da0-4f13-a4fc-e3d6b68baccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342291301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1342291301
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.62519113
Short name T334
Test name
Test status
Simulation time 2309126272 ps
CPU time 20.69 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:07:00 PM PST 24
Peak memory 198748 kb
Host smart-76a78c8b-722e-4224-864b-7d0dd243e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62519113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.62519113
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1494427430
Short name T767
Test name
Test status
Simulation time 2018906642 ps
CPU time 94.87 seconds
Started Jan 03 01:04:58 PM PST 24
Finished Jan 03 01:07:53 PM PST 24
Peak memory 198700 kb
Host smart-80b31f00-536c-4a15-9b48-0758d7197693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494427430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1494427430
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.874236316
Short name T200
Test name
Test status
Simulation time 7513585605 ps
CPU time 112.67 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:08:33 PM PST 24
Peak memory 198792 kb
Host smart-4c31aa9b-615d-436a-8ea2-9a76661b1395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874236316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.874236316
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.798023207
Short name T532
Test name
Test status
Simulation time 23990905372 ps
CPU time 76.88 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:07:34 PM PST 24
Peak memory 198824 kb
Host smart-667a76bc-c449-4ba3-8e6f-a9d221784e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798023207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.798023207
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.288022624
Short name T316
Test name
Test status
Simulation time 60714845 ps
CPU time 1.6 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:06:21 PM PST 24
Peak memory 197608 kb
Host smart-d0133419-bfc7-4c35-88d6-0d45ed99f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288022624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.288022624
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3292612769
Short name T241
Test name
Test status
Simulation time 58550829494 ps
CPU time 954.37 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:22:59 PM PST 24
Peak memory 217228 kb
Host smart-b13432c7-cfd0-4b51-af83-43f67534bdd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292612769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3292612769
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.4182077588
Short name T227
Test name
Test status
Simulation time 40094246507 ps
CPU time 574.88 seconds
Started Jan 03 01:05:26 PM PST 24
Finished Jan 03 01:16:18 PM PST 24
Peak memory 230732 kb
Host smart-846a4d94-37e1-4bb3-8460-99c0990d7537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182077588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.4182077588
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4032654804
Short name T490
Test name
Test status
Simulation time 188626036 ps
CPU time 1.1 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:25 PM PST 24
Peak memory 197764 kb
Host smart-598884f5-5ea0-46fa-8e2e-deb88e212e6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032654804 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4032654804
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.845141807
Short name T209
Test name
Test status
Simulation time 159359784216 ps
CPU time 433.67 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 198792 kb
Host smart-0287b580-b73a-479c-9453-d6c4d6d7d298
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845141807 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.hmac_test_sha_vectors.845141807
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3650470797
Short name T527
Test name
Test status
Simulation time 21038055255 ps
CPU time 37.28 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198844 kb
Host smart-1e84487f-d9a1-4051-baeb-b0704a0e4b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650470797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3650470797
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3270970606
Short name T9
Test name
Test status
Simulation time 12966608 ps
CPU time 0.55 seconds
Started Jan 03 01:04:37 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 193064 kb
Host smart-ba8600fb-471d-4b74-9662-93051f05a4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270970606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3270970606
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4114381566
Short name T616
Test name
Test status
Simulation time 4959477051 ps
CPU time 33.65 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:06:11 PM PST 24
Peak memory 214292 kb
Host smart-ea1278ba-1f22-4663-aba7-658c554615af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114381566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4114381566
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1484543602
Short name T717
Test name
Test status
Simulation time 240838842 ps
CPU time 4.47 seconds
Started Jan 03 01:04:41 PM PST 24
Finished Jan 03 01:06:16 PM PST 24
Peak memory 198652 kb
Host smart-ce9b068c-ab23-431e-9578-0bfbc9c11fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484543602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1484543602
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3640065296
Short name T769
Test name
Test status
Simulation time 8259300335 ps
CPU time 99.69 seconds
Started Jan 03 01:04:26 PM PST 24
Finished Jan 03 01:07:28 PM PST 24
Peak memory 198788 kb
Host smart-3c115b2e-5eea-46e9-ae1b-5cc9256c1dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640065296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3640065296
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3440601482
Short name T61
Test name
Test status
Simulation time 28993729339 ps
CPU time 33.17 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 198792 kb
Host smart-23e12729-7c24-4acd-857e-f48d16ebc06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440601482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3440601482
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2183590551
Short name T561
Test name
Test status
Simulation time 5812177448 ps
CPU time 74.48 seconds
Started Jan 03 01:06:01 PM PST 24
Finished Jan 03 01:08:37 PM PST 24
Peak memory 198804 kb
Host smart-5ad4c2a5-37c3-4dd2-860a-8fb1537acacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183590551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2183590551
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.568489450
Short name T416
Test name
Test status
Simulation time 430403978 ps
CPU time 2.13 seconds
Started Jan 03 01:04:29 PM PST 24
Finished Jan 03 01:05:54 PM PST 24
Peak memory 198436 kb
Host smart-db47a738-5d79-4078-b8f9-08997a0ccb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568489450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.568489450
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4293685958
Short name T707
Test name
Test status
Simulation time 14512032202 ps
CPU time 670.56 seconds
Started Jan 03 01:04:41 PM PST 24
Finished Jan 03 01:17:11 PM PST 24
Peak memory 215104 kb
Host smart-88d75847-9af8-4210-9de9-ca86f28b9db9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293685958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4293685958
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.802883569
Short name T668
Test name
Test status
Simulation time 15188963395 ps
CPU time 398.65 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 215312 kb
Host smart-2203bc14-c633-43fb-881e-5896278178eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802883569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.802883569
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1841242616
Short name T567
Test name
Test status
Simulation time 228202282 ps
CPU time 1.24 seconds
Started Jan 03 01:04:29 PM PST 24
Finished Jan 03 01:05:53 PM PST 24
Peak memory 196844 kb
Host smart-e21f0fec-bcbf-4ae8-aa47-72c21bd46f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841242616 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1841242616
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.879558195
Short name T356
Test name
Test status
Simulation time 15286635417 ps
CPU time 358.82 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:12:06 PM PST 24
Peak memory 198740 kb
Host smart-1f60b061-4829-4e31-8504-bcfb94e0b001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879558195 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.hmac_test_sha_vectors.879558195
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4286455607
Short name T677
Test name
Test status
Simulation time 10132107764 ps
CPU time 62.54 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:06:46 PM PST 24
Peak memory 198816 kb
Host smart-cf767987-11b5-46dd-a99b-0427c80cf9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286455607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4286455607
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.422238179
Short name T757
Test name
Test status
Simulation time 41578731 ps
CPU time 0.53 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 193104 kb
Host smart-e62662da-db2c-4c38-8cfd-28f8d476f644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422238179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.422238179
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1287962174
Short name T613
Test name
Test status
Simulation time 21264331851 ps
CPU time 49.32 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:07:58 PM PST 24
Peak memory 239528 kb
Host smart-ff9a290f-f83a-4d21-9e2e-876891498475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287962174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1287962174
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4090957653
Short name T653
Test name
Test status
Simulation time 1191512040 ps
CPU time 20.88 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198680 kb
Host smart-19c9f5da-aa9c-4db0-b1b5-edd0639b1047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090957653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4090957653
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.589400277
Short name T667
Test name
Test status
Simulation time 1569030281 ps
CPU time 73.29 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:07:47 PM PST 24
Peak memory 198692 kb
Host smart-50740902-fe6e-4891-a47d-05fe7c569357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589400277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.589400277
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1196842975
Short name T295
Test name
Test status
Simulation time 72449095 ps
CPU time 0.93 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 197416 kb
Host smart-901af7c0-ffca-40e3-b895-57cdf1bbaec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196842975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1196842975
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.113539738
Short name T463
Test name
Test status
Simulation time 4824195542 ps
CPU time 60.03 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:07:36 PM PST 24
Peak memory 198788 kb
Host smart-bf4ec675-273b-40c9-9fdc-29153c5c2906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113539738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.113539738
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2451691237
Short name T469
Test name
Test status
Simulation time 321190613 ps
CPU time 1.34 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:30 PM PST 24
Peak memory 198496 kb
Host smart-6890793e-6c3e-4130-b3c4-e3ee118b00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451691237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2451691237
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3345798918
Short name T123
Test name
Test status
Simulation time 112151228145 ps
CPU time 1011.85 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:23:31 PM PST 24
Peak memory 198784 kb
Host smart-a50752e1-b12e-49c6-a8ef-e029035b5fe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345798918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3345798918
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.2385545331
Short name T106
Test name
Test status
Simulation time 46574318798 ps
CPU time 684.66 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:17:58 PM PST 24
Peak memory 239924 kb
Host smart-b704c5ce-e4bc-41c5-9ef3-0a284f5e211d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385545331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.2385545331
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2304392725
Short name T453
Test name
Test status
Simulation time 36368716 ps
CPU time 0.87 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 195552 kb
Host smart-9351344c-eedd-46fa-bce9-4d270f3ab74c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304392725 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2304392725
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.4161610996
Short name T533
Test name
Test status
Simulation time 28580412874 ps
CPU time 427.23 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:13:48 PM PST 24
Peak memory 198484 kb
Host smart-6feb2883-2371-4546-8c7a-c78e8f199a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161610996 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.4161610996
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1365182526
Short name T347
Test name
Test status
Simulation time 7788209081 ps
CPU time 28.74 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 198772 kb
Host smart-3e88aab3-b59c-44e8-94c3-8c6b9a0deb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365182526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1365182526
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2445750243
Short name T603
Test name
Test status
Simulation time 11215955 ps
CPU time 0.54 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:30 PM PST 24
Peak memory 193048 kb
Host smart-654bafa3-cea3-404a-b105-970b78224512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445750243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2445750243
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1291606829
Short name T542
Test name
Test status
Simulation time 1334136445 ps
CPU time 10.41 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 206916 kb
Host smart-c92588e4-6a72-43e6-9ced-bd681b06936c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291606829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1291606829
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1782091646
Short name T343
Test name
Test status
Simulation time 1954974638 ps
CPU time 20.55 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198728 kb
Host smart-dc51d5f8-3d74-4c89-b5c1-6680643c3052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782091646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1782091646
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1087466162
Short name T44
Test name
Test status
Simulation time 1537923641 ps
CPU time 74.9 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:08:03 PM PST 24
Peak memory 198584 kb
Host smart-d68c74b1-a71d-459c-89cb-9ee423452ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087466162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1087466162
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2140357423
Short name T475
Test name
Test status
Simulation time 9220751322 ps
CPU time 111.58 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:08:43 PM PST 24
Peak memory 198868 kb
Host smart-79de03b2-39bd-4ada-9ea0-1a49044af59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140357423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2140357423
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.438607187
Short name T420
Test name
Test status
Simulation time 1058376441 ps
CPU time 17.25 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:01 PM PST 24
Peak memory 198716 kb
Host smart-7782b0ca-8738-4fa0-9dde-6c25ba3be7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438607187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.438607187
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3996479796
Short name T771
Test name
Test status
Simulation time 84295518 ps
CPU time 2.1 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:07:14 PM PST 24
Peak memory 198684 kb
Host smart-aad46bdd-af30-4920-a4cc-492137f0b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996479796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3996479796
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2283977215
Short name T105
Test name
Test status
Simulation time 261027771278 ps
CPU time 2110.98 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:41:40 PM PST 24
Peak memory 198828 kb
Host smart-e678f542-1e13-43a2-9027-e976b4023175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283977215 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2283977215
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2456662647
Short name T131
Test name
Test status
Simulation time 168403668307 ps
CPU time 2849.03 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:54:01 PM PST 24
Peak memory 264396 kb
Host smart-91376247-46e0-418e-b1d2-656a19be422d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456662647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.2456662647
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2378927774
Short name T483
Test name
Test status
Simulation time 77486375 ps
CPU time 0.88 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 195904 kb
Host smart-0a737f2a-7972-42ef-ab11-b5dd877168ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378927774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2378927774
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4054817528
Short name T339
Test name
Test status
Simulation time 70495422619 ps
CPU time 469.74 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:14:17 PM PST 24
Peak memory 198828 kb
Host smart-7e7b50b2-e2f6-4cf5-a817-a28820036a37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054817528 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.4054817528
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.429323919
Short name T777
Test name
Test status
Simulation time 650267429 ps
CPU time 10.98 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:42 PM PST 24
Peak memory 198672 kb
Host smart-b344ebad-62cd-456a-b270-faabc15ed8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429323919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.429323919
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2186369905
Short name T508
Test name
Test status
Simulation time 50666673 ps
CPU time 0.55 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 194096 kb
Host smart-1bf14659-e24a-4441-9685-888c005d48c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186369905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2186369905
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2192206184
Short name T681
Test name
Test status
Simulation time 826893614 ps
CPU time 23.28 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 198676 kb
Host smart-46ad586c-bd41-47af-b781-e24b96471e5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192206184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2192206184
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2451192823
Short name T371
Test name
Test status
Simulation time 2138884218 ps
CPU time 14.91 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198584 kb
Host smart-218f669e-e5e6-41e9-8d3b-2f74864b3473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451192823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2451192823
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1875963630
Short name T237
Test name
Test status
Simulation time 431473645 ps
CPU time 10.68 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:50 PM PST 24
Peak memory 198648 kb
Host smart-7a075612-8946-4cb6-8448-306d65c78064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875963630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1875963630
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4030554260
Short name T822
Test name
Test status
Simulation time 13503066690 ps
CPU time 149.28 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:08:44 PM PST 24
Peak memory 198876 kb
Host smart-056e66bf-5f65-4d92-baec-38ef21badad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030554260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4030554260
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3458666217
Short name T661
Test name
Test status
Simulation time 8013770724 ps
CPU time 106.15 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:08:27 PM PST 24
Peak memory 198856 kb
Host smart-bb001cb2-4e98-4598-99cb-099060e5df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458666217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3458666217
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1552205101
Short name T692
Test name
Test status
Simulation time 276079935 ps
CPU time 3.04 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198564 kb
Host smart-973b594c-a84e-4577-84d9-0c8ac13bd291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552205101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1552205101
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2492534328
Short name T98
Test name
Test status
Simulation time 600401978430 ps
CPU time 669.67 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:17:17 PM PST 24
Peak memory 239280 kb
Host smart-058bf8c0-490a-4a7b-ab3e-22c2ba9d4da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492534328 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2492534328
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.2103829056
Short name T369
Test name
Test status
Simulation time 15419725012 ps
CPU time 204.37 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:09:45 PM PST 24
Peak memory 214496 kb
Host smart-cbc09f1d-e8e6-4672-86ba-62d623f26af0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103829056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.2103829056
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3356928953
Short name T55
Test name
Test status
Simulation time 229656468 ps
CPU time 0.88 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:07:11 PM PST 24
Peak memory 195692 kb
Host smart-835ea4e3-3170-4414-82d6-952726c4eed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356928953 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3356928953
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2708962265
Short name T497
Test name
Test status
Simulation time 7481028017 ps
CPU time 350.3 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:12:32 PM PST 24
Peak memory 198816 kb
Host smart-88071bd9-288b-4c60-a1b6-8fcfbffecd97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708962265 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.2708962265
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1827464436
Short name T834
Test name
Test status
Simulation time 2908200180 ps
CPU time 47.03 seconds
Started Jan 03 01:05:33 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198836 kb
Host smart-d82ec263-1415-4678-ac56-a8aed644afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827464436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1827464436
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.597482535
Short name T382
Test name
Test status
Simulation time 12966740 ps
CPU time 0.55 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:29 PM PST 24
Peak memory 193020 kb
Host smart-20ce5ff5-8084-47de-a948-b97b671cd85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597482535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.597482535
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.148591673
Short name T215
Test name
Test status
Simulation time 1082903624 ps
CPU time 37.07 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:07:00 PM PST 24
Peak memory 223268 kb
Host smart-798e5934-4370-423d-a81c-b3a8f2ea2943
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148591673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.148591673
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2441089935
Short name T399
Test name
Test status
Simulation time 11568410394 ps
CPU time 11.79 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 198884 kb
Host smart-605e901b-ab93-4b45-9169-80986386fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441089935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2441089935
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.604803868
Short name T104
Test name
Test status
Simulation time 2367268808 ps
CPU time 117.02 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:08:15 PM PST 24
Peak memory 198896 kb
Host smart-7311dab7-2834-424c-b1bd-d7994dfff7a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604803868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.604803868
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1655513196
Short name T572
Test name
Test status
Simulation time 4071544530 ps
CPU time 198.84 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:09:56 PM PST 24
Peak memory 198868 kb
Host smart-fba3a250-6aae-4cb9-8b6f-52cbe5e5fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655513196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1655513196
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.777519022
Short name T368
Test name
Test status
Simulation time 3865724503 ps
CPU time 93.49 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:08:10 PM PST 24
Peak memory 198748 kb
Host smart-c9f83186-a0d5-4854-945d-43b2465b712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777519022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.777519022
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2118963294
Short name T766
Test name
Test status
Simulation time 921827778 ps
CPU time 3.3 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 198708 kb
Host smart-33612b59-6517-486b-ae79-7ceb29926fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118963294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2118963294
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2320451793
Short name T854
Test name
Test status
Simulation time 11641766445 ps
CPU time 203.38 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:09:47 PM PST 24
Peak memory 224480 kb
Host smart-ce98ec59-0904-4ff5-b890-6446df12452e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320451793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2320451793
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.159501378
Short name T112
Test name
Test status
Simulation time 286094121376 ps
CPU time 1900.17 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:38:25 PM PST 24
Peak memory 239948 kb
Host smart-d617060e-2485-40a7-afad-b1c6ad17c0c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159501378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.159501378
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2049781064
Short name T848
Test name
Test status
Simulation time 581605304 ps
CPU time 0.92 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:41 PM PST 24
Peak memory 195972 kb
Host smart-7b6fb6b1-aeac-4bdb-a852-64c07eb2b331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049781064 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2049781064
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3069561486
Short name T513
Test name
Test status
Simulation time 151725232650 ps
CPU time 502.51 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:14:42 PM PST 24
Peak memory 198772 kb
Host smart-03854ef7-1882-4103-8d81-cfcef90426da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069561486 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3069561486
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.396238062
Short name T556
Test name
Test status
Simulation time 11186521415 ps
CPU time 85.19 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:07:45 PM PST 24
Peak memory 198836 kb
Host smart-8efdb4db-efd4-433a-a036-8574c0668332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396238062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.396238062
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2800335256
Short name T376
Test name
Test status
Simulation time 41015335 ps
CPU time 0.53 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 193072 kb
Host smart-7a1242c8-90d0-40c5-bce4-5f5a788cc66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800335256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2800335256
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1405997162
Short name T768
Test name
Test status
Simulation time 1276088685 ps
CPU time 41.36 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:07:18 PM PST 24
Peak memory 212808 kb
Host smart-ddbfa911-fea0-47c8-b770-f84212a6e6fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405997162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1405997162
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.309508042
Short name T413
Test name
Test status
Simulation time 100383842 ps
CPU time 4 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:06:25 PM PST 24
Peak memory 198720 kb
Host smart-e1a72385-a2bc-4ab7-8315-e3281a8251c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309508042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.309508042
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3163776569
Short name T394
Test name
Test status
Simulation time 171328585 ps
CPU time 4.88 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:06:36 PM PST 24
Peak memory 198596 kb
Host smart-5f711c7a-3a6b-4295-b4ce-b64b2de50d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163776569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3163776569
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1574272984
Short name T342
Test name
Test status
Simulation time 4080472511 ps
CPU time 101.09 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:08:02 PM PST 24
Peak memory 198852 kb
Host smart-05b7dab9-b202-4a9d-874c-bec264e316fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574272984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1574272984
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.489496364
Short name T555
Test name
Test status
Simulation time 72535676 ps
CPU time 2.85 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:29 PM PST 24
Peak memory 198708 kb
Host smart-2b8b08e5-1914-4a48-8127-332612fe06dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489496364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.489496364
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.131163856
Short name T354
Test name
Test status
Simulation time 91049259 ps
CPU time 2.26 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 198668 kb
Host smart-722f532c-8a9f-4030-8db9-75e936c7608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131163856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.131163856
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.170709283
Short name T646
Test name
Test status
Simulation time 61570513257 ps
CPU time 684.5 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:17:48 PM PST 24
Peak memory 228108 kb
Host smart-81801552-bc50-43d1-85ad-933673e5679c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170709283 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.170709283
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.723873660
Short name T625
Test name
Test status
Simulation time 22332501562 ps
CPU time 165.29 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:09:30 PM PST 24
Peak memory 214584 kb
Host smart-9f6bff23-329a-4866-9a45-2fa2c777a08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723873660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.723873660
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.84772620
Short name T302
Test name
Test status
Simulation time 53977773 ps
CPU time 0.9 seconds
Started Jan 03 01:05:25 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 196368 kb
Host smart-54b26359-ca29-484c-9c55-d5378a977839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84772620 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_hmac_vectors.84772620
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3310943394
Short name T577
Test name
Test status
Simulation time 7752559631 ps
CPU time 371.52 seconds
Started Jan 03 01:04:53 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 198792 kb
Host smart-1fb20b0d-6a77-4eed-9c5a-7929e5fbfe24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310943394 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.3310943394
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.426051697
Short name T554
Test name
Test status
Simulation time 515844589 ps
CPU time 20.53 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198688 kb
Host smart-769719b4-f739-44fb-81d1-a0d1d0c00967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426051697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.426051697
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4270239724
Short name T676
Test name
Test status
Simulation time 12368377 ps
CPU time 0.56 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:07:13 PM PST 24
Peak memory 193208 kb
Host smart-bbe35db8-b4a8-4324-bb6f-d71749299ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270239724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4270239724
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1977262686
Short name T754
Test name
Test status
Simulation time 473819702 ps
CPU time 11.49 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 215108 kb
Host smart-17e9e999-f4d2-48c1-b56f-814a9f5e229b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977262686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1977262686
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3478435623
Short name T751
Test name
Test status
Simulation time 2289752099 ps
CPU time 49.1 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 01:07:50 PM PST 24
Peak memory 198808 kb
Host smart-1e5f9e0a-cc48-450c-8539-86dc68ef31d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478435623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3478435623
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3625926181
Short name T473
Test name
Test status
Simulation time 4430518547 ps
CPU time 57.42 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:07:42 PM PST 24
Peak memory 198764 kb
Host smart-d7a2ac36-c2e9-4a73-8d86-897dc4880962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625926181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3625926181
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3594122636
Short name T408
Test name
Test status
Simulation time 15228917084 ps
CPU time 84.56 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:08:09 PM PST 24
Peak memory 198872 kb
Host smart-88271bdb-3ae6-4a24-8d1d-8b9fb0a22b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594122636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3594122636
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1689491676
Short name T759
Test name
Test status
Simulation time 7524065334 ps
CPU time 17.07 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:06:56 PM PST 24
Peak memory 198820 kb
Host smart-66057dff-efd5-4b66-ad6f-8552c8e5c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689491676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1689491676
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1573192034
Short name T304
Test name
Test status
Simulation time 808991868 ps
CPU time 2.82 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:07:15 PM PST 24
Peak memory 198684 kb
Host smart-cc69b324-006f-4022-9277-760f66b93daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573192034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1573192034
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1647977811
Short name T633
Test name
Test status
Simulation time 81639290040 ps
CPU time 784.21 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:19:42 PM PST 24
Peak memory 207036 kb
Host smart-cd2e3ae6-6ee1-4595-9c87-c84926703f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647977811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1647977811
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1223830085
Short name T640
Test name
Test status
Simulation time 222247862922 ps
CPU time 2047.84 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:40:53 PM PST 24
Peak memory 264460 kb
Host smart-9af92324-7628-4e27-ae7b-e1e176142949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223830085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.1223830085
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1639476717
Short name T765
Test name
Test status
Simulation time 96394093 ps
CPU time 0.87 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:46 PM PST 24
Peak memory 195824 kb
Host smart-9a0df2e6-108a-4f35-a40a-84e937aa3d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639476717 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1639476717
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2770339101
Short name T731
Test name
Test status
Simulation time 27728666278 ps
CPU time 419.12 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:14:07 PM PST 24
Peak memory 198788 kb
Host smart-75f53e17-e39a-4f57-adc0-030c1c0cf94d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770339101 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.2770339101
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2206201922
Short name T231
Test name
Test status
Simulation time 2127214518 ps
CPU time 31.08 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 198684 kb
Host smart-cc865017-9e2f-46be-bdae-c6daf36cdca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206201922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2206201922
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2004145648
Short name T785
Test name
Test status
Simulation time 116139624 ps
CPU time 0.56 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:06:50 PM PST 24
Peak memory 193128 kb
Host smart-8b71db1b-5d62-4962-82cc-7440f799145c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004145648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2004145648
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.586307811
Short name T435
Test name
Test status
Simulation time 358637173 ps
CPU time 7.09 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:55 PM PST 24
Peak memory 206936 kb
Host smart-be1ce294-95bf-4ba8-a91f-859439036634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586307811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.586307811
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2335709562
Short name T257
Test name
Test status
Simulation time 18532398602 ps
CPU time 29.59 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:07:34 PM PST 24
Peak memory 198616 kb
Host smart-3dc83b5e-402e-483c-ba3d-9031b4ee51e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335709562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2335709562
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.4131824164
Short name T806
Test name
Test status
Simulation time 3111020426 ps
CPU time 40.02 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:07:20 PM PST 24
Peak memory 198828 kb
Host smart-388a818a-646c-4a7a-8e24-716081f5b488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131824164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4131824164
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3503311252
Short name T748
Test name
Test status
Simulation time 802149519 ps
CPU time 18.44 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:00 PM PST 24
Peak memory 198740 kb
Host smart-56610790-7d01-4a46-91de-dfa92930c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503311252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3503311252
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3350473385
Short name T503
Test name
Test status
Simulation time 555123877 ps
CPU time 26.54 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 198516 kb
Host smart-0a895869-7462-483c-aea7-7c33bf6d7c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350473385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3350473385
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2527022564
Short name T693
Test name
Test status
Simulation time 97121996 ps
CPU time 1.46 seconds
Started Jan 03 01:05:52 PM PST 24
Finished Jan 03 01:07:15 PM PST 24
Peak memory 198480 kb
Host smart-08f19f96-fef0-4577-a7bf-9e585232ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527022564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2527022564
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1717967054
Short name T351
Test name
Test status
Simulation time 12166884341 ps
CPU time 45.37 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 198852 kb
Host smart-07959507-c7a1-4b33-a44b-efacc3649bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717967054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1717967054
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.1500426170
Short name T40
Test name
Test status
Simulation time 238649990021 ps
CPU time 5265.29 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 02:34:22 PM PST 24
Peak memory 241432 kb
Host smart-8d96c263-11b9-4650-84e3-7b8e8528331e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500426170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.1500426170
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2763572571
Short name T665
Test name
Test status
Simulation time 36847965 ps
CPU time 0.9 seconds
Started Jan 03 01:05:26 PM PST 24
Finished Jan 03 01:06:47 PM PST 24
Peak memory 196248 kb
Host smart-420957fa-0dac-4961-bef5-166142af0126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763572571 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2763572571
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3874536697
Short name T252
Test name
Test status
Simulation time 27049606631 ps
CPU time 407.14 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:12:59 PM PST 24
Peak memory 198856 kb
Host smart-0d2b6c14-0efa-41aa-85d6-4a3477858f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874536697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.3874536697
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.102307292
Short name T715
Test name
Test status
Simulation time 358709756 ps
CPU time 6.43 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 198732 kb
Host smart-f5a8a093-89a3-492b-a01f-748cbffa883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102307292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.102307292
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1944657574
Short name T8
Test name
Test status
Simulation time 51712625 ps
CPU time 0.55 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 193132 kb
Host smart-0d02cb4e-2360-4811-9a4c-4f1d66bea14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944657574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1944657574
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1955552571
Short name T277
Test name
Test status
Simulation time 1554815129 ps
CPU time 21.03 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:07:09 PM PST 24
Peak memory 215152 kb
Host smart-ea8357e7-46c5-4e63-872f-21c56464808b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955552571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1955552571
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.665215339
Short name T260
Test name
Test status
Simulation time 3731343456 ps
CPU time 12.56 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198792 kb
Host smart-89fa78b5-3132-4317-8618-103e9363738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665215339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.665215339
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2980001867
Short name T292
Test name
Test status
Simulation time 5513791604 ps
CPU time 48.94 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:07:34 PM PST 24
Peak memory 198796 kb
Host smart-8d9cf16f-5780-43ce-87d5-466e1deddcf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980001867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2980001867
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3627084914
Short name T478
Test name
Test status
Simulation time 15878663 ps
CPU time 0.58 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 193288 kb
Host smart-347b2fe8-1ca7-459f-9688-dce0f10c81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627084914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3627084914
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2934417701
Short name T264
Test name
Test status
Simulation time 795593323 ps
CPU time 40 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:07:17 PM PST 24
Peak memory 198652 kb
Host smart-3d68773b-5abd-4369-930a-62328408f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934417701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2934417701
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.578867378
Short name T844
Test name
Test status
Simulation time 846086612 ps
CPU time 2.47 seconds
Started Jan 03 01:05:26 PM PST 24
Finished Jan 03 01:06:47 PM PST 24
Peak memory 198364 kb
Host smart-5bacbd03-c7b2-401d-ad30-f6fba11106fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578867378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.578867378
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.754745586
Short name T269
Test name
Test status
Simulation time 19196406293 ps
CPU time 910.42 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:21:55 PM PST 24
Peak memory 198836 kb
Host smart-fb57aa1f-07c2-4142-881d-17c7e338bc67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754745586 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.754745586
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.2978396513
Short name T758
Test name
Test status
Simulation time 68027200324 ps
CPU time 781.55 seconds
Started Jan 03 01:05:29 PM PST 24
Finished Jan 03 01:19:47 PM PST 24
Peak memory 238260 kb
Host smart-7ef7402f-87da-4ca4-8153-05664fb76211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978396513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.2978396513
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.348816846
Short name T608
Test name
Test status
Simulation time 59712988 ps
CPU time 1.14 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 197452 kb
Host smart-4d737d90-9787-4740-95a0-5fa7d270b946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348816846 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.348816846
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3134172900
Short name T287
Test name
Test status
Simulation time 109299204267 ps
CPU time 411.42 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:13:45 PM PST 24
Peak memory 198804 kb
Host smart-ca3b33c9-3849-4226-b967-147ec8a36763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134172900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3134172900
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2557182113
Short name T353
Test name
Test status
Simulation time 12289687 ps
CPU time 0.55 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 193124 kb
Host smart-b33440b0-1d67-41a3-bed8-0f64f497f299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557182113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2557182113
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4272874425
Short name T348
Test name
Test status
Simulation time 522542962 ps
CPU time 3.96 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:52 PM PST 24
Peak memory 198676 kb
Host smart-5f5c1fc8-47cf-4c09-ba12-938b02187673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272874425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4272874425
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1350156167
Short name T205
Test name
Test status
Simulation time 420041172 ps
CPU time 4.97 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 198712 kb
Host smart-c6da65b3-74f7-4eb8-8a0e-068f3b24d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350156167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1350156167
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2997693925
Short name T484
Test name
Test status
Simulation time 3174965441 ps
CPU time 30.67 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:07:18 PM PST 24
Peak memory 198700 kb
Host smart-e0a37b61-0deb-46dc-9e1f-67408013c8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997693925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2997693925
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2494369404
Short name T450
Test name
Test status
Simulation time 1779373307 ps
CPU time 43.32 seconds
Started Jan 03 01:05:06 PM PST 24
Finished Jan 03 01:07:11 PM PST 24
Peak memory 198688 kb
Host smart-e3c3d1f9-6c4c-4f85-be92-9aee3e44c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494369404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2494369404
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1366463371
Short name T524
Test name
Test status
Simulation time 5136378838 ps
CPU time 53.22 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:41 PM PST 24
Peak memory 198696 kb
Host smart-b29329ef-c84c-4820-bbc4-3c996a632a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366463371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1366463371
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3442870056
Short name T427
Test name
Test status
Simulation time 202849759 ps
CPU time 2.35 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:50 PM PST 24
Peak memory 198272 kb
Host smart-b969fb3f-6993-4e44-8217-b22c8721d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442870056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3442870056
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3739904289
Short name T114
Test name
Test status
Simulation time 107573550096 ps
CPU time 838.4 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:20:22 PM PST 24
Peak memory 247172 kb
Host smart-b4c42ae1-2ff6-4b54-8a30-d44599c902b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739904289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3739904289
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.1922449446
Short name T110
Test name
Test status
Simulation time 336801353679 ps
CPU time 3426.88 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 02:03:43 PM PST 24
Peak memory 263752 kb
Host smart-d3dafb81-662e-49c6-bb92-0ff390c4e5a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922449446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.1922449446
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.475010677
Short name T571
Test name
Test status
Simulation time 44732420 ps
CPU time 0.9 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 196380 kb
Host smart-f8261bbc-2e00-4203-8f94-7c36dfdb4296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475010677 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.475010677
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1266479579
Short name T465
Test name
Test status
Simulation time 8641176583 ps
CPU time 404.48 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:13:14 PM PST 24
Peak memory 198776 kb
Host smart-e9ad2d7a-e1a3-48a8-b8de-3dfc71d64385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266479579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.1266479579
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3288471752
Short name T320
Test name
Test status
Simulation time 1730702230 ps
CPU time 50.69 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:07:12 PM PST 24
Peak memory 198696 kb
Host smart-2baa77cc-7211-4cdd-91b9-c3b4cb4d7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288471752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3288471752
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1857786827
Short name T670
Test name
Test status
Simulation time 22427110 ps
CPU time 0.57 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 193120 kb
Host smart-aa5ff8ff-c8a9-4f88-9b59-d500b82abfb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857786827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1857786827
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1704804019
Short name T792
Test name
Test status
Simulation time 510538071 ps
CPU time 14.3 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 198700 kb
Host smart-498d9958-a43c-416b-b6bd-14b76275af5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704804019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1704804019
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2166816035
Short name T724
Test name
Test status
Simulation time 13107730955 ps
CPU time 38.39 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:14 PM PST 24
Peak memory 198820 kb
Host smart-a4441a05-56d3-4384-a277-8dcf86aae51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166816035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2166816035
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2774489175
Short name T219
Test name
Test status
Simulation time 3134131292 ps
CPU time 70.51 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:46 PM PST 24
Peak memory 198628 kb
Host smart-6841d2dc-0cde-4b74-b611-a9931da504d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774489175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2774489175
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4144850192
Short name T391
Test name
Test status
Simulation time 4152170693 ps
CPU time 12.45 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 198468 kb
Host smart-92ea8694-a909-4c0e-bc66-74dd0692103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144850192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4144850192
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2402575889
Short name T134
Test name
Test status
Simulation time 871984363 ps
CPU time 6.77 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198668 kb
Host smart-5f025660-8074-4c51-b33d-135e1839a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402575889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2402575889
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2339726373
Short name T773
Test name
Test status
Simulation time 74669196 ps
CPU time 1.25 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:07:20 PM PST 24
Peak memory 198104 kb
Host smart-22498618-54e7-4595-8580-0bcd761a0274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339726373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2339726373
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3652307510
Short name T614
Test name
Test status
Simulation time 8993083709 ps
CPU time 73.62 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:08:02 PM PST 24
Peak memory 198820 kb
Host smart-a28b33d5-2b1f-4127-ac14-67e142862690
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652307510 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3652307510
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.2953962981
Short name T824
Test name
Test status
Simulation time 97651963710 ps
CPU time 339.12 seconds
Started Jan 03 01:05:22 PM PST 24
Finished Jan 03 01:12:24 PM PST 24
Peak memory 215336 kb
Host smart-066e4811-e3c6-43c6-879f-e52c5df23bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953962981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.2953962981
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1233057991
Short name T207
Test name
Test status
Simulation time 54595694 ps
CPU time 1.13 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:41 PM PST 24
Peak memory 197324 kb
Host smart-fc36e57a-6988-4dab-9cd4-6f145d2b5ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233057991 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1233057991
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1690303794
Short name T825
Test name
Test status
Simulation time 68380315201 ps
CPU time 437.02 seconds
Started Jan 03 01:06:00 PM PST 24
Finished Jan 03 01:14:39 PM PST 24
Peak memory 198844 kb
Host smart-e7637e9f-ca07-442f-9ce7-31bedeae23ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690303794 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.1690303794
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.721154266
Short name T229
Test name
Test status
Simulation time 17160698224 ps
CPU time 42.21 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:27 PM PST 24
Peak memory 198848 kb
Host smart-60a8d615-c750-41bc-821a-62936933fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721154266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.721154266
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1705324245
Short name T655
Test name
Test status
Simulation time 20045444 ps
CPU time 0.56 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 193116 kb
Host smart-246a1840-62e3-4206-aa91-5659d636c14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705324245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1705324245
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3744517877
Short name T39
Test name
Test status
Simulation time 637253082 ps
CPU time 10.3 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 215024 kb
Host smart-5f6359b3-bff8-4b3f-9f28-abc62e26f2ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744517877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3744517877
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.304324920
Short name T808
Test name
Test status
Simulation time 3431772673 ps
CPU time 39.03 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 198756 kb
Host smart-757af5e6-a628-43f7-b6cd-ad227d4adc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304324920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.304324920
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3674028895
Short name T366
Test name
Test status
Simulation time 175162753 ps
CPU time 0.73 seconds
Started Jan 03 01:04:50 PM PST 24
Finished Jan 03 01:06:13 PM PST 24
Peak memory 195220 kb
Host smart-f910a757-8d86-4e03-9db5-59d54b07d568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674028895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3674028895
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1898550493
Short name T618
Test name
Test status
Simulation time 4999407598 ps
CPU time 81.04 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:07:43 PM PST 24
Peak memory 198780 kb
Host smart-ac6cd6b2-306b-446d-b464-0725f449f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898550493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1898550493
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2349679463
Short name T360
Test name
Test status
Simulation time 6262363958 ps
CPU time 88.35 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:07:39 PM PST 24
Peak memory 198780 kb
Host smart-e703f851-31dd-4b95-9376-8af563da2168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349679463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2349679463
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2634701999
Short name T53
Test name
Test status
Simulation time 35840566 ps
CPU time 0.76 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 215756 kb
Host smart-95f6b938-4c97-4648-b7f0-3c80e8d93a9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634701999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2634701999
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4127332677
Short name T562
Test name
Test status
Simulation time 23718176 ps
CPU time 0.76 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:07 PM PST 24
Peak memory 195708 kb
Host smart-78d176f1-2ae7-49f9-8aea-1186ec3e52d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127332677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4127332677
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1558604866
Short name T812
Test name
Test status
Simulation time 15635429280 ps
CPU time 531.19 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:15:16 PM PST 24
Peak memory 214748 kb
Host smart-045710fd-5ac6-404b-bb4b-0ed5409defa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558604866 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1558604866
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.418818272
Short name T472
Test name
Test status
Simulation time 64964129109 ps
CPU time 354.08 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:12:18 PM PST 24
Peak memory 247028 kb
Host smart-dd2e4769-5620-4da1-a7a8-a52cb06da3a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418818272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.418818272
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1534722110
Short name T728
Test name
Test status
Simulation time 198001670 ps
CPU time 0.89 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:06:12 PM PST 24
Peak memory 196480 kb
Host smart-561b5269-2be9-4226-bfa2-ecb8edbf8709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534722110 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1534722110
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3041056380
Short name T346
Test name
Test status
Simulation time 164105897177 ps
CPU time 402.24 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 198804 kb
Host smart-67f53380-696c-46fe-b909-ec4e0d2f945c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041056380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.3041056380
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2403430124
Short name T719
Test name
Test status
Simulation time 2015458326 ps
CPU time 37.39 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:06:46 PM PST 24
Peak memory 198756 kb
Host smart-9454b05b-4953-4071-be72-22570bb0ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403430124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2403430124
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.864507516
Short name T46
Test name
Test status
Simulation time 15511505 ps
CPU time 0.56 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 193196 kb
Host smart-783208a2-96ef-4364-9bae-c0e9c6660761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864507516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.864507516
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3172630847
Short name T361
Test name
Test status
Simulation time 451394859 ps
CPU time 14.24 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 207864 kb
Host smart-494fd8c5-bc1f-471f-a2a8-1cfe57409353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172630847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3172630847
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3719316692
Short name T307
Test name
Test status
Simulation time 2614121732 ps
CPU time 29.72 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:56 PM PST 24
Peak memory 198804 kb
Host smart-eb1542c0-de97-4f5d-b5c6-bc90d7ea51a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719316692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3719316692
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.25973421
Short name T573
Test name
Test status
Simulation time 1386399270 ps
CPU time 67.43 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:07:29 PM PST 24
Peak memory 198632 kb
Host smart-b4cfae48-09c3-4dbf-a663-e2a56675bc96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25973421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.25973421
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1159747220
Short name T535
Test name
Test status
Simulation time 498381524 ps
CPU time 23.43 seconds
Started Jan 03 01:05:12 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198720 kb
Host smart-a5222844-474c-4d31-9ba4-95316dca052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159747220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1159747220
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3965748821
Short name T730
Test name
Test status
Simulation time 5246251424 ps
CPU time 72.51 seconds
Started Jan 03 01:05:38 PM PST 24
Finished Jan 03 01:08:11 PM PST 24
Peak memory 198840 kb
Host smart-9c869229-03d8-4a04-9853-73a691683b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965748821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3965748821
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.61848988
Short name T770
Test name
Test status
Simulation time 325460510 ps
CPU time 3.29 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:06:50 PM PST 24
Peak memory 198408 kb
Host smart-a9ee1c5b-8bba-4bd1-877e-0e99e05b83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61848988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.61848988
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.518214302
Short name T10
Test name
Test status
Simulation time 434720938084 ps
CPU time 1678.99 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:35:08 PM PST 24
Peak memory 207024 kb
Host smart-3e070944-5947-40ae-a457-7cbaabad028b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518214302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.518214302
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.2794355986
Short name T390
Test name
Test status
Simulation time 74307075000 ps
CPU time 333.82 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:12:30 PM PST 24
Peak memory 214824 kb
Host smart-873fbd9a-75cc-43e3-8cd5-012b16821474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794355986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.2794355986
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3606899760
Short name T345
Test name
Test status
Simulation time 29412123 ps
CPU time 0.89 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 195920 kb
Host smart-912907f3-f7e3-43b8-be57-067052c91e7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606899760 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3606899760
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.573499026
Short name T206
Test name
Test status
Simulation time 744655176 ps
CPU time 4.64 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:07:07 PM PST 24
Peak memory 198444 kb
Host smart-58fec307-edca-4675-b55d-686d3871f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573499026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.573499026
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2566656676
Short name T57
Test name
Test status
Simulation time 41554025 ps
CPU time 0.55 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:07:06 PM PST 24
Peak memory 193132 kb
Host smart-6a3089c6-a273-4cad-adcf-0a9a40c57c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566656676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2566656676
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.289881354
Short name T694
Test name
Test status
Simulation time 1968684394 ps
CPU time 27.56 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:07:16 PM PST 24
Peak memory 206880 kb
Host smart-684a9eed-24b2-4dc6-8d2f-11bc3bc814d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289881354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.289881354
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1179080950
Short name T133
Test name
Test status
Simulation time 1501071356 ps
CPU time 16.64 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:07:20 PM PST 24
Peak memory 198716 kb
Host smart-9ac54a76-91e8-4e4c-8a50-3c5dc73a2a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179080950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1179080950
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3533985012
Short name T500
Test name
Test status
Simulation time 5433410465 ps
CPU time 67.95 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:49 PM PST 24
Peak memory 198748 kb
Host smart-98696130-b39e-4227-b633-fe7b35d596a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533985012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3533985012
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2455395814
Short name T583
Test name
Test status
Simulation time 2778304662 ps
CPU time 65.75 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:07:54 PM PST 24
Peak memory 198780 kb
Host smart-c1107fd9-047c-4063-8e93-122c05a32ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455395814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2455395814
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1419499160
Short name T325
Test name
Test status
Simulation time 3448319158 ps
CPU time 87.58 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:08:16 PM PST 24
Peak memory 198816 kb
Host smart-29d85b36-dc96-4e1d-a289-eb0afd2998c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419499160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1419499160
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1275589546
Short name T461
Test name
Test status
Simulation time 133260941 ps
CPU time 2.97 seconds
Started Jan 03 01:05:40 PM PST 24
Finished Jan 03 01:07:11 PM PST 24
Peak memory 198420 kb
Host smart-8b0b4c4e-f3ca-44b9-828b-19e705bf4cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275589546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1275589546
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3489601254
Short name T659
Test name
Test status
Simulation time 694013172404 ps
CPU time 836.3 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:20:59 PM PST 24
Peak memory 236712 kb
Host smart-8ffb00b4-8367-4417-a79e-9a5ab0247497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489601254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3489601254
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2393306222
Short name T733
Test name
Test status
Simulation time 77583701183 ps
CPU time 1402.1 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:30:30 PM PST 24
Peak memory 214944 kb
Host smart-16cf5f30-9a02-4ee5-8142-3cbd0ac1914f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393306222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.2393306222
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1005517691
Short name T708
Test name
Test status
Simulation time 271000717 ps
CPU time 1.15 seconds
Started Jan 03 01:06:03 PM PST 24
Finished Jan 03 01:07:25 PM PST 24
Peak memory 197364 kb
Host smart-eaee34bc-60ed-45cd-bc52-992d1ef6aecd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005517691 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1005517691
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1364849281
Short name T675
Test name
Test status
Simulation time 30902688386 ps
CPU time 352.37 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:12:36 PM PST 24
Peak memory 198800 kb
Host smart-efc97976-04e8-4992-b4c5-4f2b4a2d4dab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364849281 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1364849281
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.601875158
Short name T452
Test name
Test status
Simulation time 2258278176 ps
CPU time 47.06 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:07:35 PM PST 24
Peak memory 198808 kb
Host smart-4880203e-32b3-496a-93e1-df70cff602c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601875158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.601875158
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2966846075
Short name T525
Test name
Test status
Simulation time 50150772 ps
CPU time 0.6 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 194112 kb
Host smart-e38f98b2-713e-449a-9ceb-0f0b809dc49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966846075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2966846075
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.390359267
Short name T261
Test name
Test status
Simulation time 2498227860 ps
CPU time 13.29 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:06:58 PM PST 24
Peak memory 230484 kb
Host smart-186cefaf-55e4-4b54-a76e-2be88f8a365c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390359267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.390359267
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3655604676
Short name T202
Test name
Test status
Simulation time 4869208713 ps
CPU time 55.73 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:07:45 PM PST 24
Peak memory 198836 kb
Host smart-fb91f146-809b-4c7c-ae9e-85885836fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655604676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3655604676
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.764368485
Short name T648
Test name
Test status
Simulation time 147980553 ps
CPU time 7.37 seconds
Started Jan 03 01:05:21 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 198684 kb
Host smart-149622a5-8057-4863-a071-b88255e9f8e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764368485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.764368485
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.81622160
Short name T729
Test name
Test status
Simulation time 32922230522 ps
CPU time 194.88 seconds
Started Jan 03 01:06:05 PM PST 24
Finished Jan 03 01:10:47 PM PST 24
Peak memory 198824 kb
Host smart-080f494c-5128-4372-a81c-f5545519f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81622160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.81622160
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3637596370
Short name T493
Test name
Test status
Simulation time 16918269404 ps
CPU time 97.54 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:08:13 PM PST 24
Peak memory 198868 kb
Host smart-46f607b5-4a98-45fe-848a-54fd7a00f106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637596370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3637596370
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1592476214
Short name T781
Test name
Test status
Simulation time 406157732 ps
CPU time 3.04 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:06:52 PM PST 24
Peak memory 198676 kb
Host smart-580f6c98-9e73-4559-909f-c404f900d342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592476214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1592476214
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3467738872
Short name T488
Test name
Test status
Simulation time 39571945914 ps
CPU time 457.92 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:14:11 PM PST 24
Peak memory 215120 kb
Host smart-95550c24-fad2-470f-be02-77d261ebdde1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467738872 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3467738872
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.784199330
Short name T831
Test name
Test status
Simulation time 76899333202 ps
CPU time 3420.13 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 02:03:40 PM PST 24
Peak memory 239904 kb
Host smart-f3903aa1-07ce-425a-ac0a-dcef3d961d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784199330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.784199330
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2642734483
Short name T622
Test name
Test status
Simulation time 64865021 ps
CPU time 1.06 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 197032 kb
Host smart-53e3788f-1a78-438e-8caa-fa2408668a69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642734483 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2642734483
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1777274519
Short name T663
Test name
Test status
Simulation time 3999860462 ps
CPU time 67.56 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:07:57 PM PST 24
Peak memory 198812 kb
Host smart-61bbb8f1-2ed8-46bf-9725-d8ff54396575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777274519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1777274519
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3256290782
Short name T563
Test name
Test status
Simulation time 48480802 ps
CPU time 0.58 seconds
Started Jan 03 01:06:00 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 194136 kb
Host smart-ee1d135f-8d44-4d38-907c-83e42d3c1047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256290782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3256290782
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2509413942
Short name T363
Test name
Test status
Simulation time 56641249 ps
CPU time 2.06 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:07:20 PM PST 24
Peak memory 198692 kb
Host smart-b2b43784-c97d-4a9c-b76a-a417c7bfe670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509413942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2509413942
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.767255390
Short name T412
Test name
Test status
Simulation time 2363187412 ps
CPU time 29.78 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 198852 kb
Host smart-7a9ff833-c4b5-484d-b960-d7738abfcd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767255390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.767255390
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.457729071
Short name T318
Test name
Test status
Simulation time 64951568 ps
CPU time 0.63 seconds
Started Jan 03 01:05:29 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 193964 kb
Host smart-1562d9b9-6b08-4067-8f18-110080a5c251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457729071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.457729071
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3221909076
Short name T764
Test name
Test status
Simulation time 24110962230 ps
CPU time 188.7 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:09:57 PM PST 24
Peak memory 198880 kb
Host smart-66f93352-7eb3-4716-9216-dacbb229ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221909076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3221909076
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.781413239
Short name T786
Test name
Test status
Simulation time 2966799622 ps
CPU time 76.67 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:53 PM PST 24
Peak memory 198820 kb
Host smart-4e0e8fa9-5be1-4e14-bb64-eab47996687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781413239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.781413239
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3439579625
Short name T317
Test name
Test status
Simulation time 1363492020 ps
CPU time 3.87 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:06:56 PM PST 24
Peak memory 198732 kb
Host smart-d13116c6-6a67-48e1-b6e0-44dff2d8866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439579625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3439579625
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1942204465
Short name T119
Test name
Test status
Simulation time 207672261976 ps
CPU time 821.35 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:20:26 PM PST 24
Peak memory 240796 kb
Host smart-e0e20cae-11e4-4597-8808-551d64e20e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942204465 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1942204465
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2347515898
Short name T650
Test name
Test status
Simulation time 216294704887 ps
CPU time 1830.16 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:37:19 PM PST 24
Peak memory 245620 kb
Host smart-90441152-cb48-410e-b061-aadb818df6c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347515898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2347515898
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2691072757
Short name T11
Test name
Test status
Simulation time 86011816 ps
CPU time 0.83 seconds
Started Jan 03 01:05:24 PM PST 24
Finished Jan 03 01:06:45 PM PST 24
Peak memory 195896 kb
Host smart-7068839d-851c-45d6-8eda-8de3ed2a5372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691072757 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2691072757
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3152237625
Short name T208
Test name
Test status
Simulation time 35752656507 ps
CPU time 332.95 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:12:29 PM PST 24
Peak memory 198816 kb
Host smart-927df9dd-0b38-4016-86e2-ace9b20ea144
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152237625 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.3152237625
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2703442019
Short name T530
Test name
Test status
Simulation time 336679108 ps
CPU time 4.27 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:06:40 PM PST 24
Peak memory 198692 kb
Host smart-ade3fed6-bc62-4994-82e5-64a8c47bd467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703442019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2703442019
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.425826701
Short name T458
Test name
Test status
Simulation time 15605848 ps
CPU time 0.59 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:06:46 PM PST 24
Peak memory 194088 kb
Host smart-06175f2d-b232-4a13-be90-ca0edf850d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425826701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.425826701
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.618785138
Short name T436
Test name
Test status
Simulation time 5914037374 ps
CPU time 28.45 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 231564 kb
Host smart-8c04cfce-cd55-44e4-ac10-413d8d83c5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618785138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.618785138
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2397241740
Short name T216
Test name
Test status
Simulation time 636873162 ps
CPU time 27.19 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 198664 kb
Host smart-0bcb2ed0-c920-4d39-86a5-021364392f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397241740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2397241740
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.85931593
Short name T255
Test name
Test status
Simulation time 12454629770 ps
CPU time 122.75 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:08:40 PM PST 24
Peak memory 198812 kb
Host smart-ab745ed2-2512-4d70-a182-0cb57eaa24f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85931593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.85931593
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1569846342
Short name T787
Test name
Test status
Simulation time 320960006 ps
CPU time 15.98 seconds
Started Jan 03 01:05:25 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198452 kb
Host smart-0898083b-3aac-42b4-922b-77a4858c2e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569846342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1569846342
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2754774626
Short name T631
Test name
Test status
Simulation time 2596726718 ps
CPU time 18.54 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198884 kb
Host smart-de344284-033a-43f0-9dd7-f4b24588e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754774626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2754774626
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.582902624
Short name T243
Test name
Test status
Simulation time 1496696075 ps
CPU time 3.99 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 198652 kb
Host smart-efd490e4-c6c5-496c-b069-dda3b778c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582902624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.582902624
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3046302891
Short name T115
Test name
Test status
Simulation time 130517433818 ps
CPU time 1475.32 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:31:19 PM PST 24
Peak memory 223372 kb
Host smart-3b4412e4-c0d5-45fa-882b-fc30b493f7b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046302891 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3046302891
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3764446108
Short name T852
Test name
Test status
Simulation time 374883524017 ps
CPU time 1309.02 seconds
Started Jan 03 01:05:38 PM PST 24
Finished Jan 03 01:28:48 PM PST 24
Peak memory 228752 kb
Host smart-c4683177-a995-4623-9aee-2a17e875f2ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764446108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.3764446108
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3428919903
Short name T602
Test name
Test status
Simulation time 39045878 ps
CPU time 0.87 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 195952 kb
Host smart-61d66085-0f7b-4a04-83a1-04542faa71b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428919903 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3428919903
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.603145206
Short name T389
Test name
Test status
Simulation time 70383354541 ps
CPU time 432.31 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:14:12 PM PST 24
Peak memory 198772 kb
Host smart-e405c8c0-96b8-4472-8ed6-7b8d8129df39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603145206 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.hmac_test_sha_vectors.603145206
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.978263120
Short name T499
Test name
Test status
Simulation time 2544591327 ps
CPU time 18.33 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198820 kb
Host smart-d3393b64-bbeb-46c3-8878-50339d0fd5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978263120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.978263120
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.887302150
Short name T588
Test name
Test status
Simulation time 10882607 ps
CPU time 0.55 seconds
Started Jan 03 01:05:21 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 193100 kb
Host smart-e5074f68-1f57-4599-807d-76bf2d1855ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887302150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.887302150
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1988582717
Short name T359
Test name
Test status
Simulation time 608521011 ps
CPU time 2.52 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:06:43 PM PST 24
Peak memory 206836 kb
Host smart-28e0210c-3d34-4037-983d-62837a610d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988582717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1988582717
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2811952430
Short name T816
Test name
Test status
Simulation time 778237238 ps
CPU time 5.87 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198704 kb
Host smart-71401b0c-5da0-4297-8773-80e561b963a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811952430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2811952430
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.875254409
Short name T606
Test name
Test status
Simulation time 1853159821 ps
CPU time 23.88 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:07:30 PM PST 24
Peak memory 198668 kb
Host smart-d8dc1b7d-129e-4bc8-9989-d9e3f658402a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875254409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.875254409
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4152891526
Short name T299
Test name
Test status
Simulation time 5840520888 ps
CPU time 94.06 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:08:19 PM PST 24
Peak memory 198804 kb
Host smart-d3d00667-734a-4f05-8df3-2fa43d53a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152891526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4152891526
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1976635190
Short name T726
Test name
Test status
Simulation time 729102017 ps
CPU time 8.38 seconds
Started Jan 03 01:05:40 PM PST 24
Finished Jan 03 01:07:16 PM PST 24
Peak memory 198688 kb
Host smart-08808ab5-d9a6-4bc4-a8a9-a15eef2eeec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976635190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1976635190
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2211121142
Short name T278
Test name
Test status
Simulation time 112383081 ps
CPU time 0.78 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 194840 kb
Host smart-b783cf60-14b0-48c2-91c1-09f8320f9874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211121142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2211121142
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1416546357
Short name T795
Test name
Test status
Simulation time 6660161143 ps
CPU time 264.13 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:11:08 PM PST 24
Peak memory 198748 kb
Host smart-685317a3-4ab1-42e6-bd10-683c36ed840c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416546357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1416546357
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.1015324178
Short name T776
Test name
Test status
Simulation time 140301890156 ps
CPU time 884.57 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:21:28 PM PST 24
Peak memory 248020 kb
Host smart-d7b6744f-982d-4e88-9c56-d3b827cb81c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015324178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.1015324178
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1586598095
Short name T434
Test name
Test status
Simulation time 96842121 ps
CPU time 0.94 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 197032 kb
Host smart-2e63911f-1a82-4f9b-8ed8-c8329cdad4d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586598095 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1586598095
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3824808733
Short name T230
Test name
Test status
Simulation time 122853151449 ps
CPU time 356.54 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:12:49 PM PST 24
Peak memory 198796 kb
Host smart-62788d8f-dfe7-424a-bd12-6b0ef11b2ff6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824808733 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.3824808733
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1372667620
Short name T666
Test name
Test status
Simulation time 11262141449 ps
CPU time 63.06 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:07:37 PM PST 24
Peak memory 198848 kb
Host smart-bbf16c1b-06d6-4b88-ba99-d4eb0c29c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372667620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1372667620
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.315189508
Short name T407
Test name
Test status
Simulation time 39551065 ps
CPU time 0.55 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 193076 kb
Host smart-f1d4c6f4-7dc4-496d-8ffc-07db5998256c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315189508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.315189508
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2497565627
Short name T7
Test name
Test status
Simulation time 1455479550 ps
CPU time 45.95 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:07:31 PM PST 24
Peak memory 222100 kb
Host smart-180295b1-cdd2-403a-b87a-bc05fade6515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497565627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2497565627
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.574649219
Short name T286
Test name
Test status
Simulation time 1436159671 ps
CPU time 24.57 seconds
Started Jan 03 01:05:46 PM PST 24
Finished Jan 03 01:07:32 PM PST 24
Peak memory 198624 kb
Host smart-3c8ddedb-8cd4-4de0-816b-09441b477582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574649219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.574649219
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2473718147
Short name T203
Test name
Test status
Simulation time 4073397227 ps
CPU time 118.24 seconds
Started Jan 03 01:05:25 PM PST 24
Finished Jan 03 01:08:50 PM PST 24
Peak memory 198852 kb
Host smart-3326372b-1f25-406b-9055-2d0f2616496d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473718147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2473718147
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3941106357
Short name T405
Test name
Test status
Simulation time 62570165141 ps
CPU time 219.3 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:10:31 PM PST 24
Peak memory 198796 kb
Host smart-fcd9be9e-6dec-403d-93d5-ab5edcdb1c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941106357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3941106357
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.224654677
Short name T575
Test name
Test status
Simulation time 6098128346 ps
CPU time 17.76 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:07:28 PM PST 24
Peak memory 198792 kb
Host smart-6e66d0a8-56ed-48fa-8f8e-3f65ffff9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224654677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.224654677
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2031801708
Short name T253
Test name
Test status
Simulation time 308564527 ps
CPU time 3.14 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198712 kb
Host smart-23e8614f-8851-40d6-82ab-790e5abf49a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031801708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2031801708
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2718473903
Short name T657
Test name
Test status
Simulation time 1955398197869 ps
CPU time 2048.84 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:40:49 PM PST 24
Peak memory 231560 kb
Host smart-e46be63f-7303-43bd-8abb-30ed076b4449
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718473903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2718473903
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.250592042
Short name T523
Test name
Test status
Simulation time 89103634942 ps
CPU time 434.01 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:14:03 PM PST 24
Peak memory 214396 kb
Host smart-511a53b5-5331-427b-97d0-4f5287774d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250592042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.250592042
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1446712012
Short name T516
Test name
Test status
Simulation time 75589839 ps
CPU time 1.21 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 196472 kb
Host smart-362ef0a4-5a1b-40a1-8df6-ad2453422760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446712012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1446712012
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1726053149
Short name T419
Test name
Test status
Simulation time 71482903457 ps
CPU time 433.89 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:14:00 PM PST 24
Peak memory 198792 kb
Host smart-e2186acf-259e-4cd3-b669-b6f2cbd5d647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726053149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1726053149
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1049524827
Short name T639
Test name
Test status
Simulation time 11758853991 ps
CPU time 50.37 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:08:02 PM PST 24
Peak memory 198864 kb
Host smart-b5f283f0-c6e8-4e33-a881-95734254f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049524827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1049524827
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4039277434
Short name T600
Test name
Test status
Simulation time 49759455 ps
CPU time 0.55 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:06:48 PM PST 24
Peak memory 194100 kb
Host smart-a51e5321-6669-430b-b134-d4a0a05b573d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039277434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4039277434
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3156163110
Short name T6
Test name
Test status
Simulation time 269471308 ps
CPU time 4.5 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:06:56 PM PST 24
Peak memory 198708 kb
Host smart-3339a7da-10da-41da-8205-4cff621cf1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156163110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3156163110
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.881039407
Short name T487
Test name
Test status
Simulation time 2338757990 ps
CPU time 20.79 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 198848 kb
Host smart-24ee0814-bb85-4d75-805a-4572ae89a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881039407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.881039407
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.88152649
Short name T579
Test name
Test status
Simulation time 7187324746 ps
CPU time 88.15 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:08:05 PM PST 24
Peak memory 198836 kb
Host smart-72061f61-2a6e-4419-8c78-2c7f240dc9fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88152649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.88152649
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1997329020
Short name T289
Test name
Test status
Simulation time 507263322 ps
CPU time 8.4 seconds
Started Jan 03 01:06:02 PM PST 24
Finished Jan 03 01:07:34 PM PST 24
Peak memory 198652 kb
Host smart-045e9713-5313-446e-8da7-6aeef2019534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997329020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1997329020
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.749878014
Short name T429
Test name
Test status
Simulation time 3497006713 ps
CPU time 45.91 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198836 kb
Host smart-2c8ab544-30bc-42a8-b2aa-bd18601df9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749878014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.749878014
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2310405573
Short name T723
Test name
Test status
Simulation time 441391034 ps
CPU time 4.68 seconds
Started Jan 03 01:05:32 PM PST 24
Finished Jan 03 01:06:54 PM PST 24
Peak memory 198500 kb
Host smart-4e98356b-b37b-4ac8-95cf-14c2d59fc851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310405573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2310405573
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.51378492
Short name T132
Test name
Test status
Simulation time 650135018499 ps
CPU time 961.19 seconds
Started Jan 03 01:05:26 PM PST 24
Finished Jan 03 01:22:44 PM PST 24
Peak memory 229460 kb
Host smart-a3d53d39-fd86-4cbe-acb7-afc740138b78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51378492 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.51378492
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.4220648155
Short name T793
Test name
Test status
Simulation time 386040480424 ps
CPU time 663.36 seconds
Started Jan 03 01:05:16 PM PST 24
Finished Jan 03 01:17:36 PM PST 24
Peak memory 215312 kb
Host smart-04edfc8c-eca2-40f0-80ff-f8fc959cfda3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220648155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.4220648155
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2071306327
Short name T504
Test name
Test status
Simulation time 201440390 ps
CPU time 0.94 seconds
Started Jan 03 01:05:41 PM PST 24
Finished Jan 03 01:07:01 PM PST 24
Peak memory 196936 kb
Host smart-6f17032d-711d-4347-b022-5c8df5cef4c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071306327 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2071306327
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3166034123
Short name T275
Test name
Test status
Simulation time 40547799600 ps
CPU time 434.93 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:14:08 PM PST 24
Peak memory 198764 kb
Host smart-f343a20f-9d67-426a-9216-d943682feb7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166034123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.3166034123
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.537436959
Short name T54
Test name
Test status
Simulation time 753853497 ps
CPU time 9.36 seconds
Started Jan 03 01:05:52 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 198804 kb
Host smart-cddb4951-9ec6-4c86-a182-a1cf244e532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537436959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.537436959
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2638020006
Short name T314
Test name
Test status
Simulation time 35406691 ps
CPU time 0.54 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 193036 kb
Host smart-ec3d6b01-fec2-4772-bd3b-dbfca6c5ff38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638020006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2638020006
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.406326443
Short name T526
Test name
Test status
Simulation time 956237618 ps
CPU time 28.11 seconds
Started Jan 03 01:05:18 PM PST 24
Finished Jan 03 01:07:04 PM PST 24
Peak memory 212080 kb
Host smart-8b441c89-2408-44d1-ace2-7faaf7b59e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406326443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.406326443
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2716299515
Short name T720
Test name
Test status
Simulation time 886129426 ps
CPU time 41.58 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:07:49 PM PST 24
Peak memory 198656 kb
Host smart-31f6869f-4d07-4ea3-b72c-6efe79f9527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716299515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2716299515
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2389250584
Short name T338
Test name
Test status
Simulation time 6825560531 ps
CPU time 119.51 seconds
Started Jan 03 01:05:33 PM PST 24
Finished Jan 03 01:08:51 PM PST 24
Peak memory 198904 kb
Host smart-e72e5497-e4d2-42e4-ae12-a42bf5fac10b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389250584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2389250584
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2736349241
Short name T285
Test name
Test status
Simulation time 3162207826 ps
CPU time 48.27 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:07:28 PM PST 24
Peak memory 198856 kb
Host smart-6339a06e-7019-41e4-92c0-6d85342bffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736349241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2736349241
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1175019007
Short name T734
Test name
Test status
Simulation time 3869460309 ps
CPU time 95.42 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:08:27 PM PST 24
Peak memory 198740 kb
Host smart-523ad504-1384-456f-b9e8-91d89dab842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175019007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1175019007
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3418148396
Short name T498
Test name
Test status
Simulation time 366012707 ps
CPU time 3.97 seconds
Started Jan 03 01:05:35 PM PST 24
Finished Jan 03 01:06:56 PM PST 24
Peak memory 198748 kb
Host smart-92b94f22-25d2-4851-98d1-db57b5eefa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418148396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3418148396
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3688394455
Short name T437
Test name
Test status
Simulation time 78031513016 ps
CPU time 970.02 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:22:53 PM PST 24
Peak memory 198832 kb
Host smart-1fa10f9d-b8aa-4807-9771-57397a1e0831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688394455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3688394455
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.3589566122
Short name T462
Test name
Test status
Simulation time 314180043576 ps
CPU time 2724.79 seconds
Started Jan 03 01:05:35 PM PST 24
Finished Jan 03 01:52:17 PM PST 24
Peak memory 256388 kb
Host smart-25f5ece3-dc16-40d3-b2ad-c27e4bbc991a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589566122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.3589566122
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2776609958
Short name T441
Test name
Test status
Simulation time 47036295 ps
CPU time 0.94 seconds
Started Jan 03 01:06:01 PM PST 24
Finished Jan 03 01:07:33 PM PST 24
Peak memory 195884 kb
Host smart-bdeb54bb-2729-4fde-86ab-e4689518058f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776609958 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2776609958
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1505737541
Short name T857
Test name
Test status
Simulation time 156614258957 ps
CPU time 427.16 seconds
Started Jan 03 01:05:13 PM PST 24
Finished Jan 03 01:13:40 PM PST 24
Peak memory 198852 kb
Host smart-954d758a-db5b-4df1-bb28-a3f310295dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505737541 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.1505737541
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1265133493
Short name T501
Test name
Test status
Simulation time 17151215275 ps
CPU time 74.01 seconds
Started Jan 03 01:06:02 PM PST 24
Finished Jan 03 01:08:45 PM PST 24
Peak memory 198840 kb
Host smart-00e8c60a-fed5-4409-a6ed-0ca70a0071e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265133493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1265133493
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1740316585
Short name T250
Test name
Test status
Simulation time 40551704 ps
CPU time 0.57 seconds
Started Jan 03 01:06:03 PM PST 24
Finished Jan 03 01:07:27 PM PST 24
Peak memory 193060 kb
Host smart-f57d7e77-835e-47db-8380-288de4ed32ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740316585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1740316585
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4129910041
Short name T457
Test name
Test status
Simulation time 106587140 ps
CPU time 2.57 seconds
Started Jan 03 01:05:11 PM PST 24
Finished Jan 03 01:06:31 PM PST 24
Peak memory 198612 kb
Host smart-2331236c-c8b8-43b7-9c0e-b431ea4ac4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129910041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4129910041
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.891863257
Short name T464
Test name
Test status
Simulation time 10098225471 ps
CPU time 34.27 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:07:41 PM PST 24
Peak memory 198852 kb
Host smart-bfd6f3d3-d98c-4256-aa09-7498d40ee7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891863257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.891863257
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1689626960
Short name T705
Test name
Test status
Simulation time 2487915457 ps
CPU time 93.36 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:08:48 PM PST 24
Peak memory 198860 kb
Host smart-2c860fae-fdad-4356-bfbe-24b383fcd5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689626960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1689626960
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2938976170
Short name T702
Test name
Test status
Simulation time 15825017796 ps
CPU time 88.21 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:08:07 PM PST 24
Peak memory 198900 kb
Host smart-124b5555-a1eb-4912-89cd-e0b87e9baa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938976170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2938976170
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2275620992
Short name T378
Test name
Test status
Simulation time 3483944513 ps
CPU time 45.12 seconds
Started Jan 03 01:05:36 PM PST 24
Finished Jan 03 01:07:39 PM PST 24
Peak memory 198804 kb
Host smart-6f92f3b6-367d-4222-a229-42f67b5ca32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275620992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2275620992
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3197847151
Short name T263
Test name
Test status
Simulation time 905798760 ps
CPU time 2.65 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:06:51 PM PST 24
Peak memory 198752 kb
Host smart-c415993f-b48d-452f-86c6-b4114ced1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197847151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3197847151
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1654201952
Short name T293
Test name
Test status
Simulation time 8750258573 ps
CPU time 36.45 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:07:52 PM PST 24
Peak memory 198864 kb
Host smart-357818f3-6ec2-49b4-a608-57871b99a43d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654201952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1654201952
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.71043721
Short name T674
Test name
Test status
Simulation time 31071920832 ps
CPU time 552.12 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:16:30 PM PST 24
Peak memory 214772 kb
Host smart-d48eec48-3565-4897-bb1f-26a58665c8a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71043721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.71043721
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.291016345
Short name T194
Test name
Test status
Simulation time 621749516 ps
CPU time 1.14 seconds
Started Jan 03 01:05:46 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 197580 kb
Host smart-3b56c9e1-fa8e-4a12-b228-fea9cee7edf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291016345 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.291016345
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2780099668
Short name T557
Test name
Test status
Simulation time 34448689664 ps
CPU time 412.77 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:13:46 PM PST 24
Peak memory 198828 kb
Host smart-e434a945-07a5-424d-9f72-2cbaa100b845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780099668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.2780099668
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2793736549
Short name T303
Test name
Test status
Simulation time 1303885774 ps
CPU time 20.64 seconds
Started Jan 03 01:05:27 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 198472 kb
Host smart-f6f2b7f7-faec-40fe-aa5c-d4ebb5574fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793736549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2793736549
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1495403627
Short name T683
Test name
Test status
Simulation time 35913920 ps
CPU time 0.59 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:06:39 PM PST 24
Peak memory 193144 kb
Host smart-6f77bfb0-83a1-4ac9-b778-3ac8625f03c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495403627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1495403627
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.438581730
Short name T324
Test name
Test status
Simulation time 491696374 ps
CPU time 12.07 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:37 PM PST 24
Peak memory 206940 kb
Host smart-f7d583a4-4877-4f6e-b2ab-65417274f73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438581730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.438581730
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3741237795
Short name T247
Test name
Test status
Simulation time 564710109 ps
CPU time 6.35 seconds
Started Jan 03 01:05:09 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 198764 kb
Host smart-407362f2-8676-4ebb-95af-947d00e5a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741237795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3741237795
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2980085799
Short name T471
Test name
Test status
Simulation time 4494184563 ps
CPU time 55.94 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198828 kb
Host smart-023551a8-fe74-4127-b491-5362bbeb173f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980085799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2980085799
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.423529472
Short name T644
Test name
Test status
Simulation time 1460568127 ps
CPU time 61.92 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:07:16 PM PST 24
Peak memory 198712 kb
Host smart-f853b3f1-c881-41bc-8639-0002b731b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423529472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.423529472
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3681239107
Short name T406
Test name
Test status
Simulation time 102053376 ps
CPU time 1.23 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:26 PM PST 24
Peak memory 198444 kb
Host smart-e3ebfc80-e663-40fb-a521-c0eaca08d30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681239107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3681239107
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.541584917
Short name T672
Test name
Test status
Simulation time 178675618438 ps
CPU time 2055.78 seconds
Started Jan 03 01:05:02 PM PST 24
Finished Jan 03 01:40:37 PM PST 24
Peak memory 234452 kb
Host smart-fdb95974-4588-4204-ae8c-0e7a3e2d0d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541584917 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.541584917
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.4053659649
Short name T45
Test name
Test status
Simulation time 9218571350 ps
CPU time 467.12 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:14:05 PM PST 24
Peak memory 214744 kb
Host smart-a7b32f50-0555-4dab-badf-ed675265d4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053659649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.4053659649
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.805762809
Short name T506
Test name
Test status
Simulation time 334365868 ps
CPU time 1.06 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:28 PM PST 24
Peak memory 197116 kb
Host smart-0b8c56e0-a66e-4296-8f12-582ec1061fee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805762809 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.805762809
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3057347763
Short name T364
Test name
Test status
Simulation time 65155623310 ps
CPU time 393.98 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:12:41 PM PST 24
Peak memory 198808 kb
Host smart-15699241-7b9a-4e3f-937a-6aca88ec7b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057347763 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.3057347763
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3432949935
Short name T331
Test name
Test status
Simulation time 2225681669 ps
CPU time 39.28 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 198800 kb
Host smart-7033d449-d2dc-40ae-ab0b-53d3292c18cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432949935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3432949935
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.2678762061
Short name T282
Test name
Test status
Simulation time 39284007489 ps
CPU time 753.58 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:19:21 PM PST 24
Peak memory 241856 kb
Host smart-aaed31f5-381f-458f-a1fe-9a9fd6bfddb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678762061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.2678762061
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.3710041249
Short name T621
Test name
Test status
Simulation time 152086216152 ps
CPU time 1115.33 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 01:25:37 PM PST 24
Peak memory 239912 kb
Host smart-ad110cd5-3e30-40b5-89e9-630a8e2fb0c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710041249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.3710041249
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.3709729128
Short name T761
Test name
Test status
Simulation time 73328742574 ps
CPU time 1327.16 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:28:55 PM PST 24
Peak memory 244876 kb
Host smart-2653c4a5-7010-4be4-9063-3acf93aa9369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709729128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.3709729128
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.1321327127
Short name T669
Test name
Test status
Simulation time 553091747538 ps
CPU time 571.76 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:16:47 PM PST 24
Peak memory 223476 kb
Host smart-556b5a53-20b0-48bc-bc8b-b4404694dde1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321327127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.1321327127
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.23763526
Short name T344
Test name
Test status
Simulation time 30810105239 ps
CPU time 418.41 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:14:10 PM PST 24
Peak memory 229832 kb
Host smart-7e31183b-18b7-40e7-ad7f-8cf84b23341c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23763526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.23763526
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.973596378
Short name T636
Test name
Test status
Simulation time 680183487073 ps
CPU time 1215.78 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:27:24 PM PST 24
Peak memory 247080 kb
Host smart-8f6ad89a-4140-4588-8a61-99d89b4141df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973596378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.973596378
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.4286673396
Short name T456
Test name
Test status
Simulation time 65404027334 ps
CPU time 888.32 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:21:57 PM PST 24
Peak memory 253056 kb
Host smart-221d40dd-524f-4990-82e0-39bbe2f5e2e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286673396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.4286673396
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.3800075359
Short name T270
Test name
Test status
Simulation time 75548931698 ps
CPU time 1505.74 seconds
Started Jan 03 01:05:30 PM PST 24
Finished Jan 03 01:31:54 PM PST 24
Peak memory 247064 kb
Host smart-f5b46861-e938-4145-9085-a40bddb7f664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800075359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.3800075359
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3030785720
Short name T796
Test name
Test status
Simulation time 306799401311 ps
CPU time 3509.64 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 02:05:36 PM PST 24
Peak memory 223552 kb
Host smart-26d5b726-60c5-4370-b564-2f14c511e8b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030785720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.3030785720
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.357863602
Short name T778
Test name
Test status
Simulation time 14690839 ps
CPU time 0.54 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 193104 kb
Host smart-d110c4a8-5ad1-4fc7-98f8-21024497583a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357863602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.357863602
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3803772946
Short name T540
Test name
Test status
Simulation time 2114387172 ps
CPU time 14.79 seconds
Started Jan 03 01:05:08 PM PST 24
Finished Jan 03 01:06:41 PM PST 24
Peak memory 208972 kb
Host smart-dd1ff7f0-944d-4b82-86ae-551c1fca0775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803772946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3803772946
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1871874918
Short name T505
Test name
Test status
Simulation time 1386795596 ps
CPU time 24.86 seconds
Started Jan 03 01:05:52 PM PST 24
Finished Jan 03 01:07:38 PM PST 24
Peak memory 198700 kb
Host smart-8e154fdc-03cc-4b7f-a937-c998af3d0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871874918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1871874918
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.120177826
Short name T566
Test name
Test status
Simulation time 1879357370 ps
CPU time 96.14 seconds
Started Jan 03 01:04:53 PM PST 24
Finished Jan 03 01:07:50 PM PST 24
Peak memory 198672 kb
Host smart-c3967a9e-d824-4efc-aefe-d929810db45c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120177826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.120177826
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4258288475
Short name T476
Test name
Test status
Simulation time 5723304186 ps
CPU time 71.02 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:07:15 PM PST 24
Peak memory 198832 kb
Host smart-d02c9f69-950f-401b-819d-29fb79567f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258288475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4258288475
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1243779950
Short name T510
Test name
Test status
Simulation time 60748615337 ps
CPU time 44.39 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 198804 kb
Host smart-1ba22b49-09d2-48db-98da-48c664bbd98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243779950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1243779950
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4052873960
Short name T204
Test name
Test status
Simulation time 262864238 ps
CPU time 2.76 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:30 PM PST 24
Peak memory 198592 kb
Host smart-9d86e9c2-420e-45ac-86b1-48a961547fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052873960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4052873960
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.800696652
Short name T519
Test name
Test status
Simulation time 9653903422 ps
CPU time 450.38 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:13:34 PM PST 24
Peak memory 198844 kb
Host smart-260a23ad-0efc-4487-bffb-fd5089cf2993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800696652 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.800696652
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2135494251
Short name T691
Test name
Test status
Simulation time 387051085326 ps
CPU time 4730.91 seconds
Started Jan 03 01:04:56 PM PST 24
Finished Jan 03 02:25:10 PM PST 24
Peak memory 252052 kb
Host smart-90592b75-435c-4efa-90bd-aa7b10d03058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135494251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2135494251
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2909291668
Short name T336
Test name
Test status
Simulation time 103492221 ps
CPU time 0.87 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 195764 kb
Host smart-05b6697d-dc38-4d17-b97c-7fc95a3c2b9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909291668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2909291668
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3593840129
Short name T226
Test name
Test status
Simulation time 149060012639 ps
CPU time 411.13 seconds
Started Jan 03 01:04:41 PM PST 24
Finished Jan 03 01:12:51 PM PST 24
Peak memory 198784 kb
Host smart-d21ba5fd-d39b-4d70-884e-d3cfd6729463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593840129 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3593840129
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.975797814
Short name T197
Test name
Test status
Simulation time 1841690008 ps
CPU time 21.53 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:54 PM PST 24
Peak memory 198644 kb
Host smart-2a7b51de-78b1-42f6-93b6-ebf16b78b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975797814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.975797814
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.3105055390
Short name T455
Test name
Test status
Simulation time 256366292736 ps
CPU time 2112.43 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:42:16 PM PST 24
Peak memory 231676 kb
Host smart-cb7de280-e7a0-4b39-bfa0-523ba2447396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105055390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.3105055390
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.1937218874
Short name T451
Test name
Test status
Simulation time 22739284990 ps
CPU time 721.41 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:19:06 PM PST 24
Peak memory 235800 kb
Host smart-ff795122-e4bf-4c74-9b37-f01d763771f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937218874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.1937218874
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.474434320
Short name T699
Test name
Test status
Simulation time 440972326948 ps
CPU time 5204.3 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 02:33:46 PM PST 24
Peak memory 272644 kb
Host smart-dfc50e3e-b063-4452-ac22-b8e1de7ad0aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474434320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.474434320
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.3018929567
Short name T735
Test name
Test status
Simulation time 7493915380 ps
CPU time 397.57 seconds
Started Jan 03 01:05:42 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 215328 kb
Host smart-ea7b2d97-c8fb-4bf5-b1e1-6a9eff30d09f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018929567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.3018929567
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.874131078
Short name T5
Test name
Test status
Simulation time 84074383574 ps
CPU time 1391.32 seconds
Started Jan 03 01:05:55 PM PST 24
Finished Jan 03 01:30:29 PM PST 24
Peak memory 240920 kb
Host smart-84447f5c-008c-4b5c-823d-f408817971e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874131078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.874131078
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3069935907
Short name T111
Test name
Test status
Simulation time 68596893412 ps
CPU time 1796.68 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 01:37:09 PM PST 24
Peak memory 256216 kb
Host smart-71cdc903-6f07-464b-a26d-f3935b204f60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069935907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3069935907
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1792001546
Short name T841
Test name
Test status
Simulation time 113164398650 ps
CPU time 823 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:20:34 PM PST 24
Peak memory 223496 kb
Host smart-8a647f25-4008-4eaa-9e4b-bd098ecef5a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792001546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.1792001546
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.3124831600
Short name T38
Test name
Test status
Simulation time 249557865659 ps
CPU time 2321.04 seconds
Started Jan 03 01:05:52 PM PST 24
Finished Jan 03 01:45:55 PM PST 24
Peak memory 248068 kb
Host smart-b18a04c3-8b26-4275-a1f8-78d375af0315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124831600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.3124831600
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.1272673441
Short name T706
Test name
Test status
Simulation time 15266612079 ps
CPU time 729.02 seconds
Started Jan 03 01:05:50 PM PST 24
Finished Jan 03 01:19:20 PM PST 24
Peak memory 212816 kb
Host smart-b47a2987-8519-4788-befc-130c93f40631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272673441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.1272673441
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1484190299
Short name T283
Test name
Test status
Simulation time 50510538 ps
CPU time 0.57 seconds
Started Jan 03 01:04:52 PM PST 24
Finished Jan 03 01:06:16 PM PST 24
Peak memory 194164 kb
Host smart-5ed49577-8530-46b3-a5ac-f478ae2b36c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484190299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1484190299
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2972951468
Short name T843
Test name
Test status
Simulation time 786521949 ps
CPU time 24.22 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 214788 kb
Host smart-e5c83c77-a475-43a6-97e9-a42503de72ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972951468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2972951468
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4104007726
Short name T656
Test name
Test status
Simulation time 9741495755 ps
CPU time 29.96 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:33 PM PST 24
Peak memory 198696 kb
Host smart-f184d154-e1c8-420a-826f-3baab9f60583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104007726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4104007726
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3332811878
Short name T426
Test name
Test status
Simulation time 1018836204 ps
CPU time 8.62 seconds
Started Jan 03 01:04:41 PM PST 24
Finished Jan 03 01:06:12 PM PST 24
Peak memory 198732 kb
Host smart-ddb64270-ab57-411a-b572-3ab73f40c7b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332811878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3332811878
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1649133784
Short name T258
Test name
Test status
Simulation time 1748030313 ps
CPU time 16.62 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:19 PM PST 24
Peak memory 198496 kb
Host smart-16225eec-8be4-42a1-b428-98b3a23e47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649133784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1649133784
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1349048344
Short name T367
Test name
Test status
Simulation time 10474800602 ps
CPU time 89.86 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:07:42 PM PST 24
Peak memory 198840 kb
Host smart-85ac15ae-b6b3-4c31-99f0-4e6772d5f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349048344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1349048344
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1345343267
Short name T329
Test name
Test status
Simulation time 143410708 ps
CPU time 1.89 seconds
Started Jan 03 01:04:37 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 198640 kb
Host smart-57f691b5-33aa-4823-a1e9-a6b2d06f3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345343267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1345343267
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1303132911
Short name T431
Test name
Test status
Simulation time 26271819 ps
CPU time 0.59 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 01:06:34 PM PST 24
Peak memory 193080 kb
Host smart-463b7686-fd71-4b5e-aaaa-0c55924d761a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303132911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1303132911
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3211094067
Short name T559
Test name
Test status
Simulation time 59573695701 ps
CPU time 523.08 seconds
Started Jan 03 01:04:52 PM PST 24
Finished Jan 03 01:14:54 PM PST 24
Peak memory 247880 kb
Host smart-253c1a07-c2d4-4d03-8d4d-f5bb91cdd5ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211094067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3211094067
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.680560948
Short name T397
Test name
Test status
Simulation time 88228903 ps
CPU time 0.88 seconds
Started Jan 03 01:04:59 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 196260 kb
Host smart-187fa19b-24ad-4224-8990-7e394fa424bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680560948 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.680560948
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2208981527
Short name T593
Test name
Test status
Simulation time 30418808788 ps
CPU time 476.35 seconds
Started Jan 03 01:04:55 PM PST 24
Finished Jan 03 01:14:11 PM PST 24
Peak memory 198812 kb
Host smart-9cc18605-65e3-4546-855a-b955964d0eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208981527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.2208981527
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2805610463
Short name T432
Test name
Test status
Simulation time 10825503769 ps
CPU time 48.06 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 198824 kb
Host smart-a8bce749-a807-417a-b727-80ad96a76dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805610463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2805610463
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2236141213
Short name T833
Test name
Test status
Simulation time 29685058717 ps
CPU time 1370.65 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:30:03 PM PST 24
Peak memory 231676 kb
Host smart-ea2816f2-f4b9-414e-bd5f-a404b92cbf5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236141213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2236141213
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1908688565
Short name T494
Test name
Test status
Simulation time 23872838309 ps
CPU time 434.99 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:14:18 PM PST 24
Peak memory 223032 kb
Host smart-6e50d031-170e-41e3-802b-4387ecfe37ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908688565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1908688565
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.3892511404
Short name T627
Test name
Test status
Simulation time 44135770760 ps
CPU time 382.48 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:13:30 PM PST 24
Peak memory 241160 kb
Host smart-ede3b4da-eb9d-4321-883d-46f3219c5b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892511404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.3892511404
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.1701213135
Short name T695
Test name
Test status
Simulation time 42796984567 ps
CPU time 390.22 seconds
Started Jan 03 01:05:59 PM PST 24
Finished Jan 03 01:13:51 PM PST 24
Peak memory 215200 kb
Host smart-5633930d-8c1b-42dc-ba78-e4b4ea7987d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701213135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.1701213135
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.649638942
Short name T479
Test name
Test status
Simulation time 229159447652 ps
CPU time 2095.28 seconds
Started Jan 03 01:05:57 PM PST 24
Finished Jan 03 01:42:15 PM PST 24
Peak memory 231732 kb
Host smart-67dd7e38-e19b-43a8-9d79-667fa18fa296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649638942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.649638942
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.632289829
Short name T552
Test name
Test status
Simulation time 53098470813 ps
CPU time 435.72 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:14:31 PM PST 24
Peak memory 207132 kb
Host smart-a77f1158-b149-4016-a18e-68864cbda2d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632289829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.632289829
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.1408792116
Short name T195
Test name
Test status
Simulation time 55166882843 ps
CPU time 434.56 seconds
Started Jan 03 01:05:40 PM PST 24
Finished Jan 03 01:14:14 PM PST 24
Peak memory 231620 kb
Host smart-d30cf380-9f8e-48ab-9e80-a217036b7024
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408792116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.1408792116
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.670532213
Short name T380
Test name
Test status
Simulation time 40340364649 ps
CPU time 362.34 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:12:54 PM PST 24
Peak memory 214888 kb
Host smart-72747666-e121-499c-b087-952ad7aa26d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670532213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.670532213
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.3035913338
Short name T651
Test name
Test status
Simulation time 665536112869 ps
CPU time 3968.75 seconds
Started Jan 03 01:05:49 PM PST 24
Finished Jan 03 02:13:19 PM PST 24
Peak memory 263472 kb
Host smart-d3260921-8a71-4c38-bc24-d6949d953782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035913338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.3035913338
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.697875432
Short name T760
Test name
Test status
Simulation time 10660639437 ps
CPU time 186.86 seconds
Started Jan 03 01:05:47 PM PST 24
Finished Jan 03 01:10:13 PM PST 24
Peak memory 198780 kb
Host smart-cb5ecf5d-cd95-45b9-9ab0-384619ff227e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697875432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.697875432
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1799414809
Short name T591
Test name
Test status
Simulation time 56731732 ps
CPU time 0.54 seconds
Started Jan 03 01:04:47 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 193100 kb
Host smart-b4408db0-8f42-424e-8cd1-7e51921f9842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799414809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1799414809
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2632135704
Short name T811
Test name
Test status
Simulation time 422400816 ps
CPU time 12.8 seconds
Started Jan 03 01:04:54 PM PST 24
Finished Jan 03 01:06:27 PM PST 24
Peak memory 206900 kb
Host smart-21010f3d-8340-4ac9-b2e0-ab0a56e492a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632135704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2632135704
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2702301955
Short name T565
Test name
Test status
Simulation time 6602711557 ps
CPU time 30.89 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 198848 kb
Host smart-8cf0dbd7-63bd-444b-bb90-eaa2490ecf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702301955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2702301955
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3511233435
Short name T480
Test name
Test status
Simulation time 16577512725 ps
CPU time 78.28 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:07:45 PM PST 24
Peak memory 198728 kb
Host smart-d5724916-c957-4f0a-956c-885895a4ceb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511233435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3511233435
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3441527139
Short name T605
Test name
Test status
Simulation time 34229110596 ps
CPU time 232.63 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:10:05 PM PST 24
Peak memory 198828 kb
Host smart-71208e41-c016-41e5-839e-4079d1d23c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441527139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3441527139
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.722654654
Short name T569
Test name
Test status
Simulation time 36111422094 ps
CPU time 111.54 seconds
Started Jan 03 01:05:01 PM PST 24
Finished Jan 03 01:08:11 PM PST 24
Peak memory 198872 kb
Host smart-c4006851-f336-4ddd-9340-2e65288e77b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722654654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.722654654
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.709396369
Short name T740
Test name
Test status
Simulation time 166219598 ps
CPU time 1.45 seconds
Started Jan 03 01:04:50 PM PST 24
Finished Jan 03 01:06:14 PM PST 24
Peak memory 198420 kb
Host smart-57fbc24d-d4ff-4ddc-9b69-f3d6a1a78e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709396369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.709396369
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2651502149
Short name T117
Test name
Test status
Simulation time 30322065738 ps
CPU time 706.07 seconds
Started Jan 03 01:04:58 PM PST 24
Finished Jan 03 01:18:04 PM PST 24
Peak memory 198836 kb
Host smart-da26d291-3146-403d-acac-736ef44e818e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651502149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2651502149
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4061559708
Short name T328
Test name
Test status
Simulation time 79485059001 ps
CPU time 1065.61 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:24:02 PM PST 24
Peak memory 215272 kb
Host smart-59913012-3041-4cea-9cc9-c61b99e3acac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061559708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4061559708
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3850910761
Short name T248
Test name
Test status
Simulation time 34611729 ps
CPU time 0.91 seconds
Started Jan 03 01:05:03 PM PST 24
Finished Jan 03 01:06:22 PM PST 24
Peak memory 195956 kb
Host smart-8a2354e9-60e3-4136-bc8a-84a606a6368f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850910761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3850910761
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3448841409
Short name T246
Test name
Test status
Simulation time 18973526336 ps
CPU time 380.37 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 198888 kb
Host smart-febfc4da-d2ee-42e3-b197-6811b9773e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448841409 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.3448841409
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3075782547
Short name T470
Test name
Test status
Simulation time 453026972 ps
CPU time 17.8 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:06:42 PM PST 24
Peak memory 198624 kb
Host smart-4f66b945-4ab7-4806-aa24-3a7686413d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075782547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3075782547
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1360635823
Short name T511
Test name
Test status
Simulation time 163351314622 ps
CPU time 3861.93 seconds
Started Jan 03 01:05:43 PM PST 24
Finished Jan 03 02:11:25 PM PST 24
Peak memory 264392 kb
Host smart-fde3d4c2-f315-4911-a655-84eddc499722
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360635823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.1360635823
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4037262256
Short name T520
Test name
Test status
Simulation time 49253100991 ps
CPU time 674.7 seconds
Started Jan 03 01:05:56 PM PST 24
Finished Jan 03 01:18:33 PM PST 24
Peak memory 215248 kb
Host smart-3b0ba286-7909-458d-b1a2-d63199330ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037262256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.4037262256
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.2101334701
Short name T233
Test name
Test status
Simulation time 19124278689 ps
CPU time 282.59 seconds
Started Jan 03 01:05:17 PM PST 24
Finished Jan 03 01:11:23 PM PST 24
Peak memory 207112 kb
Host smart-a23dc451-4073-44ff-9355-e2edc8e72857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2101334701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.2101334701
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.330587703
Short name T840
Test name
Test status
Simulation time 86149874921 ps
CPU time 884.14 seconds
Started Jan 03 01:06:01 PM PST 24
Finished Jan 03 01:22:16 PM PST 24
Peak memory 223508 kb
Host smart-a986571a-b23b-4b44-9c33-17d774011a20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330587703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.330587703
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1415306588
Short name T267
Test name
Test status
Simulation time 18892110616 ps
CPU time 888.54 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:21:40 PM PST 24
Peak memory 215284 kb
Host smart-5227e16f-6450-45e1-acab-1a4e825046dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415306588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.1415306588
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.290448001
Short name T541
Test name
Test status
Simulation time 21322504442 ps
CPU time 147.21 seconds
Started Jan 03 01:05:25 PM PST 24
Finished Jan 03 01:09:16 PM PST 24
Peak memory 214884 kb
Host smart-dbbba390-643c-4099-8f91-7e7cae268006
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290448001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.290448001
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.3140391328
Short name T738
Test name
Test status
Simulation time 374294898979 ps
CPU time 3259.66 seconds
Started Jan 03 01:05:15 PM PST 24
Finished Jan 03 02:00:54 PM PST 24
Peak memory 257296 kb
Host smart-6260250a-e47d-491b-abab-d29c790bd701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140391328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.3140391328
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1054948649
Short name T124
Test name
Test status
Simulation time 283349882639 ps
CPU time 825.99 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:20:24 PM PST 24
Peak memory 244168 kb
Host smart-8a7002a3-65bc-4762-b9f4-a3e1db28aab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054948649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.1054948649
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3025022016
Short name T321
Test name
Test status
Simulation time 66848447150 ps
CPU time 313.51 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 01:12:02 PM PST 24
Peak memory 223524 kb
Host smart-0e4a6853-444d-447f-bdde-5c8c2729cf6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025022016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.3025022016
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.435158800
Short name T357
Test name
Test status
Simulation time 26971370853 ps
CPU time 598.5 seconds
Started Jan 03 01:05:38 PM PST 24
Finished Jan 03 01:16:55 PM PST 24
Peak memory 215224 kb
Host smart-7220fba4-534f-4600-882f-69306d7f8967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435158800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.435158800
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3328051157
Short name T337
Test name
Test status
Simulation time 18070449 ps
CPU time 0.54 seconds
Started Jan 03 01:04:50 PM PST 24
Finished Jan 03 01:06:13 PM PST 24
Peak memory 193216 kb
Host smart-1f9d8025-8405-4dc3-a2c3-56bcd7d63bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328051157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3328051157
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2564154856
Short name T601
Test name
Test status
Simulation time 1041259204 ps
CPU time 32.67 seconds
Started Jan 03 01:05:07 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 214752 kb
Host smart-50ec0190-6c11-4239-b5f0-5b211b0e6187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564154856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2564154856
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3741071290
Short name T265
Test name
Test status
Simulation time 1987010164 ps
CPU time 45.61 seconds
Started Jan 03 01:05:20 PM PST 24
Finished Jan 03 01:07:22 PM PST 24
Peak memory 198640 kb
Host smart-553800a5-0487-4aac-97f4-bf96f744557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741071290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3741071290
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3989195437
Short name T804
Test name
Test status
Simulation time 9722701730 ps
CPU time 134.72 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:08:49 PM PST 24
Peak memory 198836 kb
Host smart-a4ddf74a-8988-4bf1-b21c-7577f2dcf485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989195437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3989195437
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3270846293
Short name T732
Test name
Test status
Simulation time 4521181352 ps
CPU time 111.22 seconds
Started Jan 03 01:05:04 PM PST 24
Finished Jan 03 01:08:14 PM PST 24
Peak memory 198744 kb
Host smart-9b295a16-1793-466a-bfe0-f8e4a3253850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270846293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3270846293
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.302002258
Short name T721
Test name
Test status
Simulation time 5846694316 ps
CPU time 103.26 seconds
Started Jan 03 01:05:45 PM PST 24
Finished Jan 03 01:08:48 PM PST 24
Peak memory 198864 kb
Host smart-1af8f03a-020e-41bb-ad57-0640d076b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302002258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.302002258
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1097849349
Short name T276
Test name
Test status
Simulation time 449271901 ps
CPU time 1.46 seconds
Started Jan 03 01:05:10 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 198068 kb
Host smart-7c56a082-8fc5-4cc9-9497-f9b0cd08d7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097849349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1097849349
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3336298652
Short name T679
Test name
Test status
Simulation time 201364914949 ps
CPU time 112.32 seconds
Started Jan 03 01:04:57 PM PST 24
Finished Jan 03 01:08:09 PM PST 24
Peak memory 198824 kb
Host smart-a5a6f4c0-cfa2-4316-9637-31e578e0d926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336298652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3336298652
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1483634947
Short name T125
Test name
Test status
Simulation time 47639827166 ps
CPU time 790.62 seconds
Started Jan 03 01:05:05 PM PST 24
Finished Jan 03 01:19:39 PM PST 24
Peak memory 208184 kb
Host smart-b5ff7441-8c2c-4c00-8e09-7c0df1e5fe48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483634947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1483634947
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.391069929
Short name T545
Test name
Test status
Simulation time 108408767 ps
CPU time 1.11 seconds
Started Jan 03 01:05:00 PM PST 24
Finished Jan 03 01:06:21 PM PST 24
Peak memory 197280 kb
Host smart-44223be8-b04f-4490-9f20-bd8de7497307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391069929 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.391069929
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2426901100
Short name T607
Test name
Test status
Simulation time 94912620900 ps
CPU time 380.84 seconds
Started Jan 03 01:05:14 PM PST 24
Finished Jan 03 01:13:06 PM PST 24
Peak memory 198776 kb
Host smart-698dfd94-7d0f-49aa-8b92-16c481117e22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426901100 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.2426901100
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3187902250
Short name T553
Test name
Test status
Simulation time 2512248696 ps
CPU time 54.79 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:07:06 PM PST 24
Peak memory 198792 kb
Host smart-c25c2e02-603a-4be4-8370-d28484164ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187902250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3187902250
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.4067281434
Short name T560
Test name
Test status
Simulation time 96648735018 ps
CPU time 1012.18 seconds
Started Jan 03 01:05:34 PM PST 24
Finished Jan 03 01:23:44 PM PST 24
Peak memory 245852 kb
Host smart-3a822faf-8178-4fe1-8a98-7d7c810c0ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067281434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.4067281434
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3472572422
Short name T649
Test name
Test status
Simulation time 107919379282 ps
CPU time 1840.92 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:37:56 PM PST 24
Peak memory 247608 kb
Host smart-4e4093e2-a57d-4e07-a1cc-6e30e8de181f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472572422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.3472572422
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.3933382063
Short name T36
Test name
Test status
Simulation time 87643096618 ps
CPU time 3157.73 seconds
Started Jan 03 01:05:28 PM PST 24
Finished Jan 03 01:59:32 PM PST 24
Peak memory 249144 kb
Host smart-6cd98bef-d508-4bcd-9381-9dd736fd4451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933382063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.3933382063
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1544192
Short name T615
Test name
Test status
Simulation time 46706437534 ps
CPU time 704.41 seconds
Started Jan 03 01:05:53 PM PST 24
Finished Jan 03 01:18:59 PM PST 24
Peak memory 225728 kb
Host smart-f402c123-af38-468d-b162-39d60b405fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.1544192
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.4290717714
Short name T654
Test name
Test status
Simulation time 113429990870 ps
CPU time 399.86 seconds
Started Jan 03 01:05:23 PM PST 24
Finished Jan 03 01:13:19 PM PST 24
Peak memory 245300 kb
Host smart-c7f35452-d0f0-4a56-800e-dd387eeb1ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290717714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.4290717714
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3789262627
Short name T240
Test name
Test status
Simulation time 11342906362 ps
CPU time 547.16 seconds
Started Jan 03 01:05:19 PM PST 24
Finished Jan 03 01:15:44 PM PST 24
Peak memory 207152 kb
Host smart-cf1e36b5-98fa-4845-9687-6e2ed85de238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789262627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3789262627
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3615512772
Short name T664
Test name
Test status
Simulation time 162666507959 ps
CPU time 1372.94 seconds
Started Jan 03 01:05:44 PM PST 24
Finished Jan 03 01:29:58 PM PST 24
Peak memory 248108 kb
Host smart-08a533d0-2d5c-465a-a3c8-b19cba16420d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615512772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.3615512772
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1054624145
Short name T515
Test name
Test status
Simulation time 109517547937 ps
CPU time 994.41 seconds
Started Jan 03 01:05:51 PM PST 24
Finished Jan 03 01:23:47 PM PST 24
Peak memory 245736 kb
Host smart-237cc0ab-9af2-493b-8342-e31d61d2cea9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054624145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1054624145
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.4175215960
Short name T379
Test name
Test status
Simulation time 118130545274 ps
CPU time 5571.45 seconds
Started Jan 03 01:05:31 PM PST 24
Finished Jan 03 02:39:48 PM PST 24
Peak memory 258636 kb
Host smart-dc9884ae-d476-4623-81b0-14958880f01b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175215960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.4175215960
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.678417836
Short name T352
Test name
Test status
Simulation time 66053407747 ps
CPU time 989.52 seconds
Started Jan 03 01:05:48 PM PST 24
Finished Jan 03 01:23:37 PM PST 24
Peak memory 233608 kb
Host smart-dad34c9a-92ad-493b-ab7a-7868901a592e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678417836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.678417836
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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