Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	113907249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127571270

1

T12

749

T13

19

T14

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95062851	1			T12	542		T13	29		T14	61
values[0x0]	67896634	1			T12	241		T13	11		T14	29
values[0x1]	78519034	1			T12	239		T13	18		T14	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	83275535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158202984

1

T12

844

T13

23

T14

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	876403	1			T17	23		T22	1		T34	3
valid_sources[0x01]	902563	1			T12	2		T16	4		T17	6
valid_sources[0x02]	878490	1			T12	9		T14	12		T19	12
valid_sources[0x03]	870895	1			T12	2		T13	1		T17	7
valid_sources[0x04]	973861	1			T34	2		T35	1		T24	5
valid_sources[0x05]	890832	1			T17	2		T22	2		T35	2
valid_sources[0x06]	911891	1			T12	15		T17	1		T18	6
valid_sources[0x07]	912556	1			T12	6		T15	14		T16	1
valid_sources[0x08]	870625	1			T12	3		T17	8		T22	1
valid_sources[0x09]	908532	1			T12	2		T20	3		T22	2
valid_sources[0x0a]	880087	1			T12	1		T17	28		T22	1
valid_sources[0x0b]	878976	1			T12	10		T13	1		T14	39
valid_sources[0x0c]	878833	1			T17	7		T22	2		T34	3
valid_sources[0x0d]	1353923	1			T17	1		T34	18		T67	3
valid_sources[0x0e]	850428	1			T12	1		T17	1		T22	1
valid_sources[0x0f]	854887	1			T12	4		T14	17		T15	12
valid_sources[0x10]	1296789	1			T12	9		T13	1		T17	35
valid_sources[0x11]	883707	1			T12	5		T19	7		T20	1
valid_sources[0x12]	872614	1			T12	4		T13	2		T17	13
valid_sources[0x13]	891893	1			T17	1		T22	1		T34	10
valid_sources[0x14]	883695	1			T17	12		T22	1		T34	10
valid_sources[0x15]	916529	1			T12	1		T19	26		T22	1
valid_sources[0x16]	901187	1			T12	14		T17	3		T22	1
valid_sources[0x17]	866311	1			T12	4		T17	7		T34	4
valid_sources[0x18]	903809	1			T12	6		T16	9		T17	15
valid_sources[0x19]	856045	1			T12	10		T17	13		T20	1
valid_sources[0x1a]	936611	1			T12	5		T17	16		T32	2
valid_sources[0x1b]	1253143	1			T13	1		T17	1		T22	1
valid_sources[0x1c]	903977	1			T12	5		T15	24		T17	3
valid_sources[0x1d]	940712	1			T16	3		T17	3		T19	49
valid_sources[0x1e]	909717	1			T12	4		T15	16		T17	4
valid_sources[0x1f]	846959	1			T12	7		T17	2		T32	1
valid_sources[0x20]	870685	1			T12	5		T17	3		T22	2
valid_sources[0x21]	873566	1			T12	19		T17	5		T22	2
valid_sources[0x22]	881536	1			T17	19		T34	6		T35	2
valid_sources[0x23]	1616096	1			T12	1		T15	24		T17	2
valid_sources[0x24]	874111	1			T12	3		T13	1		T17	8
valid_sources[0x25]	891421	1			T34	15		T67	3		T70	20
valid_sources[0x26]	1240287	1			T12	4		T13	1		T17	6
valid_sources[0x27]	909877	1			T13	2		T16	1		T19	1
valid_sources[0x28]	884284	1			T12	4		T15	16		T17	3
valid_sources[0x29]	895677	1			T15	15		T22	5		T34	7
valid_sources[0x2a]	883079	1			T12	2		T13	1		T22	3
valid_sources[0x2b]	901258	1			T12	4		T16	2		T17	3
valid_sources[0x2c]	886189	1			T12	1		T13	1		T17	16
valid_sources[0x2d]	1597712	1			T12	1		T17	2		T19	16
valid_sources[0x2e]	878346	1			T12	8		T17	3		T22	2
valid_sources[0x2f]	866027	1			T17	33		T22	2		T34	3
valid_sources[0x30]	1237598	1			T17	8		T22	1		T34	10
valid_sources[0x31]	1627379	1			T12	4		T13	1		T17	25
valid_sources[0x32]	896599	1			T15	1		T17	2		T19	4
valid_sources[0x33]	850878	1			T17	13		T32	1		T22	1
valid_sources[0x34]	872627	1			T12	2		T13	1		T17	12
valid_sources[0x35]	1294981	1			T17	6		T34	1		T35	1
valid_sources[0x36]	1028706	1			T12	6		T13	1		T19	16
valid_sources[0x37]	901999	1			T17	14		T32	1		T34	6
valid_sources[0x38]	920158	1			T12	1		T13	1		T17	13
valid_sources[0x39]	894250	1			T12	10		T17	7		T32	1
valid_sources[0x3a]	869727	1			T12	1		T17	1		T32	3
valid_sources[0x3b]	888512	1			T12	2		T13	1		T34	1
valid_sources[0x3c]	919581	1			T12	5		T17	2		T19	13
valid_sources[0x3d]	868809	1			T12	5		T17	2		T22	3
valid_sources[0x3e]	1213168	1			T17	4		T19	5		T22	2
valid_sources[0x3f]	869835	1			T12	8		T21	16		T22	4
valid_sources[0x40]	863938	1			T12	9		T15	5		T17	1
valid_sources[0x41]	916614	1			T12	1		T17	13		T22	2
valid_sources[0x42]	876518	1			T15	8		T17	11		T22	1
valid_sources[0x43]	1316428	1			T12	5		T17	2		T22	1
valid_sources[0x44]	910840	1			T12	3		T13	1		T17	1
valid_sources[0x45]	918719	1			T17	5		T19	19		T22	1
valid_sources[0x46]	911853	1			T17	73		T22	2		T34	2
valid_sources[0x47]	1135414	1			T12	2		T13	1		T17	3
valid_sources[0x48]	935281	1			T17	3		T22	1		T34	3
valid_sources[0x49]	860511	1			T12	10		T17	1		T19	34
valid_sources[0x4a]	1321150	1			T12	2		T17	9		T32	1
valid_sources[0x4b]	872992	1			T12	2		T17	4		T20	1
valid_sources[0x4c]	1796329	1			T12	3		T32	1		T22	2
valid_sources[0x4d]	873367	1			T17	5		T22	1		T34	3
valid_sources[0x4e]	844503	1			T32	1		T22	2		T35	1
valid_sources[0x4f]	1237463	1			T12	11		T15	9		T17	10
valid_sources[0x50]	925375	1			T12	1		T22	1		T34	4
valid_sources[0x51]	854294	1			T12	15		T17	6		T34	4
valid_sources[0x52]	874664	1			T12	2		T15	30		T17	6
valid_sources[0x53]	897418	1			T14	27		T15	1		T17	6
valid_sources[0x54]	886008	1			T12	1		T13	2		T20	2
valid_sources[0x55]	935286	1			T12	2		T13	1		T17	2
valid_sources[0x56]	878890	1			T12	4		T13	1		T17	2
valid_sources[0x57]	861745	1			T12	3		T17	4		T34	4
valid_sources[0x58]	876524	1			T12	2		T13	1		T15	9
valid_sources[0x59]	902571	1			T12	2		T17	5		T23	58
valid_sources[0x5a]	863026	1			T17	3		T19	4		T34	7
valid_sources[0x5b]	896970	1			T12	4		T17	4		T19	15
valid_sources[0x5c]	907063	1			T12	4		T17	5		T32	1
valid_sources[0x5d]	903790	1			T12	12		T19	1		T34	9
valid_sources[0x5e]	888463	1			T12	14		T13	1		T17	8
valid_sources[0x5f]	916285	1			T12	1		T17	3		T32	1
valid_sources[0x60]	874752	1			T13	1		T17	2		T34	5
valid_sources[0x61]	871024	1			T13	1		T14	2		T17	13
valid_sources[0x62]	902671	1			T12	5		T17	18		T19	8
valid_sources[0x63]	886385	1			T12	1		T17	8		T32	1
valid_sources[0x64]	881586	1			T12	8		T15	27		T16	4
valid_sources[0x65]	866670	1			T12	3		T17	15		T20	1
valid_sources[0x66]	857001	1			T17	10		T19	39		T32	1
valid_sources[0x67]	883312	1			T13	2		T17	15		T22	2
valid_sources[0x68]	894317	1			T12	1		T34	10		T24	16
valid_sources[0x69]	921747	1			T17	2		T19	4		T22	3
valid_sources[0x6a]	927410	1			T18	3		T22	2		T34	20
valid_sources[0x6b]	893853	1			T12	3		T17	50		T34	12
valid_sources[0x6c]	889385	1			T12	1		T13	1		T17	5
valid_sources[0x6d]	892829	1			T12	6		T17	3		T22	2
valid_sources[0x6e]	845405	1			T12	11		T22	4		T34	16
valid_sources[0x6f]	871576	1			T17	1		T18	2		T37	3
valid_sources[0x70]	872812	1			T17	13		T22	1		T34	3
valid_sources[0x71]	881731	1			T12	7		T17	2		T20	1
valid_sources[0x72]	1026177	1			T12	6		T17	1		T20	2
valid_sources[0x73]	902009	1			T12	4		T13	1		T17	6
valid_sources[0x74]	858951	1			T13	1		T22	2		T34	4
valid_sources[0x75]	889755	1			T12	11		T17	12		T22	2
valid_sources[0x76]	897727	1			T12	3		T17	5		T67	1
valid_sources[0x77]	897827	1			T12	8		T35	3		T25	1
valid_sources[0x78]	860298	1			T17	5		T22	2		T34	8
valid_sources[0x79]	867717	1			T13	1		T15	9		T17	2
valid_sources[0x7a]	1305615	1			T17	5		T19	4		T20	2
valid_sources[0x7b]	888373	1			T13	1		T17	9		T19	29
valid_sources[0x7c]	881848	1			T17	7		T19	8		T22	1
valid_sources[0x7d]	915562	1			T17	10		T35	1		T135	1
valid_sources[0x7e]	947132	1			T12	1		T17	3		T34	7
valid_sources[0x7f]	866634	1			T17	18		T19	29		T22	1
valid_sources[0x80]	864188	1			T12	12		T13	1		T17	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46053857

1

T12

323

T13

14

T14

35

values[0x0]

all_enables

biggest_size

42469775

1

T12

221

T13

3

T14

26

values[0x1]

all_enables

biggest_size

39047638

1

T12

205

T13

2

T14

16