Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

169466680

1

T12

278

T13

39

T14

32

full_word

131768677

1

T12

749

T13

19

T14

77

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	301234987	1			T12	1007		T13	58		T14	109
auto[TlIntgErrCmd]	135	1			T12	4		T15	4		T19	9
auto[TlIntgErrData]	119	1			T12	7		T15	3		T19	8
auto[TlIntgErrBoth]	116	1			T12	9		T15	3		T19	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117019287

1

T12

543

T13

29

T14

61

auto[1]

184216070

1

T12

484

T13

29

T14

48

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	69295465	1			T12	214		T13	15		T14	26
auto[TlIntgErrNone]	partial	auto[1]	100170878	1			T12	46		T13	24		T14	6
auto[TlIntgErrNone]	full_word	auto[0]	47723671	1			T12	322		T13	14		T14	35
auto[TlIntgErrNone]	full_word	auto[1]	84044973	1			T12	425		T13	5		T14	42
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T19	5		T34	2		T67	6
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T12	3		T15	3		T19	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T12	1		T130	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T15	1		T34	1		T68	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T12	3		T19	4		T34	4
auto[TlIntgErrData]	partial	auto[1]	65	1			T12	4		T15	3		T19	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T131	1		T132	1		T66	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T67	1		T133	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T12	3		T15	3		T19	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T12	5		T19	1		T34	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T19	1		T68	1		T134	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T12	1		T73	1		T130	1