Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123146991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

137033202

1

T14

32

T15

763

T16

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	103090635	1			T14	21		T15	553		T16	20
values[0x0]	72930857	1			T14	9		T15	239		T16	14
values[0x1]	84158701	1			T14	13		T15	251		T16	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90029903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

170150290

1

T14

34

T15

848

T16

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1024538	1			T15	7		T23	1		T25	12
valid_sources[0x01]	1029263	1			T15	3		T73	1		T70	81
valid_sources[0x02]	1340386	1			T15	3		T23	2		T107	2
valid_sources[0x03]	1029739	1			T15	2		T18	1		T23	1
valid_sources[0x04]	965156	1			T15	3		T23	2		T30	1
valid_sources[0x05]	959040	1			T15	4		T23	1		T67	1
valid_sources[0x06]	975419	1			T15	4		T18	1		T100	2
valid_sources[0x07]	1018525	1			T22	1		T23	3		T30	1
valid_sources[0x08]	1014576	1			T15	6		T16	1		T24	1
valid_sources[0x09]	1406308	1			T15	3		T16	1		T25	11
valid_sources[0x0a]	966835	1			T15	3		T62	1		T27	16
valid_sources[0x0b]	967185	1			T15	10		T67	1		T30	1
valid_sources[0x0c]	992915	1			T15	3		T16	1		T23	2
valid_sources[0x0d]	993722	1			T15	2		T22	2		T23	2
valid_sources[0x0e]	944120	1			T14	4		T32	3		T24	1
valid_sources[0x0f]	956551	1			T15	6		T23	1		T25	16
valid_sources[0x10]	968205	1			T15	4		T26	4		T63	34
valid_sources[0x11]	1003033	1			T15	3		T19	20		T21	7
valid_sources[0x12]	1355614	1			T15	5		T23	3		T24	1
valid_sources[0x13]	964243	1			T15	2		T23	1		T34	12
valid_sources[0x14]	1460868	1			T19	15		T23	4		T25	19
valid_sources[0x15]	989039	1			T14	2		T15	10		T19	2
valid_sources[0x16]	1370180	1			T15	6		T23	5		T100	1
valid_sources[0x17]	962727	1			T15	7		T23	5		T63	3
valid_sources[0x18]	998656	1			T15	1		T24	3		T65	2
valid_sources[0x19]	983806	1			T14	1		T23	1		T26	2
valid_sources[0x1a]	1023504	1			T15	9		T25	6		T33	2
valid_sources[0x1b]	980001	1			T15	2		T23	1		T24	1
valid_sources[0x1c]	1166144	1			T18	1		T21	5		T25	11
valid_sources[0x1d]	970135	1			T15	5		T16	1		T22	1
valid_sources[0x1e]	988311	1			T15	2		T16	2		T18	1
valid_sources[0x1f]	986917	1			T15	7		T18	1		T24	1
valid_sources[0x20]	1016758	1			T17	40		T21	2		T22	2
valid_sources[0x21]	989927	1			T15	8		T23	1		T25	2
valid_sources[0x22]	1031661	1			T15	2		T18	1		T23	2
valid_sources[0x23]	995166	1			T15	18		T63	8		T29	9
valid_sources[0x24]	946105	1			T15	2		T18	2		T23	1
valid_sources[0x25]	1389178	1			T15	3		T25	1		T24	2
valid_sources[0x26]	968361	1			T15	14		T18	1		T26	2
valid_sources[0x27]	976482	1			T15	9		T63	21		T73	10
valid_sources[0x28]	1331756	1			T15	2		T23	5		T25	15
valid_sources[0x29]	956476	1			T14	4		T15	1		T21	10
valid_sources[0x2a]	1022310	1			T15	5		T20	45		T23	2
valid_sources[0x2b]	972980	1			T63	2		T73	1		T146	1
valid_sources[0x2c]	1029243	1			T15	5		T19	1		T23	3
valid_sources[0x2d]	972812	1			T28	8		T30	1		T64	15
valid_sources[0x2e]	978951	1			T15	10		T23	1		T62	1
valid_sources[0x2f]	963564	1			T15	3		T18	1		T21	2
valid_sources[0x30]	1001568	1			T15	4		T23	1		T67	1
valid_sources[0x31]	997037	1			T15	10		T23	1		T64	3
valid_sources[0x32]	971237	1			T15	17		T30	1		T101	6
valid_sources[0x33]	993490	1			T20	66		T25	4		T62	1
valid_sources[0x34]	1003448	1			T15	5		T25	7		T24	2
valid_sources[0x35]	956386	1			T15	1		T24	2		T63	1
valid_sources[0x36]	946656	1			T15	6		T23	3		T63	23
valid_sources[0x37]	966834	1			T15	1		T23	1		T25	13
valid_sources[0x38]	969863	1			T15	4		T23	7		T100	1
valid_sources[0x39]	975475	1			T15	2		T100	2		T65	1
valid_sources[0x3a]	1004448	1			T14	1		T15	5		T19	59
valid_sources[0x3b]	981465	1			T15	11		T23	1		T25	21
valid_sources[0x3c]	975482	1			T15	7		T23	1		T28	11
valid_sources[0x3d]	984378	1			T15	3		T19	24		T23	4
valid_sources[0x3e]	976790	1			T15	11		T61	2		T28	5
valid_sources[0x3f]	995775	1			T23	1		T28	2		T30	1
valid_sources[0x40]	970322	1			T19	44		T20	84		T23	6
valid_sources[0x41]	955540	1			T15	9		T16	1		T18	1
valid_sources[0x42]	1016646	1			T15	2		T23	5		T25	78
valid_sources[0x43]	982315	1			T15	6		T16	1		T28	2
valid_sources[0x44]	1334454	1			T15	1		T23	1		T29	6
valid_sources[0x45]	1014442	1			T23	3		T67	1		T64	3
valid_sources[0x46]	1066987	1			T15	4		T18	1		T23	1
valid_sources[0x47]	969046	1			T22	1		T23	2		T63	13
valid_sources[0x48]	984324	1			T15	3		T18	1		T23	1
valid_sources[0x49]	1011184	1			T15	3		T25	37		T63	16
valid_sources[0x4a]	990923	1			T73	2		T100	1		T65	1
valid_sources[0x4b]	995580	1			T15	3		T23	4		T26	1
valid_sources[0x4c]	991968	1			T15	8		T23	2		T107	1
valid_sources[0x4d]	983243	1			T14	3		T15	4		T19	5
valid_sources[0x4e]	964099	1			T15	1		T25	1		T32	17
valid_sources[0x4f]	964833	1			T15	4		T63	14		T28	11
valid_sources[0x50]	1004679	1			T15	6		T23	1		T27	41
valid_sources[0x51]	952636	1			T15	5		T16	1		T18	1
valid_sources[0x52]	969535	1			T14	3		T15	2		T23	2
valid_sources[0x53]	973961	1			T15	4		T23	1		T63	8
valid_sources[0x54]	954017	1			T25	26		T61	1		T28	3
valid_sources[0x55]	1389674	1			T23	2		T33	3		T26	33
valid_sources[0x56]	1013315	1			T22	3		T23	2		T63	26
valid_sources[0x57]	976979	1			T15	3		T18	1		T32	10
valid_sources[0x58]	980244	1			T18	1		T23	1		T26	1
valid_sources[0x59]	1003398	1			T15	4		T63	16		T73	2
valid_sources[0x5a]	1100437	1			T15	3		T19	14		T23	1
valid_sources[0x5b]	974230	1			T15	5		T18	1		T26	3
valid_sources[0x5c]	980032	1			T15	3		T22	1		T25	1
valid_sources[0x5d]	1008316	1			T15	2		T22	1		T25	146
valid_sources[0x5e]	978860	1			T15	19		T18	1		T21	1
valid_sources[0x5f]	967087	1			T15	13		T23	2		T25	22
valid_sources[0x60]	1010188	1			T63	3		T27	12		T65	1
valid_sources[0x61]	976802	1			T15	1		T18	1		T67	2
valid_sources[0x62]	996664	1			T15	2		T23	6		T26	9
valid_sources[0x63]	1411384	1			T14	6		T27	2		T28	2
valid_sources[0x64]	964193	1			T15	2		T19	10		T23	1
valid_sources[0x65]	957148	1			T15	14		T23	4		T25	69
valid_sources[0x66]	1158870	1			T15	1		T28	1		T30	1
valid_sources[0x67]	973743	1			T15	5		T23	2		T25	12
valid_sources[0x68]	984719	1			T15	4		T23	2		T25	3
valid_sources[0x69]	1403514	1			T15	1		T18	1		T23	1
valid_sources[0x6a]	980179	1			T19	16		T23	2		T26	12
valid_sources[0x6b]	1029855	1			T15	6		T23	2		T63	23
valid_sources[0x6c]	994974	1			T15	4		T19	1		T23	2
valid_sources[0x6d]	970708	1			T15	7		T23	1		T61	3
valid_sources[0x6e]	1060892	1			T15	5		T18	1		T23	2
valid_sources[0x6f]	1342066	1			T15	2		T22	1		T25	24
valid_sources[0x70]	1023283	1			T15	9		T23	4		T26	31
valid_sources[0x71]	987391	1			T23	2		T28	6		T100	3
valid_sources[0x72]	975550	1			T15	2		T23	4		T25	82
valid_sources[0x73]	971518	1			T15	4		T107	1		T73	1
valid_sources[0x74]	978695	1			T15	2		T16	2		T63	1
valid_sources[0x75]	987523	1			T15	3		T34	22		T63	8
valid_sources[0x76]	961299	1			T15	6		T16	1		T18	1
valid_sources[0x77]	991720	1			T15	3		T19	11		T23	1
valid_sources[0x78]	983664	1			T15	9		T34	2		T63	13
valid_sources[0x79]	979651	1			T15	1		T19	15		T23	1
valid_sources[0x7a]	986681	1			T15	1		T23	3		T25	11
valid_sources[0x7b]	978017	1			T28	21		T107	1		T100	2
valid_sources[0x7c]	1040192	1			T63	4		T147	3		T65	1
valid_sources[0x7d]	958200	1			T15	12		T19	2		T22	1
valid_sources[0x7e]	1361298	1			T15	2		T16	3		T24	1
valid_sources[0x7f]	988761	1			T70	9		T100	1		T102	2
valid_sources[0x80]	1002817	1			T15	5		T23	1		T62	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49557791

1

T14

14

T15

321

T16

9

values[0x0]

all_enables

biggest_size

45579713

1

T14

7

T15

217

T16

6

values[0x1]

all_enables

biggest_size

41895698

1

T14

11

T15

225

T17

3