Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

180027509

1

T14

11

T15

283

T16

25

full_word

141330227

1

T14

32

T15

763

T16

15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	321357436	1			T14	43		T15	1026		T16	40
auto[TlIntgErrCmd]	90	1			T15	5		T25	9		T63	8
auto[TlIntgErrData]	108	1			T15	8		T25	10		T63	5
auto[TlIntgErrBoth]	102	1			T15	7		T25	11		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125582402

1

T14

21

T15

553

T16

20

auto[1]

195775334

1

T14

22

T15

493

T16

20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	74312577	1			T14	7		T15	227		T16	11
auto[TlIntgErrNone]	partial	auto[1]	105714656	1			T14	4		T15	38		T16	14
auto[TlIntgErrNone]	full_word	auto[0]	51269696	1			T14	14		T15	321		T16	9
auto[TlIntgErrNone]	full_word	auto[1]	90060507	1			T14	18		T15	440		T16	6
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T15	1		T25	5		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T15	3		T25	4		T63	6
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T15	1		T70	1		T72	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T15	3		T25	7		T63	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T15	5		T25	2		T63	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T25	1		T72	1		T103	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T70	1		T71	1		T104	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T15	1		T25	5		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T15	5		T25	5		T63	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T25	1		T72	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T15	1		T104	1		T106	2