Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1422044895	37171766	0	0
intr_enable_rd_A	1422044895	11110	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422044895	37171766	0	0
T15	8927	4	0	0
T16	1127	0	0	0
T17	1197	0	0	0
T18	1224	0	0	0
T19	1763	5	0	0
T20	3170	0	0	0
T21	1033	0	0	0
T22	1042	0	0	0
T23	3863	0	0	0
T24	0	231	0	0
T25	11826	5	0	0
T26	0	9	0	0
T27	0	41	0	0
T28	0	428	0	0
T29	0	1	0	0
T30	0	1	0	0
T63	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422044895	11110	0	0
T14	1384	8	0	0
T15	8927	0	0	0
T16	1127	0	0	0
T17	1197	0	0	0
T18	1224	10	0	0
T19	1763	0	0	0
T20	3170	0	0	0
T21	1033	0	0	0
T22	1042	0	0	0
T23	3863	51	0	0
T29	0	7	0	0
T31	0	4	0	0
T34	0	5	0	0
T61	0	8	0	0
T63	0	105	0	0
T67	0	22	0	0
T68	0	239	0	0