Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	37854416	1			T13	1		T15	8		T16	5
all_values[1]	37854416	1			T13	1		T15	8		T16	5
all_values[2]	37854416	1			T13	1		T15	8		T16	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112403

1

T13

3

T15

18

T16

7

auto[1]

113450845

1

T15

6

T16

8

T18

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82142477

1

T13

3

T15

9

T16

6

auto[1]

31420771

1

T15

15

T16

9

T18

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38391	1			T13	1		T15	3		T16	2
all_values[0]	auto[0]	auto[1]	1201	1			T15	2		T16	3		T18	3
all_values[0]	auto[1]	auto[0]	37652766	1			T15	1		T18	1		T20	3
all_values[0]	auto[1]	auto[1]	162058	1			T15	2		T18	3		T85	3
all_values[1]	auto[0]	auto[0]	22953	1			T13	1		T15	1		T16	1
all_values[1]	auto[0]	auto[1]	15126	1			T15	5		T18	3		T20	1
all_values[1]	auto[1]	auto[0]	20929123	1			T16	1		T18	3		T20	5
all_values[1]	auto[1]	auto[1]	16887214	1			T15	2		T16	3		T18	2
all_values[2]	auto[0]	auto[0]	26595	1			T13	1		T15	4		T18	2
all_values[2]	auto[0]	auto[1]	8137	1			T15	3		T16	1		T20	1
all_values[2]	auto[1]	auto[0]	23472649	1			T16	2		T18	4		T20	1
all_values[2]	auto[1]	auto[1]	14347035	1			T15	1		T16	2		T18	5