Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.53 98.47 100.00 100.00 99.76 99.49 99.72


Total tests in report: 907
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
49.96 49.96 40.00 40.00 38.47 38.47 57.04 57.04 100.00 100.00 26.59 26.59 81.82 81.82 5.78 5.78 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2745849500
84.23 34.28 97.82 57.82 84.15 45.68 61.56 4.52 100.00 0.00 95.06 68.47 95.45 13.64 55.57 49.79 /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3368114160
93.33 9.10 98.75 0.93 93.99 9.84 89.20 27.64 100.00 0.00 96.71 1.65 97.47 2.02 77.17 21.60 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3169824203
95.67 2.34 98.99 0.23 96.83 2.84 95.48 6.28 100.00 0.00 98.12 1.41 97.47 0.00 82.81 5.64 /workspace/coverage/cover_reg_top/33.hmac_intr_test.22581764
97.09 1.42 99.30 0.31 97.38 0.55 95.48 0.00 100.00 0.00 98.59 0.47 98.23 0.76 90.65 7.84 /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1027774231
98.31 1.22 99.46 0.16 97.81 0.44 99.50 4.02 100.00 0.00 99.06 0.47 98.23 0.00 94.09 3.44 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1397119048
98.48 0.18 99.46 0.00 98.03 0.22 100.00 0.50 100.00 0.00 99.06 0.00 98.48 0.25 94.36 0.28 /workspace/coverage/default/4.hmac_sec_cm.463889215
98.66 0.18 99.46 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.06 0.00 98.48 0.00 95.60 1.24 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1870395010
98.84 0.18 99.46 0.00 98.03 0.00 100.00 0.00 100.00 0.00 99.06 0.00 98.48 0.00 96.84 1.24 /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.776455554
98.95 0.11 99.53 0.08 98.14 0.11 100.00 0.00 100.00 0.00 99.53 0.47 98.48 0.00 96.97 0.14 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2172535122
99.05 0.10 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 97.66 0.69 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1525571653
99.15 0.10 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 98.35 0.69 /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.2942421183
99.21 0.06 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 98.76 0.41 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1085180689
99.26 0.05 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.76 0.24 98.48 0.00 98.90 0.14 /workspace/coverage/default/0.hmac_stress_all.1731052490
99.30 0.04 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.28 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.357659887
99.34 0.04 99.53 0.00 98.14 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.28 /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.3395514810
99.37 0.03 99.53 0.00 98.36 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.00 /workspace/coverage/default/0.hmac_alert_test.989775349
99.39 0.02 99.53 0.00 98.36 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.2999200586
99.41 0.02 99.53 0.00 98.36 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.1167790272
99.43 0.02 99.53 0.00 98.47 0.11 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.00 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3306905288

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3997892769
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1572146986
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3469893581
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1552185599
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.2312784416
/workspace/coverage/cover_reg_top/0.hmac_intr_test.2641339767
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.763989598
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3558659650
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3469687068
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1848870655
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.837996167
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1099467152
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.1605753473
/workspace/coverage/cover_reg_top/1.hmac_intr_test.609225953
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2444096234
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.188200107
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.249344644
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.411183067
/workspace/coverage/cover_reg_top/10.hmac_intr_test.3263738222
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1095332891
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.2559320224
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1962005069
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.962546436
/workspace/coverage/cover_reg_top/11.hmac_intr_test.136918055
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3413737716
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.2250297272
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3588590458
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.615497967
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.1934708095
/workspace/coverage/cover_reg_top/12.hmac_intr_test.3048411529
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3820458258
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.2095112740
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1794242227
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.2899464064
/workspace/coverage/cover_reg_top/13.hmac_intr_test.1732701109
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1365037749
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.2772796811
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2145280503
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1870645317
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.3963661234
/workspace/coverage/cover_reg_top/14.hmac_intr_test.2565379755
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2393763527
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.3932743267
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3570560837
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1588829182
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.528227275
/workspace/coverage/cover_reg_top/15.hmac_intr_test.425281626
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3560961573
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.2629491276
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4160714206
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.3544276308
/workspace/coverage/cover_reg_top/16.hmac_intr_test.3544202221
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2743469738
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.2701885265
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3300384726
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3616026881
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.3300443936
/workspace/coverage/cover_reg_top/17.hmac_intr_test.362306220
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3935166627
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.1740018807
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3281643836
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2497235794
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.2966947860
/workspace/coverage/cover_reg_top/18.hmac_intr_test.2631160370
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.130226079
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.2116368578
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.606924100
/workspace/coverage/cover_reg_top/19.hmac_intr_test.300609969
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3138141861
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.3636366417
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1439460431
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3275191957
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.75878804
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4255114702
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2517725771
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.3409256713
/workspace/coverage/cover_reg_top/2.hmac_intr_test.3715591854
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.851091531
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.398285893
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.321195763
/workspace/coverage/cover_reg_top/20.hmac_intr_test.982173391
/workspace/coverage/cover_reg_top/21.hmac_intr_test.905204906
/workspace/coverage/cover_reg_top/22.hmac_intr_test.1913033555
/workspace/coverage/cover_reg_top/23.hmac_intr_test.1610644060
/workspace/coverage/cover_reg_top/24.hmac_intr_test.2107859116
/workspace/coverage/cover_reg_top/25.hmac_intr_test.4166935082
/workspace/coverage/cover_reg_top/26.hmac_intr_test.3750571169
/workspace/coverage/cover_reg_top/27.hmac_intr_test.3959751836
/workspace/coverage/cover_reg_top/28.hmac_intr_test.3808459064
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2705814375
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1216830760
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2306069939
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2788275009
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2467345754
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.2069354305
/workspace/coverage/cover_reg_top/3.hmac_intr_test.3664537928
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.766083129
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.2687779053
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1417903605
/workspace/coverage/cover_reg_top/30.hmac_intr_test.1516729712
/workspace/coverage/cover_reg_top/31.hmac_intr_test.3584420820
/workspace/coverage/cover_reg_top/32.hmac_intr_test.3027753880
/workspace/coverage/cover_reg_top/34.hmac_intr_test.577879652
/workspace/coverage/cover_reg_top/35.hmac_intr_test.255177378
/workspace/coverage/cover_reg_top/36.hmac_intr_test.2022228610
/workspace/coverage/cover_reg_top/37.hmac_intr_test.1862709709
/workspace/coverage/cover_reg_top/38.hmac_intr_test.3522649498
/workspace/coverage/cover_reg_top/39.hmac_intr_test.3718566698
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1798200749
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.687755825
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1062147454
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1337148144
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.3804296740
/workspace/coverage/cover_reg_top/4.hmac_intr_test.516538154
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.110026510
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.4097375565
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.415061151
/workspace/coverage/cover_reg_top/40.hmac_intr_test.1849178771
/workspace/coverage/cover_reg_top/42.hmac_intr_test.1031895242
/workspace/coverage/cover_reg_top/43.hmac_intr_test.1812088999
/workspace/coverage/cover_reg_top/44.hmac_intr_test.2639507272
/workspace/coverage/cover_reg_top/45.hmac_intr_test.632546570
/workspace/coverage/cover_reg_top/46.hmac_intr_test.531655340
/workspace/coverage/cover_reg_top/47.hmac_intr_test.2283748265
/workspace/coverage/cover_reg_top/48.hmac_intr_test.314613076
/workspace/coverage/cover_reg_top/49.hmac_intr_test.2011586676
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3955812865
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.3301688045
/workspace/coverage/cover_reg_top/5.hmac_intr_test.1356519958
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.769898167
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.2068580821
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1137171591
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3525345846
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.2796119799
/workspace/coverage/cover_reg_top/6.hmac_intr_test.2271343651
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.394164826
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.1515670939
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3502518577
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.201510295
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2795519242
/workspace/coverage/cover_reg_top/7.hmac_intr_test.397606987
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3946088141
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.714457499
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.102308264
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.414461340
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.250305501
/workspace/coverage/cover_reg_top/8.hmac_intr_test.758933962
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2763469260
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.1536971075
/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.176681358
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2057595811
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.4071679827
/workspace/coverage/cover_reg_top/9.hmac_intr_test.3213160546
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2640089948
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.68102630
/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.271117281
/workspace/coverage/default/0.hmac_back_pressure.838914015
/workspace/coverage/default/0.hmac_burst_wr.3949912752
/workspace/coverage/default/0.hmac_datapath_stress.1300648609
/workspace/coverage/default/0.hmac_error.1172695943
/workspace/coverage/default/0.hmac_long_msg.202232007
/workspace/coverage/default/0.hmac_sec_cm.403049502
/workspace/coverage/default/0.hmac_smoke.3310728272
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1379518165
/workspace/coverage/default/0.hmac_test_hmac_vectors.1051872856
/workspace/coverage/default/0.hmac_test_sha_vectors.1839506319
/workspace/coverage/default/0.hmac_wipe_secret.1347954264
/workspace/coverage/default/1.hmac_alert_test.3772189394
/workspace/coverage/default/1.hmac_back_pressure.505992778
/workspace/coverage/default/1.hmac_burst_wr.2554692774
/workspace/coverage/default/1.hmac_datapath_stress.3928573494
/workspace/coverage/default/1.hmac_error.433470028
/workspace/coverage/default/1.hmac_long_msg.3787574951
/workspace/coverage/default/1.hmac_sec_cm.2883844203
/workspace/coverage/default/1.hmac_smoke.529093162
/workspace/coverage/default/1.hmac_stress_all.3921195519
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.259782897
/workspace/coverage/default/1.hmac_test_hmac_vectors.3781218767
/workspace/coverage/default/1.hmac_test_sha_vectors.1359267878
/workspace/coverage/default/1.hmac_wipe_secret.3476389518
/workspace/coverage/default/10.hmac_alert_test.2066073679
/workspace/coverage/default/10.hmac_back_pressure.539264520
/workspace/coverage/default/10.hmac_burst_wr.1021520969
/workspace/coverage/default/10.hmac_datapath_stress.1675839037
/workspace/coverage/default/10.hmac_error.1970126052
/workspace/coverage/default/10.hmac_long_msg.790502860
/workspace/coverage/default/10.hmac_smoke.671080785
/workspace/coverage/default/10.hmac_stress_all.1986501322
/workspace/coverage/default/10.hmac_test_hmac_vectors.249921029
/workspace/coverage/default/10.hmac_test_sha_vectors.792035983
/workspace/coverage/default/10.hmac_wipe_secret.2239423673
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2864039257
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.3132984153
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.700708538
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.333867148
/workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1181303186
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2632153690
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.2331839365
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1730425913
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2712982443
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3439633469
/workspace/coverage/default/11.hmac_alert_test.2874626644
/workspace/coverage/default/11.hmac_back_pressure.740261757
/workspace/coverage/default/11.hmac_burst_wr.3577685073
/workspace/coverage/default/11.hmac_datapath_stress.839680990
/workspace/coverage/default/11.hmac_error.2583113925
/workspace/coverage/default/11.hmac_long_msg.1311317103
/workspace/coverage/default/11.hmac_smoke.3930507803
/workspace/coverage/default/11.hmac_stress_all.931243735
/workspace/coverage/default/11.hmac_stress_all_with_rand_reset.3938807343
/workspace/coverage/default/11.hmac_test_hmac_vectors.220336350
/workspace/coverage/default/11.hmac_test_sha_vectors.670869997
/workspace/coverage/default/11.hmac_wipe_secret.1140140419
/workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2161370482
/workspace/coverage/default/111.hmac_stress_all_with_rand_reset.3247351173
/workspace/coverage/default/112.hmac_stress_all_with_rand_reset.3467816699
/workspace/coverage/default/113.hmac_stress_all_with_rand_reset.2908622603
/workspace/coverage/default/114.hmac_stress_all_with_rand_reset.338414164
/workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2329935405
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/workspace/coverage/default/8.hmac_long_msg.333110014
/workspace/coverage/default/8.hmac_smoke.666975586
/workspace/coverage/default/8.hmac_stress_all.1478380863
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3658958780
/workspace/coverage/default/8.hmac_test_hmac_vectors.646938349
/workspace/coverage/default/8.hmac_test_sha_vectors.163799953
/workspace/coverage/default/8.hmac_wipe_secret.3472068460
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.3195861622
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1515013056
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.354389588
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.1547959157
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1971215065
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.682991627
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.1430510113
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2829732467
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3546270032
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.2377326484
/workspace/coverage/default/9.hmac_alert_test.2577974995
/workspace/coverage/default/9.hmac_back_pressure.2794948477
/workspace/coverage/default/9.hmac_burst_wr.2273049245
/workspace/coverage/default/9.hmac_datapath_stress.3562433957
/workspace/coverage/default/9.hmac_error.2504004012
/workspace/coverage/default/9.hmac_long_msg.1470185577
/workspace/coverage/default/9.hmac_smoke.102409453
/workspace/coverage/default/9.hmac_stress_all.3590534165
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.23274741
/workspace/coverage/default/9.hmac_test_hmac_vectors.4238260024
/workspace/coverage/default/9.hmac_test_sha_vectors.643924420
/workspace/coverage/default/9.hmac_wipe_secret.364127118
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3100731930
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.1603416264
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.3433324430
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.3195702298
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.2711573458
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1089815037
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3922132651
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2194760470
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2077610181



Total test records in report: 907
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T12 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2745849500 Jan 14 12:23:37 PM PST 24 Jan 14 12:23:39 PM PST 24 12272290 ps
T13 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3169824203 Jan 14 12:22:38 PM PST 24 Jan 14 12:22:42 PM PST 24 3171701880 ps
T14 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.415061151 Jan 14 12:22:41 PM PST 24 Jan 14 12:22:44 PM PST 24 1666293915 ps
T15 /workspace/coverage/cover_reg_top/33.hmac_intr_test.22581764 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:33 PM PST 24 51491500 ps
T16 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2705814375 Jan 14 12:23:25 PM PST 24 Jan 14 12:23:28 PM PST 24 42823045 ps
T17 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1439460431 Jan 14 12:23:36 PM PST 24 Jan 14 12:23:40 PM PST 24 277314535 ps
T18 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3522649498 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:33 PM PST 24 14956118 ps
T19 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3301688045 Jan 14 12:22:55 PM PST 24 Jan 14 12:22:56 PM PST 24 15171323 ps
T20 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1812088999 Jan 14 12:23:13 PM PST 24 Jan 14 12:23:21 PM PST 24 17171508 ps
T21 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3300443936 Jan 14 12:23:23 PM PST 24 Jan 14 12:23:28 PM PST 24 44946803 ps
T23 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.394164826 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:07 PM PST 24 201103819 ps
T22 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1536971075 Jan 14 12:23:02 PM PST 24 Jan 14 12:23:07 PM PST 24 477883994 ps
T117 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2283748265 Jan 14 12:23:17 PM PST 24 Jan 14 12:23:22 PM PST 24 52340419 ps
T85 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2565379755 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:07 PM PST 24 18931762 ps
T62 /workspace/coverage/cover_reg_top/11.hmac_intr_test.136918055 Jan 14 12:22:52 PM PST 24 Jan 14 12:22:54 PM PST 24 36481159 ps
T118 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1870395010 Jan 14 12:23:37 PM PST 24 Jan 14 12:23:38 PM PST 24 14224193 ps
T24 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.615497967 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 26424708 ps
T63 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3935166627 Jan 14 12:23:23 PM PST 24 Jan 14 12:23:28 PM PST 24 65115886 ps
T129 /workspace/coverage/cover_reg_top/21.hmac_intr_test.905204906 Jan 14 12:23:25 PM PST 24 Jan 14 12:23:28 PM PST 24 43848518 ps
T130 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3664537928 Jan 14 12:22:45 PM PST 24 Jan 14 12:22:46 PM PST 24 38368157 ps
T60 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1397119048 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:09 PM PST 24 160494744 ps
T25 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2172535122 Jan 14 12:23:25 PM PST 24 Jan 14 12:23:29 PM PST 24 33738168 ps
T131 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2271343651 Jan 14 12:23:07 PM PST 24 Jan 14 12:23:10 PM PST 24 41378570 ps
T61 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.357659887 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:08 PM PST 24 212840288 ps
T26 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2116368578 Jan 14 12:23:27 PM PST 24 Jan 14 12:23:31 PM PST 24 156418104 ps
T64 /workspace/coverage/cover_reg_top/45.hmac_intr_test.632546570 Jan 14 12:23:14 PM PST 24 Jan 14 12:23:21 PM PST 24 57759721 ps
T82 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3544276308 Jan 14 12:23:30 PM PST 24 Jan 14 12:23:31 PM PST 24 17473456 ps
T69 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3469893581 Jan 14 12:22:35 PM PST 24 Jan 14 12:22:36 PM PST 24 66120342 ps
T132 /workspace/coverage/cover_reg_top/35.hmac_intr_test.255177378 Jan 14 12:23:31 PM PST 24 Jan 14 12:23:32 PM PST 24 15302392 ps
T65 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3804296740 Jan 14 12:22:45 PM PST 24 Jan 14 12:22:46 PM PST 24 41309023 ps
T66 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3213160546 Jan 14 12:22:49 PM PST 24 Jan 14 12:22:53 PM PST 24 19473346 ps
T84 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2312784416 Jan 14 12:24:09 PM PST 24 Jan 14 12:24:10 PM PST 24 58041324 ps
T27 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2095112740 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 27565678 ps
T68 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3281643836 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:35 PM PST 24 89274265 ps
T28 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.68102630 Jan 14 12:23:02 PM PST 24 Jan 14 12:23:05 PM PST 24 51662690 ps
T70 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3413737716 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 137251590 ps
T83 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3946088141 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:06 PM PST 24 47290748 ps
T67 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2743469738 Jan 14 12:23:14 PM PST 24 Jan 14 12:23:21 PM PST 24 99878906 ps
T133 /workspace/coverage/cover_reg_top/34.hmac_intr_test.577879652 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:33 PM PST 24 90479061 ps
T71 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2788275009 Jan 14 12:22:44 PM PST 24 Jan 14 12:22:46 PM PST 24 79329574 ps
T72 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.75878804 Jan 14 12:22:57 PM PST 24 Jan 14 12:23:06 PM PST 24 197394432 ps
T134 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2306069939 Jan 14 12:22:53 PM PST 24 Jan 14 12:22:59 PM PST 24 3661012410 ps
T29 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4097375565 Jan 14 12:22:57 PM PST 24 Jan 14 12:23:00 PM PST 24 56004523 ps
T73 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2393763527 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 48095403 ps
T74 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.766083129 Jan 14 12:22:44 PM PST 24 Jan 14 12:22:45 PM PST 24 62010840 ps
T135 /workspace/coverage/cover_reg_top/7.hmac_intr_test.397606987 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:07 PM PST 24 40881438 ps
T30 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1588829182 Jan 14 12:23:27 PM PST 24 Jan 14 12:38:12 PM PST 24 403851875298 ps
T136 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1417903605 Jan 14 12:22:57 PM PST 24 Jan 14 12:22:59 PM PST 24 81824151 ps
T137 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3263738222 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 37591011 ps
T138 /workspace/coverage/cover_reg_top/20.hmac_intr_test.982173391 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:35 PM PST 24 72848104 ps
T75 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2795519242 Jan 14 12:22:42 PM PST 24 Jan 14 12:22:43 PM PST 24 31111291 ps
T139 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3750571169 Jan 14 12:23:20 PM PST 24 Jan 14 12:23:27 PM PST 24 38781974 ps
T31 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1870645317 Jan 14 12:23:05 PM PST 24 Jan 14 12:37:35 PM PST 24 260888094490 ps
T119 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.188200107 Jan 14 12:22:52 PM PST 24 Jan 14 12:22:54 PM PST 24 258679792 ps
T140 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2057595811 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 47022894 ps
T141 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1515670939 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 46967748 ps
T142 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3808459064 Jan 14 12:23:28 PM PST 24 Jan 14 12:23:29 PM PST 24 16119887 ps
T128 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1552185599 Jan 14 12:22:36 PM PST 24 Jan 14 12:22:37 PM PST 24 68172036 ps
T76 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1216830760 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:08 PM PST 24 145622289 ps
T143 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2068580821 Jan 14 12:22:41 PM PST 24 Jan 14 12:22:44 PM PST 24 144292845 ps
T77 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3409256713 Jan 14 12:22:45 PM PST 24 Jan 14 12:22:46 PM PST 24 14060272 ps
T144 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3306905288 Jan 14 12:22:34 PM PST 24 Jan 14 12:22:38 PM PST 24 204486814 ps
T145 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2639507272 Jan 14 12:23:16 PM PST 24 Jan 14 12:23:22 PM PST 24 14129295 ps
T146 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.271117281 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 153571202 ps
T147 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1848870655 Jan 14 12:22:54 PM PST 24 Jan 14 12:22:59 PM PST 24 90868003 ps
T148 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3820458258 Jan 14 12:22:52 PM PST 24 Jan 14 12:22:55 PM PST 24 150936045 ps
T149 /workspace/coverage/cover_reg_top/1.hmac_intr_test.609225953 Jan 14 12:22:50 PM PST 24 Jan 14 12:22:53 PM PST 24 33148572 ps
T150 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.769898167 Jan 14 12:22:55 PM PST 24 Jan 14 12:22:57 PM PST 24 55910014 ps
T151 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2559320224 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:07 PM PST 24 764233636 ps
T152 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1794242227 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:08 PM PST 24 31119883 ps
T153 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2444096234 Jan 14 12:24:08 PM PST 24 Jan 14 12:24:10 PM PST 24 29029224 ps
T78 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.837996167 Jan 14 12:22:38 PM PST 24 Jan 14 12:22:39 PM PST 24 27496713 ps
T154 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.687755825 Jan 14 12:23:02 PM PST 24 Jan 14 12:23:09 PM PST 24 451313896 ps
T155 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2107859116 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:30 PM PST 24 36815943 ps
T79 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3275191957 Jan 14 12:23:00 PM PST 24 Jan 14 12:23:04 PM PST 24 204023401 ps
T156 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2467345754 Jan 14 12:22:45 PM PST 24 Jan 14 12:22:49 PM PST 24 130148310 ps
T157 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3560961573 Jan 14 12:23:18 PM PST 24 Jan 14 12:23:22 PM PST 24 321849811 ps
T158 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.201510295 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 29439489 ps
T159 /workspace/coverage/cover_reg_top/19.hmac_intr_test.300609969 Jan 14 12:23:17 PM PST 24 Jan 14 12:23:22 PM PST 24 96767501 ps
T160 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1365037749 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 282273911 ps
T161 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.528227275 Jan 14 12:23:30 PM PST 24 Jan 14 12:23:31 PM PST 24 37348654 ps
T162 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3932743267 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:07 PM PST 24 318180403 ps
T163 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1605753473 Jan 14 12:22:43 PM PST 24 Jan 14 12:22:44 PM PST 24 15527181 ps
T164 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2069354305 Jan 14 12:23:07 PM PST 24 Jan 14 12:23:10 PM PST 24 98656578 ps
T165 /workspace/coverage/cover_reg_top/46.hmac_intr_test.531655340 Jan 14 12:23:17 PM PST 24 Jan 14 12:23:22 PM PST 24 44067894 ps
T166 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1610644060 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:30 PM PST 24 39483651 ps
T167 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4255114702 Jan 14 12:23:07 PM PST 24 Jan 14 12:23:10 PM PST 24 15480268 ps
T168 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1516729712 Jan 14 12:23:28 PM PST 24 Jan 14 12:23:29 PM PST 24 41889148 ps
T169 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.411183067 Jan 14 12:23:01 PM PST 24 Jan 14 12:23:03 PM PST 24 29967910 ps
T170 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2517725771 Jan 14 12:22:54 PM PST 24 Jan 14 12:28:31 PM PST 24 150542711304 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1798200749 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:08 PM PST 24 136888229 ps
T171 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3955812865 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:09 PM PST 24 38250979 ps
T172 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3959751836 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:30 PM PST 24 16952173 ps
T173 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1913033555 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:30 PM PST 24 13432788 ps
T174 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3138141861 Jan 14 12:23:25 PM PST 24 Jan 14 12:23:28 PM PST 24 28957035 ps
T175 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2640089948 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 23573142 ps
T176 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1740018807 Jan 14 12:23:14 PM PST 24 Jan 14 12:23:24 PM PST 24 1046317209 ps
T177 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.249344644 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 199386724 ps
T120 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.176681358 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:06 PM PST 24 347336178 ps
T178 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3715591854 Jan 14 12:22:52 PM PST 24 Jan 14 12:22:54 PM PST 24 55405978 ps
T121 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3300384726 Jan 14 12:23:17 PM PST 24 Jan 14 12:23:23 PM PST 24 73244657 ps
T179 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1934708095 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 77298391 ps
T180 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2763469260 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:09 PM PST 24 502748140 ps
T181 /workspace/coverage/cover_reg_top/4.hmac_intr_test.516538154 Jan 14 12:23:00 PM PST 24 Jan 14 12:23:02 PM PST 24 14630535 ps
T126 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3502518577 Jan 14 12:22:57 PM PST 24 Jan 14 12:23:00 PM PST 24 814380407 ps
T182 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3616026881 Jan 14 12:23:24 PM PST 24 Jan 14 12:23:28 PM PST 24 22047282 ps
T183 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2011586676 Jan 14 12:23:13 PM PST 24 Jan 14 12:23:21 PM PST 24 12643495 ps
T1 /workspace/coverage/default/46.hmac_stress_all.2080479217 Jan 14 01:51:12 PM PST 24 Jan 14 01:58:05 PM PST 24 33651506129 ps
T2 /workspace/coverage/default/34.hmac_smoke.8512760 Jan 14 01:50:16 PM PST 24 Jan 14 01:50:20 PM PST 24 122211376 ps
T3 /workspace/coverage/default/8.hmac_burst_wr.2758364458 Jan 14 01:48:25 PM PST 24 Jan 14 01:48:57 PM PST 24 1301241443 ps
T7 /workspace/coverage/default/11.hmac_error.2583113925 Jan 14 01:48:37 PM PST 24 Jan 14 01:52:14 PM PST 24 19662931800 ps
T4 /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.354389588 Jan 14 01:51:38 PM PST 24 Jan 14 01:57:59 PM PST 24 29764414065 ps
T9 /workspace/coverage/default/13.hmac_burst_wr.4046961615 Jan 14 01:48:44 PM PST 24 Jan 14 01:48:53 PM PST 24 707274019 ps
T5 /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3368114160 Jan 14 01:51:27 PM PST 24 Jan 14 02:15:38 PM PST 24 304583013893 ps
T10 /workspace/coverage/default/16.hmac_stress_all.3507983415 Jan 14 01:48:58 PM PST 24 Jan 14 01:57:01 PM PST 24 150725614594 ps
T8 /workspace/coverage/default/13.hmac_wipe_secret.2579943193 Jan 14 01:48:45 PM PST 24 Jan 14 01:49:11 PM PST 24 2194145565 ps
T11 /workspace/coverage/default/36.hmac_test_sha_vectors.3052560026 Jan 14 01:50:24 PM PST 24 Jan 14 01:57:55 PM PST 24 116732898640 ps
T6 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1525571653 Jan 14 01:48:45 PM PST 24 Jan 14 02:28:07 PM PST 24 281113143037 ps
T33 /workspace/coverage/default/34.hmac_wipe_secret.224961895 Jan 14 01:50:15 PM PST 24 Jan 14 01:50:25 PM PST 24 577600569 ps
T39 /workspace/coverage/default/26.hmac_burst_wr.1416396879 Jan 14 01:49:36 PM PST 24 Jan 14 01:50:18 PM PST 24 5459969097 ps
T40 /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.2436713412 Jan 14 01:51:41 PM PST 24 Jan 14 02:03:07 PM PST 24 189137923290 ps
T184 /workspace/coverage/default/5.hmac_test_hmac_vectors.2460944714 Jan 14 01:48:20 PM PST 24 Jan 14 01:48:21 PM PST 24 90050931 ps
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