Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18845320

1

T1

37463

T2

93

T3

3986

auto[1]

9272564

1

T2

86

T3

12267

T7

2962

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9328555

1

T2

78

T3

10052

T7

8277

auto[1]

18789329

1

T1

37463

T2

101

T3

6201

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16325481

1

T1

37429

T2

79

T3

11730

auto[1]

11792403

1

T1

34

T2

100

T3

4523

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16016143	1			T1	24961		T2	94		T3	222
fifo_depth[1]	1388595	1			T1	2478		T2	14		T3	175
fifo_depth[2]	1236747	1			T1	2352		T2	13		T3	377
fifo_depth[3]	1049163	1			T1	1883		T2	9		T3	376
fifo_depth[4]	1028410	1			T1	1397		T2	17		T3	969
fifo_depth[5]	881219	1			T1	1197		T2	10		T3	482
fifo_depth[6]	916127	1			T1	981		T2	4		T3	1036
fifo_depth[7]	781565	1			T1	785		T2	4		T3	536
fifo_depth[8]	922172	1			T1	571		T2	6		T3	2057
fifo_depth[9]	552545	1			T1	383		T2	3		T3	547
fifo_depth[10]	559567	1			T1	211		T2	2		T3	1561
fifo_depth[11]	345545	1			T1	163		T2	1		T3	562
fifo_depth[12]	568420	1			T1	57		T2	1		T3	1930
fifo_depth[13]	262456	1			T1	24		T3	513		T4	73
fifo_depth[14]	417508	1			T1	10		T3	1546		T4	44
fifo_depth[15]	234572	1			T1	7		T2	1		T3	551
fifo_depth[16]	957130	1			T1	3		T3	2813		T4	9

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12101741

1

T1

12502

T2

85

T3

16031

auto[1]

16016143

1

T1

24961

T2

94

T3

222

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27160754

1

T1

37460

T2

179

T3

13440

auto[1]

957130

1

T1

3

T3

2813

T4

9

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

980533

1

T3

868

T7

125

T4

2399

auto[0]

auto[0]

auto[0]

auto[1]

911704

1

T3

7268

T7

53

T4

1976

auto[0]

auto[0]

auto[1]

auto[0]

2992088

1

T1

12489

T3

821

T4

2246

auto[0]

auto[0]

auto[1]

auto[1]

987528

1

T3

2603

T7

64

T4

1979

auto[0]

auto[1]

auto[0]

auto[0]

1554630

1

T2

21

T3

692

T7

14

auto[0]

auto[1]

auto[0]

auto[1]

1543976

1

T2

17

T3

1150

T4

2838

auto[0]

auto[1]

auto[1]

auto[0]

1607311

1

T1

13

T2

30

T3

1499

auto[0]

auto[1]

auto[1]

auto[1]

1523971

1

T2

17

T3

1130

T7

6

auto[1]

auto[0]

auto[0]

auto[0]

744439

1

T2

29

T3

3

T7

4408

auto[1]

auto[0]

auto[0]

auto[1]

797077

1

T2

5

T3

66

T7

765

auto[1]

auto[0]

auto[1]

auto[0]

8136513

1

T1

24940

T2

5

T3

86

auto[1]

auto[0]

auto[1]

auto[1]

775599

1

T2

40

T3

15

T7

1058

auto[1]

auto[1]

auto[0]

auto[0]

1420638

1

T2

3

T3

1

T7

2473

auto[1]

auto[1]

auto[0]

auto[1]

1375558

1

T2

3

T3

4

T7

439

auto[1]

auto[1]

auto[1]

auto[0]

1409168

1

T1

21

T2

5

T3

16

auto[1]

auto[1]

auto[1]

auto[1]

1357151

1

T2

4

T3

31

T7

577

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1598139

1

T2

29

T3

775

T7

4533

auto[0]

auto[0]

auto[0]

auto[1]

1601035

1

T2

5

T3

5936

T7

818

auto[0]

auto[0]

auto[1]

auto[0]

11004386

1

T1

37426

T2

5

T3

795

auto[0]

auto[0]

auto[1]

auto[1]

1637471

1

T2

40

T3

2351

T7

1122

auto[0]

auto[1]

auto[0]

auto[0]

2864436

1

T2

24

T3

558

T7

2487

auto[0]

auto[1]

auto[0]

auto[1]

2802931

1

T2

20

T3

473

T7

439

auto[0]

auto[1]

auto[1]

auto[0]

2893458

1

T1

34

T2

35

T3

1420

auto[0]

auto[1]

auto[1]

auto[1]

2758898

1

T2

21

T3

1132

T7

583

auto[1]

auto[0]

auto[0]

auto[0]

126833

1

T3

96

T4

1

T9

45

auto[1]

auto[0]

auto[0]

auto[1]

107746

1

T3

1398

T9

28

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

124215

1

T1

3

T3

112

T4

2

auto[1]

auto[0]

auto[1]

auto[1]

125656

1

T3

267

T4

1

T6

5580

auto[1]

auto[1]

auto[0]

auto[0]

110832

1

T3

135

T6

2699

T39

1984

auto[1]

auto[1]

auto[0]

auto[1]

116603

1

T3

681

T4

2

T9

1121

auto[1]

auto[1]

auto[1]

auto[0]

123021

1

T3

95

T4

1

T9

445

auto[1]

auto[1]

auto[1]

auto[1]

122224

1

T3

29

T4

2

T6

5325

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	744439	1			T2	29		T3	3		T7	4408
fifo_depth[0]	auto[0]	auto[0]	auto[1]	797077	1			T2	5		T3	66		T7	765
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8136513	1			T1	24940		T2	5		T3	86
fifo_depth[0]	auto[0]	auto[1]	auto[1]	775599	1			T2	40		T3	15		T7	1058
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1420638	1			T2	3		T3	1		T7	2473
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1375558	1			T2	3		T3	4		T7	439
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1409168	1			T1	21		T2	5		T3	16
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1357151	1			T2	4		T3	31		T7	577
fifo_depth[1]	auto[0]	auto[0]	auto[0]	69629	1			T7	91		T4	252		T9	4
fifo_depth[1]	auto[0]	auto[0]	auto[1]	70755	1			T3	83		T7	34		T4	225
fifo_depth[1]	auto[0]	auto[1]	auto[0]	549134	1			T1	2473		T3	23		T4	258
fifo_depth[1]	auto[0]	auto[1]	auto[1]	72625	1			T3	12		T7	37		T4	221
fifo_depth[1]	auto[1]	auto[0]	auto[0]	158005	1			T2	5		T7	13		T4	100
fifo_depth[1]	auto[1]	auto[0]	auto[1]	154277	1			T2	1		T4	278		T9	4
fifo_depth[1]	auto[1]	auto[1]	auto[0]	161444	1			T1	5		T2	6		T3	35
fifo_depth[1]	auto[1]	auto[1]	auto[1]	152726	1			T2	2		T3	22		T7	6
fifo_depth[2]	auto[0]	auto[0]	auto[0]	67499	1			T3	8		T7	27		T4	285
fifo_depth[2]	auto[0]	auto[0]	auto[1]	66262	1			T3	208		T7	16		T4	231
fifo_depth[2]	auto[0]	auto[1]	auto[0]	455649	1			T1	2349		T3	23		T4	271
fifo_depth[2]	auto[0]	auto[1]	auto[1]	68952	1			T3	25		T7	15		T4	213
fifo_depth[2]	auto[1]	auto[0]	auto[0]	146177	1			T2	3		T3	1		T7	1
fifo_depth[2]	auto[1]	auto[0]	auto[1]	142696	1			T2	6		T3	1		T4	317
fifo_depth[2]	auto[1]	auto[1]	auto[0]	148332	1			T1	3		T2	2		T3	31
fifo_depth[2]	auto[1]	auto[1]	auto[1]	141180	1			T2	2		T3	80		T4	325
fifo_depth[3]	auto[0]	auto[0]	auto[0]	59001	1			T3	1		T7	6		T4	289
fifo_depth[3]	auto[0]	auto[0]	auto[1]	57614	1			T3	204		T7	2		T4	219
fifo_depth[3]	auto[0]	auto[1]	auto[0]	359676	1			T1	1880		T3	34		T4	265
fifo_depth[3]	auto[0]	auto[1]	auto[1]	60811	1			T3	14		T7	9		T4	220
fifo_depth[3]	auto[1]	auto[0]	auto[0]	129263	1			T2	2		T3	8		T4	91
fifo_depth[3]	auto[1]	auto[0]	auto[1]	126780	1			T2	1		T3	1		T4	309
fifo_depth[3]	auto[1]	auto[1]	auto[0]	131244	1			T1	3		T2	3		T3	36
fifo_depth[3]	auto[1]	auto[1]	auto[1]	124774	1			T2	3		T3	78		T4	334
fifo_depth[4]	auto[0]	auto[0]	auto[0]	71953	1			T3	9		T7	1		T4	260
fifo_depth[4]	auto[0]	auto[0]	auto[1]	65147	1			T3	497		T7	1		T4	222
fifo_depth[4]	auto[0]	auto[1]	auto[0]	285896	1			T1	1396		T3	41		T4	251
fifo_depth[4]	auto[0]	auto[1]	auto[1]	71341	1			T3	35		T7	3		T4	228
fifo_depth[4]	auto[1]	auto[0]	auto[0]	133882	1			T2	3		T3	22		T4	101
fifo_depth[4]	auto[1]	auto[0]	auto[1]	131989	1			T2	5		T3	43		T4	340
fifo_depth[4]	auto[1]	auto[1]	auto[0]	138540	1			T1	1		T2	6		T3	217
fifo_depth[4]	auto[1]	auto[1]	auto[1]	129662	1			T2	3		T3	105		T4	317
fifo_depth[5]	auto[0]	auto[0]	auto[0]	58072	1			T3	20		T4	255		T9	3
fifo_depth[5]	auto[0]	auto[0]	auto[1]	54443	1			T3	231		T4	200		T9	13
fifo_depth[5]	auto[0]	auto[1]	auto[0]	234400	1			T1	1196		T3	38		T4	261
fifo_depth[5]	auto[0]	auto[1]	auto[1]	57919	1			T3	31		T4	214		T5	56
fifo_depth[5]	auto[1]	auto[0]	auto[0]	119893	1			T2	1		T3	13		T4	99
fifo_depth[5]	auto[1]	auto[0]	auto[1]	117993	1			T2	4		T3	24		T4	316
fifo_depth[5]	auto[1]	auto[1]	auto[0]	122923	1			T1	1		T2	2		T3	31
fifo_depth[5]	auto[1]	auto[1]	auto[1]	115576	1			T2	3		T3	94		T4	321
fifo_depth[6]	auto[0]	auto[0]	auto[0]	68308	1			T3	25		T4	233		T9	15
fifo_depth[6]	auto[0]	auto[0]	auto[1]	63317	1			T3	495		T4	210		T9	54
fifo_depth[6]	auto[0]	auto[1]	auto[0]	216627	1			T1	981		T3	31		T4	239
fifo_depth[6]	auto[0]	auto[1]	auto[1]	66995	1			T3	121		T4	221		T5	49
fifo_depth[6]	auto[1]	auto[0]	auto[0]	124870	1			T2	2		T3	13		T4	91
fifo_depth[6]	auto[1]	auto[0]	auto[1]	124232	1			T3	60		T4	316		T9	12
fifo_depth[6]	auto[1]	auto[1]	auto[0]	130558	1			T2	2		T3	198		T4	87
fifo_depth[6]	auto[1]	auto[1]	auto[1]	121220	1			T3	93		T4	352		T5	58
fifo_depth[7]	auto[0]	auto[0]	auto[0]	56298	1			T3	20		T4	240		T9	25
fifo_depth[7]	auto[0]	auto[0]	auto[1]	54450	1			T3	236		T4	204		T9	11
fifo_depth[7]	auto[0]	auto[1]	auto[0]	170301	1			T1	785		T3	31		T4	206
fifo_depth[7]	auto[0]	auto[1]	auto[1]	55253	1			T3	110		T4	211		T5	26
fifo_depth[7]	auto[1]	auto[0]	auto[0]	112627	1			T2	1		T3	25		T4	96
fifo_depth[7]	auto[1]	auto[0]	auto[1]	111156	1			T4	268		T9	25		T5	62
fifo_depth[7]	auto[1]	auto[1]	auto[0]	114562	1			T2	2		T3	28		T4	71
fifo_depth[7]	auto[1]	auto[1]	auto[1]	106918	1			T2	1		T3	86		T4	292
fifo_depth[8]	auto[0]	auto[0]	auto[0]	84353	1			T3	211		T4	217		T9	117
fifo_depth[8]	auto[0]	auto[0]	auto[1]	81848	1			T3	1025		T4	177		T9	73
fifo_depth[8]	auto[0]	auto[1]	auto[0]	164170	1			T1	571		T3	242		T4	173
fifo_depth[8]	auto[0]	auto[1]	auto[1]	85640	1			T3	206		T4	160		T5	28
fifo_depth[8]	auto[1]	auto[0]	auto[0]	125969	1			T2	1		T3	20		T4	70
fifo_depth[8]	auto[1]	auto[0]	auto[1]	125113	1			T3	63		T4	256		T9	107
fifo_depth[8]	auto[1]	auto[1]	auto[0]	128951	1			T2	4		T3	205		T4	70
fifo_depth[8]	auto[1]	auto[1]	auto[1]	126128	1			T2	1		T3	85		T4	244
fifo_depth[9]	auto[0]	auto[0]	auto[0]	45170	1			T3	17		T4	146		T9	92
fifo_depth[9]	auto[0]	auto[0]	auto[1]	42644	1			T3	213		T4	116		T9	8
fifo_depth[9]	auto[0]	auto[1]	auto[0]	98424	1			T1	383		T3	24		T4	133
fifo_depth[9]	auto[0]	auto[1]	auto[1]	44158	1			T3	172		T4	126		T5	3
fifo_depth[9]	auto[1]	auto[0]	auto[0]	81786	1			T3	13		T4	53		T5	7
fifo_depth[9]	auto[1]	auto[0]	auto[1]	79543	1			T3	10		T4	181		T9	39
fifo_depth[9]	auto[1]	auto[1]	auto[0]	82124	1			T2	2		T3	21		T4	50
fifo_depth[9]	auto[1]	auto[1]	auto[1]	78696	1			T2	1		T3	77		T4	198
fifo_depth[10]	auto[0]	auto[0]	auto[0]	54740	1			T3	174		T4	131		T9	89
fifo_depth[10]	auto[0]	auto[0]	auto[1]	51444	1			T3	768		T4	79		T9	65
fifo_depth[10]	auto[0]	auto[1]	auto[0]	89194	1			T1	211		T3	22		T4	82
fifo_depth[10]	auto[0]	auto[1]	auto[1]	56863	1			T3	251		T4	81		T5	9
fifo_depth[10]	auto[1]	auto[0]	auto[0]	76725	1			T2	1		T3	12		T4	27
fifo_depth[10]	auto[1]	auto[0]	auto[1]	75085	1			T3	47		T4	124		T9	115
fifo_depth[10]	auto[1]	auto[1]	auto[0]	80385	1			T2	1		T3	211		T4	40
fifo_depth[10]	auto[1]	auto[1]	auto[1]	75131	1			T3	76		T4	138		T5	10
fifo_depth[11]	auto[0]	auto[0]	auto[0]	33386	1			T3	12		T4	54		T9	91
fifo_depth[11]	auto[0]	auto[0]	auto[1]	31407	1			T3	226		T4	50		T9	5
fifo_depth[11]	auto[0]	auto[1]	auto[0]	53303	1			T1	163		T3	15		T4	54
fifo_depth[11]	auto[0]	auto[1]	auto[1]	35361	1			T3	201		T4	42		T5	2
fifo_depth[11]	auto[1]	auto[0]	auto[0]	48830	1			T2	1		T3	12		T4	20
fifo_depth[11]	auto[1]	auto[0]	auto[1]	48666	1			T3	11		T4	74		T9	100
fifo_depth[11]	auto[1]	auto[1]	auto[0]	49097	1			T3	14		T4	21		T9	14
fifo_depth[11]	auto[1]	auto[1]	auto[1]	45495	1			T3	71		T4	74		T5	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	69887	1			T3	129		T4	26		T9	77
fifo_depth[12]	auto[0]	auto[0]	auto[1]	61744	1			T3	796		T4	27		T9	65
fifo_depth[12]	auto[0]	auto[1]	auto[0]	74050	1			T1	57		T3	172		T4	36
fifo_depth[12]	auto[0]	auto[1]	auto[1]	72096	1			T3	469		T4	18		T8	20
fifo_depth[12]	auto[1]	auto[0]	auto[0]	70571	1			T2	1		T3	34		T4	9
fifo_depth[12]	auto[1]	auto[0]	auto[1]	71254	1			T3	79		T4	27		T9	148
fifo_depth[12]	auto[1]	auto[1]	auto[0]	73821	1			T3	187		T4	9		T9	44
fifo_depth[12]	auto[1]	auto[1]	auto[1]	74997	1			T3	64		T4	46		T8	2
fifo_depth[13]	auto[0]	auto[0]	auto[0]	30387	1			T3	10		T4	7		T9	73
fifo_depth[13]	auto[0]	auto[0]	auto[1]	27304	1			T3	197		T4	9		T9	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	35619	1			T1	24		T3	5		T4	12
fifo_depth[13]	auto[0]	auto[1]	auto[1]	31866	1			T3	178		T4	11		T5	4
fifo_depth[13]	auto[1]	auto[0]	auto[0]	35032	1			T3	28		T4	2		T6	752
fifo_depth[13]	auto[1]	auto[0]	auto[1]	34668	1			T3	31		T4	10		T9	115
fifo_depth[13]	auto[1]	auto[1]	auto[0]	35587	1			T3	8		T4	3		T9	14
fifo_depth[13]	auto[1]	auto[1]	auto[1]	31993	1			T3	56		T4	19		T8	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	55533	1			T3	132		T4	2		T9	51
fifo_depth[14]	auto[0]	auto[0]	auto[1]	48235	1			T3	568		T4	7		T9	36
fifo_depth[14]	auto[0]	auto[1]	auto[0]	51987	1			T1	10		T3	4		T4	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	53415	1			T3	361		T4	9		T8	7
fifo_depth[14]	auto[1]	auto[0]	auto[0]	50378	1			T3	177		T4	2		T6	1228
fifo_depth[14]	auto[1]	auto[0]	auto[1]	52010	1			T3	68		T4	13		T9	116
fifo_depth[14]	auto[1]	auto[1]	auto[0]	55288	1			T3	178		T4	4		T9	15
fifo_depth[14]	auto[1]	auto[1]	auto[1]	50662	1			T3	58		T4	5		T8	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	29484	1			T3	4		T4	1		T9	69
fifo_depth[15]	auto[0]	auto[0]	auto[1]	27344	1			T3	123		T9	2		T8	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	29443	1			T1	7		T3	4		T4	1
fifo_depth[15]	auto[0]	auto[1]	auto[1]	28577	1			T3	150		T4	3		T8	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	29790	1			T3	179		T6	643		T33	3
fifo_depth[15]	auto[1]	auto[0]	auto[1]	31911	1			T3	31		T4	7		T9	85
fifo_depth[15]	auto[1]	auto[1]	auto[0]	31434	1			T3	4		T9	14		T6	965
fifo_depth[15]	auto[1]	auto[1]	auto[1]	26589	1			T2	1		T3	56		T6	312
fifo_depth[16]	auto[0]	auto[0]	auto[0]	126833	1			T3	96		T4	1		T9	45
fifo_depth[16]	auto[0]	auto[0]	auto[1]	107746	1			T3	1398		T9	28		T8	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	124215	1			T1	3		T3	112		T4	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	125656	1			T3	267		T4	1		T6	5580
fifo_depth[16]	auto[1]	auto[0]	auto[0]	110832	1			T3	135		T6	2699		T39	1984
fifo_depth[16]	auto[1]	auto[0]	auto[1]	116603	1			T3	681		T4	2		T9	1121
fifo_depth[16]	auto[1]	auto[1]	auto[0]	123021	1			T3	95		T4	1		T9	445
fifo_depth[16]	auto[1]	auto[1]	auto[1]	122224	1			T3	29		T4	2		T6	5325