Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	4115	1			T15	7		T16	4		T18	10
all_values[1]	4115	1			T15	7		T16	4		T18	10
all_values[2]	4115	1			T15	7		T16	4		T18	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5830

1

T15

17

T16

6

T18

15

auto[1]

6515

1

T15

4

T16

6

T18

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4632

1

T15

4

T16

3

T18

10

auto[1]

7713

1

T15

17

T16

9

T18

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6983

1

T15

10

T16

6

T18

18

auto[1]

5362

1

T15

11

T16

6

T18

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

767

1

T15

2

T16

1

T18

3

all_values[0]

auto[0]

auto[0]

auto[1]

397

1

T15

1

T16

1

T18

1

all_values[0]

auto[0]

auto[1]

auto[0]

770

1

T20

2

T117

3

T62

1

all_values[0]

auto[0]

auto[1]

auto[1]

393

1

T15

1

T18

2

T62

1

all_values[0]

auto[1]

auto[0]

auto[1]

782

1

T15

2

T16

2

T18

2

all_values[0]

auto[1]

auto[1]

auto[1]

1006

1

T15

1

T18

2

T20

1

all_values[1]

auto[0]

auto[0]

auto[0]

716

1

T16

1

T18

2

T20

3

all_values[1]

auto[0]

auto[0]

auto[1]

410

1

T15

2

T18

1

T117

1

all_values[1]

auto[0]

auto[1]

auto[0]

814

1

T18

1

T20

2

T117

1

all_values[1]

auto[0]

auto[1]

auto[1]

373

1

T16

1

T18

2

T118

2

all_values[1]

auto[1]

auto[0]

auto[1]

887

1

T15

4

T18

3

T20

1

all_values[1]

auto[1]

auto[1]

auto[1]

915

1

T15

1

T16

2

T18

1

all_values[2]

auto[0]

auto[0]

auto[0]

691

1

T15

2

T18

2

T20

2

all_values[2]

auto[0]

auto[0]

auto[1]

365

1

T15

2

T85

1

T118

1

all_values[2]

auto[0]

auto[1]

auto[0]

874

1

T16

1

T18

2

T85

2

all_values[2]

auto[0]

auto[1]

auto[1]

413

1

T16

1

T18

2

T20

2

all_values[2]

auto[1]

auto[0]

auto[1]

815

1

T15

2

T16

1

T18

1

all_values[2]

auto[1]

auto[1]

auto[1]

957

1

T15

1

T16

1

T18

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal