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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.53 98.47 100.00 100.00 99.76 99.49 99.72


Total test records in report: 907
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T760 /workspace/coverage/default/46.hmac_long_msg.2251877635 Jan 14 01:51:15 PM PST 24 Jan 14 01:52:18 PM PST 24 1159028006 ps
T761 /workspace/coverage/default/18.hmac_long_msg.3149715945 Jan 14 01:49:24 PM PST 24 Jan 14 01:49:43 PM PST 24 748586840 ps
T762 /workspace/coverage/default/23.hmac_alert_test.1747315953 Jan 14 01:49:56 PM PST 24 Jan 14 01:49:58 PM PST 24 30866367 ps
T763 /workspace/coverage/default/24.hmac_burst_wr.3210713703 Jan 14 01:49:50 PM PST 24 Jan 14 01:49:56 PM PST 24 301044890 ps
T100 /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3306617753 Jan 14 01:52:00 PM PST 24 Jan 14 02:39:06 PM PST 24 287639441759 ps
T764 /workspace/coverage/default/23.hmac_test_sha_vectors.3768976204 Jan 14 01:49:54 PM PST 24 Jan 14 01:57:48 PM PST 24 166483368360 ps
T765 /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.3302121096 Jan 14 01:49:00 PM PST 24 Jan 14 02:05:45 PM PST 24 124401575161 ps
T766 /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.576213680 Jan 14 01:51:48 PM PST 24 Jan 14 02:51:57 PM PST 24 68313181841 ps
T767 /workspace/coverage/default/39.hmac_back_pressure.3284722855 Jan 14 01:50:37 PM PST 24 Jan 14 01:51:14 PM PST 24 1969340823 ps
T768 /workspace/coverage/default/11.hmac_datapath_stress.839680990 Jan 14 01:48:39 PM PST 24 Jan 14 01:50:47 PM PST 24 3186973626 ps
T769 /workspace/coverage/default/45.hmac_test_hmac_vectors.3477666816 Jan 14 01:50:59 PM PST 24 Jan 14 01:51:03 PM PST 24 67304004 ps
T770 /workspace/coverage/default/6.hmac_error.3522480354 Jan 14 01:48:22 PM PST 24 Jan 14 01:49:02 PM PST 24 779998306 ps
T771 /workspace/coverage/default/43.hmac_long_msg.1407949412 Jan 14 01:50:47 PM PST 24 Jan 14 01:51:36 PM PST 24 887954779 ps
T772 /workspace/coverage/default/14.hmac_burst_wr.721229230 Jan 14 01:48:52 PM PST 24 Jan 14 01:49:00 PM PST 24 522935592 ps
T773 /workspace/coverage/default/42.hmac_test_hmac_vectors.2938740341 Jan 14 01:50:49 PM PST 24 Jan 14 01:50:52 PM PST 24 33565118 ps
T774 /workspace/coverage/default/27.hmac_smoke.945314923 Jan 14 01:49:56 PM PST 24 Jan 14 01:50:00 PM PST 24 443834273 ps
T775 /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2329935405 Jan 14 01:51:40 PM PST 24 Jan 14 02:09:43 PM PST 24 62599319790 ps
T776 /workspace/coverage/default/25.hmac_test_sha_vectors.2129383097 Jan 14 01:49:40 PM PST 24 Jan 14 01:56:40 PM PST 24 17524393484 ps
T777 /workspace/coverage/default/25.hmac_smoke.3306345031 Jan 14 01:49:59 PM PST 24 Jan 14 01:50:02 PM PST 24 190819846 ps
T778 /workspace/coverage/default/26.hmac_smoke.3437776040 Jan 14 01:49:44 PM PST 24 Jan 14 01:49:52 PM PST 24 447140311 ps
T779 /workspace/coverage/default/13.hmac_stress_all.361208512 Jan 14 01:48:49 PM PST 24 Jan 14 02:07:38 PM PST 24 68600070153 ps
T780 /workspace/coverage/default/13.hmac_long_msg.1262371901 Jan 14 01:48:53 PM PST 24 Jan 14 01:50:02 PM PST 24 15233096628 ps
T781 /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1971811826 Jan 14 01:50:56 PM PST 24 Jan 14 02:18:22 PM PST 24 42062454652 ps
T782 /workspace/coverage/default/7.hmac_burst_wr.302977792 Jan 14 01:48:28 PM PST 24 Jan 14 01:48:41 PM PST 24 259182222 ps
T783 /workspace/coverage/default/2.hmac_error.3308513205 Jan 14 01:48:05 PM PST 24 Jan 14 01:49:53 PM PST 24 9088172294 ps
T784 /workspace/coverage/default/47.hmac_stress_all.793339445 Jan 14 01:51:11 PM PST 24 Jan 14 01:51:13 PM PST 24 141479343 ps
T785 /workspace/coverage/default/4.hmac_alert_test.3279709907 Jan 14 01:48:13 PM PST 24 Jan 14 01:48:15 PM PST 24 49687403 ps
T786 /workspace/coverage/default/33.hmac_long_msg.1145064678 Jan 14 01:50:15 PM PST 24 Jan 14 01:50:32 PM PST 24 300877841 ps
T787 /workspace/coverage/default/40.hmac_stress_all.3164874350 Jan 14 01:50:42 PM PST 24 Jan 14 01:57:39 PM PST 24 16958739082 ps
T788 /workspace/coverage/default/7.hmac_alert_test.1867172236 Jan 14 01:48:24 PM PST 24 Jan 14 01:48:25 PM PST 24 29144715 ps
T102 /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.3345687511 Jan 14 01:52:06 PM PST 24 Jan 14 03:02:44 PM PST 24 484365872552 ps
T789 /workspace/coverage/default/48.hmac_error.2598726701 Jan 14 01:51:14 PM PST 24 Jan 14 01:52:13 PM PST 24 3746268710 ps
T103 /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.3087426092 Jan 14 01:51:28 PM PST 24 Jan 14 02:32:47 PM PST 24 68755861428 ps
T790 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3248989686 Jan 14 01:52:03 PM PST 24 Jan 14 02:07:54 PM PST 24 64713658203 ps
T791 /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2450246587 Jan 14 01:48:12 PM PST 24 Jan 14 01:57:07 PM PST 24 181008266675 ps
T792 /workspace/coverage/default/35.hmac_test_hmac_vectors.638091194 Jan 14 01:50:19 PM PST 24 Jan 14 01:50:21 PM PST 24 32635969 ps
T793 /workspace/coverage/default/19.hmac_long_msg.218842082 Jan 14 01:49:14 PM PST 24 Jan 14 01:49:45 PM PST 24 2472882565 ps
T794 /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1482900491 Jan 14 01:49:20 PM PST 24 Jan 14 01:56:50 PM PST 24 48148817791 ps
T795 /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.844505671 Jan 14 01:51:43 PM PST 24 Jan 14 02:37:12 PM PST 24 55107339822 ps
T796 /workspace/coverage/default/22.hmac_back_pressure.1371308553 Jan 14 01:49:16 PM PST 24 Jan 14 01:49:58 PM PST 24 2992386998 ps
T797 /workspace/coverage/default/13.hmac_alert_test.4200970533 Jan 14 01:48:43 PM PST 24 Jan 14 01:48:45 PM PST 24 17025022 ps
T798 /workspace/coverage/default/5.hmac_back_pressure.309199073 Jan 14 01:48:15 PM PST 24 Jan 14 01:48:30 PM PST 24 2012945633 ps
T799 /workspace/coverage/default/32.hmac_wipe_secret.2211097402 Jan 14 01:50:08 PM PST 24 Jan 14 01:51:01 PM PST 24 3985022581 ps
T800 /workspace/coverage/default/43.hmac_stress_all.3340526626 Jan 14 01:51:09 PM PST 24 Jan 14 01:52:49 PM PST 24 2950480661 ps
T801 /workspace/coverage/default/18.hmac_smoke.3079208125 Jan 14 01:49:24 PM PST 24 Jan 14 01:49:27 PM PST 24 173937649 ps
T802 /workspace/coverage/default/8.hmac_test_sha_vectors.163799953 Jan 14 01:48:28 PM PST 24 Jan 14 01:55:18 PM PST 24 38580726590 ps
T803 /workspace/coverage/default/19.hmac_back_pressure.1814753539 Jan 14 01:49:11 PM PST 24 Jan 14 01:49:43 PM PST 24 3650332892 ps
T804 /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.2828074980 Jan 14 01:52:07 PM PST 24 Jan 14 02:11:44 PM PST 24 262794006617 ps
T805 /workspace/coverage/default/13.hmac_back_pressure.2754702417 Jan 14 01:48:47 PM PST 24 Jan 14 01:49:28 PM PST 24 3353268570 ps
T806 /workspace/coverage/default/31.hmac_wipe_secret.1819824801 Jan 14 01:50:02 PM PST 24 Jan 14 01:50:59 PM PST 24 15003094461 ps
T807 /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.4050840285 Jan 14 01:51:41 PM PST 24 Jan 14 01:54:42 PM PST 24 28697372600 ps
T808 /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2963689216 Jan 14 01:52:04 PM PST 24 Jan 14 02:06:37 PM PST 24 69394612839 ps
T809 /workspace/coverage/default/28.hmac_smoke.3372231969 Jan 14 01:50:18 PM PST 24 Jan 14 01:50:22 PM PST 24 455850968 ps
T810 /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.164900700 Jan 14 01:51:39 PM PST 24 Jan 14 02:19:48 PM PST 24 195922051060 ps
T811 /workspace/coverage/default/23.hmac_wipe_secret.3375169177 Jan 14 01:50:00 PM PST 24 Jan 14 01:50:55 PM PST 24 2870976780 ps
T812 /workspace/coverage/default/5.hmac_burst_wr.1374007044 Jan 14 01:48:07 PM PST 24 Jan 14 01:48:40 PM PST 24 1869707141 ps
T813 /workspace/coverage/default/48.hmac_back_pressure.444146486 Jan 14 01:51:14 PM PST 24 Jan 14 01:51:40 PM PST 24 3261435054 ps
T814 /workspace/coverage/default/4.hmac_stress_all.255737617 Jan 14 01:48:09 PM PST 24 Jan 14 01:58:11 PM PST 24 148898123786 ps
T815 /workspace/coverage/default/39.hmac_datapath_stress.1672079945 Jan 14 01:50:37 PM PST 24 Jan 14 01:51:33 PM PST 24 4014982008 ps
T816 /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.3195702298 Jan 14 01:51:34 PM PST 24 Jan 14 02:18:53 PM PST 24 36557922514 ps
T817 /workspace/coverage/default/15.hmac_back_pressure.676304413 Jan 14 01:48:56 PM PST 24 Jan 14 01:49:46 PM PST 24 7683550649 ps
T818 /workspace/coverage/default/2.hmac_wipe_secret.4213568566 Jan 14 01:48:02 PM PST 24 Jan 14 01:49:09 PM PST 24 3480818506 ps
T819 /workspace/coverage/default/37.hmac_test_sha_vectors.3940767033 Jan 14 01:50:25 PM PST 24 Jan 14 01:57:50 PM PST 24 35563849730 ps
T820 /workspace/coverage/default/4.hmac_datapath_stress.1091007336 Jan 14 01:48:09 PM PST 24 Jan 14 01:48:56 PM PST 24 918263511 ps
T821 /workspace/coverage/default/30.hmac_back_pressure.3147742290 Jan 14 01:50:07 PM PST 24 Jan 14 01:51:11 PM PST 24 3143082625 ps
T822 /workspace/coverage/default/15.hmac_burst_wr.3270008738 Jan 14 01:48:56 PM PST 24 Jan 14 01:49:09 PM PST 24 1440851086 ps
T823 /workspace/coverage/default/41.hmac_test_hmac_vectors.2896482232 Jan 14 01:50:45 PM PST 24 Jan 14 01:50:47 PM PST 24 117560797 ps
T824 /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1866144586 Jan 14 01:50:20 PM PST 24 Jan 14 02:15:21 PM PST 24 478160521815 ps
T825 /workspace/coverage/default/16.hmac_alert_test.4267059126 Jan 14 01:49:04 PM PST 24 Jan 14 01:49:06 PM PST 24 41593043 ps
T826 /workspace/coverage/default/26.hmac_back_pressure.393977958 Jan 14 01:49:40 PM PST 24 Jan 14 01:50:16 PM PST 24 911929107 ps
T827 /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.3718217822 Jan 14 01:52:08 PM PST 24 Jan 14 01:59:55 PM PST 24 29777169659 ps
T828 /workspace/coverage/default/27.hmac_error.2493280969 Jan 14 01:50:09 PM PST 24 Jan 14 01:52:35 PM PST 24 2876704598 ps
T829 /workspace/coverage/default/47.hmac_error.1893708465 Jan 14 01:51:15 PM PST 24 Jan 14 01:51:21 PM PST 24 87670447 ps
T830 /workspace/coverage/default/23.hmac_smoke.1616246597 Jan 14 01:49:37 PM PST 24 Jan 14 01:49:42 PM PST 24 153961324 ps
T831 /workspace/coverage/default/21.hmac_wipe_secret.4010196724 Jan 14 01:49:20 PM PST 24 Jan 14 01:49:36 PM PST 24 1412736133 ps
T832 /workspace/coverage/default/4.hmac_long_msg.2697350110 Jan 14 01:48:11 PM PST 24 Jan 14 01:48:38 PM PST 24 4695223941 ps
T833 /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.834720089 Jan 14 01:51:14 PM PST 24 Jan 14 02:20:08 PM PST 24 87450481008 ps
T834 /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.1068098082 Jan 14 01:51:29 PM PST 24 Jan 14 02:00:38 PM PST 24 117557611125 ps
T835 /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.2335102070 Jan 14 01:51:49 PM PST 24 Jan 14 02:08:21 PM PST 24 881074932475 ps
T836 /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.1603416264 Jan 14 01:51:33 PM PST 24 Jan 14 02:46:57 PM PST 24 426128603658 ps
T837 /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.3467816699 Jan 14 01:51:41 PM PST 24 Jan 14 02:05:42 PM PST 24 174921880310 ps
T838 /workspace/coverage/default/8.hmac_datapath_stress.2926797370 Jan 14 01:48:27 PM PST 24 Jan 14 01:50:29 PM PST 24 2337438176 ps
T839 /workspace/coverage/default/23.hmac_error.1634069499 Jan 14 01:49:46 PM PST 24 Jan 14 01:51:05 PM PST 24 3265779546 ps
T840 /workspace/coverage/default/42.hmac_back_pressure.728170494 Jan 14 01:50:59 PM PST 24 Jan 14 01:51:25 PM PST 24 706329565 ps
T841 /workspace/coverage/default/7.hmac_long_msg.2175949390 Jan 14 01:48:17 PM PST 24 Jan 14 01:49:28 PM PST 24 14983123912 ps
T842 /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.4040745979 Jan 14 01:50:56 PM PST 24 Jan 14 02:48:46 PM PST 24 1705064800734 ps
T843 /workspace/coverage/default/6.hmac_test_hmac_vectors.3755911352 Jan 14 01:48:20 PM PST 24 Jan 14 01:48:21 PM PST 24 98201511 ps
T844 /workspace/coverage/default/45.hmac_error.4219852626 Jan 14 01:51:00 PM PST 24 Jan 14 01:54:03 PM PST 24 15892005547 ps
T845 /workspace/coverage/default/5.hmac_stress_all.4139875056 Jan 14 01:48:30 PM PST 24 Jan 14 02:13:26 PM PST 24 265208624714 ps
T846 /workspace/coverage/default/5.hmac_error.1738817157 Jan 14 01:48:10 PM PST 24 Jan 14 01:48:57 PM PST 24 3602632842 ps
T847 /workspace/coverage/default/19.hmac_wipe_secret.3809437349 Jan 14 01:49:24 PM PST 24 Jan 14 01:49:45 PM PST 24 4378299356 ps
T848 /workspace/coverage/default/16.hmac_long_msg.2223884216 Jan 14 01:49:06 PM PST 24 Jan 14 01:50:16 PM PST 24 1321239394 ps
T849 /workspace/coverage/default/29.hmac_long_msg.2816385013 Jan 14 01:50:10 PM PST 24 Jan 14 01:50:32 PM PST 24 966663206 ps
T850 /workspace/coverage/default/22.hmac_wipe_secret.3952279272 Jan 14 01:49:44 PM PST 24 Jan 14 01:50:14 PM PST 24 2091070462 ps
T851 /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.2848968235 Jan 14 01:50:20 PM PST 24 Jan 14 02:18:06 PM PST 24 140329437722 ps
T852 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.20881353 Jan 14 01:51:58 PM PST 24 Jan 14 02:20:18 PM PST 24 33412649712 ps
T853 /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.917152192 Jan 14 01:52:11 PM PST 24 Jan 14 02:10:17 PM PST 24 125267261473 ps
T854 /workspace/coverage/default/16.hmac_burst_wr.1886353709 Jan 14 01:48:53 PM PST 24 Jan 14 01:49:22 PM PST 24 2750861494 ps
T855 /workspace/coverage/default/25.hmac_wipe_secret.2276874593 Jan 14 01:49:40 PM PST 24 Jan 14 01:50:33 PM PST 24 1409876185 ps
T856 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2772796811 Jan 14 12:23:00 PM PST 24 Jan 14 12:23:02 PM PST 24 199999522 ps
T857 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4071679827 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 46571450 ps
T81 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1572146986 Jan 14 12:24:31 PM PST 24 Jan 14 12:24:37 PM PST 24 770612310 ps
T858 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.763989598 Jan 14 12:22:52 PM PST 24 Jan 14 12:22:55 PM PST 24 78277841 ps
T859 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.414461340 Jan 14 12:22:56 PM PST 24 Jan 14 12:22:59 PM PST 24 152397832 ps
T860 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3963661234 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:05 PM PST 24 63890967 ps
T861 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2497235794 Jan 14 12:23:16 PM PST 24 Jan 14 12:23:23 PM PST 24 170641411 ps
T123 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.102308264 Jan 14 12:22:41 PM PST 24 Jan 14 12:22:43 PM PST 24 226668208 ps
T862 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1095332891 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 22108982 ps
T863 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3048411529 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 18678664 ps
T864 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1356519958 Jan 14 12:22:43 PM PST 24 Jan 14 12:22:44 PM PST 24 16647771 ps
T865 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3570560837 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 121771248 ps
T866 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.714457499 Jan 14 12:23:00 PM PST 24 Jan 14 12:23:02 PM PST 24 254743802 ps
T124 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3588590458 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 45763169 ps
T867 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.130226079 Jan 14 12:23:26 PM PST 24 Jan 14 12:23:28 PM PST 24 116867759 ps
T868 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.962546436 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 21275450 ps
T869 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3718566698 Jan 14 12:23:31 PM PST 24 Jan 14 12:23:32 PM PST 24 18965022 ps
T870 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1732701109 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:07 PM PST 24 41883622 ps
T871 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4166935082 Jan 14 12:23:29 PM PST 24 Jan 14 12:23:30 PM PST 24 41592340 ps
T872 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3997892769 Jan 14 12:22:54 PM PST 24 Jan 14 12:22:57 PM PST 24 92430840 ps
T873 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2687779053 Jan 14 12:22:46 PM PST 24 Jan 14 12:22:50 PM PST 24 62651868 ps
T874 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1099467152 Jan 14 12:22:54 PM PST 24 Jan 14 12:22:57 PM PST 24 37044015 ps
T875 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.398285893 Jan 14 12:22:38 PM PST 24 Jan 14 12:22:40 PM PST 24 82183613 ps
T876 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1962005069 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:06 PM PST 24 91053398 ps
T125 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2145280503 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:08 PM PST 24 217792398 ps
T877 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2796119799 Jan 14 12:23:02 PM PST 24 Jan 14 12:23:04 PM PST 24 51341277 ps
T878 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3544202221 Jan 14 12:23:17 PM PST 24 Jan 14 12:23:22 PM PST 24 16891599 ps
T879 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3469687068 Jan 14 12:22:43 PM PST 24 Jan 14 12:22:45 PM PST 24 775611550 ps
T880 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2250297272 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:09 PM PST 24 161031315 ps
T881 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3636366417 Jan 14 12:23:37 PM PST 24 Jan 14 12:23:42 PM PST 24 372343104 ps
T882 /workspace/coverage/cover_reg_top/8.hmac_intr_test.758933962 Jan 14 12:23:05 PM PST 24 Jan 14 12:23:07 PM PST 24 30789215 ps
T883 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2899464064 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 19322136 ps
T884 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.851091531 Jan 14 12:22:40 PM PST 24 Jan 14 12:22:42 PM PST 24 29077744 ps
T885 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2966947860 Jan 14 12:23:26 PM PST 24 Jan 14 12:23:28 PM PST 24 15187319 ps
T886 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3558659650 Jan 14 12:24:08 PM PST 24 Jan 14 12:24:11 PM PST 24 144275405 ps
T887 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.110026510 Jan 14 12:22:42 PM PST 24 Jan 14 12:22:43 PM PST 24 61107121 ps
T888 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2631160370 Jan 14 12:23:27 PM PST 24 Jan 14 12:23:29 PM PST 24 85486784 ps
T889 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1031895242 Jan 14 12:23:19 PM PST 24 Jan 14 12:23:22 PM PST 24 14105768 ps
T890 /workspace/coverage/cover_reg_top/15.hmac_intr_test.425281626 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 37212477 ps
T891 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3584420820 Jan 14 12:23:26 PM PST 24 Jan 14 12:23:28 PM PST 24 15136147 ps
T892 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4160714206 Jan 14 12:23:16 PM PST 24 Jan 14 12:23:24 PM PST 24 287384296 ps
T893 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2641339767 Jan 14 12:22:36 PM PST 24 Jan 14 12:22:37 PM PST 24 11995324 ps
T894 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2701885265 Jan 14 12:23:18 PM PST 24 Jan 14 12:23:23 PM PST 24 283971138 ps
T895 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1849178771 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:33 PM PST 24 26300257 ps
T896 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1062147454 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:06 PM PST 24 21377842 ps
T897 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3525345846 Jan 14 12:23:00 PM PST 24 Jan 14 12:23:03 PM PST 24 21894834 ps
T898 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1862709709 Jan 14 12:23:31 PM PST 24 Jan 14 12:23:32 PM PST 24 13768581 ps
T127 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.606924100 Jan 14 12:23:23 PM PST 24 Jan 14 12:23:29 PM PST 24 746851981 ps
T899 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1085180689 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:06 PM PST 24 361486007 ps
T900 /workspace/coverage/cover_reg_top/48.hmac_intr_test.314613076 Jan 14 12:23:13 PM PST 24 Jan 14 12:23:21 PM PST 24 14559817 ps
T901 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.321195763 Jan 14 12:22:39 PM PST 24 Jan 14 12:22:42 PM PST 24 163668144 ps
T902 /workspace/coverage/cover_reg_top/17.hmac_intr_test.362306220 Jan 14 12:23:23 PM PST 24 Jan 14 12:23:27 PM PST 24 13655987 ps
T903 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2022228610 Jan 14 12:23:32 PM PST 24 Jan 14 12:23:33 PM PST 24 28885261 ps
T904 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3027753880 Jan 14 12:23:31 PM PST 24 Jan 14 12:23:32 PM PST 24 60750468 ps
T905 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.250305501 Jan 14 12:23:04 PM PST 24 Jan 14 12:23:07 PM PST 24 24079559 ps
T906 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2629491276 Jan 14 12:23:03 PM PST 24 Jan 14 12:23:05 PM PST 24 89350055 ps
T122 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1137171591 Jan 14 12:23:07 PM PST 24 Jan 14 12:23:12 PM PST 24 616415095 ps
T907 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1337148144 Jan 14 12:23:07 PM PST 24 Jan 14 12:25:17 PM PST 24 36445654782 ps

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2745849500
Short name T12
Test name
Test status
Simulation time 12272290 ps
CPU time 0.65 seconds
Started Jan 14 12:23:37 PM PST 24
Finished Jan 14 12:23:39 PM PST 24
Peak memory 194432 kb
Host smart-bc7f9402-6166-46aa-8d3d-a5f1392e07f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745849500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2745849500
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3368114160
Short name T5
Test name
Test status
Simulation time 304583013893 ps
CPU time 1450.16 seconds
Started Jan 14 01:51:27 PM PST 24
Finished Jan 14 02:15:38 PM PST 24
Peak memory 239932 kb
Host smart-fcda8119-ac17-4e45-93b0-9244c3e1fbea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368114160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.3368114160
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3169824203
Short name T13
Test name
Test status
Simulation time 3171701880 ps
CPU time 3.53 seconds
Started Jan 14 12:22:38 PM PST 24
Finished Jan 14 12:22:42 PM PST 24
Peak memory 198732 kb
Host smart-83e1526a-3887-4499-97f4-0087a41268e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169824203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3169824203
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.22581764
Short name T15
Test name
Test status
Simulation time 51491500 ps
CPU time 0.56 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 193080 kb
Host smart-7f558a70-942f-435e-b295-73d22a402426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.22581764
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1027774231
Short name T35
Test name
Test status
Simulation time 222204209742 ps
CPU time 2816.62 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 02:38:30 PM PST 24
Peak memory 245472 kb
Host smart-e64ebe16-ea24-4e11-9001-b5a66babe73b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027774231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.1027774231
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1397119048
Short name T60
Test name
Test status
Simulation time 160494744 ps
CPU time 2.43 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:09 PM PST 24
Peak memory 198464 kb
Host smart-8ddd266d-d547-499b-93ef-248b0889eb9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397119048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1397119048
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.463889215
Short name T47
Test name
Test status
Simulation time 37636396 ps
CPU time 0.79 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:48:12 PM PST 24
Peak memory 216012 kb
Host smart-5c4bfffa-1290-4d50-8ef9-b12a3853db29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463889215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.463889215
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1870395010
Short name T118
Test name
Test status
Simulation time 14224193 ps
CPU time 0.59 seconds
Started Jan 14 12:23:37 PM PST 24
Finished Jan 14 12:23:38 PM PST 24
Peak memory 192992 kb
Host smart-8b406a67-456b-4af1-a473-9e07f15bc3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870395010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1870395010
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.776455554
Short name T42
Test name
Test status
Simulation time 126399739477 ps
CPU time 5076.4 seconds
Started Jan 14 01:52:04 PM PST 24
Finished Jan 14 03:16:42 PM PST 24
Peak memory 273232 kb
Host smart-c5609ec2-1ef6-48d9-a5a9-e0fdba26ac16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776455554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.776455554
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2172535122
Short name T25
Test name
Test status
Simulation time 33738168 ps
CPU time 2.36 seconds
Started Jan 14 12:23:25 PM PST 24
Finished Jan 14 12:23:29 PM PST 24
Peak memory 198592 kb
Host smart-adbbe3d8-6a8e-4abc-9e83-2b6f51ea18ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172535122 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2172535122
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1525571653
Short name T6
Test name
Test status
Simulation time 281113143037 ps
CPU time 2360.23 seconds
Started Jan 14 01:48:45 PM PST 24
Finished Jan 14 02:28:07 PM PST 24
Peak memory 242740 kb
Host smart-856613d5-7b7e-47c4-b5e5-cd6966c35646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525571653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.1525571653
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.2942421183
Short name T106
Test name
Test status
Simulation time 197287689218 ps
CPU time 2084.7 seconds
Started Jan 14 01:52:16 PM PST 24
Finished Jan 14 02:27:02 PM PST 24
Peak memory 256236 kb
Host smart-a6350d29-ffdd-462c-a593-9c30bc7d1c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942421183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.2942421183
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1085180689
Short name T899
Test name
Test status
Simulation time 361486007 ps
CPU time 2.42 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 198424 kb
Host smart-e6b5077d-09b1-4e1c-b2ef-b0992f4c6367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085180689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1085180689
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1731052490
Short name T90
Test name
Test status
Simulation time 162790429652 ps
CPU time 1091.48 seconds
Started Jan 14 01:47:54 PM PST 24
Finished Jan 14 02:06:06 PM PST 24
Peak memory 241596 kb
Host smart-3b60421b-abca-42ed-be9c-454ba4da415b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731052490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1731052490
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.357659887
Short name T61
Test name
Test status
Simulation time 212840288 ps
CPU time 2.23 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 198388 kb
Host smart-19c026de-7692-479d-80a5-7c2b5d6f8fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357659887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.357659887
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.3395514810
Short name T114
Test name
Test status
Simulation time 50621416470 ps
CPU time 1009.58 seconds
Started Jan 14 01:52:00 PM PST 24
Finished Jan 14 02:08:50 PM PST 24
Peak memory 248076 kb
Host smart-12c2ae01-a46b-4eb8-9152-f8dc57cbba14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395514810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.3395514810
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_alert_test.989775349
Short name T293
Test name
Test status
Simulation time 20260098 ps
CPU time 0.58 seconds
Started Jan 14 01:47:55 PM PST 24
Finished Jan 14 01:47:57 PM PST 24
Peak memory 193200 kb
Host smart-5380ba9e-d816-4f1c-82be-145594c50f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989775349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.989775349
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.2999200586
Short name T463
Test name
Test status
Simulation time 53661090879 ps
CPU time 2316.11 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:30:25 PM PST 24
Peak memory 255432 kb
Host smart-2e1fc65a-5e2f-425a-8ce0-f7cc5a443f1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999200586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.2999200586
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.1167790272
Short name T101
Test name
Test status
Simulation time 82210885588 ps
CPU time 3734.8 seconds
Started Jan 14 01:51:47 PM PST 24
Finished Jan 14 02:54:03 PM PST 24
Peak memory 231608 kb
Host smart-f8fc01b8-58dd-49df-93f7-2629f71e3428
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167790272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.1167790272
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3306905288
Short name T144
Test name
Test status
Simulation time 204486814 ps
CPU time 2.95 seconds
Started Jan 14 12:22:34 PM PST 24
Finished Jan 14 12:22:38 PM PST 24
Peak memory 198680 kb
Host smart-cc37b3e5-77da-4921-9975-1881c10d6c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306905288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3306905288
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3997892769
Short name T872
Test name
Test status
Simulation time 92430840 ps
CPU time 1.92 seconds
Started Jan 14 12:22:54 PM PST 24
Finished Jan 14 12:22:57 PM PST 24
Peak memory 192284 kb
Host smart-db25d18f-9645-4a50-96cd-e4586ecd7f83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997892769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3997892769
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1572146986
Short name T81
Test name
Test status
Simulation time 770612310 ps
CPU time 5.35 seconds
Started Jan 14 12:24:31 PM PST 24
Finished Jan 14 12:24:37 PM PST 24
Peak memory 192168 kb
Host smart-7be36693-db54-49ab-9989-a9899c60931b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572146986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1572146986
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3469893581
Short name T69
Test name
Test status
Simulation time 66120342 ps
CPU time 0.71 seconds
Started Jan 14 12:22:35 PM PST 24
Finished Jan 14 12:22:36 PM PST 24
Peak memory 194212 kb
Host smart-99041e94-a307-4a5a-9a48-d1d267f75da9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469893581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3469893581
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1552185599
Short name T128
Test name
Test status
Simulation time 68172036 ps
CPU time 1.08 seconds
Started Jan 14 12:22:36 PM PST 24
Finished Jan 14 12:22:37 PM PST 24
Peak memory 198528 kb
Host smart-54c5748d-2eb3-4950-8661-85bc88324bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552185599 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1552185599
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2312784416
Short name T84
Test name
Test status
Simulation time 58041324 ps
CPU time 0.63 seconds
Started Jan 14 12:24:09 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 193132 kb
Host smart-0ea8b738-c7a4-4869-b40c-7dbca0b4c192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312784416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2312784416
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2641339767
Short name T893
Test name
Test status
Simulation time 11995324 ps
CPU time 0.58 seconds
Started Jan 14 12:22:36 PM PST 24
Finished Jan 14 12:22:37 PM PST 24
Peak memory 193188 kb
Host smart-53334ef6-1d18-44be-8c05-94710f32e910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641339767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2641339767
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.763989598
Short name T858
Test name
Test status
Simulation time 78277841 ps
CPU time 0.95 seconds
Started Jan 14 12:22:52 PM PST 24
Finished Jan 14 12:22:55 PM PST 24
Peak memory 192436 kb
Host smart-e13e5abf-6b09-42a2-953f-dae2f3b081df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763989598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.763989598
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3558659650
Short name T886
Test name
Test status
Simulation time 144275405 ps
CPU time 1.85 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:11 PM PST 24
Peak memory 196668 kb
Host smart-0d7c91f6-d5a2-414d-a848-59359847d8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558659650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3558659650
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3469687068
Short name T879
Test name
Test status
Simulation time 775611550 ps
CPU time 1.92 seconds
Started Jan 14 12:22:43 PM PST 24
Finished Jan 14 12:22:45 PM PST 24
Peak memory 184040 kb
Host smart-58059b2f-2686-4fbc-bf61-0fdaa3e2580e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469687068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3469687068
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1848870655
Short name T147
Test name
Test status
Simulation time 90868003 ps
CPU time 3.01 seconds
Started Jan 14 12:22:54 PM PST 24
Finished Jan 14 12:22:59 PM PST 24
Peak memory 192284 kb
Host smart-023ceb73-9576-420a-80f6-32d2eed07767
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848870655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1848870655
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.837996167
Short name T78
Test name
Test status
Simulation time 27496713 ps
CPU time 0.72 seconds
Started Jan 14 12:22:38 PM PST 24
Finished Jan 14 12:22:39 PM PST 24
Peak memory 194708 kb
Host smart-f8e47656-7fdb-4fc7-a78d-89450c75a746
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837996167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.837996167
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1099467152
Short name T874
Test name
Test status
Simulation time 37044015 ps
CPU time 1.62 seconds
Started Jan 14 12:22:54 PM PST 24
Finished Jan 14 12:22:57 PM PST 24
Peak memory 198716 kb
Host smart-96502382-2d95-4e3f-a3e6-a8391a34ff3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099467152 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1099467152
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1605753473
Short name T163
Test name
Test status
Simulation time 15527181 ps
CPU time 0.68 seconds
Started Jan 14 12:22:43 PM PST 24
Finished Jan 14 12:22:44 PM PST 24
Peak memory 193956 kb
Host smart-2a0f632a-aaea-45d3-aef1-1d25338d22f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605753473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1605753473
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.609225953
Short name T149
Test name
Test status
Simulation time 33148572 ps
CPU time 0.58 seconds
Started Jan 14 12:22:50 PM PST 24
Finished Jan 14 12:22:53 PM PST 24
Peak memory 193072 kb
Host smart-66ed6d7f-b730-4c6e-9820-ebbb4c1c8d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609225953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.609225953
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2444096234
Short name T153
Test name
Test status
Simulation time 29029224 ps
CPU time 0.82 seconds
Started Jan 14 12:24:08 PM PST 24
Finished Jan 14 12:24:10 PM PST 24
Peak memory 193736 kb
Host smart-3c52a9ed-e525-4379-b996-b0a4b1ccccaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444096234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2444096234
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.188200107
Short name T119
Test name
Test status
Simulation time 258679792 ps
CPU time 1.67 seconds
Started Jan 14 12:22:52 PM PST 24
Finished Jan 14 12:22:54 PM PST 24
Peak memory 198228 kb
Host smart-85ce98c8-58f8-43ac-9a06-7ef9f99ba383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188200107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.188200107
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.249344644
Short name T177
Test name
Test status
Simulation time 199386724 ps
CPU time 1.8 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 198636 kb
Host smart-307200ca-b01e-4751-a013-b0f1d8036729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249344644 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.249344644
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.411183067
Short name T169
Test name
Test status
Simulation time 29967910 ps
CPU time 0.59 seconds
Started Jan 14 12:23:01 PM PST 24
Finished Jan 14 12:23:03 PM PST 24
Peak memory 194324 kb
Host smart-619ef613-a825-4da7-a522-f851af76e67d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411183067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.411183067
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3263738222
Short name T137
Test name
Test status
Simulation time 37591011 ps
CPU time 0.62 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192764 kb
Host smart-f137d4b6-d9b9-4597-a49a-b97e14f7a02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263738222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3263738222
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1095332891
Short name T862
Test name
Test status
Simulation time 22108982 ps
CPU time 1.04 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 196708 kb
Host smart-79616ef6-d83f-4a8d-af33-6d39cc8568e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095332891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1095332891
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2559320224
Short name T151
Test name
Test status
Simulation time 764233636 ps
CPU time 2.97 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 198628 kb
Host smart-4fe465dc-f593-42fa-bf1c-2e6b7305f59c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559320224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2559320224
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1962005069
Short name T876
Test name
Test status
Simulation time 91053398 ps
CPU time 1.4 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 198664 kb
Host smart-c2ce44fa-8182-43ca-998f-b1d7b5909749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962005069 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1962005069
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.962546436
Short name T868
Test name
Test status
Simulation time 21275450 ps
CPU time 0.7 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 194336 kb
Host smart-9783394b-0fed-4ae4-b141-d465a1873ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962546436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.962546436
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.136918055
Short name T62
Test name
Test status
Simulation time 36481159 ps
CPU time 0.58 seconds
Started Jan 14 12:22:52 PM PST 24
Finished Jan 14 12:22:54 PM PST 24
Peak memory 193148 kb
Host smart-92f63606-5841-47a1-b0f2-bc3d3bb8b73d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136918055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.136918055
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3413737716
Short name T70
Test name
Test status
Simulation time 137251590 ps
CPU time 1.32 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 192292 kb
Host smart-ff4aff97-1744-4184-8e4b-7e8f5b172cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413737716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3413737716
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2250297272
Short name T880
Test name
Test status
Simulation time 161031315 ps
CPU time 2.61 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:09 PM PST 24
Peak memory 198700 kb
Host smart-a86b052d-6b53-4fa8-b327-50cf4680759f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250297272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2250297272
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3588590458
Short name T124
Test name
Test status
Simulation time 45763169 ps
CPU time 1.16 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 198544 kb
Host smart-ac2ad698-7214-4a3f-b926-841d13babc48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588590458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3588590458
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.615497967
Short name T24
Test name
Test status
Simulation time 26424708 ps
CPU time 1.37 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 197984 kb
Host smart-052d3cff-1c68-4e62-b053-bf10d80a933d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615497967 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.615497967
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1934708095
Short name T179
Test name
Test status
Simulation time 77298391 ps
CPU time 0.66 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 194480 kb
Host smart-5f09118a-7bf5-4118-b7b8-3381bf435ada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934708095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1934708095
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3048411529
Short name T863
Test name
Test status
Simulation time 18678664 ps
CPU time 0.69 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192832 kb
Host smart-128cd4a8-a1f3-4437-a29a-f247a5004b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048411529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3048411529
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3820458258
Short name T148
Test name
Test status
Simulation time 150936045 ps
CPU time 1.28 seconds
Started Jan 14 12:22:52 PM PST 24
Finished Jan 14 12:22:55 PM PST 24
Peak memory 196592 kb
Host smart-0ff8aeeb-655c-47bf-8a8f-f489014d563a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820458258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3820458258
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2095112740
Short name T27
Test name
Test status
Simulation time 27565678 ps
CPU time 1.46 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 198596 kb
Host smart-020b3935-19b5-4931-ae73-cb93b3d08db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095112740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2095112740
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1794242227
Short name T152
Test name
Test status
Simulation time 31119883 ps
CPU time 2.76 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 198332 kb
Host smart-568d12e7-06af-4013-a724-58e95b02f61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794242227 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1794242227
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2899464064
Short name T883
Test name
Test status
Simulation time 19322136 ps
CPU time 0.6 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 193908 kb
Host smart-e3234e81-f054-4d39-befb-1fbfaf3a974e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899464064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2899464064
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1732701109
Short name T870
Test name
Test status
Simulation time 41883622 ps
CPU time 0.62 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 193072 kb
Host smart-a25f0c3e-3fd3-4c75-bd88-c4a428808980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732701109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1732701109
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1365037749
Short name T160
Test name
Test status
Simulation time 282273911 ps
CPU time 1.22 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192396 kb
Host smart-7d4902bc-440b-4f1b-82f2-563cdfc33415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365037749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1365037749
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2772796811
Short name T856
Test name
Test status
Simulation time 199999522 ps
CPU time 1.73 seconds
Started Jan 14 12:23:00 PM PST 24
Finished Jan 14 12:23:02 PM PST 24
Peak memory 198540 kb
Host smart-0d08f983-aa6e-44e4-a712-f0970188b6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772796811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2772796811
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2145280503
Short name T125
Test name
Test status
Simulation time 217792398 ps
CPU time 1.21 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 197920 kb
Host smart-331da5a4-ca60-46a3-8a26-234aa065594d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145280503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2145280503
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1870645317
Short name T31
Test name
Test status
Simulation time 260888094490 ps
CPU time 868.07 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:37:35 PM PST 24
Peak memory 219396 kb
Host smart-50b28028-d176-4474-8fbb-675438ba1b8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870645317 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1870645317
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3963661234
Short name T860
Test name
Test status
Simulation time 63890967 ps
CPU time 0.69 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 194748 kb
Host smart-9ee2417e-9369-4815-a365-49ff7d37d814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963661234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3963661234
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2565379755
Short name T85
Test name
Test status
Simulation time 18931762 ps
CPU time 0.57 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 193088 kb
Host smart-b5e74561-3345-4a84-8f44-3e4fe989e1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565379755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2565379755
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2393763527
Short name T73
Test name
Test status
Simulation time 48095403 ps
CPU time 1.07 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 196316 kb
Host smart-0e92ac1f-b941-4aba-8b4c-fc7ddaaf9d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393763527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2393763527
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3932743267
Short name T162
Test name
Test status
Simulation time 318180403 ps
CPU time 3.43 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 198740 kb
Host smart-09edf312-46f2-463c-a397-f77815691269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932743267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3932743267
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3570560837
Short name T865
Test name
Test status
Simulation time 121771248 ps
CPU time 1.08 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 197644 kb
Host smart-2a4d8e42-117c-4f6b-94f1-c3155563f1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570560837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3570560837
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1588829182
Short name T30
Test name
Test status
Simulation time 403851875298 ps
CPU time 883.09 seconds
Started Jan 14 12:23:27 PM PST 24
Finished Jan 14 12:38:12 PM PST 24
Peak memory 210052 kb
Host smart-2c0b4aee-ee0c-44f0-bcde-93649b496914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588829182 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1588829182
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.528227275
Short name T161
Test name
Test status
Simulation time 37348654 ps
CPU time 0.77 seconds
Started Jan 14 12:23:30 PM PST 24
Finished Jan 14 12:23:31 PM PST 24
Peak memory 194812 kb
Host smart-906cf345-3db1-43ff-b213-16ee257abbb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528227275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.528227275
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.425281626
Short name T890
Test name
Test status
Simulation time 37212477 ps
CPU time 0.58 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 193024 kb
Host smart-9279d209-2c4d-4f7b-956a-aa8eb4aac12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425281626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.425281626
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3560961573
Short name T157
Test name
Test status
Simulation time 321849811 ps
CPU time 1.29 seconds
Started Jan 14 12:23:18 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 191752 kb
Host smart-4852e7fd-4390-4743-bc8a-aa5eab88a400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560961573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3560961573
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2629491276
Short name T906
Test name
Test status
Simulation time 89350055 ps
CPU time 1.28 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 198680 kb
Host smart-a8e43292-363b-42f0-99bf-817fea5f1074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629491276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2629491276
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4160714206
Short name T892
Test name
Test status
Simulation time 287384296 ps
CPU time 2.55 seconds
Started Jan 14 12:23:16 PM PST 24
Finished Jan 14 12:23:24 PM PST 24
Peak memory 198684 kb
Host smart-27db405a-5e3b-40f4-a645-d1195251fd26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160714206 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4160714206
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3544276308
Short name T82
Test name
Test status
Simulation time 17473456 ps
CPU time 0.74 seconds
Started Jan 14 12:23:30 PM PST 24
Finished Jan 14 12:23:31 PM PST 24
Peak memory 194504 kb
Host smart-15f9b5c1-11e8-46a0-a976-d373a27dd4db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544276308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3544276308
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3544202221
Short name T878
Test name
Test status
Simulation time 16891599 ps
CPU time 0.56 seconds
Started Jan 14 12:23:17 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 192416 kb
Host smart-dd9d9966-1cfe-4b00-8e9b-b4fb13471ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544202221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3544202221
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2743469738
Short name T67
Test name
Test status
Simulation time 99878906 ps
CPU time 1.03 seconds
Started Jan 14 12:23:14 PM PST 24
Finished Jan 14 12:23:21 PM PST 24
Peak memory 196184 kb
Host smart-2af4188f-77c7-4bbe-b5f9-a0198b97f4d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743469738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2743469738
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2701885265
Short name T894
Test name
Test status
Simulation time 283971138 ps
CPU time 1.75 seconds
Started Jan 14 12:23:18 PM PST 24
Finished Jan 14 12:23:23 PM PST 24
Peak memory 198604 kb
Host smart-a86a1fb0-1c1f-44a8-9189-28a122dad5e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701885265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2701885265
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3300384726
Short name T121
Test name
Test status
Simulation time 73244657 ps
CPU time 1.15 seconds
Started Jan 14 12:23:17 PM PST 24
Finished Jan 14 12:23:23 PM PST 24
Peak memory 197932 kb
Host smart-f2e22d7f-82c1-4511-a06b-2994d9a1e20b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300384726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3300384726
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3616026881
Short name T182
Test name
Test status
Simulation time 22047282 ps
CPU time 1.2 seconds
Started Jan 14 12:23:24 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 198632 kb
Host smart-30307fda-86b1-4941-a73a-a568cbcf77e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616026881 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3616026881
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3300443936
Short name T21
Test name
Test status
Simulation time 44946803 ps
CPU time 0.73 seconds
Started Jan 14 12:23:23 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 194740 kb
Host smart-94f13816-e999-4f94-ad42-8cb7bcf0724e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300443936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3300443936
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.362306220
Short name T902
Test name
Test status
Simulation time 13655987 ps
CPU time 0.56 seconds
Started Jan 14 12:23:23 PM PST 24
Finished Jan 14 12:23:27 PM PST 24
Peak memory 193056 kb
Host smart-f397ead3-88be-427a-ad52-e8c28fcaf848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362306220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.362306220
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3935166627
Short name T63
Test name
Test status
Simulation time 65115886 ps
CPU time 0.9 seconds
Started Jan 14 12:23:23 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 195668 kb
Host smart-1dff40f9-b008-4703-a46f-c5cc1eccf0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935166627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3935166627
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1740018807
Short name T176
Test name
Test status
Simulation time 1046317209 ps
CPU time 3.64 seconds
Started Jan 14 12:23:14 PM PST 24
Finished Jan 14 12:23:24 PM PST 24
Peak memory 198544 kb
Host smart-ae82846d-8199-4496-9f90-5a31231d1fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740018807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1740018807
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3281643836
Short name T68
Test name
Test status
Simulation time 89274265 ps
CPU time 1.74 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:35 PM PST 24
Peak memory 198296 kb
Host smart-92169004-273f-4bf5-bb9b-8dea33713846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281643836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3281643836
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2497235794
Short name T861
Test name
Test status
Simulation time 170641411 ps
CPU time 1.07 seconds
Started Jan 14 12:23:16 PM PST 24
Finished Jan 14 12:23:23 PM PST 24
Peak memory 198448 kb
Host smart-0a8a96fc-87f2-484c-832b-7c789bcd0ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497235794 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2497235794
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2966947860
Short name T885
Test name
Test status
Simulation time 15187319 ps
CPU time 0.73 seconds
Started Jan 14 12:23:26 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 194532 kb
Host smart-8f1db20f-0026-4b5b-85bd-32977af18551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966947860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2966947860
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2631160370
Short name T888
Test name
Test status
Simulation time 85486784 ps
CPU time 0.59 seconds
Started Jan 14 12:23:27 PM PST 24
Finished Jan 14 12:23:29 PM PST 24
Peak memory 193176 kb
Host smart-c8a16881-c310-4a0c-b027-bac0adebf059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631160370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2631160370
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.130226079
Short name T867
Test name
Test status
Simulation time 116867759 ps
CPU time 1.17 seconds
Started Jan 14 12:23:26 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 196708 kb
Host smart-caf24df4-f772-4e7d-9b27-afe6da07ff7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130226079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.130226079
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2116368578
Short name T26
Test name
Test status
Simulation time 156418104 ps
CPU time 3.06 seconds
Started Jan 14 12:23:27 PM PST 24
Finished Jan 14 12:23:31 PM PST 24
Peak memory 198740 kb
Host smart-64f4d4d2-192d-44a0-9598-b5721915826e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116368578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2116368578
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.606924100
Short name T127
Test name
Test status
Simulation time 746851981 ps
CPU time 1.9 seconds
Started Jan 14 12:23:23 PM PST 24
Finished Jan 14 12:23:29 PM PST 24
Peak memory 198524 kb
Host smart-68de7827-9917-4a89-a2be-eb16c5b54e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606924100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.606924100
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.300609969
Short name T159
Test name
Test status
Simulation time 96767501 ps
CPU time 0.6 seconds
Started Jan 14 12:23:17 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 192992 kb
Host smart-69e46bc1-19ac-472f-a183-2de26b086ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300609969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.300609969
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3138141861
Short name T174
Test name
Test status
Simulation time 28957035 ps
CPU time 0.82 seconds
Started Jan 14 12:23:25 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 192020 kb
Host smart-de6a5e32-2111-47fb-94b3-d986bb104de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138141861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3138141861
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3636366417
Short name T881
Test name
Test status
Simulation time 372343104 ps
CPU time 3.46 seconds
Started Jan 14 12:23:37 PM PST 24
Finished Jan 14 12:23:42 PM PST 24
Peak memory 198588 kb
Host smart-af944be7-f863-4448-9599-a43abb73bea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636366417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3636366417
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1439460431
Short name T17
Test name
Test status
Simulation time 277314535 ps
CPU time 1.18 seconds
Started Jan 14 12:23:36 PM PST 24
Finished Jan 14 12:23:40 PM PST 24
Peak memory 197852 kb
Host smart-df5ecfa8-92f1-44fe-ab02-69634c05bdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439460431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1439460431
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3275191957
Short name T79
Test name
Test status
Simulation time 204023401 ps
CPU time 2.36 seconds
Started Jan 14 12:23:00 PM PST 24
Finished Jan 14 12:23:04 PM PST 24
Peak memory 192072 kb
Host smart-c7b478e9-734b-49c8-813a-0c4ced98eaf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275191957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3275191957
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.75878804
Short name T72
Test name
Test status
Simulation time 197394432 ps
CPU time 8.16 seconds
Started Jan 14 12:22:57 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 192304 kb
Host smart-b080ee40-466a-43e4-ad1f-8f8b5ad591e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75878804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.75878804
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4255114702
Short name T167
Test name
Test status
Simulation time 15480268 ps
CPU time 0.62 seconds
Started Jan 14 12:23:07 PM PST 24
Finished Jan 14 12:23:10 PM PST 24
Peak memory 193680 kb
Host smart-9bb23f70-ad42-464b-a97a-e088ece95c79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255114702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4255114702
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2517725771
Short name T170
Test name
Test status
Simulation time 150542711304 ps
CPU time 335.58 seconds
Started Jan 14 12:22:54 PM PST 24
Finished Jan 14 12:28:31 PM PST 24
Peak memory 200808 kb
Host smart-c9ea79b2-859b-4568-a8c1-898ffc864cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517725771 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2517725771
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3409256713
Short name T77
Test name
Test status
Simulation time 14060272 ps
CPU time 0.63 seconds
Started Jan 14 12:22:45 PM PST 24
Finished Jan 14 12:22:46 PM PST 24
Peak memory 194016 kb
Host smart-2e0b221d-3ab0-477b-a9a1-67db08ff7bb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409256713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3409256713
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3715591854
Short name T178
Test name
Test status
Simulation time 55405978 ps
CPU time 0.58 seconds
Started Jan 14 12:22:52 PM PST 24
Finished Jan 14 12:22:54 PM PST 24
Peak memory 193060 kb
Host smart-b84ef549-9594-4aa0-a36e-4a48f40a37fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715591854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3715591854
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.851091531
Short name T884
Test name
Test status
Simulation time 29077744 ps
CPU time 0.78 seconds
Started Jan 14 12:22:40 PM PST 24
Finished Jan 14 12:22:42 PM PST 24
Peak memory 194888 kb
Host smart-10808afc-0b05-4768-bb01-802bd7a9a72d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851091531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.851091531
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.398285893
Short name T875
Test name
Test status
Simulation time 82183613 ps
CPU time 1.15 seconds
Started Jan 14 12:22:38 PM PST 24
Finished Jan 14 12:22:40 PM PST 24
Peak memory 198564 kb
Host smart-5a6c62c8-6c0c-40fa-ab5b-005d027c040c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398285893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.398285893
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.321195763
Short name T901
Test name
Test status
Simulation time 163668144 ps
CPU time 2.47 seconds
Started Jan 14 12:22:39 PM PST 24
Finished Jan 14 12:22:42 PM PST 24
Peak memory 198296 kb
Host smart-6b531288-34d9-408d-a001-84ec139c239d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321195763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.321195763
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.982173391
Short name T138
Test name
Test status
Simulation time 72848104 ps
CPU time 0.56 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:35 PM PST 24
Peak memory 193076 kb
Host smart-7a20ef6c-0bdf-437c-b815-def95f847f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982173391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.982173391
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.905204906
Short name T129
Test name
Test status
Simulation time 43848518 ps
CPU time 0.61 seconds
Started Jan 14 12:23:25 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 193028 kb
Host smart-24be97f2-6bc2-489f-a231-df469d283c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905204906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.905204906
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1913033555
Short name T173
Test name
Test status
Simulation time 13432788 ps
CPU time 0.6 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:30 PM PST 24
Peak memory 193060 kb
Host smart-3678cfa1-7bca-4a77-bf22-2f872e35288a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913033555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1913033555
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1610644060
Short name T166
Test name
Test status
Simulation time 39483651 ps
CPU time 0.58 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:30 PM PST 24
Peak memory 192976 kb
Host smart-e3921a9f-58ae-4bdb-bd56-6e3f2a02447b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610644060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1610644060
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2107859116
Short name T155
Test name
Test status
Simulation time 36815943 ps
CPU time 0.59 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:30 PM PST 24
Peak memory 192904 kb
Host smart-f85cdd4c-f7c1-4187-af76-67d8c53e7203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107859116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2107859116
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4166935082
Short name T871
Test name
Test status
Simulation time 41592340 ps
CPU time 0.6 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:30 PM PST 24
Peak memory 192944 kb
Host smart-f52969ef-9823-490e-8b85-e8497564e08c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166935082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4166935082
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3750571169
Short name T139
Test name
Test status
Simulation time 38781974 ps
CPU time 0.59 seconds
Started Jan 14 12:23:20 PM PST 24
Finished Jan 14 12:23:27 PM PST 24
Peak memory 193032 kb
Host smart-ef85bf3f-a86c-4802-b462-607a0ef15d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750571169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3750571169
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3959751836
Short name T172
Test name
Test status
Simulation time 16952173 ps
CPU time 0.64 seconds
Started Jan 14 12:23:29 PM PST 24
Finished Jan 14 12:23:30 PM PST 24
Peak memory 192976 kb
Host smart-9f0150f9-ec1d-433f-ad17-d94056e2f735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959751836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3959751836
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3808459064
Short name T142
Test name
Test status
Simulation time 16119887 ps
CPU time 0.59 seconds
Started Jan 14 12:23:28 PM PST 24
Finished Jan 14 12:23:29 PM PST 24
Peak memory 192804 kb
Host smart-56450917-d5e5-4db6-a7a0-7d7fa86250c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808459064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3808459064
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2705814375
Short name T16
Test name
Test status
Simulation time 42823045 ps
CPU time 0.55 seconds
Started Jan 14 12:23:25 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 193080 kb
Host smart-35213f31-b13d-4739-9fc4-1ad9387825d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705814375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2705814375
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1216830760
Short name T76
Test name
Test status
Simulation time 145622289 ps
CPU time 2.62 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 192184 kb
Host smart-ce0d237e-ee6b-449f-81a4-26b0a2114420
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216830760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1216830760
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2306069939
Short name T134
Test name
Test status
Simulation time 3661012410 ps
CPU time 3.39 seconds
Started Jan 14 12:22:53 PM PST 24
Finished Jan 14 12:22:59 PM PST 24
Peak memory 192332 kb
Host smart-0f0189d8-a843-4676-97df-f0ca2f5f9ae9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306069939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2306069939
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2788275009
Short name T71
Test name
Test status
Simulation time 79329574 ps
CPU time 0.73 seconds
Started Jan 14 12:22:44 PM PST 24
Finished Jan 14 12:22:46 PM PST 24
Peak memory 193948 kb
Host smart-554580db-5d9f-443a-b116-1a14071a5e8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788275009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2788275009
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2467345754
Short name T156
Test name
Test status
Simulation time 130148310 ps
CPU time 1.75 seconds
Started Jan 14 12:22:45 PM PST 24
Finished Jan 14 12:22:49 PM PST 24
Peak memory 198636 kb
Host smart-6dfff53b-8bd0-4d50-8814-a0dadec5441e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467345754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2467345754
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2069354305
Short name T164
Test name
Test status
Simulation time 98656578 ps
CPU time 0.67 seconds
Started Jan 14 12:23:07 PM PST 24
Finished Jan 14 12:23:10 PM PST 24
Peak memory 194832 kb
Host smart-142f7abe-834f-4858-b013-a920afb60765
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069354305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2069354305
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3664537928
Short name T130
Test name
Test status
Simulation time 38368157 ps
CPU time 0.61 seconds
Started Jan 14 12:22:45 PM PST 24
Finished Jan 14 12:22:46 PM PST 24
Peak memory 193000 kb
Host smart-69515081-e4db-4b26-993f-0578b192dc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664537928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3664537928
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.766083129
Short name T74
Test name
Test status
Simulation time 62010840 ps
CPU time 0.76 seconds
Started Jan 14 12:22:44 PM PST 24
Finished Jan 14 12:22:45 PM PST 24
Peak memory 195424 kb
Host smart-739dc2eb-70ca-4e45-b3fe-4835ef5a8391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766083129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.766083129
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2687779053
Short name T873
Test name
Test status
Simulation time 62651868 ps
CPU time 3.21 seconds
Started Jan 14 12:22:46 PM PST 24
Finished Jan 14 12:22:50 PM PST 24
Peak memory 198548 kb
Host smart-c1f50f24-4108-4837-a6db-3348565eeff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687779053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2687779053
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1417903605
Short name T136
Test name
Test status
Simulation time 81824151 ps
CPU time 1.19 seconds
Started Jan 14 12:22:57 PM PST 24
Finished Jan 14 12:22:59 PM PST 24
Peak memory 198120 kb
Host smart-86bd7c83-6279-456a-9149-06dcf0145716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417903605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1417903605
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1516729712
Short name T168
Test name
Test status
Simulation time 41889148 ps
CPU time 0.54 seconds
Started Jan 14 12:23:28 PM PST 24
Finished Jan 14 12:23:29 PM PST 24
Peak memory 192864 kb
Host smart-2f9781d4-ed4a-493b-bed5-d248f0ec0456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516729712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1516729712
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3584420820
Short name T891
Test name
Test status
Simulation time 15136147 ps
CPU time 0.58 seconds
Started Jan 14 12:23:26 PM PST 24
Finished Jan 14 12:23:28 PM PST 24
Peak memory 193076 kb
Host smart-83c23aad-1e8a-4988-97e4-df37e468065b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584420820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3584420820
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3027753880
Short name T904
Test name
Test status
Simulation time 60750468 ps
CPU time 0.58 seconds
Started Jan 14 12:23:31 PM PST 24
Finished Jan 14 12:23:32 PM PST 24
Peak memory 193000 kb
Host smart-6ba8a46e-7cf0-4627-8aaa-0f6bce7ee92c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027753880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3027753880
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.577879652
Short name T133
Test name
Test status
Simulation time 90479061 ps
CPU time 0.56 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 193080 kb
Host smart-42b354ab-168e-4c0f-ab3a-eef5db5e8b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577879652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.577879652
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.255177378
Short name T132
Test name
Test status
Simulation time 15302392 ps
CPU time 0.58 seconds
Started Jan 14 12:23:31 PM PST 24
Finished Jan 14 12:23:32 PM PST 24
Peak memory 192036 kb
Host smart-80865963-8387-4ce7-a5f8-6e5046cbec51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255177378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.255177378
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2022228610
Short name T903
Test name
Test status
Simulation time 28885261 ps
CPU time 0.54 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 193076 kb
Host smart-51e0cb97-be85-45a7-9402-5bd40d0bcb8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022228610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2022228610
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1862709709
Short name T898
Test name
Test status
Simulation time 13768581 ps
CPU time 0.59 seconds
Started Jan 14 12:23:31 PM PST 24
Finished Jan 14 12:23:32 PM PST 24
Peak memory 192020 kb
Host smart-efe1202f-652c-4a43-b22c-8496d429643d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862709709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1862709709
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3522649498
Short name T18
Test name
Test status
Simulation time 14956118 ps
CPU time 0.58 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 193072 kb
Host smart-b023af39-bcc6-48e0-bd5a-78456c16d7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522649498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3522649498
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3718566698
Short name T869
Test name
Test status
Simulation time 18965022 ps
CPU time 0.6 seconds
Started Jan 14 12:23:31 PM PST 24
Finished Jan 14 12:23:32 PM PST 24
Peak memory 193008 kb
Host smart-7b5f52ca-e675-4f4a-864e-a9bb298ca527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718566698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3718566698
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1798200749
Short name T80
Test name
Test status
Simulation time 136888229 ps
CPU time 2.64 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 192180 kb
Host smart-dbdd8170-d8e7-4bea-8939-b88c0665f872
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798200749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1798200749
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.687755825
Short name T154
Test name
Test status
Simulation time 451313896 ps
CPU time 6.29 seconds
Started Jan 14 12:23:02 PM PST 24
Finished Jan 14 12:23:09 PM PST 24
Peak memory 192304 kb
Host smart-bfccea9a-7f2d-4434-acb3-5a5292afb73e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687755825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.687755825
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1062147454
Short name T896
Test name
Test status
Simulation time 21377842 ps
CPU time 0.7 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 193820 kb
Host smart-653b689a-39f9-454d-a436-97686c2057f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062147454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1062147454
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1337148144
Short name T907
Test name
Test status
Simulation time 36445654782 ps
CPU time 127.47 seconds
Started Jan 14 12:23:07 PM PST 24
Finished Jan 14 12:25:17 PM PST 24
Peak memory 206660 kb
Host smart-5d96ad37-e041-47d7-ac20-e56f765352e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337148144 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1337148144
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3804296740
Short name T65
Test name
Test status
Simulation time 41309023 ps
CPU time 0.63 seconds
Started Jan 14 12:22:45 PM PST 24
Finished Jan 14 12:22:46 PM PST 24
Peak memory 193916 kb
Host smart-34f6402c-b0b5-420b-bb15-33f703e51e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804296740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3804296740
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.516538154
Short name T181
Test name
Test status
Simulation time 14630535 ps
CPU time 0.58 seconds
Started Jan 14 12:23:00 PM PST 24
Finished Jan 14 12:23:02 PM PST 24
Peak memory 193032 kb
Host smart-9f31f9b7-5a11-41b6-986d-be8861938ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516538154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.516538154
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.110026510
Short name T887
Test name
Test status
Simulation time 61107121 ps
CPU time 1.09 seconds
Started Jan 14 12:22:42 PM PST 24
Finished Jan 14 12:22:43 PM PST 24
Peak memory 192204 kb
Host smart-7478cc4c-3303-4cc1-8ff3-60a58b28d78e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110026510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.110026510
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4097375565
Short name T29
Test name
Test status
Simulation time 56004523 ps
CPU time 1.54 seconds
Started Jan 14 12:22:57 PM PST 24
Finished Jan 14 12:23:00 PM PST 24
Peak memory 198740 kb
Host smart-4ff5f0a6-d7d0-4074-84a2-d7720547e736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097375565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4097375565
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.415061151
Short name T14
Test name
Test status
Simulation time 1666293915 ps
CPU time 1.68 seconds
Started Jan 14 12:22:41 PM PST 24
Finished Jan 14 12:22:44 PM PST 24
Peak memory 198296 kb
Host smart-3c808b69-cccf-4133-9f23-7a9d1315ff0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415061151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.415061151
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1849178771
Short name T895
Test name
Test status
Simulation time 26300257 ps
CPU time 0.56 seconds
Started Jan 14 12:23:32 PM PST 24
Finished Jan 14 12:23:33 PM PST 24
Peak memory 193052 kb
Host smart-245f1c6a-d12b-4820-a51d-d5748c27dc0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849178771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1849178771
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1031895242
Short name T889
Test name
Test status
Simulation time 14105768 ps
CPU time 0.58 seconds
Started Jan 14 12:23:19 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 193032 kb
Host smart-e4c993a2-e71d-43e1-8ac7-40d94f5953b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031895242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1031895242
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1812088999
Short name T20
Test name
Test status
Simulation time 17171508 ps
CPU time 0.54 seconds
Started Jan 14 12:23:13 PM PST 24
Finished Jan 14 12:23:21 PM PST 24
Peak memory 193060 kb
Host smart-7c259939-caad-4712-a8c2-8368294c3fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812088999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1812088999
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2639507272
Short name T145
Test name
Test status
Simulation time 14129295 ps
CPU time 0.61 seconds
Started Jan 14 12:23:16 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 193188 kb
Host smart-4713e469-f529-4d2e-b655-2d23db87906d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639507272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2639507272
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.632546570
Short name T64
Test name
Test status
Simulation time 57759721 ps
CPU time 0.64 seconds
Started Jan 14 12:23:14 PM PST 24
Finished Jan 14 12:23:21 PM PST 24
Peak memory 193096 kb
Host smart-1b9c6290-75e5-4835-9540-18fdb2ed82c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632546570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.632546570
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.531655340
Short name T165
Test name
Test status
Simulation time 44067894 ps
CPU time 0.6 seconds
Started Jan 14 12:23:17 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 192424 kb
Host smart-cb1a6ea5-43c1-48bc-88b4-a6c69b236f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531655340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.531655340
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2283748265
Short name T117
Test name
Test status
Simulation time 52340419 ps
CPU time 0.57 seconds
Started Jan 14 12:23:17 PM PST 24
Finished Jan 14 12:23:22 PM PST 24
Peak memory 193092 kb
Host smart-916757ed-39de-48b1-80e4-0489232eb99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283748265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2283748265
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.314613076
Short name T900
Test name
Test status
Simulation time 14559817 ps
CPU time 0.55 seconds
Started Jan 14 12:23:13 PM PST 24
Finished Jan 14 12:23:21 PM PST 24
Peak memory 193068 kb
Host smart-cc24cfef-bb2a-436b-ac4e-98d6ece91f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314613076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.314613076
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2011586676
Short name T183
Test name
Test status
Simulation time 12643495 ps
CPU time 0.53 seconds
Started Jan 14 12:23:13 PM PST 24
Finished Jan 14 12:23:21 PM PST 24
Peak memory 193068 kb
Host smart-69d4ed43-30ef-4f2d-95b4-baa93aa262db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011586676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2011586676
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3955812865
Short name T171
Test name
Test status
Simulation time 38250979 ps
CPU time 3.38 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:09 PM PST 24
Peak memory 198556 kb
Host smart-5c53e9e7-4ca3-4dd3-ab3e-1cc5a0b34cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955812865 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3955812865
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3301688045
Short name T19
Test name
Test status
Simulation time 15171323 ps
CPU time 0.59 seconds
Started Jan 14 12:22:55 PM PST 24
Finished Jan 14 12:22:56 PM PST 24
Peak memory 193832 kb
Host smart-bc8873cd-b783-4e6b-b5fb-da1f71e44bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301688045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3301688045
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1356519958
Short name T864
Test name
Test status
Simulation time 16647771 ps
CPU time 0.61 seconds
Started Jan 14 12:22:43 PM PST 24
Finished Jan 14 12:22:44 PM PST 24
Peak memory 193088 kb
Host smart-4580cd75-8713-426b-af9e-d55bf527b684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356519958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1356519958
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.769898167
Short name T150
Test name
Test status
Simulation time 55910014 ps
CPU time 0.82 seconds
Started Jan 14 12:22:55 PM PST 24
Finished Jan 14 12:22:57 PM PST 24
Peak memory 192144 kb
Host smart-ad5bc964-61e7-466a-8c3f-a085d16a74fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769898167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.769898167
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2068580821
Short name T143
Test name
Test status
Simulation time 144292845 ps
CPU time 2.81 seconds
Started Jan 14 12:22:41 PM PST 24
Finished Jan 14 12:22:44 PM PST 24
Peak memory 198632 kb
Host smart-33518bdc-d5c2-439e-b920-5fbd463af6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068580821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2068580821
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1137171591
Short name T122
Test name
Test status
Simulation time 616415095 ps
CPU time 2.33 seconds
Started Jan 14 12:23:07 PM PST 24
Finished Jan 14 12:23:12 PM PST 24
Peak memory 198308 kb
Host smart-89bac10e-6264-4f1f-bd63-b53ee96d1458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137171591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1137171591
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3525345846
Short name T897
Test name
Test status
Simulation time 21894834 ps
CPU time 1.68 seconds
Started Jan 14 12:23:00 PM PST 24
Finished Jan 14 12:23:03 PM PST 24
Peak memory 198512 kb
Host smart-f8c256ab-20d4-4488-be61-f1b8cb8cd6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525345846 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3525345846
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2796119799
Short name T877
Test name
Test status
Simulation time 51341277 ps
CPU time 0.7 seconds
Started Jan 14 12:23:02 PM PST 24
Finished Jan 14 12:23:04 PM PST 24
Peak memory 195016 kb
Host smart-b3e3632b-ad25-4fef-b36a-52cb4fd2f456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796119799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2796119799
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2271343651
Short name T131
Test name
Test status
Simulation time 41378570 ps
CPU time 0.57 seconds
Started Jan 14 12:23:07 PM PST 24
Finished Jan 14 12:23:10 PM PST 24
Peak memory 192996 kb
Host smart-707d7949-b0b2-4ed0-a8c0-bd035dd98c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271343651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2271343651
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.394164826
Short name T23
Test name
Test status
Simulation time 201103819 ps
CPU time 0.73 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192004 kb
Host smart-44eec46e-f303-40a0-b6d3-c023f77901a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394164826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.394164826
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1515670939
Short name T141
Test name
Test status
Simulation time 46967748 ps
CPU time 2.27 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 198564 kb
Host smart-32171744-f63a-457c-bd1d-76204bcb3b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515670939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1515670939
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3502518577
Short name T126
Test name
Test status
Simulation time 814380407 ps
CPU time 2.31 seconds
Started Jan 14 12:22:57 PM PST 24
Finished Jan 14 12:23:00 PM PST 24
Peak memory 198512 kb
Host smart-bdc60b9e-fc5a-4880-82d5-10cbba2b4d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502518577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3502518577
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.201510295
Short name T158
Test name
Test status
Simulation time 29439489 ps
CPU time 1.64 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:08 PM PST 24
Peak memory 198584 kb
Host smart-d4a24e34-e47b-4c70-927e-ce6b2f63145d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201510295 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.201510295
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2795519242
Short name T75
Test name
Test status
Simulation time 31111291 ps
CPU time 0.57 seconds
Started Jan 14 12:22:42 PM PST 24
Finished Jan 14 12:22:43 PM PST 24
Peak memory 193844 kb
Host smart-9fbea5c3-6013-447c-80a0-e46197a2caa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795519242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2795519242
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.397606987
Short name T135
Test name
Test status
Simulation time 40881438 ps
CPU time 0.56 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192992 kb
Host smart-b316b46d-87ab-4122-b10a-f3af88ef003c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397606987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.397606987
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3946088141
Short name T83
Test name
Test status
Simulation time 47290748 ps
CPU time 0.97 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 196696 kb
Host smart-6ee8d8eb-550f-4532-9836-ee863dc978b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946088141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3946088141
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.714457499
Short name T866
Test name
Test status
Simulation time 254743802 ps
CPU time 1.12 seconds
Started Jan 14 12:23:00 PM PST 24
Finished Jan 14 12:23:02 PM PST 24
Peak memory 198628 kb
Host smart-54c86085-c349-40a0-8eba-7ff93b02769a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714457499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.714457499
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.102308264
Short name T123
Test name
Test status
Simulation time 226668208 ps
CPU time 1.11 seconds
Started Jan 14 12:22:41 PM PST 24
Finished Jan 14 12:22:43 PM PST 24
Peak memory 198164 kb
Host smart-b5beaa89-f6d6-4879-b4d8-e19717708a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102308264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.102308264
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.414461340
Short name T859
Test name
Test status
Simulation time 152397832 ps
CPU time 2.37 seconds
Started Jan 14 12:22:56 PM PST 24
Finished Jan 14 12:22:59 PM PST 24
Peak memory 198624 kb
Host smart-859b2244-1db3-4523-93c3-705d27332f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414461340 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.414461340
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.250305501
Short name T905
Test name
Test status
Simulation time 24079559 ps
CPU time 0.78 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 194932 kb
Host smart-2bd1ea91-16a5-4512-8d95-cd45012903af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250305501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.250305501
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.758933962
Short name T882
Test name
Test status
Simulation time 30789215 ps
CPU time 0.57 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 193088 kb
Host smart-2a6c8c3e-8871-4cec-847c-25b7d3651eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758933962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.758933962
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2763469260
Short name T180
Test name
Test status
Simulation time 502748140 ps
CPU time 1.35 seconds
Started Jan 14 12:23:05 PM PST 24
Finished Jan 14 12:23:09 PM PST 24
Peak memory 196904 kb
Host smart-24a5917b-d2b4-457d-a61f-f5f8de25ae22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763469260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2763469260
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1536971075
Short name T22
Test name
Test status
Simulation time 477883994 ps
CPU time 3.11 seconds
Started Jan 14 12:23:02 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 198744 kb
Host smart-e1a6e44d-938c-49ef-8579-9d924187f253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536971075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1536971075
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.176681358
Short name T120
Test name
Test status
Simulation time 347336178 ps
CPU time 1.86 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:06 PM PST 24
Peak memory 198312 kb
Host smart-7d991fe5-1c1e-4aae-a461-922cea0e5a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176681358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.176681358
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2057595811
Short name T140
Test name
Test status
Simulation time 47022894 ps
CPU time 1.59 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 198720 kb
Host smart-8235c688-5c98-45ea-9077-c870ba080015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057595811 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2057595811
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4071679827
Short name T857
Test name
Test status
Simulation time 46571450 ps
CPU time 0.63 seconds
Started Jan 14 12:23:03 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 194404 kb
Host smart-00d8e6f9-5550-4988-94e8-8514912bc1fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071679827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4071679827
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3213160546
Short name T66
Test name
Test status
Simulation time 19473346 ps
CPU time 0.58 seconds
Started Jan 14 12:22:49 PM PST 24
Finished Jan 14 12:22:53 PM PST 24
Peak memory 193092 kb
Host smart-d825d080-4b18-40c9-b75c-d15d3098128a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213160546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3213160546
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2640089948
Short name T175
Test name
Test status
Simulation time 23573142 ps
CPU time 1.04 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 192224 kb
Host smart-427f82e6-83d7-4e26-825f-c97f6fe937b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640089948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2640089948
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.68102630
Short name T28
Test name
Test status
Simulation time 51662690 ps
CPU time 1.41 seconds
Started Jan 14 12:23:02 PM PST 24
Finished Jan 14 12:23:05 PM PST 24
Peak memory 198580 kb
Host smart-9e6de2bf-78d5-4d61-a7ed-9eff9e587d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68102630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.68102630
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.271117281
Short name T146
Test name
Test status
Simulation time 153571202 ps
CPU time 1.79 seconds
Started Jan 14 12:23:04 PM PST 24
Finished Jan 14 12:23:07 PM PST 24
Peak memory 197944 kb
Host smart-419f5ea7-f46c-43fe-8cc3-e64786661c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271117281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.271117281
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.838914015
Short name T726
Test name
Test status
Simulation time 6108506271 ps
CPU time 10.9 seconds
Started Jan 14 01:47:54 PM PST 24
Finished Jan 14 01:48:06 PM PST 24
Peak memory 207048 kb
Host smart-84a91ba5-74d4-496b-9d36-266f4b392b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838914015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.838914015
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3949912752
Short name T485
Test name
Test status
Simulation time 3532378789 ps
CPU time 28.16 seconds
Started Jan 14 01:47:59 PM PST 24
Finished Jan 14 01:48:28 PM PST 24
Peak memory 198832 kb
Host smart-297eb605-ca31-41db-9390-2e58f58e7368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949912752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3949912752
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1300648609
Short name T57
Test name
Test status
Simulation time 284516964 ps
CPU time 14.63 seconds
Started Jan 14 01:47:52 PM PST 24
Finished Jan 14 01:48:07 PM PST 24
Peak memory 198700 kb
Host smart-35be3aeb-5561-4a76-a2cd-70e035daf41f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300648609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1300648609
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1172695943
Short name T392
Test name
Test status
Simulation time 52288006303 ps
CPU time 104.7 seconds
Started Jan 14 01:47:52 PM PST 24
Finished Jan 14 01:49:37 PM PST 24
Peak memory 198836 kb
Host smart-27cb4dda-44b2-4707-a113-6b590b5a6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172695943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1172695943
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.202232007
Short name T268
Test name
Test status
Simulation time 2722279256 ps
CPU time 48.11 seconds
Started Jan 14 01:47:59 PM PST 24
Finished Jan 14 01:48:48 PM PST 24
Peak memory 198856 kb
Host smart-45e5d697-9250-4ba1-9963-283c56edae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202232007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.202232007
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.403049502
Short name T48
Test name
Test status
Simulation time 354276859 ps
CPU time 1 seconds
Started Jan 14 01:47:58 PM PST 24
Finished Jan 14 01:48:00 PM PST 24
Peak memory 218120 kb
Host smart-f5a8af72-3a3f-4008-8255-8ddfd234a96f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403049502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.403049502
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3310728272
Short name T282
Test name
Test status
Simulation time 117968099 ps
CPU time 3.18 seconds
Started Jan 14 01:47:54 PM PST 24
Finished Jan 14 01:47:58 PM PST 24
Peak memory 198700 kb
Host smart-7a222e84-02b6-41ad-85de-4d2c3f53f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310728272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3310728272
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1379518165
Short name T503
Test name
Test status
Simulation time 292496964596 ps
CPU time 1314.95 seconds
Started Jan 14 01:47:55 PM PST 24
Finished Jan 14 02:09:51 PM PST 24
Peak memory 227852 kb
Host smart-70773291-cf95-439c-92ff-33e9e210dcc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379518165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1379518165
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1051872856
Short name T411
Test name
Test status
Simulation time 73141072 ps
CPU time 1.04 seconds
Started Jan 14 01:47:53 PM PST 24
Finished Jan 14 01:47:55 PM PST 24
Peak memory 196492 kb
Host smart-9e5e1b01-0de0-42a6-8783-f7ab186996c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051872856 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1051872856
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1839506319
Short name T386
Test name
Test status
Simulation time 31156860923 ps
CPU time 359.48 seconds
Started Jan 14 01:47:51 PM PST 24
Finished Jan 14 01:53:51 PM PST 24
Peak memory 198676 kb
Host smart-abea7418-4555-4abb-9d0e-92c78f4a3f82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839506319 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.1839506319
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1347954264
Short name T644
Test name
Test status
Simulation time 1645891925 ps
CPU time 47.35 seconds
Started Jan 14 01:47:52 PM PST 24
Finished Jan 14 01:48:40 PM PST 24
Peak memory 198832 kb
Host smart-6fc9f310-21b9-45a4-800d-3e9e5173dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347954264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1347954264
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3772189394
Short name T58
Test name
Test status
Simulation time 18227796 ps
CPU time 0.55 seconds
Started Jan 14 01:48:01 PM PST 24
Finished Jan 14 01:48:03 PM PST 24
Peak memory 193168 kb
Host smart-11b64f3a-57e9-4eec-8d71-0c3f723c86ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772189394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3772189394
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.505992778
Short name T445
Test name
Test status
Simulation time 2634445127 ps
CPU time 44.88 seconds
Started Jan 14 01:47:53 PM PST 24
Finished Jan 14 01:48:38 PM PST 24
Peak memory 223404 kb
Host smart-29a260a5-fab9-4090-814e-1f1b794e7b82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505992778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.505992778
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2554692774
Short name T537
Test name
Test status
Simulation time 4769657376 ps
CPU time 52.99 seconds
Started Jan 14 01:48:05 PM PST 24
Finished Jan 14 01:49:00 PM PST 24
Peak memory 198916 kb
Host smart-ae92cde6-0775-49c1-b263-dc1a8a5a9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554692774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2554692774
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3928573494
Short name T593
Test name
Test status
Simulation time 811135466 ps
CPU time 41.3 seconds
Started Jan 14 01:53:04 PM PST 24
Finished Jan 14 01:53:50 PM PST 24
Peak memory 198808 kb
Host smart-3d73fc8b-c3eb-44ee-a6bf-bc07c0b31d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928573494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3928573494
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.433470028
Short name T657
Test name
Test status
Simulation time 19246294635 ps
CPU time 82.27 seconds
Started Jan 14 01:47:59 PM PST 24
Finished Jan 14 01:49:23 PM PST 24
Peak memory 198868 kb
Host smart-c28605dd-46fe-4741-a9cd-4ea09d7f9cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433470028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.433470028
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3787574951
Short name T646
Test name
Test status
Simulation time 5896539768 ps
CPU time 53.22 seconds
Started Jan 14 01:47:53 PM PST 24
Finished Jan 14 01:48:47 PM PST 24
Peak memory 198796 kb
Host smart-a378a3fe-0156-4869-bd32-35ed0320c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787574951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3787574951
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2883844203
Short name T51
Test name
Test status
Simulation time 238327408 ps
CPU time 0.86 seconds
Started Jan 14 01:48:03 PM PST 24
Finished Jan 14 01:48:04 PM PST 24
Peak memory 215852 kb
Host smart-422f8f90-fb31-438f-b018-3f9030dd2e24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883844203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2883844203
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.529093162
Short name T608
Test name
Test status
Simulation time 363099573 ps
CPU time 2.34 seconds
Started Jan 14 01:47:55 PM PST 24
Finished Jan 14 01:47:58 PM PST 24
Peak memory 198708 kb
Host smart-73318aa8-1499-4a36-9f7f-39607d08b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529093162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.529093162
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3921195519
Short name T95
Test name
Test status
Simulation time 375914694537 ps
CPU time 1096.33 seconds
Started Jan 14 01:48:05 PM PST 24
Finished Jan 14 02:06:22 PM PST 24
Peak memory 230016 kb
Host smart-e8327276-bf15-4dc4-a1d2-8c089884e710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921195519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3921195519
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.259782897
Short name T195
Test name
Test status
Simulation time 232342829247 ps
CPU time 840.67 seconds
Started Jan 14 01:48:06 PM PST 24
Finished Jan 14 02:02:09 PM PST 24
Peak memory 214704 kb
Host smart-820a2144-4ed6-49d3-8220-525df6bc4373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259782897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.259782897
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3781218767
Short name T56
Test name
Test status
Simulation time 351122492 ps
CPU time 1.12 seconds
Started Jan 14 01:48:03 PM PST 24
Finished Jan 14 01:48:05 PM PST 24
Peak memory 197708 kb
Host smart-f1349168-5018-46e7-acf3-f1e6651e2f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781218767 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3781218767
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1359267878
Short name T305
Test name
Test status
Simulation time 28015595374 ps
CPU time 449.93 seconds
Started Jan 14 01:48:02 PM PST 24
Finished Jan 14 01:55:33 PM PST 24
Peak memory 198768 kb
Host smart-5cfc4517-8b84-4657-8202-a308346e30e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359267878 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.1359267878
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3476389518
Short name T296
Test name
Test status
Simulation time 11058121248 ps
CPU time 50 seconds
Started Jan 14 01:48:01 PM PST 24
Finished Jan 14 01:48:52 PM PST 24
Peak memory 198916 kb
Host smart-1fbddd5e-8f1d-4650-8aec-bb5d33ac5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476389518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3476389518
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2066073679
Short name T460
Test name
Test status
Simulation time 22390301 ps
CPU time 0.57 seconds
Started Jan 14 01:48:35 PM PST 24
Finished Jan 14 01:48:36 PM PST 24
Peak memory 193136 kb
Host smart-52dff394-3eb4-4c7f-9ff7-a9b3d3238580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066073679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2066073679
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.539264520
Short name T396
Test name
Test status
Simulation time 8971803029 ps
CPU time 22.6 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 211188 kb
Host smart-4caf32a3-688d-49ee-8478-f7f4371c5e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539264520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.539264520
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1021520969
Short name T456
Test name
Test status
Simulation time 1511993065 ps
CPU time 69.47 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:49:40 PM PST 24
Peak memory 198760 kb
Host smart-c0422c38-7a0c-44d3-b9d2-b360ec05b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021520969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1021520969
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1675839037
Short name T758
Test name
Test status
Simulation time 2299512565 ps
CPU time 116.4 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:50:25 PM PST 24
Peak memory 198852 kb
Host smart-675b5edf-0c53-49d8-b251-00785daee5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675839037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1675839037
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1970126052
Short name T523
Test name
Test status
Simulation time 23024227091 ps
CPU time 96.9 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198884 kb
Host smart-1388da22-7960-46ff-9b36-4dd69d65c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970126052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1970126052
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.790502860
Short name T486
Test name
Test status
Simulation time 916589969 ps
CPU time 11.31 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 01:48:39 PM PST 24
Peak memory 198808 kb
Host smart-d5ec17b7-bb13-4506-a26f-950545490e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790502860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.790502860
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.671080785
Short name T399
Test name
Test status
Simulation time 4180188055 ps
CPU time 2.98 seconds
Started Jan 14 01:48:33 PM PST 24
Finished Jan 14 01:48:36 PM PST 24
Peak memory 198864 kb
Host smart-bfcafb73-bcf6-4136-a93e-a19d24019e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671080785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.671080785
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1986501322
Short name T447
Test name
Test status
Simulation time 323627202909 ps
CPU time 1417.8 seconds
Started Jan 14 01:48:35 PM PST 24
Finished Jan 14 02:12:13 PM PST 24
Peak memory 198904 kb
Host smart-e7234343-2cb7-4d58-83e5-17ea6306c371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986501322 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1986501322
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.249921029
Short name T722
Test name
Test status
Simulation time 243171874 ps
CPU time 0.94 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:48:40 PM PST 24
Peak memory 196708 kb
Host smart-69c10afa-b84e-491c-a5ab-bbd2fffd790b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249921029 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.249921029
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.792035983
Short name T714
Test name
Test status
Simulation time 31698274131 ps
CPU time 379.13 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:54:59 PM PST 24
Peak memory 198812 kb
Host smart-341451c4-f0ab-4f7e-a728-0e810b9afd60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792035983 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_test_sha_vectors.792035983
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2239423673
Short name T612
Test name
Test status
Simulation time 2600475365 ps
CPU time 20.4 seconds
Started Jan 14 01:48:37 PM PST 24
Finished Jan 14 01:48:58 PM PST 24
Peak memory 198868 kb
Host smart-de7748ba-3eeb-4e21-8322-e77b90d9c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239423673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2239423673
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2864039257
Short name T712
Test name
Test status
Simulation time 387640534017 ps
CPU time 1685.02 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:19:39 PM PST 24
Peak memory 257332 kb
Host smart-c1ccaae2-baf0-42db-b810-8aad8d49878a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864039257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.2864039257
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.3132984153
Short name T242
Test name
Test status
Simulation time 69860127982 ps
CPU time 286.38 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 01:56:19 PM PST 24
Peak memory 215368 kb
Host smart-e3631bdd-0ba6-4a47-9175-7cecf216da98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132984153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.3132984153
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.700708538
Short name T418
Test name
Test status
Simulation time 35633504415 ps
CPU time 256.8 seconds
Started Jan 14 01:51:34 PM PST 24
Finished Jan 14 01:55:53 PM PST 24
Peak memory 215308 kb
Host smart-ca976f95-6a98-41c1-bba7-2a3796fac986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700708538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.700708538
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.333867148
Short name T96
Test name
Test status
Simulation time 78838027849 ps
CPU time 2257.37 seconds
Started Jan 14 01:51:35 PM PST 24
Finished Jan 14 02:29:14 PM PST 24
Peak memory 231180 kb
Host smart-33e75ea4-8960-4b15-9bc0-2fd10579875a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333867148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.333867148
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1181303186
Short name T605
Test name
Test status
Simulation time 81608854119 ps
CPU time 1188.4 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:11:23 PM PST 24
Peak memory 215292 kb
Host smart-2cb6ce4d-e47e-46f6-b9eb-14fd54a091fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181303186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.1181303186
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2632153690
Short name T273
Test name
Test status
Simulation time 76922619999 ps
CPU time 344.1 seconds
Started Jan 14 01:51:35 PM PST 24
Finished Jan 14 01:57:20 PM PST 24
Peak memory 215076 kb
Host smart-557d5a3d-16c7-4e43-84d6-c4f56cc2305c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632153690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.2632153690
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.2331839365
Short name T498
Test name
Test status
Simulation time 26241678434 ps
CPU time 397.18 seconds
Started Jan 14 01:51:37 PM PST 24
Finished Jan 14 01:58:16 PM PST 24
Peak memory 238592 kb
Host smart-ba5f9c24-1907-46cb-ac7d-4ae6ab8677e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331839365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.2331839365
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1730425913
Short name T748
Test name
Test status
Simulation time 130599406473 ps
CPU time 1762.19 seconds
Started Jan 14 01:51:44 PM PST 24
Finished Jan 14 02:21:07 PM PST 24
Peak memory 215300 kb
Host smart-a25fb327-9249-406f-bbc6-69d53439b5b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730425913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.1730425913
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2712982443
Short name T105
Test name
Test status
Simulation time 140411276444 ps
CPU time 2701.9 seconds
Started Jan 14 01:51:39 PM PST 24
Finished Jan 14 02:36:44 PM PST 24
Peak memory 256328 kb
Host smart-7abf425c-e813-4783-b85c-5f9ed3bb83ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712982443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.2712982443
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3439633469
Short name T697
Test name
Test status
Simulation time 464478073548 ps
CPU time 1185.06 seconds
Started Jan 14 01:51:41 PM PST 24
Finished Jan 14 02:11:28 PM PST 24
Peak memory 236836 kb
Host smart-29be2fef-057f-4f29-826f-b499b06b5700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439633469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.3439633469
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2874626644
Short name T674
Test name
Test status
Simulation time 15859215 ps
CPU time 0.56 seconds
Started Jan 14 01:48:35 PM PST 24
Finished Jan 14 01:48:37 PM PST 24
Peak memory 193248 kb
Host smart-f3a92480-9c7c-491f-85d4-ea6a41eee9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874626644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2874626644
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.740261757
Short name T733
Test name
Test status
Simulation time 6607993966 ps
CPU time 24.21 seconds
Started Jan 14 01:48:38 PM PST 24
Finished Jan 14 01:49:03 PM PST 24
Peak memory 221796 kb
Host smart-f6b16076-671b-4987-9a48-58b7ad1b6517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740261757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.740261757
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3577685073
Short name T281
Test name
Test status
Simulation time 1068285605 ps
CPU time 50.54 seconds
Started Jan 14 01:48:38 PM PST 24
Finished Jan 14 01:49:30 PM PST 24
Peak memory 198808 kb
Host smart-05963945-b728-4a78-b8f0-9e2491625734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577685073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3577685073
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.839680990
Short name T768
Test name
Test status
Simulation time 3186973626 ps
CPU time 127.4 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:50:47 PM PST 24
Peak memory 198868 kb
Host smart-71d4e232-b837-4eaa-ab2c-3eacf0349d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839680990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.839680990
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2583113925
Short name T7
Test name
Test status
Simulation time 19662931800 ps
CPU time 215.71 seconds
Started Jan 14 01:48:37 PM PST 24
Finished Jan 14 01:52:14 PM PST 24
Peak memory 198884 kb
Host smart-f74a5a59-c232-468a-9668-c057345ee369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583113925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2583113925
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1311317103
Short name T519
Test name
Test status
Simulation time 1826154408 ps
CPU time 15.36 seconds
Started Jan 14 01:48:35 PM PST 24
Finished Jan 14 01:48:51 PM PST 24
Peak memory 198772 kb
Host smart-becf6737-81fd-40b7-b5b4-d3a5e6072c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311317103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1311317103
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3930507803
Short name T549
Test name
Test status
Simulation time 129695183 ps
CPU time 3.18 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:48:43 PM PST 24
Peak memory 198792 kb
Host smart-8af4a361-1d5e-45dc-b1d1-a1fa10dd0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930507803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3930507803
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.931243735
Short name T693
Test name
Test status
Simulation time 33961232123 ps
CPU time 574.07 seconds
Started Jan 14 01:48:36 PM PST 24
Finished Jan 14 01:58:12 PM PST 24
Peak memory 228612 kb
Host smart-eb5d9f61-3bc5-4779-819a-b0432a56fcaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931243735 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.931243735
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.3938807343
Short name T221
Test name
Test status
Simulation time 93006773355 ps
CPU time 941.92 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 02:04:22 PM PST 24
Peak memory 240976 kb
Host smart-1f6489bc-9a27-4616-ae18-5f9b0bd0d5bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938807343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.3938807343
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.220336350
Short name T604
Test name
Test status
Simulation time 142320086 ps
CPU time 0.86 seconds
Started Jan 14 01:48:36 PM PST 24
Finished Jan 14 01:48:37 PM PST 24
Peak memory 195668 kb
Host smart-a3defdc7-c96c-4400-ba42-adcd7d829b50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220336350 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.220336350
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.670869997
Short name T586
Test name
Test status
Simulation time 26063470883 ps
CPU time 397.23 seconds
Started Jan 14 01:48:38 PM PST 24
Finished Jan 14 01:55:17 PM PST 24
Peak memory 198764 kb
Host smart-7c3f9751-79b1-4fc0-a3e6-58ac503f0b15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670869997 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.hmac_test_sha_vectors.670869997
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1140140419
Short name T187
Test name
Test status
Simulation time 19946382419 ps
CPU time 61.01 seconds
Started Jan 14 01:48:35 PM PST 24
Finished Jan 14 01:49:36 PM PST 24
Peak memory 198788 kb
Host smart-104a9ad5-7ddf-4fb3-adc6-f86d3c49edf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140140419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1140140419
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2161370482
Short name T452
Test name
Test status
Simulation time 26409658564 ps
CPU time 1058.8 seconds
Started Jan 14 01:51:37 PM PST 24
Finished Jan 14 02:09:19 PM PST 24
Peak memory 215392 kb
Host smart-6014bda8-b022-47d8-919a-c382e448f74a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161370482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.2161370482
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.3247351173
Short name T109
Test name
Test status
Simulation time 58415153992 ps
CPU time 233.81 seconds
Started Jan 14 01:51:38 PM PST 24
Finished Jan 14 01:55:35 PM PST 24
Peak memory 234664 kb
Host smart-47c78735-0bba-4135-ae38-d05ac2daa0b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247351173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.3247351173
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.3467816699
Short name T837
Test name
Test status
Simulation time 174921880310 ps
CPU time 838.67 seconds
Started Jan 14 01:51:41 PM PST 24
Finished Jan 14 02:05:42 PM PST 24
Peak memory 224204 kb
Host smart-af9b58e8-7210-4309-b329-eb7bed8b216b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467816699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.3467816699
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.2908622603
Short name T720
Test name
Test status
Simulation time 185610462108 ps
CPU time 1963.93 seconds
Started Jan 14 01:51:42 PM PST 24
Finished Jan 14 02:24:27 PM PST 24
Peak memory 247020 kb
Host smart-5f39e5a5-38bc-4ece-8416-7e07597ffa9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908622603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.2908622603
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.338414164
Short name T484
Test name
Test status
Simulation time 105617316243 ps
CPU time 2650.85 seconds
Started Jan 14 01:51:44 PM PST 24
Finished Jan 14 02:35:56 PM PST 24
Peak memory 243576 kb
Host smart-ee1376e5-b5f9-4f18-9b4c-d552caaacae2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338414164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.338414164
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2329935405
Short name T775
Test name
Test status
Simulation time 62599319790 ps
CPU time 1081.23 seconds
Started Jan 14 01:51:40 PM PST 24
Finished Jan 14 02:09:43 PM PST 24
Peak memory 231732 kb
Host smart-b34b6cc5-e074-4d19-9cd8-fedb2c784d54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329935405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.2329935405
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.4050840285
Short name T807
Test name
Test status
Simulation time 28697372600 ps
CPU time 179.66 seconds
Started Jan 14 01:51:41 PM PST 24
Finished Jan 14 01:54:42 PM PST 24
Peak memory 215268 kb
Host smart-6cbe85c5-a154-408e-8dce-74bd4c25e3f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050840285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.4050840285
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.979497059
Short name T598
Test name
Test status
Simulation time 38161244843 ps
CPU time 1945.01 seconds
Started Jan 14 01:51:43 PM PST 24
Finished Jan 14 02:24:09 PM PST 24
Peak memory 223496 kb
Host smart-507ce505-c640-472f-8577-8bff08073cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979497059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.979497059
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.164900700
Short name T810
Test name
Test status
Simulation time 195922051060 ps
CPU time 1686.5 seconds
Started Jan 14 01:51:39 PM PST 24
Finished Jan 14 02:19:48 PM PST 24
Peak memory 243036 kb
Host smart-10140b09-dd75-4016-ad2f-b4a828550ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164900700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.164900700
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.844505671
Short name T795
Test name
Test status
Simulation time 55107339822 ps
CPU time 2727.79 seconds
Started Jan 14 01:51:43 PM PST 24
Finished Jan 14 02:37:12 PM PST 24
Peak memory 248108 kb
Host smart-a71e89f5-187a-46fd-97ab-98b129ecd157
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844505671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.844505671
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1094294932
Short name T46
Test name
Test status
Simulation time 15801679 ps
CPU time 0.58 seconds
Started Jan 14 01:48:48 PM PST 24
Finished Jan 14 01:48:49 PM PST 24
Peak memory 193140 kb
Host smart-ae86af17-dc12-4bfa-a12d-a9fedbb6c6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094294932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1094294932
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1447099222
Short name T301
Test name
Test status
Simulation time 472963701 ps
CPU time 3.51 seconds
Started Jan 14 01:48:34 PM PST 24
Finished Jan 14 01:48:38 PM PST 24
Peak memory 198708 kb
Host smart-9eafd4c5-f036-428d-a450-535fbe0648a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447099222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1447099222
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.854055134
Short name T455
Test name
Test status
Simulation time 79352661 ps
CPU time 1.81 seconds
Started Jan 14 01:48:44 PM PST 24
Finished Jan 14 01:48:47 PM PST 24
Peak memory 198796 kb
Host smart-6442a933-bdb1-4acc-8a1f-479ccb15cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854055134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.854055134
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.70080849
Short name T359
Test name
Test status
Simulation time 1131054096 ps
CPU time 49.91 seconds
Started Jan 14 01:48:36 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 198736 kb
Host smart-de9ab4d9-29e9-4b9b-94a4-3ac016964abc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70080849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.70080849
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3467469805
Short name T659
Test name
Test status
Simulation time 4332942523 ps
CPU time 106.89 seconds
Started Jan 14 01:48:43 PM PST 24
Finished Jan 14 01:50:30 PM PST 24
Peak memory 198740 kb
Host smart-90cc0d2f-0021-4dc0-a6dc-a332291e8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467469805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3467469805
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1141453842
Short name T410
Test name
Test status
Simulation time 8165509842 ps
CPU time 99.36 seconds
Started Jan 14 01:48:39 PM PST 24
Finished Jan 14 01:50:19 PM PST 24
Peak memory 198916 kb
Host smart-e79624b5-1933-4a21-865b-b96a526cc7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141453842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1141453842
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1690882550
Short name T423
Test name
Test status
Simulation time 70463246 ps
CPU time 1.37 seconds
Started Jan 14 01:48:37 PM PST 24
Finished Jan 14 01:48:39 PM PST 24
Peak memory 198508 kb
Host smart-f766cc75-af37-4968-95b6-e6873cfb1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690882550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1690882550
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2928470615
Short name T112
Test name
Test status
Simulation time 103205961008 ps
CPU time 931.64 seconds
Started Jan 14 01:48:43 PM PST 24
Finished Jan 14 02:04:15 PM PST 24
Peak memory 198940 kb
Host smart-d2510741-b57b-45ca-990e-11bd5d64b8db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928470615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2928470615
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1198778643
Short name T432
Test name
Test status
Simulation time 57652721 ps
CPU time 1.12 seconds
Started Jan 14 01:48:50 PM PST 24
Finished Jan 14 01:48:51 PM PST 24
Peak memory 197264 kb
Host smart-a0874af1-d53e-47dd-ac3d-a61264e9ba19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198778643 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1198778643
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.4258733746
Short name T415
Test name
Test status
Simulation time 83822914959 ps
CPU time 417.98 seconds
Started Jan 14 01:48:45 PM PST 24
Finished Jan 14 01:55:44 PM PST 24
Peak memory 198772 kb
Host smart-9fa4fb07-a19d-4ce4-8836-e31048893d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258733746 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.4258733746
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.295218881
Short name T610
Test name
Test status
Simulation time 14832130519 ps
CPU time 49.79 seconds
Started Jan 14 01:48:43 PM PST 24
Finished Jan 14 01:49:33 PM PST 24
Peak memory 198924 kb
Host smart-38ff0451-6fe9-4474-9865-0b3e850ffaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295218881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.295218881
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2212789360
Short name T532
Test name
Test status
Simulation time 23390834865 ps
CPU time 453.18 seconds
Started Jan 14 01:51:42 PM PST 24
Finished Jan 14 01:59:16 PM PST 24
Peak memory 231736 kb
Host smart-6dd8afa8-8bab-4346-87ae-4689ab6ff571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212789360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2212789360
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.3491717747
Short name T200
Test name
Test status
Simulation time 432604239270 ps
CPU time 1755.17 seconds
Started Jan 14 01:51:43 PM PST 24
Finished Jan 14 02:20:59 PM PST 24
Peak memory 248128 kb
Host smart-f7c7793d-b9af-4ad3-a6e2-89870fd14b6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491717747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.3491717747
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.2436713412
Short name T40
Test name
Test status
Simulation time 189137923290 ps
CPU time 684.23 seconds
Started Jan 14 01:51:41 PM PST 24
Finished Jan 14 02:03:07 PM PST 24
Peak memory 251572 kb
Host smart-0d913016-c90b-4ba7-92c7-f81106c2a4cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436713412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.2436713412
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.3806230434
Short name T496
Test name
Test status
Simulation time 338454524126 ps
CPU time 4026.2 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:58:56 PM PST 24
Peak memory 231792 kb
Host smart-f4195def-afcc-4e2b-b7da-784fdfc51d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806230434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.3806230434
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.3902088671
Short name T701
Test name
Test status
Simulation time 18116941773 ps
CPU time 629.81 seconds
Started Jan 14 01:51:41 PM PST 24
Finished Jan 14 02:02:13 PM PST 24
Peak memory 240384 kb
Host smart-5cfe899f-481e-465e-a65a-35f64efd213a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902088671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.3902088671
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.1368912098
Short name T624
Test name
Test status
Simulation time 202571770207 ps
CPU time 2217.37 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:28:47 PM PST 24
Peak memory 241956 kb
Host smart-96b051f6-4695-426e-8d53-10a3d2d93aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368912098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.1368912098
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.410170962
Short name T194
Test name
Test status
Simulation time 50361677022 ps
CPU time 761.64 seconds
Started Jan 14 01:51:47 PM PST 24
Finished Jan 14 02:04:30 PM PST 24
Peak memory 223596 kb
Host smart-948cc768-a7ea-48aa-aa92-d88f41c4ade4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410170962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.410170962
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.2620378125
Short name T606
Test name
Test status
Simulation time 28311845428 ps
CPU time 549.51 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:00:59 PM PST 24
Peak memory 228624 kb
Host smart-8a247e47-a0ee-4277-8a97-080a795a8dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2620378125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.2620378125
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.1640789969
Short name T508
Test name
Test status
Simulation time 84283235266 ps
CPU time 1636.58 seconds
Started Jan 14 01:51:39 PM PST 24
Finished Jan 14 02:18:59 PM PST 24
Peak memory 239964 kb
Host smart-c9d552a6-6fb7-448e-88c5-7a821e9b6089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640789969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.1640789969
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4200970533
Short name T797
Test name
Test status
Simulation time 17025022 ps
CPU time 0.58 seconds
Started Jan 14 01:48:43 PM PST 24
Finished Jan 14 01:48:45 PM PST 24
Peak memory 193196 kb
Host smart-24c8c8e3-9404-4b8a-8f33-254fd5c19c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200970533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4200970533
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2754702417
Short name T805
Test name
Test status
Simulation time 3353268570 ps
CPU time 40.99 seconds
Started Jan 14 01:48:47 PM PST 24
Finished Jan 14 01:49:28 PM PST 24
Peak memory 226416 kb
Host smart-4c57b856-70ea-4649-b907-503d52f54bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754702417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2754702417
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4046961615
Short name T9
Test name
Test status
Simulation time 707274019 ps
CPU time 8.08 seconds
Started Jan 14 01:48:44 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 198804 kb
Host smart-1fcb5b01-04da-4075-91c0-41558a6fab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046961615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4046961615
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2129122429
Short name T596
Test name
Test status
Simulation time 27179133023 ps
CPU time 96.06 seconds
Started Jan 14 01:48:48 PM PST 24
Finished Jan 14 01:50:24 PM PST 24
Peak memory 198832 kb
Host smart-2daca185-bb3a-46fe-95fb-99cc3d485508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129122429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2129122429
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2604161976
Short name T328
Test name
Test status
Simulation time 4015972774 ps
CPU time 50.34 seconds
Started Jan 14 01:48:53 PM PST 24
Finished Jan 14 01:49:44 PM PST 24
Peak memory 198748 kb
Host smart-0c833a27-7601-41a4-8981-a0d8f69be5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604161976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2604161976
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1262371901
Short name T780
Test name
Test status
Simulation time 15233096628 ps
CPU time 68.68 seconds
Started Jan 14 01:48:53 PM PST 24
Finished Jan 14 01:50:02 PM PST 24
Peak memory 198884 kb
Host smart-383b09f9-61fd-4817-9a08-3326b63701ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262371901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1262371901
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1786422493
Short name T678
Test name
Test status
Simulation time 264925862 ps
CPU time 3.01 seconds
Started Jan 14 01:48:45 PM PST 24
Finished Jan 14 01:48:49 PM PST 24
Peak memory 198696 kb
Host smart-6ad20dca-4a82-49d5-8285-3ac22761486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786422493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1786422493
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.361208512
Short name T779
Test name
Test status
Simulation time 68600070153 ps
CPU time 1128.51 seconds
Started Jan 14 01:48:49 PM PST 24
Finished Jan 14 02:07:38 PM PST 24
Peak memory 198848 kb
Host smart-ed382ff5-9253-4cbd-a1d5-d93515098406
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361208512 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.361208512
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.1971793374
Short name T696
Test name
Test status
Simulation time 6773968634 ps
CPU time 70.02 seconds
Started Jan 14 01:48:49 PM PST 24
Finished Jan 14 01:50:00 PM PST 24
Peak memory 214760 kb
Host smart-5a5f2fd9-cedb-4350-8962-5229ce076f25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971793374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.1971793374
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2816134917
Short name T477
Test name
Test status
Simulation time 239798700 ps
CPU time 1.11 seconds
Started Jan 14 01:48:48 PM PST 24
Finished Jan 14 01:48:50 PM PST 24
Peak memory 197324 kb
Host smart-48206be9-79b3-4acf-a9c8-60c95cc72b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816134917 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2816134917
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2983594148
Short name T244
Test name
Test status
Simulation time 49998475150 ps
CPU time 501.9 seconds
Started Jan 14 01:48:44 PM PST 24
Finished Jan 14 01:57:07 PM PST 24
Peak memory 198804 kb
Host smart-db3e7fbc-cd55-4f24-9892-e9054a6225df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983594148 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.2983594148
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2579943193
Short name T8
Test name
Test status
Simulation time 2194145565 ps
CPU time 25.61 seconds
Started Jan 14 01:48:45 PM PST 24
Finished Jan 14 01:49:11 PM PST 24
Peak memory 198796 kb
Host smart-f94f2a18-f7df-48ba-945f-9bb86f71c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579943193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2579943193
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.576213680
Short name T766
Test name
Test status
Simulation time 68313181841 ps
CPU time 3608.09 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:51:57 PM PST 24
Peak memory 248144 kb
Host smart-8c5f525c-cdbd-4a0b-9abc-aeb94d98436f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576213680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.576213680
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.2335102070
Short name T835
Test name
Test status
Simulation time 881074932475 ps
CPU time 990.97 seconds
Started Jan 14 01:51:49 PM PST 24
Finished Jan 14 02:08:21 PM PST 24
Peak memory 231752 kb
Host smart-aa64b3d5-ea07-4f6c-8915-ac1bb009642c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335102070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.2335102070
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.57405342
Short name T527
Test name
Test status
Simulation time 29066532244 ps
CPU time 414.07 seconds
Started Jan 14 01:51:45 PM PST 24
Finished Jan 14 01:58:40 PM PST 24
Peak memory 247384 kb
Host smart-c635ca1c-bbaf-48b5-92ea-12d75909a5fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57405342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.57405342
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.414812327
Short name T675
Test name
Test status
Simulation time 260249226671 ps
CPU time 3004.94 seconds
Started Jan 14 01:51:46 PM PST 24
Finished Jan 14 02:41:52 PM PST 24
Peak memory 256220 kb
Host smart-cfa11e3f-a61c-4907-87a1-3d11dffb0ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414812327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.414812327
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.299872375
Short name T116
Test name
Test status
Simulation time 62700023870 ps
CPU time 2439.51 seconds
Started Jan 14 01:51:46 PM PST 24
Finished Jan 14 02:32:27 PM PST 24
Peak memory 239972 kb
Host smart-9d83dad6-27ac-4da9-8ae3-86a7210ecb13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299872375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.299872375
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.4170277701
Short name T115
Test name
Test status
Simulation time 87535229919 ps
CPU time 1039.58 seconds
Started Jan 14 01:51:46 PM PST 24
Finished Jan 14 02:09:06 PM PST 24
Peak memory 247988 kb
Host smart-833bbcf0-3bf0-4333-8e17-b93c27296877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170277701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.4170277701
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2958181087
Short name T688
Test name
Test status
Simulation time 15329475 ps
CPU time 0.55 seconds
Started Jan 14 01:48:51 PM PST 24
Finished Jan 14 01:48:52 PM PST 24
Peak memory 193164 kb
Host smart-5680e502-35fe-4174-b594-96c9790100f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958181087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2958181087
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1853637654
Short name T738
Test name
Test status
Simulation time 528131409 ps
CPU time 16.81 seconds
Started Jan 14 01:48:44 PM PST 24
Finished Jan 14 01:49:02 PM PST 24
Peak memory 211672 kb
Host smart-ceaf1d00-57ef-48fa-b38f-e1a44d21a909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853637654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1853637654
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.721229230
Short name T772
Test name
Test status
Simulation time 522935592 ps
CPU time 7.07 seconds
Started Jan 14 01:48:52 PM PST 24
Finished Jan 14 01:49:00 PM PST 24
Peak memory 198784 kb
Host smart-600ccbc6-2ced-49f6-92c9-f34d549731ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721229230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.721229230
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2879857326
Short name T257
Test name
Test status
Simulation time 1466354293 ps
CPU time 38.17 seconds
Started Jan 14 01:48:48 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 198792 kb
Host smart-9c895886-6109-4baa-8ee8-91eeaab34ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879857326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2879857326
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3923646337
Short name T54
Test name
Test status
Simulation time 5109064907 ps
CPU time 134.19 seconds
Started Jan 14 01:48:51 PM PST 24
Finished Jan 14 01:51:05 PM PST 24
Peak memory 198864 kb
Host smart-b2af9b48-5dab-45e6-8c26-e38253e02208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923646337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3923646337
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.120100020
Short name T746
Test name
Test status
Simulation time 16658890940 ps
CPU time 73.8 seconds
Started Jan 14 01:48:43 PM PST 24
Finished Jan 14 01:49:57 PM PST 24
Peak memory 198900 kb
Host smart-28a8d173-264d-4577-bc3f-0764353f5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120100020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.120100020
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1104740398
Short name T622
Test name
Test status
Simulation time 229067063 ps
CPU time 2.83 seconds
Started Jan 14 01:48:44 PM PST 24
Finished Jan 14 01:48:48 PM PST 24
Peak memory 198760 kb
Host smart-abac503e-1424-4eec-81c5-8991cf54829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104740398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1104740398
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.37850573
Short name T225
Test name
Test status
Simulation time 199900420615 ps
CPU time 567.48 seconds
Started Jan 14 01:49:01 PM PST 24
Finished Jan 14 01:58:29 PM PST 24
Peak memory 216276 kb
Host smart-4fc878bd-106c-4f4a-86e5-418438f61520
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850573 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.37850573
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.3302121096
Short name T765
Test name
Test status
Simulation time 124401575161 ps
CPU time 1003.94 seconds
Started Jan 14 01:49:00 PM PST 24
Finished Jan 14 02:05:45 PM PST 24
Peak memory 239908 kb
Host smart-22e7c830-1f48-43dc-84cc-537522dd0455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302121096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.3302121096
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2697717413
Short name T671
Test name
Test status
Simulation time 32841860 ps
CPU time 1.11 seconds
Started Jan 14 01:49:04 PM PST 24
Finished Jan 14 01:49:06 PM PST 24
Peak memory 196864 kb
Host smart-3430ca3f-691b-43fb-b074-574953a66104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697717413 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2697717413
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1383732758
Short name T528
Test name
Test status
Simulation time 40674284209 ps
CPU time 463.02 seconds
Started Jan 14 01:48:55 PM PST 24
Finished Jan 14 01:56:39 PM PST 24
Peak memory 198760 kb
Host smart-4bf8d25f-f828-4423-9422-ac1e75decf02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383732758 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.1383732758
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.624527437
Short name T700
Test name
Test status
Simulation time 1021807401 ps
CPU time 31.91 seconds
Started Jan 14 01:48:48 PM PST 24
Finished Jan 14 01:49:21 PM PST 24
Peak memory 198808 kb
Host smart-3081ab22-94ff-405f-a234-d7fdf67d0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624527437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.624527437
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.3132000030
Short name T529
Test name
Test status
Simulation time 448933381091 ps
CPU time 2029.24 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:25:38 PM PST 24
Peak memory 230428 kb
Host smart-daee8b5a-bf15-46df-b299-0af420a5d388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132000030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.3132000030
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.4199093232
Short name T405
Test name
Test status
Simulation time 136937872840 ps
CPU time 1322.67 seconds
Started Jan 14 01:51:47 PM PST 24
Finished Jan 14 02:13:51 PM PST 24
Peak memory 255516 kb
Host smart-e808bead-2488-4eeb-a5f7-92bbe1470f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199093232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.4199093232
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.2982220186
Short name T344
Test name
Test status
Simulation time 64970921980 ps
CPU time 1269.73 seconds
Started Jan 14 01:51:48 PM PST 24
Finished Jan 14 02:12:59 PM PST 24
Peak memory 256176 kb
Host smart-e2b502c1-a084-44f1-b451-5ed5846ca468
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982220186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.2982220186
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.2599914118
Short name T673
Test name
Test status
Simulation time 443486478236 ps
CPU time 3044.22 seconds
Started Jan 14 01:51:46 PM PST 24
Finished Jan 14 02:42:32 PM PST 24
Peak memory 272384 kb
Host smart-c32a427d-efb3-486f-976a-3e291496c2f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599914118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.2599914118
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.667047161
Short name T203
Test name
Test status
Simulation time 27808713674 ps
CPU time 1231.21 seconds
Started Jan 14 01:52:04 PM PST 24
Finished Jan 14 02:12:36 PM PST 24
Peak memory 247400 kb
Host smart-eb8b4048-1380-4c78-8806-4f6334a79103
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667047161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.667047161
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.3654852407
Short name T354
Test name
Test status
Simulation time 241940596303 ps
CPU time 867.73 seconds
Started Jan 14 01:51:58 PM PST 24
Finished Jan 14 02:06:27 PM PST 24
Peak memory 215324 kb
Host smart-052c3905-40f3-40af-8473-43d1f8ae834d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654852407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.3654852407
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.20881353
Short name T852
Test name
Test status
Simulation time 33412649712 ps
CPU time 1698.73 seconds
Started Jan 14 01:51:58 PM PST 24
Finished Jan 14 02:20:18 PM PST 24
Peak memory 233736 kb
Host smart-7d38de91-9462-4af8-911c-cb62d95e374d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20881353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.20881353
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.3345687511
Short name T102
Test name
Test status
Simulation time 484365872552 ps
CPU time 4237.13 seconds
Started Jan 14 01:52:06 PM PST 24
Finished Jan 14 03:02:44 PM PST 24
Peak memory 257816 kb
Host smart-9955558e-ba7e-4d72-bc01-2cb66a9c53af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345687511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.3345687511
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1005135465
Short name T642
Test name
Test status
Simulation time 310640818639 ps
CPU time 2892.57 seconds
Started Jan 14 01:52:03 PM PST 24
Finished Jan 14 02:40:17 PM PST 24
Peak memory 256188 kb
Host smart-a060d004-a3cf-4868-ad35-62e36c9b8644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005135465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1005135465
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2118776285
Short name T747
Test name
Test status
Simulation time 13043502 ps
CPU time 0.58 seconds
Started Jan 14 01:48:57 PM PST 24
Finished Jan 14 01:48:58 PM PST 24
Peak memory 193200 kb
Host smart-8ef7e572-bdd8-4992-9f99-a771c9fd640d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118776285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2118776285
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.676304413
Short name T817
Test name
Test status
Simulation time 7683550649 ps
CPU time 49.05 seconds
Started Jan 14 01:48:56 PM PST 24
Finished Jan 14 01:49:46 PM PST 24
Peak memory 215144 kb
Host smart-c111f73b-3979-4b34-9dd4-41cd115f1c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676304413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.676304413
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3270008738
Short name T822
Test name
Test status
Simulation time 1440851086 ps
CPU time 12.72 seconds
Started Jan 14 01:48:56 PM PST 24
Finished Jan 14 01:49:09 PM PST 24
Peak memory 198832 kb
Host smart-5b4e51c5-3024-4137-82a9-cd44ae1848af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270008738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3270008738
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2287298300
Short name T271
Test name
Test status
Simulation time 18815615878 ps
CPU time 80.91 seconds
Started Jan 14 01:48:59 PM PST 24
Finished Jan 14 01:50:21 PM PST 24
Peak memory 198832 kb
Host smart-b09e7f25-398d-433c-989b-71d8d5a1bf61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287298300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2287298300
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3785508402
Short name T655
Test name
Test status
Simulation time 80896435006 ps
CPU time 107.68 seconds
Started Jan 14 01:48:52 PM PST 24
Finished Jan 14 01:50:40 PM PST 24
Peak memory 198808 kb
Host smart-35ea5659-4ed9-4b69-98ae-22c3e9c5acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785508402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3785508402
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.896301433
Short name T323
Test name
Test status
Simulation time 3856505542 ps
CPU time 13.86 seconds
Started Jan 14 01:48:57 PM PST 24
Finished Jan 14 01:49:11 PM PST 24
Peak memory 198868 kb
Host smart-5bcd3207-681f-4f3c-bef6-e86b63f267a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896301433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.896301433
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.312381235
Short name T561
Test name
Test status
Simulation time 430315889 ps
CPU time 1.35 seconds
Started Jan 14 01:48:58 PM PST 24
Finished Jan 14 01:49:00 PM PST 24
Peak memory 198200 kb
Host smart-59b4da2e-05ba-432b-b46a-0ac31968f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312381235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.312381235
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1576995186
Short name T538
Test name
Test status
Simulation time 159130785217 ps
CPU time 2148.02 seconds
Started Jan 14 01:49:03 PM PST 24
Finished Jan 14 02:24:51 PM PST 24
Peak memory 230260 kb
Host smart-254605b2-1229-4ac6-bea1-267345c20dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576995186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1576995186
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2845260025
Short name T717
Test name
Test status
Simulation time 52355840403 ps
CPU time 1223.85 seconds
Started Jan 14 01:48:59 PM PST 24
Finished Jan 14 02:09:23 PM PST 24
Peak memory 256364 kb
Host smart-b3e8e8ff-15f9-4516-a99f-e56a6ac7fcd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845260025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2845260025
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3432965931
Short name T602
Test name
Test status
Simulation time 119408881 ps
CPU time 0.93 seconds
Started Jan 14 01:48:56 PM PST 24
Finished Jan 14 01:48:57 PM PST 24
Peak memory 196768 kb
Host smart-132d8a0e-59ab-4cf5-abcd-124dc7bb4bc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432965931 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3432965931
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.861313391
Short name T550
Test name
Test status
Simulation time 8445542636 ps
CPU time 363.62 seconds
Started Jan 14 01:48:53 PM PST 24
Finished Jan 14 01:54:57 PM PST 24
Peak memory 198844 kb
Host smart-8d297580-6175-41c7-ada1-24f2987d2c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861313391 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.hmac_test_sha_vectors.861313391
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2844339790
Short name T384
Test name
Test status
Simulation time 19680649647 ps
CPU time 71.5 seconds
Started Jan 14 01:48:59 PM PST 24
Finished Jan 14 01:50:12 PM PST 24
Peak memory 198872 kb
Host smart-4329c54f-e7c5-43c7-a6ae-b4ae7559e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844339790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2844339790
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.4249554106
Short name T576
Test name
Test status
Simulation time 267958985601 ps
CPU time 996.67 seconds
Started Jan 14 01:52:02 PM PST 24
Finished Jan 14 02:08:39 PM PST 24
Peak memory 223576 kb
Host smart-0d7f40dd-8cf4-4793-be3f-02c50d1096db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249554106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.4249554106
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.3357883636
Short name T735
Test name
Test status
Simulation time 138086635142 ps
CPU time 2392.03 seconds
Started Jan 14 01:52:01 PM PST 24
Finished Jan 14 02:31:54 PM PST 24
Peak memory 262456 kb
Host smart-3d85f965-d52d-460c-b764-b0b9420656cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357883636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.3357883636
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.3718217822
Short name T827
Test name
Test status
Simulation time 29777169659 ps
CPU time 466.02 seconds
Started Jan 14 01:52:08 PM PST 24
Finished Jan 14 01:59:55 PM PST 24
Peak memory 223572 kb
Host smart-c0360a0b-4b9b-402d-9207-d9471cbf79bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718217822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.3718217822
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3306617753
Short name T100
Test name
Test status
Simulation time 287639441759 ps
CPU time 2824.62 seconds
Started Jan 14 01:52:00 PM PST 24
Finished Jan 14 02:39:06 PM PST 24
Peak memory 261052 kb
Host smart-660756ae-adee-49a4-8285-6a38bc2d41c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306617753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.3306617753
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.341008392
Short name T507
Test name
Test status
Simulation time 138606227661 ps
CPU time 1903.85 seconds
Started Jan 14 01:52:01 PM PST 24
Finished Jan 14 02:23:46 PM PST 24
Peak memory 244228 kb
Host smart-73742879-6444-4ab1-9f36-8a45d8e7502d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341008392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.341008392
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.1203492992
Short name T333
Test name
Test status
Simulation time 230919048433 ps
CPU time 1166.41 seconds
Started Jan 14 01:52:07 PM PST 24
Finished Jan 14 02:11:35 PM PST 24
Peak memory 242100 kb
Host smart-842b6657-fb51-48f0-86da-5f917a839e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203492992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.1203492992
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.2415536178
Short name T358
Test name
Test status
Simulation time 284277486584 ps
CPU time 1390.5 seconds
Started Jan 14 01:52:09 PM PST 24
Finished Jan 14 02:15:20 PM PST 24
Peak memory 248104 kb
Host smart-500351f2-9249-4d1d-9922-08d21f92db13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415536178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.2415536178
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.2828074980
Short name T804
Test name
Test status
Simulation time 262794006617 ps
CPU time 1175 seconds
Started Jan 14 01:52:07 PM PST 24
Finished Jan 14 02:11:44 PM PST 24
Peak memory 230632 kb
Host smart-2fccf572-c88b-4e3f-a228-4dc46479b893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828074980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.2828074980
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.1763248239
Short name T660
Test name
Test status
Simulation time 34725027352 ps
CPU time 633.85 seconds
Started Jan 14 01:52:13 PM PST 24
Finished Jan 14 02:02:48 PM PST 24
Peak memory 231000 kb
Host smart-51171713-27ed-426d-8b8a-9b5d22cd956e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763248239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.1763248239
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4267059126
Short name T825
Test name
Test status
Simulation time 41593043 ps
CPU time 0.55 seconds
Started Jan 14 01:49:04 PM PST 24
Finished Jan 14 01:49:06 PM PST 24
Peak memory 193168 kb
Host smart-cff7e94b-05f6-44c9-ae94-e0060acb955e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267059126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4267059126
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4098281828
Short name T263
Test name
Test status
Simulation time 1317215107 ps
CPU time 39.08 seconds
Started Jan 14 01:48:53 PM PST 24
Finished Jan 14 01:49:33 PM PST 24
Peak memory 213572 kb
Host smart-998756f7-67c9-49de-8d16-1de524389fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098281828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4098281828
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1886353709
Short name T854
Test name
Test status
Simulation time 2750861494 ps
CPU time 28.76 seconds
Started Jan 14 01:48:53 PM PST 24
Finished Jan 14 01:49:22 PM PST 24
Peak memory 198884 kb
Host smart-5c7995e7-7512-40d5-ba1e-e92e8438af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886353709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1886353709
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2479033877
Short name T341
Test name
Test status
Simulation time 4340821566 ps
CPU time 54.32 seconds
Started Jan 14 01:48:58 PM PST 24
Finished Jan 14 01:49:53 PM PST 24
Peak memory 198924 kb
Host smart-a5156f83-30e2-4d37-b3b5-c37b33b2e80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479033877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2479033877
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3625699931
Short name T571
Test name
Test status
Simulation time 799887319 ps
CPU time 37.62 seconds
Started Jan 14 01:48:58 PM PST 24
Finished Jan 14 01:49:37 PM PST 24
Peak memory 198840 kb
Host smart-12313d66-7841-475f-9308-8ae391919a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625699931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3625699931
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2223884216
Short name T848
Test name
Test status
Simulation time 1321239394 ps
CPU time 68.14 seconds
Started Jan 14 01:49:06 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198804 kb
Host smart-8ad67342-ba4b-452b-8a74-c26bf3c68d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223884216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2223884216
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2712248296
Short name T398
Test name
Test status
Simulation time 604466096 ps
CPU time 3.97 seconds
Started Jan 14 01:48:59 PM PST 24
Finished Jan 14 01:49:04 PM PST 24
Peak memory 198712 kb
Host smart-1da06130-5747-4625-bc13-46dc1a752f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712248296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2712248296
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3507983415
Short name T10
Test name
Test status
Simulation time 150725614594 ps
CPU time 481.7 seconds
Started Jan 14 01:48:58 PM PST 24
Finished Jan 14 01:57:01 PM PST 24
Peak memory 198888 kb
Host smart-7cffce35-a735-4f87-be61-04d4897d6ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507983415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3507983415
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.255672880
Short name T459
Test name
Test status
Simulation time 40945827727 ps
CPU time 301.95 seconds
Started Jan 14 01:49:00 PM PST 24
Finished Jan 14 01:54:03 PM PST 24
Peak memory 215288 kb
Host smart-debf973d-c55d-4333-b397-70e999964d78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255672880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.255672880
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3212320589
Short name T388
Test name
Test status
Simulation time 291643539 ps
CPU time 1.08 seconds
Started Jan 14 01:48:57 PM PST 24
Finished Jan 14 01:48:58 PM PST 24
Peak memory 197484 kb
Host smart-41a10013-5e79-4d8d-950f-e3d6f4c6bafb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212320589 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3212320589
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2780738288
Short name T413
Test name
Test status
Simulation time 36743157685 ps
CPU time 409.52 seconds
Started Jan 14 01:48:55 PM PST 24
Finished Jan 14 01:55:45 PM PST 24
Peak memory 198760 kb
Host smart-3c9f5721-d43b-46b5-8eec-734deb4f70b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780738288 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.2780738288
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3384638917
Short name T349
Test name
Test status
Simulation time 3047670026 ps
CPU time 24.62 seconds
Started Jan 14 01:48:58 PM PST 24
Finished Jan 14 01:49:23 PM PST 24
Peak memory 198876 kb
Host smart-89be420e-3a7e-477e-bccc-9af266a502ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384638917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3384638917
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1570940691
Short name T198
Test name
Test status
Simulation time 117230703301 ps
CPU time 444.65 seconds
Started Jan 14 01:52:00 PM PST 24
Finished Jan 14 01:59:25 PM PST 24
Peak memory 214812 kb
Host smart-201e3800-0db2-452d-9ad7-9c354682c384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570940691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.1570940691
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.951054280
Short name T320
Test name
Test status
Simulation time 469091292847 ps
CPU time 2239.98 seconds
Started Jan 14 01:52:06 PM PST 24
Finished Jan 14 02:29:26 PM PST 24
Peak memory 231776 kb
Host smart-91018550-798c-4fff-94a2-f4307291db77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951054280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.951054280
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.2937142206
Short name T397
Test name
Test status
Simulation time 898315512157 ps
CPU time 624.01 seconds
Started Jan 14 01:52:10 PM PST 24
Finished Jan 14 02:02:35 PM PST 24
Peak memory 230908 kb
Host smart-1c64db16-ff3a-4c84-810c-39e5e66d5e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937142206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.2937142206
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.917152192
Short name T853
Test name
Test status
Simulation time 125267261473 ps
CPU time 1085.17 seconds
Started Jan 14 01:52:11 PM PST 24
Finished Jan 14 02:10:17 PM PST 24
Peak memory 256332 kb
Host smart-8ef33ed6-8220-4e82-a8d8-6c533f749990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917152192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.917152192
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.88250621
Short name T87
Test name
Test status
Simulation time 97061503445 ps
CPU time 2475.63 seconds
Started Jan 14 01:52:09 PM PST 24
Finished Jan 14 02:33:26 PM PST 24
Peak memory 248116 kb
Host smart-29f0bbaa-8aa8-4a05-b603-2d4feb09da20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88250621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.88250621
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.516378095
Short name T322
Test name
Test status
Simulation time 67240470545 ps
CPU time 869.14 seconds
Started Jan 14 01:52:08 PM PST 24
Finished Jan 14 02:06:39 PM PST 24
Peak memory 215320 kb
Host smart-baff5932-2b15-4aad-ae5a-944b00f040af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516378095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.516378095
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.2673721368
Short name T727
Test name
Test status
Simulation time 27279904260 ps
CPU time 431.27 seconds
Started Jan 14 01:52:03 PM PST 24
Finished Jan 14 01:59:15 PM PST 24
Peak memory 214996 kb
Host smart-1dddcefb-637d-464a-8803-d02e603c2dde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673721368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.2673721368
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.1860015805
Short name T715
Test name
Test status
Simulation time 30685708252 ps
CPU time 131.07 seconds
Started Jan 14 01:52:04 PM PST 24
Finished Jan 14 01:54:15 PM PST 24
Peak memory 234732 kb
Host smart-f7c0dcde-a3e7-4c44-b180-5311629d4e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860015805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.1860015805
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3293256146
Short name T651
Test name
Test status
Simulation time 12788653 ps
CPU time 0.57 seconds
Started Jan 14 01:49:06 PM PST 24
Finished Jan 14 01:49:07 PM PST 24
Peak memory 193268 kb
Host smart-9664aa0f-7d82-4540-a40b-3866cbb02c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293256146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3293256146
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3107938730
Short name T32
Test name
Test status
Simulation time 681369270 ps
CPU time 22.23 seconds
Started Jan 14 01:49:10 PM PST 24
Finished Jan 14 01:49:33 PM PST 24
Peak memory 215192 kb
Host smart-d76e1522-fe8b-4b4d-9018-4722fb54db17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107938730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3107938730
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3809415570
Short name T259
Test name
Test status
Simulation time 7828431611 ps
CPU time 23.77 seconds
Started Jan 14 01:49:10 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 198868 kb
Host smart-77ab1f8e-f185-429d-ada4-689012825cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809415570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3809415570
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3110593345
Short name T471
Test name
Test status
Simulation time 794776872 ps
CPU time 40.34 seconds
Started Jan 14 01:49:05 PM PST 24
Finished Jan 14 01:49:46 PM PST 24
Peak memory 198808 kb
Host smart-a0372002-3963-4ae4-98a1-90cb1c92288f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110593345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3110593345
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.741405876
Short name T363
Test name
Test status
Simulation time 36419578824 ps
CPU time 117.66 seconds
Started Jan 14 01:49:03 PM PST 24
Finished Jan 14 01:51:02 PM PST 24
Peak memory 198884 kb
Host smart-eaeb6e2b-0a20-4f70-979c-cd894b2f141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741405876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.741405876
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.327712014
Short name T514
Test name
Test status
Simulation time 1625382149 ps
CPU time 41.6 seconds
Started Jan 14 01:49:05 PM PST 24
Finished Jan 14 01:49:48 PM PST 24
Peak memory 198816 kb
Host smart-8f26815b-8003-434a-a649-e0cace0aef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327712014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.327712014
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.4166276463
Short name T756
Test name
Test status
Simulation time 159671178 ps
CPU time 2.01 seconds
Started Jan 14 01:49:01 PM PST 24
Finished Jan 14 01:49:04 PM PST 24
Peak memory 198624 kb
Host smart-30cc00bd-4a14-494a-a4fb-73c75d55c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166276463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4166276463
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3617969097
Short name T223
Test name
Test status
Simulation time 16495302409 ps
CPU time 407.92 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:56:00 PM PST 24
Peak memory 198860 kb
Host smart-8895c8ac-8e91-46a9-9e51-c1c0c3b516e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617969097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3617969097
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.3933640046
Short name T248
Test name
Test status
Simulation time 77649019454 ps
CPU time 1036.06 seconds
Started Jan 14 01:49:04 PM PST 24
Finished Jan 14 02:06:21 PM PST 24
Peak memory 223552 kb
Host smart-df0878e9-f7c3-4fe1-aa2b-09294c8e3e77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933640046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.3933640046
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.431725613
Short name T734
Test name
Test status
Simulation time 211448076 ps
CPU time 1.21 seconds
Started Jan 14 01:49:05 PM PST 24
Finished Jan 14 01:49:06 PM PST 24
Peak memory 196932 kb
Host smart-5a78ca3f-1e44-4dd2-bc4a-132abf600c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431725613 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.431725613
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1128502282
Short name T294
Test name
Test status
Simulation time 120569480091 ps
CPU time 506.52 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:57:38 PM PST 24
Peak memory 198824 kb
Host smart-c43c055e-566c-4c64-b0f8-bd61086aac70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128502282 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.1128502282
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.318974577
Short name T302
Test name
Test status
Simulation time 26445068316 ps
CPU time 77.7 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:50:29 PM PST 24
Peak memory 198848 kb
Host smart-2fddb9f8-acd4-4645-aecd-71f8b3fed2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318974577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.318974577
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1730185800
Short name T55
Test name
Test status
Simulation time 109690534803 ps
CPU time 1003.96 seconds
Started Jan 14 01:52:06 PM PST 24
Finished Jan 14 02:08:51 PM PST 24
Peak memory 240376 kb
Host smart-660cd439-422a-4dbd-8449-d68f94e27059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730185800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.1730185800
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.3201048651
Short name T213
Test name
Test status
Simulation time 58000829171 ps
CPU time 211.44 seconds
Started Jan 14 01:52:08 PM PST 24
Finished Jan 14 01:55:41 PM PST 24
Peak memory 213676 kb
Host smart-f8446005-37a4-44a8-83af-467cfea45350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201048651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.3201048651
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.714066473
Short name T500
Test name
Test status
Simulation time 205360295547 ps
CPU time 616.62 seconds
Started Jan 14 01:52:11 PM PST 24
Finished Jan 14 02:02:28 PM PST 24
Peak memory 223560 kb
Host smart-09a41c67-e0df-4fab-b35b-5869a7a1408a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714066473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.714066473
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.3130662352
Short name T711
Test name
Test status
Simulation time 109721983508 ps
CPU time 895.37 seconds
Started Jan 14 01:52:09 PM PST 24
Finished Jan 14 02:07:05 PM PST 24
Peak memory 236884 kb
Host smart-25e7529d-30cc-4244-a262-c9ebe040a1ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130662352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.3130662352
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.1518829611
Short name T43
Test name
Test status
Simulation time 115134115832 ps
CPU time 1241.82 seconds
Started Jan 14 01:52:05 PM PST 24
Finished Jan 14 02:12:47 PM PST 24
Peak memory 248156 kb
Host smart-ca33f27c-583a-44d9-bb9a-62c92aa31c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518829611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.1518829611
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3443037161
Short name T438
Test name
Test status
Simulation time 90443657013 ps
CPU time 745.3 seconds
Started Jan 14 01:52:09 PM PST 24
Finished Jan 14 02:04:35 PM PST 24
Peak memory 215312 kb
Host smart-033c8994-3b06-4867-bcbd-e27ad16d1163
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443037161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.3443037161
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.2185587181
Short name T406
Test name
Test status
Simulation time 139352156968 ps
CPU time 264.48 seconds
Started Jan 14 01:52:05 PM PST 24
Finished Jan 14 01:56:30 PM PST 24
Peak memory 213232 kb
Host smart-cce1ebd7-2c8d-4ee8-a600-e935cc2f307c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185587181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.2185587181
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.3740749574
Short name T662
Test name
Test status
Simulation time 221801057179 ps
CPU time 223.24 seconds
Started Jan 14 01:52:10 PM PST 24
Finished Jan 14 01:55:54 PM PST 24
Peak memory 214588 kb
Host smart-6c4ee584-1528-47ff-b468-c71ad5e21f0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740749574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.3740749574
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2963689216
Short name T808
Test name
Test status
Simulation time 69394612839 ps
CPU time 871.38 seconds
Started Jan 14 01:52:04 PM PST 24
Finished Jan 14 02:06:37 PM PST 24
Peak memory 210392 kb
Host smart-f287a41d-b1ae-41d3-81c0-f5572cee41c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963689216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2963689216
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.1226397372
Short name T414
Test name
Test status
Simulation time 123494162946 ps
CPU time 385.78 seconds
Started Jan 14 01:52:08 PM PST 24
Finished Jan 14 01:58:35 PM PST 24
Peak memory 244976 kb
Host smart-b2b16b2e-e7a5-45e4-b88e-cbd9cfe559f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226397372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.1226397372
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3811078497
Short name T374
Test name
Test status
Simulation time 14366224 ps
CPU time 0.57 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:13 PM PST 24
Peak memory 193140 kb
Host smart-8db5567c-43c3-4fc8-8f7d-ae759284289d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811078497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3811078497
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2996269975
Short name T639
Test name
Test status
Simulation time 6714493250 ps
CPU time 38.11 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:50 PM PST 24
Peak memory 217324 kb
Host smart-d92015c8-b0bb-4385-a5fd-c8cbb392be5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996269975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2996269975
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1169526972
Short name T645
Test name
Test status
Simulation time 2018685121 ps
CPU time 36.02 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:48 PM PST 24
Peak memory 198828 kb
Host smart-e0d4bcf9-7289-425d-bd56-2d314b88dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169526972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1169526972
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1428880229
Short name T37
Test name
Test status
Simulation time 331592489 ps
CPU time 17.54 seconds
Started Jan 14 01:49:08 PM PST 24
Finished Jan 14 01:49:26 PM PST 24
Peak memory 198740 kb
Host smart-33ef30a8-fb15-4fe7-84c6-1a42c0d2d636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428880229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1428880229
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1765970037
Short name T286
Test name
Test status
Simulation time 209118554 ps
CPU time 2.5 seconds
Started Jan 14 01:49:10 PM PST 24
Finished Jan 14 01:49:13 PM PST 24
Peak memory 198288 kb
Host smart-db7f8843-c180-4aba-8b98-6f0d2e40c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765970037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1765970037
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3149715945
Short name T761
Test name
Test status
Simulation time 748586840 ps
CPU time 18.69 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:43 PM PST 24
Peak memory 198784 kb
Host smart-5fd5840d-e31d-46e2-8859-b5ec97693203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149715945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3149715945
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3079208125
Short name T801
Test name
Test status
Simulation time 173937649 ps
CPU time 2.18 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 198776 kb
Host smart-f8ba625a-833b-49da-93eb-c644cfd4bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079208125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3079208125
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1981029532
Short name T36
Test name
Test status
Simulation time 14500646436 ps
CPU time 675.82 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 02:00:27 PM PST 24
Peak memory 207064 kb
Host smart-04f9e811-b929-4880-999b-3f1b0184c18f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981029532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1981029532
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.3127616072
Short name T672
Test name
Test status
Simulation time 182996027828 ps
CPU time 1737.17 seconds
Started Jan 14 01:49:04 PM PST 24
Finished Jan 14 02:18:02 PM PST 24
Peak memory 247328 kb
Host smart-4d5487aa-750f-4d4e-adcc-0f56b28e61d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127616072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.3127616072
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4168273536
Short name T210
Test name
Test status
Simulation time 78553932 ps
CPU time 1.09 seconds
Started Jan 14 01:49:08 PM PST 24
Finished Jan 14 01:49:10 PM PST 24
Peak memory 197196 kb
Host smart-c05ae7d4-32a6-46ff-a606-8a15178a99b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168273536 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4168273536
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.4158291740
Short name T421
Test name
Test status
Simulation time 114533314391 ps
CPU time 480.36 seconds
Started Jan 14 01:49:08 PM PST 24
Finished Jan 14 01:57:09 PM PST 24
Peak memory 198796 kb
Host smart-8d9b8f04-d173-4cba-9639-a9274a992830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158291740 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.4158291740
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2168754955
Short name T689
Test name
Test status
Simulation time 1264851895 ps
CPU time 16.11 seconds
Started Jan 14 01:49:05 PM PST 24
Finished Jan 14 01:49:22 PM PST 24
Peak memory 198820 kb
Host smart-71fc142c-3f84-4544-b331-a9c6b888b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168754955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2168754955
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.1655746713
Short name T92
Test name
Test status
Simulation time 280951141571 ps
CPU time 3018.46 seconds
Started Jan 14 01:52:10 PM PST 24
Finished Jan 14 02:42:29 PM PST 24
Peak memory 263008 kb
Host smart-5945cd3a-34d4-49b2-b59b-2a7317c59ead
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655746713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.1655746713
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.1651121640
Short name T380
Test name
Test status
Simulation time 310928395525 ps
CPU time 1409.49 seconds
Started Jan 14 01:52:13 PM PST 24
Finished Jan 14 02:15:44 PM PST 24
Peak memory 226164 kb
Host smart-ff535658-bf8b-49ec-9f48-c2c00bf7cc16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651121640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.1651121640
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.2582241084
Short name T275
Test name
Test status
Simulation time 364030423524 ps
CPU time 1761.92 seconds
Started Jan 14 01:52:09 PM PST 24
Finished Jan 14 02:21:32 PM PST 24
Peak memory 223556 kb
Host smart-58520437-462f-4c9e-b17c-9d92da16c225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582241084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.2582241084
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3248989686
Short name T790
Test name
Test status
Simulation time 64713658203 ps
CPU time 949.83 seconds
Started Jan 14 01:52:03 PM PST 24
Finished Jan 14 02:07:54 PM PST 24
Peak memory 239920 kb
Host smart-154449ec-93dc-4aed-9e0d-a4acbb7c61b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248989686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.3248989686
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2934659149
Short name T685
Test name
Test status
Simulation time 352822478934 ps
CPU time 4143.78 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 03:01:23 PM PST 24
Peak memory 255796 kb
Host smart-79ecb029-7dd0-42e7-b247-ed1fb0f9acac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934659149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.2934659149
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.3439579941
Short name T505
Test name
Test status
Simulation time 15829747879 ps
CPU time 275.69 seconds
Started Jan 14 01:52:17 PM PST 24
Finished Jan 14 01:56:53 PM PST 24
Peak memory 198956 kb
Host smart-282d3f31-58e4-4f0c-801b-c9ef6dac81f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439579941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.3439579941
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.320727876
Short name T609
Test name
Test status
Simulation time 166340541421 ps
CPU time 1424.86 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 02:16:04 PM PST 24
Peak memory 226560 kb
Host smart-30f49e80-b8c0-49be-83df-c8827eba097e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320727876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.320727876
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.494275178
Short name T113
Test name
Test status
Simulation time 76645662887 ps
CPU time 807.95 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 02:05:47 PM PST 24
Peak memory 229244 kb
Host smart-e95e1288-4d84-4817-ab83-8eecf3588fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494275178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.494275178
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.789196291
Short name T401
Test name
Test status
Simulation time 104518312352 ps
CPU time 2502.06 seconds
Started Jan 14 01:52:17 PM PST 24
Finished Jan 14 02:34:00 PM PST 24
Peak memory 256356 kb
Host smart-9aba9755-a967-4c25-9678-c3ce701b897e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789196291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.789196291
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.806486248
Short name T448
Test name
Test status
Simulation time 30093795 ps
CPU time 0.57 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:13 PM PST 24
Peak memory 193176 kb
Host smart-fd5cd404-12b8-49d6-8801-57acd8d807b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806486248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.806486248
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1814753539
Short name T803
Test name
Test status
Simulation time 3650332892 ps
CPU time 31.62 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:43 PM PST 24
Peak memory 225536 kb
Host smart-8f184522-9386-4158-9837-25f7b2240424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814753539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1814753539
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.507582062
Short name T632
Test name
Test status
Simulation time 2898668602 ps
CPU time 33.45 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:58 PM PST 24
Peak memory 198744 kb
Host smart-5c2b258a-f863-4cbc-9af2-a2b30fb1425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507582062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.507582062
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1036065350
Short name T403
Test name
Test status
Simulation time 180798626 ps
CPU time 10.01 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 198724 kb
Host smart-5d1f6e16-9254-409d-b6aa-512e2f2a8b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036065350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1036065350
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3652398447
Short name T369
Test name
Test status
Simulation time 3278006223 ps
CPU time 39.74 seconds
Started Jan 14 01:49:10 PM PST 24
Finished Jan 14 01:49:50 PM PST 24
Peak memory 198856 kb
Host smart-874659c3-1536-4ec5-a9fc-994e29d2f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652398447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3652398447
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.218842082
Short name T793
Test name
Test status
Simulation time 2472882565 ps
CPU time 31.1 seconds
Started Jan 14 01:49:14 PM PST 24
Finished Jan 14 01:49:45 PM PST 24
Peak memory 198852 kb
Host smart-0fff5359-8079-49fe-b8ab-12ad05bdef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218842082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.218842082
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3672237939
Short name T534
Test name
Test status
Simulation time 289247344 ps
CPU time 3.12 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:15 PM PST 24
Peak memory 198560 kb
Host smart-09c5d797-e1a8-434f-b0a0-2e1e6f62e178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672237939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3672237939
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3516404133
Short name T563
Test name
Test status
Simulation time 47183406866 ps
CPU time 578.33 seconds
Started Jan 14 01:49:12 PM PST 24
Finished Jan 14 01:58:52 PM PST 24
Peak memory 231692 kb
Host smart-f3342009-91ec-4aad-bc04-cfe09ad82831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516404133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3516404133
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.2768720665
Short name T713
Test name
Test status
Simulation time 48694401434 ps
CPU time 2631.86 seconds
Started Jan 14 01:49:12 PM PST 24
Finished Jan 14 02:33:05 PM PST 24
Peak memory 248088 kb
Host smart-61a925c3-4620-4e4c-8292-2341d0f549c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768720665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.2768720665
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.238672556
Short name T342
Test name
Test status
Simulation time 41182273 ps
CPU time 0.9 seconds
Started Jan 14 01:49:09 PM PST 24
Finished Jan 14 01:49:10 PM PST 24
Peak memory 195728 kb
Host smart-e9a46d4b-fa8c-45ba-b722-6b26d068d241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238672556 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.238672556
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3787695937
Short name T351
Test name
Test status
Simulation time 15337311320 ps
CPU time 353.41 seconds
Started Jan 14 01:49:12 PM PST 24
Finished Jan 14 01:55:06 PM PST 24
Peak memory 198760 kb
Host smart-1e153202-3fac-4f4e-a05f-75cfa01bb95a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787695937 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.3787695937
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3809437349
Short name T847
Test name
Test status
Simulation time 4378299356 ps
CPU time 20.32 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:45 PM PST 24
Peak memory 198852 kb
Host smart-dd297caa-d6fe-4bf5-925b-13a1f80ea4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809437349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3809437349
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3835999626
Short name T466
Test name
Test status
Simulation time 24097771845 ps
CPU time 381.21 seconds
Started Jan 14 01:52:20 PM PST 24
Finished Jan 14 01:58:42 PM PST 24
Peak memory 218392 kb
Host smart-7b75cd2a-819d-4802-b462-a41dfcaac833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835999626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3835999626
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.323791064
Short name T590
Test name
Test status
Simulation time 18920791875 ps
CPU time 359.75 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 01:58:19 PM PST 24
Peak memory 247460 kb
Host smart-70e1c82c-2be4-4387-8b33-e34b088f1312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323791064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.323791064
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.145288775
Short name T633
Test name
Test status
Simulation time 261895092151 ps
CPU time 2067.03 seconds
Started Jan 14 01:52:16 PM PST 24
Finished Jan 14 02:26:44 PM PST 24
Peak memory 256164 kb
Host smart-1f87f1ad-55ea-42d8-93ce-b70046965644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145288775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.145288775
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3295609165
Short name T729
Test name
Test status
Simulation time 134339626793 ps
CPU time 647.78 seconds
Started Jan 14 01:52:17 PM PST 24
Finished Jan 14 02:03:06 PM PST 24
Peak memory 224096 kb
Host smart-aa51e067-7499-4579-9240-6017c882c156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295609165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3295609165
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.3813352516
Short name T623
Test name
Test status
Simulation time 79692330271 ps
CPU time 183.28 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 01:55:23 PM PST 24
Peak memory 215376 kb
Host smart-ab537c6c-150c-4806-b960-3484e01324e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813352516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.3813352516
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.369324806
Short name T649
Test name
Test status
Simulation time 74280815829 ps
CPU time 2366.49 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 02:31:46 PM PST 24
Peak memory 250160 kb
Host smart-ba287e1a-f632-4b90-843e-3ce57d6e3ebf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369324806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.369324806
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.180024868
Short name T94
Test name
Test status
Simulation time 44432989666 ps
CPU time 795.41 seconds
Started Jan 14 01:52:19 PM PST 24
Finished Jan 14 02:05:36 PM PST 24
Peak memory 233160 kb
Host smart-6e2032e7-7624-4c6b-b380-d03fcc97eaca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180024868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.180024868
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3988481362
Short name T572
Test name
Test status
Simulation time 33167432329 ps
CPU time 622.16 seconds
Started Jan 14 01:52:17 PM PST 24
Finished Jan 14 02:02:40 PM PST 24
Peak memory 215316 kb
Host smart-37761ac9-62a7-4182-83f7-835bf6e6abae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988481362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3988481362
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.2963239495
Short name T653
Test name
Test status
Simulation time 264954575477 ps
CPU time 2867.3 seconds
Started Jan 14 01:52:18 PM PST 24
Finished Jan 14 02:40:07 PM PST 24
Peak memory 248108 kb
Host smart-00d50c50-0929-4926-a617-a6b12c9a7f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963239495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.2963239495
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.542294502
Short name T666
Test name
Test status
Simulation time 31954802 ps
CPU time 0.57 seconds
Started Jan 14 01:48:05 PM PST 24
Finished Jan 14 01:48:07 PM PST 24
Peak memory 193256 kb
Host smart-cc7830dd-0513-486f-a1cc-35c909b80eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542294502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.542294502
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.112625094
Short name T628
Test name
Test status
Simulation time 3118415293 ps
CPU time 9.91 seconds
Started Jan 14 01:48:04 PM PST 24
Finished Jan 14 01:48:15 PM PST 24
Peak memory 215268 kb
Host smart-97a6d276-2b72-45d0-9c6d-310ea0fff454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112625094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.112625094
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1382546415
Short name T721
Test name
Test status
Simulation time 19507919864 ps
CPU time 46.48 seconds
Started Jan 14 01:48:05 PM PST 24
Finished Jan 14 01:48:52 PM PST 24
Peak memory 198864 kb
Host smart-4e26e210-e281-4e23-9c44-3eac8e5ca0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382546415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1382546415
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2662904975
Short name T709
Test name
Test status
Simulation time 8537979689 ps
CPU time 131.27 seconds
Started Jan 14 01:48:03 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198836 kb
Host smart-626d1838-9dbc-4491-ac82-c6a902b1acee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662904975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2662904975
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3308513205
Short name T783
Test name
Test status
Simulation time 9088172294 ps
CPU time 106.68 seconds
Started Jan 14 01:48:05 PM PST 24
Finished Jan 14 01:49:53 PM PST 24
Peak memory 198832 kb
Host smart-e9d3ddf9-b3c8-429d-928c-f8371a8eb55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308513205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3308513205
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.309470517
Short name T316
Test name
Test status
Simulation time 7172845393 ps
CPU time 86.04 seconds
Started Jan 14 01:48:03 PM PST 24
Finished Jan 14 01:49:30 PM PST 24
Peak memory 198892 kb
Host smart-de1fc7fc-abf5-474b-b539-2614d47aac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309470517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.309470517
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2373559461
Short name T50
Test name
Test status
Simulation time 36682585 ps
CPU time 0.78 seconds
Started Jan 14 01:48:04 PM PST 24
Finished Jan 14 01:48:06 PM PST 24
Peak memory 215828 kb
Host smart-a3bf5646-d052-4542-b5d3-0488810571db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373559461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2373559461
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3635479591
Short name T317
Test name
Test status
Simulation time 555725239 ps
CPU time 2.22 seconds
Started Jan 14 01:48:01 PM PST 24
Finished Jan 14 01:48:04 PM PST 24
Peak memory 198448 kb
Host smart-d8ceaf9f-64a7-4768-a6e6-521036ec1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635479591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3635479591
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4066290179
Short name T601
Test name
Test status
Simulation time 1947268173 ps
CPU time 80.57 seconds
Started Jan 14 01:48:04 PM PST 24
Finished Jan 14 01:49:25 PM PST 24
Peak memory 198744 kb
Host smart-83214717-1b7a-453c-b73b-ea57cc3e2335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066290179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4066290179
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2450246587
Short name T791
Test name
Test status
Simulation time 181008266675 ps
CPU time 533.62 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:57:07 PM PST 24
Peak memory 239284 kb
Host smart-dc758106-af48-48f4-bd5c-e6d9dac9f6c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450246587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2450246587
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2555736587
Short name T313
Test name
Test status
Simulation time 473647045 ps
CPU time 1.2 seconds
Started Jan 14 01:48:06 PM PST 24
Finished Jan 14 01:48:09 PM PST 24
Peak memory 197176 kb
Host smart-a838c896-3334-4d8c-a781-c8f9c655df76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555736587 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2555736587
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.562423638
Short name T687
Test name
Test status
Simulation time 58902798736 ps
CPU time 451.51 seconds
Started Jan 14 01:48:07 PM PST 24
Finished Jan 14 01:55:40 PM PST 24
Peak memory 198740 kb
Host smart-cc0feade-2db9-435c-b5c9-74f71bb1dca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562423638 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_sha_vectors.562423638
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4213568566
Short name T818
Test name
Test status
Simulation time 3480818506 ps
CPU time 65.26 seconds
Started Jan 14 01:48:02 PM PST 24
Finished Jan 14 01:49:09 PM PST 24
Peak memory 198904 kb
Host smart-6dccd111-810d-4d6d-9747-5fa6f71e8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213568566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4213568566
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1057069049
Short name T283
Test name
Test status
Simulation time 23728383 ps
CPU time 0.61 seconds
Started Jan 14 01:49:17 PM PST 24
Finished Jan 14 01:49:18 PM PST 24
Peak memory 194216 kb
Host smart-db613fad-811b-4274-9368-2650bb299265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057069049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1057069049
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1900974718
Short name T741
Test name
Test status
Simulation time 1729672107 ps
CPU time 28.57 seconds
Started Jan 14 01:49:14 PM PST 24
Finished Jan 14 01:49:43 PM PST 24
Peak memory 207048 kb
Host smart-757a5fa2-d20a-4b9a-91ad-03c20fd89631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900974718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1900974718
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.171114511
Short name T435
Test name
Test status
Simulation time 6293171115 ps
CPU time 23.61 seconds
Started Jan 14 01:49:11 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 198748 kb
Host smart-6e702f99-d4a6-4d52-a601-43d91fc59d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171114511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.171114511
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.409862942
Short name T564
Test name
Test status
Simulation time 6069254251 ps
CPU time 67.12 seconds
Started Jan 14 01:49:10 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 198676 kb
Host smart-f313d665-1850-4021-8378-bb00a6c7c484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409862942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.409862942
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1108954379
Short name T350
Test name
Test status
Simulation time 39781995699 ps
CPU time 146.32 seconds
Started Jan 14 01:49:13 PM PST 24
Finished Jan 14 01:51:40 PM PST 24
Peak memory 198852 kb
Host smart-0d2139f5-c9ec-4d9a-b2e6-9860073e8192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108954379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1108954379
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1733801981
Short name T627
Test name
Test status
Simulation time 13632532393 ps
CPU time 99.49 seconds
Started Jan 14 01:49:12 PM PST 24
Finished Jan 14 01:50:52 PM PST 24
Peak memory 198808 kb
Host smart-69a9e2e6-caa5-4ac5-9b57-a772cd9d0c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733801981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1733801981
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2629306738
Short name T692
Test name
Test status
Simulation time 885089592 ps
CPU time 1.66 seconds
Started Jan 14 01:49:24 PM PST 24
Finished Jan 14 01:49:26 PM PST 24
Peak memory 198288 kb
Host smart-5c6b92ce-8169-45f8-9b4d-ed38c993537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629306738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2629306738
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3224107907
Short name T38
Test name
Test status
Simulation time 28739546006 ps
CPU time 1390.48 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 02:12:30 PM PST 24
Peak memory 207116 kb
Host smart-10cfc758-523b-404c-b8f9-6b4708c667f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224107907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3224107907
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1482900491
Short name T794
Test name
Test status
Simulation time 48148817791 ps
CPU time 449.12 seconds
Started Jan 14 01:49:20 PM PST 24
Finished Jan 14 01:56:50 PM PST 24
Peak memory 215340 kb
Host smart-e57b31ed-0dea-49a8-b34a-6196fa4a4844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482900491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1482900491
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3847312475
Short name T227
Test name
Test status
Simulation time 113468798 ps
CPU time 1.13 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:49:20 PM PST 24
Peak memory 197560 kb
Host smart-ab49cc5d-6b62-4466-991b-4f6ab24a20de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847312475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3847312475
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.4011751512
Short name T303
Test name
Test status
Simulation time 31951679475 ps
CPU time 374.97 seconds
Started Jan 14 01:49:17 PM PST 24
Finished Jan 14 01:55:32 PM PST 24
Peak memory 198728 kb
Host smart-cef21f14-07d8-4db4-b9c1-a85a6f22b35f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011751512 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.4011751512
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1137740991
Short name T652
Test name
Test status
Simulation time 7367929331 ps
CPU time 64.36 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:50:24 PM PST 24
Peak memory 198804 kb
Host smart-d72b16b0-1993-4c1f-b377-43292d37cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137740991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1137740991
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3100877216
Short name T736
Test name
Test status
Simulation time 13431269 ps
CPU time 0.57 seconds
Started Jan 14 01:49:18 PM PST 24
Finished Jan 14 01:49:19 PM PST 24
Peak memory 193136 kb
Host smart-d269e106-9555-40df-9380-b856590bd3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100877216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3100877216
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.986600983
Short name T513
Test name
Test status
Simulation time 9511570378 ps
CPU time 14.3 seconds
Started Jan 14 01:49:20 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 207064 kb
Host smart-298afa32-05ac-4ef3-8c04-3f41626d14e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986600983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.986600983
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2794678248
Short name T256
Test name
Test status
Simulation time 5160654835 ps
CPU time 38.56 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:49:58 PM PST 24
Peak memory 198828 kb
Host smart-ccdb0017-89f5-4e44-abf3-9cc3b5232570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794678248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2794678248
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3552026200
Short name T377
Test name
Test status
Simulation time 7706933289 ps
CPU time 99.1 seconds
Started Jan 14 01:49:18 PM PST 24
Finished Jan 14 01:50:57 PM PST 24
Peak memory 198864 kb
Host smart-c054c39f-3d84-40e7-beee-17db94568bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552026200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3552026200
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2242232257
Short name T308
Test name
Test status
Simulation time 8247682068 ps
CPU time 34.23 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:49:54 PM PST 24
Peak memory 198824 kb
Host smart-c0bb67f2-2969-47ad-82a6-844acbfc7c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242232257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2242232257
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3734046136
Short name T545
Test name
Test status
Simulation time 23662932761 ps
CPU time 82.77 seconds
Started Jan 14 01:49:18 PM PST 24
Finished Jan 14 01:50:41 PM PST 24
Peak memory 198852 kb
Host smart-94298d97-0496-4a83-911f-c2273b35e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734046136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3734046136
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4118515440
Short name T326
Test name
Test status
Simulation time 736957301 ps
CPU time 2.68 seconds
Started Jan 14 01:49:18 PM PST 24
Finished Jan 14 01:49:22 PM PST 24
Peak memory 198732 kb
Host smart-a25b8050-5aea-4bd3-81a3-070003c1d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118515440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4118515440
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.798397728
Short name T250
Test name
Test status
Simulation time 50213202769 ps
CPU time 175.68 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:52:16 PM PST 24
Peak memory 215240 kb
Host smart-8d3755fb-3254-48d8-b900-946905d1695f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798397728 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.798397728
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.3862333775
Short name T97
Test name
Test status
Simulation time 295372950998 ps
CPU time 1329.46 seconds
Started Jan 14 01:49:21 PM PST 24
Finished Jan 14 02:11:31 PM PST 24
Peak memory 259408 kb
Host smart-c4d398cb-a348-42bf-8502-d4b78719c3ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862333775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.3862333775
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.573347870
Short name T663
Test name
Test status
Simulation time 58724905 ps
CPU time 1.14 seconds
Started Jan 14 01:49:25 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 197848 kb
Host smart-d21de9df-6cb7-4284-bcb2-f76219173917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573347870 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.573347870
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3536909533
Short name T739
Test name
Test status
Simulation time 187240073444 ps
CPU time 437.19 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:56:37 PM PST 24
Peak memory 198808 kb
Host smart-7ca79f5d-e2db-41ec-85ce-6f31200820e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536909533 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3536909533
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4010196724
Short name T831
Test name
Test status
Simulation time 1412736133 ps
CPU time 15.26 seconds
Started Jan 14 01:49:20 PM PST 24
Finished Jan 14 01:49:36 PM PST 24
Peak memory 198812 kb
Host smart-ba98418b-83da-4f54-af59-96779669ebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010196724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4010196724
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2267600004
Short name T489
Test name
Test status
Simulation time 22526392 ps
CPU time 0.55 seconds
Started Jan 14 01:49:38 PM PST 24
Finished Jan 14 01:49:39 PM PST 24
Peak memory 193176 kb
Host smart-4313c46a-80e8-4f39-b6fc-0d59046b3cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267600004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2267600004
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1371308553
Short name T796
Test name
Test status
Simulation time 2992386998 ps
CPU time 42.04 seconds
Started Jan 14 01:49:16 PM PST 24
Finished Jan 14 01:49:58 PM PST 24
Peak memory 207052 kb
Host smart-ff425989-4927-4636-b4bb-d2431a60aa66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371308553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1371308553
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1493882703
Short name T224
Test name
Test status
Simulation time 553997417 ps
CPU time 11.12 seconds
Started Jan 14 01:49:46 PM PST 24
Finished Jan 14 01:50:00 PM PST 24
Peak memory 198796 kb
Host smart-53711351-19c4-4fd0-ba08-296ae05a8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493882703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1493882703
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1608024326
Short name T542
Test name
Test status
Simulation time 1093059884 ps
CPU time 13.96 seconds
Started Jan 14 01:49:39 PM PST 24
Finished Jan 14 01:49:53 PM PST 24
Peak memory 198808 kb
Host smart-6b4c6038-a645-47ea-bce6-8bb15658cda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608024326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1608024326
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3937891147
Short name T229
Test name
Test status
Simulation time 24501585126 ps
CPU time 76.04 seconds
Started Jan 14 01:49:37 PM PST 24
Finished Jan 14 01:50:54 PM PST 24
Peak memory 198796 kb
Host smart-6f935186-bf94-480d-931e-0e693552395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937891147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3937891147
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3827181113
Short name T230
Test name
Test status
Simulation time 7471707471 ps
CPU time 127 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:51:27 PM PST 24
Peak memory 198892 kb
Host smart-1618776e-1ed6-4b5f-9a06-ed05d1383da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827181113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3827181113
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3177645724
Short name T752
Test name
Test status
Simulation time 135235162 ps
CPU time 2.1 seconds
Started Jan 14 01:49:19 PM PST 24
Finished Jan 14 01:49:21 PM PST 24
Peak memory 198748 kb
Host smart-79afec22-61ed-4280-bed7-a5276a70388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177645724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3177645724
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2330237616
Short name T211
Test name
Test status
Simulation time 8446107225 ps
CPU time 415.65 seconds
Started Jan 14 01:49:41 PM PST 24
Finished Jan 14 01:56:43 PM PST 24
Peak memory 198888 kb
Host smart-7aa21ac9-c87b-4015-a76c-c3d017a44aae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330237616 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2330237616
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.526007792
Short name T428
Test name
Test status
Simulation time 30641827 ps
CPU time 1.08 seconds
Started Jan 14 01:49:42 PM PST 24
Finished Jan 14 01:49:50 PM PST 24
Peak memory 197312 kb
Host smart-1131c78a-3203-44ef-9df8-18b64075e021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526007792 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.526007792
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3000159384
Short name T702
Test name
Test status
Simulation time 7756410721 ps
CPU time 361.93 seconds
Started Jan 14 01:49:42 PM PST 24
Finished Jan 14 01:55:51 PM PST 24
Peak memory 198840 kb
Host smart-6223fc78-74b0-4a42-9555-289bf83a0291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000159384 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3000159384
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3952279272
Short name T850
Test name
Test status
Simulation time 2091070462 ps
CPU time 25.39 seconds
Started Jan 14 01:49:44 PM PST 24
Finished Jan 14 01:50:14 PM PST 24
Peak memory 198792 kb
Host smart-2cd42808-3e58-42b0-b84d-01782d702cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952279272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3952279272
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1747315953
Short name T762
Test name
Test status
Simulation time 30866367 ps
CPU time 0.57 seconds
Started Jan 14 01:49:56 PM PST 24
Finished Jan 14 01:49:58 PM PST 24
Peak memory 193160 kb
Host smart-b5f3878a-76e0-41a5-bf6c-65c6797d2dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747315953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1747315953
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.944354642
Short name T680
Test name
Test status
Simulation time 347745320 ps
CPU time 8.15 seconds
Started Jan 14 01:49:42 PM PST 24
Finished Jan 14 01:49:57 PM PST 24
Peak memory 226232 kb
Host smart-65e2b94b-94dd-4f5d-b4fb-c19112d56e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944354642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.944354642
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3216050565
Short name T267
Test name
Test status
Simulation time 3935624718 ps
CPU time 44.71 seconds
Started Jan 14 01:49:48 PM PST 24
Finished Jan 14 01:50:36 PM PST 24
Peak memory 198808 kb
Host smart-0c05dfd7-80cb-4e37-b4ff-ae473336202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216050565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3216050565
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4029004498
Short name T361
Test name
Test status
Simulation time 45687797579 ps
CPU time 120.18 seconds
Started Jan 14 01:49:46 PM PST 24
Finished Jan 14 01:51:49 PM PST 24
Peak memory 198860 kb
Host smart-40ac400f-93d1-4b8e-8a08-68785e0c147c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029004498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4029004498
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1634069499
Short name T839
Test name
Test status
Simulation time 3265779546 ps
CPU time 76.27 seconds
Started Jan 14 01:49:46 PM PST 24
Finished Jan 14 01:51:05 PM PST 24
Peak memory 198888 kb
Host smart-563c84a9-0a2e-4377-8f8e-47099f0aa94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634069499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1634069499
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3303990892
Short name T425
Test name
Test status
Simulation time 1856455839 ps
CPU time 96.18 seconds
Started Jan 14 01:49:44 PM PST 24
Finished Jan 14 01:51:25 PM PST 24
Peak memory 198784 kb
Host smart-d025fd32-f13c-4180-ac96-417dc296d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303990892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3303990892
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1616246597
Short name T830
Test name
Test status
Simulation time 153961324 ps
CPU time 4.03 seconds
Started Jan 14 01:49:37 PM PST 24
Finished Jan 14 01:49:42 PM PST 24
Peak memory 198740 kb
Host smart-2e79b30f-120f-45a0-a8bc-9f10b34993f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616246597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1616246597
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2522366107
Short name T266
Test name
Test status
Simulation time 61310315739 ps
CPU time 520.51 seconds
Started Jan 14 01:49:53 PM PST 24
Finished Jan 14 01:58:34 PM PST 24
Peak memory 198900 kb
Host smart-150f0b3d-5481-44c9-b597-5a3c0b663fff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522366107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2522366107
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.2880687907
Short name T488
Test name
Test status
Simulation time 360915913238 ps
CPU time 2790.9 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 02:36:33 PM PST 24
Peak memory 263020 kb
Host smart-af6681e3-2932-454e-ba59-e85b133f63f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880687907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.2880687907
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.650712516
Short name T492
Test name
Test status
Simulation time 88178601 ps
CPU time 0.95 seconds
Started Jan 14 01:49:53 PM PST 24
Finished Jan 14 01:49:55 PM PST 24
Peak memory 196672 kb
Host smart-736a0cfa-43fd-46ef-88b7-cb3142eed18b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650712516 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.650712516
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3768976204
Short name T764
Test name
Test status
Simulation time 166483368360 ps
CPU time 473.18 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 01:57:48 PM PST 24
Peak memory 198804 kb
Host smart-fe72e787-df1c-4b7f-ba2a-cb5437a918ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768976204 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.3768976204
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3375169177
Short name T811
Test name
Test status
Simulation time 2870976780 ps
CPU time 53.13 seconds
Started Jan 14 01:50:00 PM PST 24
Finished Jan 14 01:50:55 PM PST 24
Peak memory 198832 kb
Host smart-493b2631-cdc4-4641-beae-a0b8cff7afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375169177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3375169177
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.921540066
Short name T504
Test name
Test status
Simulation time 15426158 ps
CPU time 0.63 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 01:49:55 PM PST 24
Peak memory 193148 kb
Host smart-b1c14246-dcc0-4773-ae16-09e9c1589afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921540066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.921540066
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4260923017
Short name T389
Test name
Test status
Simulation time 748403091 ps
CPU time 14.16 seconds
Started Jan 14 01:49:53 PM PST 24
Finished Jan 14 01:50:08 PM PST 24
Peak memory 225632 kb
Host smart-cfdbac74-89c9-4e4a-8c1c-bbd1a913ef32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260923017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4260923017
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3210713703
Short name T763
Test name
Test status
Simulation time 301044890 ps
CPU time 4.13 seconds
Started Jan 14 01:49:50 PM PST 24
Finished Jan 14 01:49:56 PM PST 24
Peak memory 198848 kb
Host smart-24993b5e-dabc-4d98-930a-599cfa17bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210713703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3210713703
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4204473467
Short name T343
Test name
Test status
Simulation time 6518984724 ps
CPU time 83.44 seconds
Started Jan 14 01:49:55 PM PST 24
Finished Jan 14 01:51:19 PM PST 24
Peak memory 198840 kb
Host smart-b0ad5878-93ac-4c1a-a82b-37b257cc1a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204473467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4204473467
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2571820919
Short name T41
Test name
Test status
Simulation time 3555493428 ps
CPU time 174.35 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 01:52:56 PM PST 24
Peak memory 198828 kb
Host smart-c2b66a87-bf55-4142-8cae-35deeaef8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571820919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2571820919
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2451218315
Short name T473
Test name
Test status
Simulation time 968296858 ps
CPU time 53.85 seconds
Started Jan 14 01:49:50 PM PST 24
Finished Jan 14 01:50:46 PM PST 24
Peak memory 198780 kb
Host smart-59539103-708d-4904-9836-fc252c5ea403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451218315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2451218315
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.419830609
Short name T487
Test name
Test status
Simulation time 353003696 ps
CPU time 3.64 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:50:01 PM PST 24
Peak memory 198836 kb
Host smart-61e6d580-7e89-4b83-8e68-6a9ef202490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419830609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.419830609
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3364026334
Short name T217
Test name
Test status
Simulation time 57160956693 ps
CPU time 678 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 02:01:30 PM PST 24
Peak memory 215088 kb
Host smart-0885dcde-008d-47dc-b447-841095e28c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364026334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3364026334
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.223454643
Short name T684
Test name
Test status
Simulation time 303500999195 ps
CPU time 1075.19 seconds
Started Jan 14 01:49:55 PM PST 24
Finished Jan 14 02:07:51 PM PST 24
Peak memory 231652 kb
Host smart-4b0f9015-1658-4fe2-950b-d71f911b3634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223454643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.223454643
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2476861319
Short name T404
Test name
Test status
Simulation time 95296653 ps
CPU time 0.87 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:50:13 PM PST 24
Peak memory 195652 kb
Host smart-9117a912-2e7f-4dc7-b59a-9508c3101d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476861319 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2476861319
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1866955620
Short name T199
Test name
Test status
Simulation time 7208645526 ps
CPU time 349.11 seconds
Started Jan 14 01:49:58 PM PST 24
Finished Jan 14 01:55:48 PM PST 24
Peak memory 198696 kb
Host smart-23a3d762-6185-4fa9-897a-ebeebb55fd06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866955620 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.1866955620
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.405217514
Short name T325
Test name
Test status
Simulation time 2391766923 ps
CPU time 20.89 seconds
Started Jan 14 01:50:06 PM PST 24
Finished Jan 14 01:50:33 PM PST 24
Peak memory 198900 kb
Host smart-4120221a-1f8e-4dd3-934e-a2c1f5f62b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405217514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.405217514
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3829907401
Short name T45
Test name
Test status
Simulation time 17979705 ps
CPU time 0.55 seconds
Started Jan 14 01:49:43 PM PST 24
Finished Jan 14 01:49:49 PM PST 24
Peak memory 193192 kb
Host smart-32c12678-bf41-4ee5-8052-10d03bd8b38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829907401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3829907401
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4237862318
Short name T226
Test name
Test status
Simulation time 391331604 ps
CPU time 5.31 seconds
Started Jan 14 01:49:39 PM PST 24
Finished Jan 14 01:49:46 PM PST 24
Peak memory 198732 kb
Host smart-535d75fb-46b3-4416-bb81-3fdce860fad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237862318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4237862318
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1265631224
Short name T330
Test name
Test status
Simulation time 3146324128 ps
CPU time 41.54 seconds
Started Jan 14 01:49:43 PM PST 24
Finished Jan 14 01:50:30 PM PST 24
Peak memory 198812 kb
Host smart-401ef052-a178-481f-b7e3-bde0e6051bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265631224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1265631224
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2950436640
Short name T231
Test name
Test status
Simulation time 13420807101 ps
CPU time 128.8 seconds
Started Jan 14 01:49:38 PM PST 24
Finished Jan 14 01:51:48 PM PST 24
Peak memory 198872 kb
Host smart-64c3d03b-26fd-44ba-a5fc-c6b46818b228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950436640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2950436640
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1753706657
Short name T743
Test name
Test status
Simulation time 5086560337 ps
CPU time 57.26 seconds
Started Jan 14 01:49:37 PM PST 24
Finished Jan 14 01:50:35 PM PST 24
Peak memory 198840 kb
Host smart-734841cd-d8fd-4fa6-816e-3a0b59dcf32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753706657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1753706657
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3406238700
Short name T613
Test name
Test status
Simulation time 67836181814 ps
CPU time 73.76 seconds
Started Jan 14 01:50:07 PM PST 24
Finished Jan 14 01:51:26 PM PST 24
Peak memory 198840 kb
Host smart-327cedbb-57d0-46c5-b04b-f3857023569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406238700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3406238700
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3306345031
Short name T777
Test name
Test status
Simulation time 190819846 ps
CPU time 2.35 seconds
Started Jan 14 01:49:59 PM PST 24
Finished Jan 14 01:50:02 PM PST 24
Peak memory 198836 kb
Host smart-95e5e7a3-1d0f-490e-a22d-1352586424ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306345031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3306345031
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2122674625
Short name T661
Test name
Test status
Simulation time 48903833787 ps
CPU time 844.36 seconds
Started Jan 14 01:49:37 PM PST 24
Finished Jan 14 02:03:42 PM PST 24
Peak memory 198852 kb
Host smart-012094d8-8655-4f9d-9866-cba6738cd819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122674625 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2122674625
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.3347505982
Short name T710
Test name
Test status
Simulation time 44307620033 ps
CPU time 510.39 seconds
Started Jan 14 01:49:42 PM PST 24
Finished Jan 14 01:58:18 PM PST 24
Peak memory 247176 kb
Host smart-61338245-a619-463e-97b5-d829fab4cb52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347505982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.3347505982
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1974863017
Short name T206
Test name
Test status
Simulation time 187994824 ps
CPU time 0.87 seconds
Started Jan 14 01:49:43 PM PST 24
Finished Jan 14 01:49:50 PM PST 24
Peak memory 196652 kb
Host smart-b3f760a6-b608-47cc-b03a-1115b55d48d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974863017 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1974863017
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2129383097
Short name T776
Test name
Test status
Simulation time 17524393484 ps
CPU time 418.38 seconds
Started Jan 14 01:49:40 PM PST 24
Finished Jan 14 01:56:40 PM PST 24
Peak memory 198780 kb
Host smart-1c92e8ee-959c-4070-a4e0-4bcdacc5112f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129383097 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.2129383097
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2276874593
Short name T855
Test name
Test status
Simulation time 1409876185 ps
CPU time 52.09 seconds
Started Jan 14 01:49:40 PM PST 24
Finished Jan 14 01:50:33 PM PST 24
Peak memory 198792 kb
Host smart-c494a7ca-c2c9-42c0-886e-cba1b218e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276874593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2276874593
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1935088560
Short name T44
Test name
Test status
Simulation time 22451939 ps
CPU time 0.55 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:50:13 PM PST 24
Peak memory 193172 kb
Host smart-9228ff85-fdc4-4cd9-8c25-f0b8829b7c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935088560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1935088560
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.393977958
Short name T826
Test name
Test status
Simulation time 911929107 ps
CPU time 34.5 seconds
Started Jan 14 01:49:40 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 232576 kb
Host smart-97e657d8-f43b-462b-a728-bb48e26ada61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393977958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.393977958
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1416396879
Short name T39
Test name
Test status
Simulation time 5459969097 ps
CPU time 41.7 seconds
Started Jan 14 01:49:36 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 198876 kb
Host smart-a33e0247-4b33-4366-9b10-c1c777fe97d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416396879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1416396879
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2547843083
Short name T469
Test name
Test status
Simulation time 627964179 ps
CPU time 17.02 seconds
Started Jan 14 01:49:37 PM PST 24
Finished Jan 14 01:49:54 PM PST 24
Peak memory 198808 kb
Host smart-bd2be232-328e-4c95-8eba-14b0be73316d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547843083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2547843083
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2475303419
Short name T265
Test name
Test status
Simulation time 13226525997 ps
CPU time 170.31 seconds
Started Jan 14 01:49:45 PM PST 24
Finished Jan 14 01:52:39 PM PST 24
Peak memory 198884 kb
Host smart-e6e3b851-5e30-464d-91c5-04838bb70253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475303419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2475303419
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3887603688
Short name T196
Test name
Test status
Simulation time 819127064 ps
CPU time 40.85 seconds
Started Jan 14 01:49:39 PM PST 24
Finished Jan 14 01:50:21 PM PST 24
Peak memory 198748 kb
Host smart-f48d7d0b-a019-4427-ae60-21e56959de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887603688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3887603688
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3437776040
Short name T778
Test name
Test status
Simulation time 447140311 ps
CPU time 2.83 seconds
Started Jan 14 01:49:44 PM PST 24
Finished Jan 14 01:49:52 PM PST 24
Peak memory 198828 kb
Host smart-a95205da-acbb-4b09-92a6-c888eecb53ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437776040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3437776040
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.895942401
Short name T502
Test name
Test status
Simulation time 56080992075 ps
CPU time 482.56 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:58:00 PM PST 24
Peak memory 198852 kb
Host smart-8c95ad80-a334-4b2d-8bad-b1eb86786e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895942401 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.895942401
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.707557087
Short name T526
Test name
Test status
Simulation time 182668412999 ps
CPU time 729.75 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 02:02:08 PM PST 24
Peak memory 256284 kb
Host smart-94c43b1e-d364-4efb-8d57-ea77e74b27ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707557087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.707557087
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3820621841
Short name T352
Test name
Test status
Simulation time 1146266193 ps
CPU time 1.17 seconds
Started Jan 14 01:50:03 PM PST 24
Finished Jan 14 01:50:06 PM PST 24
Peak memory 197656 kb
Host smart-19a3ab17-b3f4-4eed-9ff7-4e8afce8aa75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820621841 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3820621841
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3450559721
Short name T395
Test name
Test status
Simulation time 46754451044 ps
CPU time 402.52 seconds
Started Jan 14 01:50:02 PM PST 24
Finished Jan 14 01:56:46 PM PST 24
Peak memory 198748 kb
Host smart-d47255b2-a23e-43d1-beb9-f5e936d30605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450559721 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.3450559721
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2670265636
Short name T190
Test name
Test status
Simulation time 8252741507 ps
CPU time 61.06 seconds
Started Jan 14 01:49:56 PM PST 24
Finished Jan 14 01:50:59 PM PST 24
Peak memory 198808 kb
Host smart-603ea342-4687-4b22-974d-73b3e9b6dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670265636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2670265636
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.521172435
Short name T732
Test name
Test status
Simulation time 22044817 ps
CPU time 0.57 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:50:17 PM PST 24
Peak memory 193184 kb
Host smart-fc07158f-1a74-4dbe-a0f2-a024caf64222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521172435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.521172435
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.605086897
Short name T450
Test name
Test status
Simulation time 1464001712 ps
CPU time 13.21 seconds
Started Jan 14 01:50:00 PM PST 24
Finished Jan 14 01:50:14 PM PST 24
Peak memory 218272 kb
Host smart-fe445154-3a48-4044-8e0f-a052ccf52f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605086897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.605086897
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1631182333
Short name T578
Test name
Test status
Simulation time 12292112520 ps
CPU time 23.27 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:50:35 PM PST 24
Peak memory 198864 kb
Host smart-98a4b202-08ee-4e77-9020-419c1ef26095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631182333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1631182333
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.726371136
Short name T338
Test name
Test status
Simulation time 732485486 ps
CPU time 19.43 seconds
Started Jan 14 01:50:10 PM PST 24
Finished Jan 14 01:50:33 PM PST 24
Peak memory 198736 kb
Host smart-63e4c59a-ba8c-43de-93b0-186d07d10cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726371136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.726371136
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2493280969
Short name T828
Test name
Test status
Simulation time 2876704598 ps
CPU time 143.23 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:52:35 PM PST 24
Peak memory 198836 kb
Host smart-5189e3d4-3000-464b-a4f8-9b8ead6b1c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493280969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2493280969
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.597630886
Short name T728
Test name
Test status
Simulation time 2121926619 ps
CPU time 15.8 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 01:50:10 PM PST 24
Peak memory 198636 kb
Host smart-f23dc807-5a16-4848-9c0d-3617aead7c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597630886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.597630886
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.945314923
Short name T774
Test name
Test status
Simulation time 443834273 ps
CPU time 3.2 seconds
Started Jan 14 01:49:56 PM PST 24
Finished Jan 14 01:50:00 PM PST 24
Peak memory 198716 kb
Host smart-5ff46024-6ffc-46da-aac9-78919cf009d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945314923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.945314923
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1003672649
Short name T759
Test name
Test status
Simulation time 174329585353 ps
CPU time 536.83 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:59:09 PM PST 24
Peak memory 198924 kb
Host smart-40af65b3-869c-4ea2-a83a-2db0ee1d8fd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003672649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1003672649
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.1858100723
Short name T315
Test name
Test status
Simulation time 35385902159 ps
CPU time 529.33 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:59:01 PM PST 24
Peak memory 215328 kb
Host smart-ceb1793e-f5fd-4c63-8e97-e9d792b94257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858100723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.1858100723
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.688933290
Short name T568
Test name
Test status
Simulation time 36554221 ps
CPU time 1.14 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:50:13 PM PST 24
Peak memory 197888 kb
Host smart-8f9b3fca-a84d-4a04-ab6d-73032502f40f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688933290 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.688933290
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2675627275
Short name T683
Test name
Test status
Simulation time 33627018054 ps
CPU time 369.31 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:56:30 PM PST 24
Peak memory 198836 kb
Host smart-ee6cc0de-1be7-45c6-9129-4e6907844099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675627275 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.2675627275
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1947008333
Short name T335
Test name
Test status
Simulation time 7658251060 ps
CPU time 72.41 seconds
Started Jan 14 01:50:07 PM PST 24
Finished Jan 14 01:51:24 PM PST 24
Peak memory 198828 kb
Host smart-e514f35c-8764-47a4-92e5-ad72eac5efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947008333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1947008333
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1079244840
Short name T393
Test name
Test status
Simulation time 17315203 ps
CPU time 0.53 seconds
Started Jan 14 01:50:14 PM PST 24
Finished Jan 14 01:50:17 PM PST 24
Peak memory 193180 kb
Host smart-fb606db5-5462-4ed7-8325-391a807faf81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079244840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1079244840
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.139608591
Short name T441
Test name
Test status
Simulation time 1246414081 ps
CPU time 38.57 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:51:00 PM PST 24
Peak memory 225288 kb
Host smart-a70d96ee-d70e-4e58-a6ff-34a5bb2ed719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139608591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.139608591
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3844003652
Short name T382
Test name
Test status
Simulation time 18940366719 ps
CPU time 43.75 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:51:00 PM PST 24
Peak memory 198748 kb
Host smart-5c669432-61c4-4114-81ff-dc7cb74011ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844003652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3844003652
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.947496530
Short name T607
Test name
Test status
Simulation time 4066549679 ps
CPU time 136.81 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:52:32 PM PST 24
Peak memory 198888 kb
Host smart-bdca2f99-a4f8-4c78-8975-0dccbb3873e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947496530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.947496530
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4002907768
Short name T235
Test name
Test status
Simulation time 5368328949 ps
CPU time 72.07 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:51:28 PM PST 24
Peak memory 198816 kb
Host smart-b0a7315b-4c6d-4b0e-9e90-7c85fcd49c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002907768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4002907768
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.478069119
Short name T362
Test name
Test status
Simulation time 2167835744 ps
CPU time 28.98 seconds
Started Jan 14 01:50:19 PM PST 24
Finished Jan 14 01:50:49 PM PST 24
Peak memory 198868 kb
Host smart-a5902510-1feb-47c5-8c60-e877caceddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478069119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.478069119
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3372231969
Short name T809
Test name
Test status
Simulation time 455850968 ps
CPU time 3.16 seconds
Started Jan 14 01:50:18 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 198616 kb
Host smart-eda4424b-99eb-4288-aa5a-25b735ead8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372231969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3372231969
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2024996496
Short name T634
Test name
Test status
Simulation time 61081128204 ps
CPU time 257.9 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:54:39 PM PST 24
Peak memory 198908 kb
Host smart-af2ce106-137c-48b5-bd84-0c92856f446c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024996496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2024996496
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.4284999454
Short name T443
Test name
Test status
Simulation time 39950378185 ps
CPU time 629.41 seconds
Started Jan 14 01:50:10 PM PST 24
Finished Jan 14 02:00:44 PM PST 24
Peak memory 238856 kb
Host smart-d67f9c6b-5533-444a-9258-47d17d9ca131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284999454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.4284999454
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2263142373
Short name T533
Test name
Test status
Simulation time 105048524 ps
CPU time 1.05 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 196984 kb
Host smart-2427fe66-b529-428c-b4a3-e84a67340a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263142373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2263142373
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3382947381
Short name T371
Test name
Test status
Simulation time 1064709973 ps
CPU time 11.57 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:50:24 PM PST 24
Peak memory 198820 kb
Host smart-e32c5403-9d7b-41f3-99c2-9670030d38e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382947381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3382947381
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2331078978
Short name T565
Test name
Test status
Simulation time 10598345 ps
CPU time 0.59 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:49:59 PM PST 24
Peak memory 193128 kb
Host smart-9f06d793-07bb-4d05-a703-6e82f60cefc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331078978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2331078978
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3205240643
Short name T345
Test name
Test status
Simulation time 1365151255 ps
CPU time 10.48 seconds
Started Jan 14 01:50:07 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 198792 kb
Host smart-51e1f1cc-f484-4e21-8d8a-d8972b99440d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205240643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3205240643
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4227415138
Short name T387
Test name
Test status
Simulation time 2320404506 ps
CPU time 26 seconds
Started Jan 14 01:50:00 PM PST 24
Finished Jan 14 01:50:27 PM PST 24
Peak memory 198780 kb
Host smart-478e71ea-9971-49e3-b93c-6cb3c65262fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227415138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4227415138
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3499922355
Short name T255
Test name
Test status
Simulation time 1351701381 ps
CPU time 72.16 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 01:51:07 PM PST 24
Peak memory 198796 kb
Host smart-b9d92811-2fd1-4904-80a6-a247f8307dc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499922355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3499922355
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3832297938
Short name T419
Test name
Test status
Simulation time 13454463021 ps
CPU time 170.46 seconds
Started Jan 14 01:49:56 PM PST 24
Finished Jan 14 01:52:47 PM PST 24
Peak memory 198820 kb
Host smart-bd2d0acf-854f-4e98-b75a-4ad1c0c9df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832297938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3832297938
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2816385013
Short name T849
Test name
Test status
Simulation time 966663206 ps
CPU time 16.94 seconds
Started Jan 14 01:50:10 PM PST 24
Finished Jan 14 01:50:32 PM PST 24
Peak memory 198648 kb
Host smart-bfaa2e9a-775b-4738-818a-4d7c6290a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816385013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2816385013
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.966494034
Short name T462
Test name
Test status
Simulation time 345635600 ps
CPU time 2.15 seconds
Started Jan 14 01:50:02 PM PST 24
Finished Jan 14 01:50:06 PM PST 24
Peak memory 198744 kb
Host smart-83b42df4-f107-4485-b1d7-76e68eb2cbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966494034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.966494034
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4156599638
Short name T611
Test name
Test status
Simulation time 52606576341 ps
CPU time 573.57 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 01:59:28 PM PST 24
Peak memory 198876 kb
Host smart-714b6d9a-2095-491d-bad3-5e2bfe496d28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156599638 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4156599638
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.2623830211
Short name T93
Test name
Test status
Simulation time 49272894025 ps
CPU time 2617.69 seconds
Started Jan 14 01:49:54 PM PST 24
Finished Jan 14 02:33:32 PM PST 24
Peak memory 253064 kb
Host smart-306956ae-20c2-417b-a057-a0e5dadc5e52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623830211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.2623830211
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4284507117
Short name T228
Test name
Test status
Simulation time 91723867 ps
CPU time 0.94 seconds
Started Jan 14 01:49:59 PM PST 24
Finished Jan 14 01:50:02 PM PST 24
Peak memory 196136 kb
Host smart-e0190925-094a-4835-92f8-b38972ba528c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284507117 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4284507117
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3749904392
Short name T621
Test name
Test status
Simulation time 39879648380 ps
CPU time 463.74 seconds
Started Jan 14 01:49:55 PM PST 24
Finished Jan 14 01:57:39 PM PST 24
Peak memory 198788 kb
Host smart-4b010497-5462-4f34-898b-d57aa0fd72e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749904392 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3749904392
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3739902930
Short name T483
Test name
Test status
Simulation time 1590144820 ps
CPU time 17.43 seconds
Started Jan 14 01:49:58 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198700 kb
Host smart-d6f508c1-9aae-43f7-87dc-860393c94653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739902930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3739902930
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1196779271
Short name T360
Test name
Test status
Simulation time 13505665 ps
CPU time 0.61 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:48:11 PM PST 24
Peak memory 193220 kb
Host smart-869a768d-53f6-4155-8d4b-e23d7e7b9d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196779271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1196779271
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3988363298
Short name T193
Test name
Test status
Simulation time 1282606559 ps
CPU time 40.33 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 229528 kb
Host smart-c059f6e4-07de-45e9-a01c-254f5ff942a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988363298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3988363298
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2908519563
Short name T239
Test name
Test status
Simulation time 1358332686 ps
CPU time 26.99 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:48:39 PM PST 24
Peak memory 198768 kb
Host smart-ab8d928a-113b-431a-8f0a-d995af669f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908519563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2908519563
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.711422751
Short name T524
Test name
Test status
Simulation time 1656361534 ps
CPU time 42.27 seconds
Started Jan 14 01:48:09 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 198764 kb
Host smart-18daca6a-a30b-4c3c-a2e7-6358563abbe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711422751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.711422751
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1418463191
Short name T365
Test name
Test status
Simulation time 9335320155 ps
CPU time 235.99 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:52:09 PM PST 24
Peak memory 198844 kb
Host smart-49ba8bc3-074d-443f-8aed-da18dfae8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418463191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1418463191
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3547799998
Short name T501
Test name
Test status
Simulation time 17399915036 ps
CPU time 64.08 seconds
Started Jan 14 01:48:03 PM PST 24
Finished Jan 14 01:49:08 PM PST 24
Peak memory 198888 kb
Host smart-069c2803-f62c-4b6d-8a28-ae7beb91fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547799998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3547799998
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1386230352
Short name T49
Test name
Test status
Simulation time 122706876 ps
CPU time 0.78 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:48:14 PM PST 24
Peak memory 216052 kb
Host smart-2d9d3002-2672-4f45-b1cc-bf3b676ea0ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386230352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1386230352
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1727912318
Short name T444
Test name
Test status
Simulation time 131303658 ps
CPU time 2.08 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:48:16 PM PST 24
Peak memory 197916 kb
Host smart-547a8669-c2c3-45f8-bfb1-6b2e9bced8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727912318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1727912318
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3743696451
Short name T724
Test name
Test status
Simulation time 167748663406 ps
CPU time 1002.56 seconds
Started Jan 14 01:48:08 PM PST 24
Finished Jan 14 02:04:52 PM PST 24
Peak memory 227576 kb
Host smart-5af6316b-f2c0-4956-8a21-fc20db7535f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743696451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3743696451
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2415529587
Short name T91
Test name
Test status
Simulation time 91868069101 ps
CPU time 3162.24 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 02:40:55 PM PST 24
Peak memory 254504 kb
Host smart-5594d48b-2c65-4837-a3bc-97548c11863c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415529587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2415529587
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3095447177
Short name T440
Test name
Test status
Simulation time 32873156 ps
CPU time 1.09 seconds
Started Jan 14 01:48:07 PM PST 24
Finished Jan 14 01:48:09 PM PST 24
Peak memory 197784 kb
Host smart-05fb37e1-9c30-4daf-b484-cceedec314b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095447177 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3095447177
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4287282053
Short name T725
Test name
Test status
Simulation time 12591191756 ps
CPU time 53.18 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:49:06 PM PST 24
Peak memory 198904 kb
Host smart-1499770b-fe89-4c59-b873-83ce83a9f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287282053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4287282053
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2885877153
Short name T750
Test name
Test status
Simulation time 31366150 ps
CPU time 0.55 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 01:50:03 PM PST 24
Peak memory 193144 kb
Host smart-73f441af-4201-42af-ae28-14e8070f6266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885877153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2885877153
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3147742290
Short name T821
Test name
Test status
Simulation time 3143082625 ps
CPU time 58.58 seconds
Started Jan 14 01:50:07 PM PST 24
Finished Jan 14 01:51:11 PM PST 24
Peak memory 227492 kb
Host smart-55dfaa62-85c5-4bdc-90b2-ac3ba944bf86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147742290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3147742290
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3498261091
Short name T276
Test name
Test status
Simulation time 86417880 ps
CPU time 1.61 seconds
Started Jan 14 01:49:53 PM PST 24
Finished Jan 14 01:49:55 PM PST 24
Peak memory 198716 kb
Host smart-153c8594-3af2-4841-ba23-50d46e7ee6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498261091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3498261091
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2134875438
Short name T531
Test name
Test status
Simulation time 1607708094 ps
CPU time 80.93 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 01:51:23 PM PST 24
Peak memory 198820 kb
Host smart-2b99b97a-ac02-4b03-bfab-216b6522dd1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134875438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2134875438
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3441914536
Short name T755
Test name
Test status
Simulation time 810541544 ps
CPU time 6.86 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 01:50:09 PM PST 24
Peak memory 198268 kb
Host smart-730e23ec-f94d-4f4f-8604-baf35c734829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441914536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3441914536
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3202843171
Short name T595
Test name
Test status
Simulation time 4298246612 ps
CPU time 49.5 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:50:48 PM PST 24
Peak memory 198844 kb
Host smart-3d537f0a-a1fd-47f5-ab6c-212dfd6c3f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202843171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3202843171
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1430141080
Short name T390
Test name
Test status
Simulation time 165850620 ps
CPU time 2.2 seconds
Started Jan 14 01:49:58 PM PST 24
Finished Jan 14 01:50:01 PM PST 24
Peak memory 198696 kb
Host smart-ec56d88e-84c6-4f9d-bc15-5acf85715ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430141080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1430141080
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2163575746
Short name T261
Test name
Test status
Simulation time 69813113047 ps
CPU time 298.1 seconds
Started Jan 14 01:51:01 PM PST 24
Finished Jan 14 01:56:01 PM PST 24
Peak memory 207064 kb
Host smart-7479eeae-c9aa-468f-8874-bcc84f9c2f64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163575746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2163575746
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.2756050644
Short name T86
Test name
Test status
Simulation time 64022124234 ps
CPU time 1236.61 seconds
Started Jan 14 01:50:00 PM PST 24
Finished Jan 14 02:10:38 PM PST 24
Peak memory 235612 kb
Host smart-08548233-1026-4af6-94d9-222b5b67c170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756050644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.2756050644
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1361832262
Short name T543
Test name
Test status
Simulation time 211552521 ps
CPU time 1.18 seconds
Started Jan 14 01:49:55 PM PST 24
Finished Jan 14 01:49:57 PM PST 24
Peak memory 197812 kb
Host smart-c7e9a07d-cfc1-4821-b10d-f894b041884a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361832262 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1361832262
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2643117197
Short name T536
Test name
Test status
Simulation time 27621911757 ps
CPU time 455.8 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:57:34 PM PST 24
Peak memory 198812 kb
Host smart-23b3219a-8f09-4663-a6b6-e7f90d69c73f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643117197 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.2643117197
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1316649269
Short name T218
Test name
Test status
Simulation time 1819261074 ps
CPU time 6.64 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:50:19 PM PST 24
Peak memory 198824 kb
Host smart-1d721329-4a13-4f73-bcb1-8c7745c9b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316649269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1316649269
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.707272180
Short name T490
Test name
Test status
Simulation time 13092979 ps
CPU time 0.57 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 01:50:03 PM PST 24
Peak memory 194208 kb
Host smart-c0871dff-6ecc-4556-965f-8cc9d000beec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707272180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.707272180
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2646781008
Short name T412
Test name
Test status
Simulation time 927788608 ps
CPU time 27.38 seconds
Started Jan 14 01:50:10 PM PST 24
Finished Jan 14 01:50:42 PM PST 24
Peak memory 207056 kb
Host smart-8c7dff9b-0dbe-44f0-8ac4-8f1a2490caf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646781008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2646781008
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3802704679
Short name T575
Test name
Test status
Simulation time 807098890 ps
CPU time 15.21 seconds
Started Jan 14 01:50:10 PM PST 24
Finished Jan 14 01:50:30 PM PST 24
Peak memory 198812 kb
Host smart-1f90a967-87f4-4033-ba29-9d7febf5d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802704679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3802704679
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2150899929
Short name T719
Test name
Test status
Simulation time 4411869241 ps
CPU time 53.03 seconds
Started Jan 14 01:49:59 PM PST 24
Finished Jan 14 01:50:53 PM PST 24
Peak memory 198720 kb
Host smart-cc819934-2154-4595-925c-6a7b06dfc6ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150899929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2150899929
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1878128963
Short name T718
Test name
Test status
Simulation time 23594557990 ps
CPU time 191.86 seconds
Started Jan 14 01:49:57 PM PST 24
Finished Jan 14 01:53:10 PM PST 24
Peak memory 198816 kb
Host smart-32fc6388-dbbc-4d27-bd94-b14f2cebd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878128963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1878128963
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3970285306
Short name T699
Test name
Test status
Simulation time 1427030497 ps
CPU time 18.43 seconds
Started Jan 14 01:50:02 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 198780 kb
Host smart-e4a9117f-61a6-45ca-93c7-4b2e66fd6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970285306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3970285306
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4159901135
Short name T332
Test name
Test status
Simulation time 129983551 ps
CPU time 2.82 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 198688 kb
Host smart-2c02bf0c-03f4-4c62-95b2-fd290f3f59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159901135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4159901135
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2755376517
Short name T299
Test name
Test status
Simulation time 125718986795 ps
CPU time 1655.98 seconds
Started Jan 14 01:50:01 PM PST 24
Finished Jan 14 02:17:39 PM PST 24
Peak memory 198928 kb
Host smart-5c154d0b-bdeb-487e-9c69-0fd16fb28923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755376517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2755376517
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.1659083634
Short name T599
Test name
Test status
Simulation time 29338321578 ps
CPU time 545.29 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:59:17 PM PST 24
Peak memory 215356 kb
Host smart-60ebf0c7-16da-4850-94cd-e5908e0bd489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659083634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.1659083634
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1663513288
Short name T691
Test name
Test status
Simulation time 25644394 ps
CPU time 0.9 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 196104 kb
Host smart-f6367244-3a38-4eb5-9c39-843777e59e7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663513288 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1663513288
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1617842516
Short name T740
Test name
Test status
Simulation time 159197901593 ps
CPU time 432.08 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:57:33 PM PST 24
Peak memory 198836 kb
Host smart-8ecde8be-403b-420a-b09e-8f060e8bacaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617842516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1617842516
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1819824801
Short name T806
Test name
Test status
Simulation time 15003094461 ps
CPU time 54.49 seconds
Started Jan 14 01:50:02 PM PST 24
Finished Jan 14 01:50:59 PM PST 24
Peak memory 198912 kb
Host smart-7fb81281-c078-4d88-a5c9-52f8b01a9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819824801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1819824801
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1112953106
Short name T677
Test name
Test status
Simulation time 13190976 ps
CPU time 0.59 seconds
Started Jan 14 01:50:15 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 193248 kb
Host smart-c5a1d0e7-b4f3-43ba-91c7-7d1f4238ced9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112953106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1112953106
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.520644075
Short name T518
Test name
Test status
Simulation time 4681237190 ps
CPU time 39.82 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:55 PM PST 24
Peak memory 229956 kb
Host smart-8198d418-20b6-444e-b6da-358e503083df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520644075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.520644075
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2936264547
Short name T737
Test name
Test status
Simulation time 783397031 ps
CPU time 11.47 seconds
Started Jan 14 01:50:18 PM PST 24
Finished Jan 14 01:50:31 PM PST 24
Peak memory 198760 kb
Host smart-5277aff1-a305-4446-8550-9f269624a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936264547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2936264547
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3486069052
Short name T391
Test name
Test status
Simulation time 4673428707 ps
CPU time 57.12 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:51:09 PM PST 24
Peak memory 198848 kb
Host smart-5cd2ed6e-6ad0-43a8-9165-cdb22dfe28b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486069052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3486069052
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1580258615
Short name T493
Test name
Test status
Simulation time 14033776552 ps
CPU time 181.83 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:53:18 PM PST 24
Peak memory 198720 kb
Host smart-66f4f746-0078-4ee8-80b5-93995bd26838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580258615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1580258615
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1610265662
Short name T366
Test name
Test status
Simulation time 1076524074 ps
CPU time 3.97 seconds
Started Jan 14 01:50:07 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198792 kb
Host smart-e3bcfb48-b82c-4bd4-b6ef-f74baae1b2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610265662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1610265662
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.261522495
Short name T704
Test name
Test status
Simulation time 703384455 ps
CPU time 3.74 seconds
Started Jan 14 01:50:06 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 198876 kb
Host smart-e781bfe4-d07e-4f7f-8c4d-eec5138c2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261522495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.261522495
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.86214535
Short name T331
Test name
Test status
Simulation time 92955029680 ps
CPU time 283.79 seconds
Started Jan 14 01:50:14 PM PST 24
Finished Jan 14 01:55:01 PM PST 24
Peak memory 198948 kb
Host smart-60568e22-074a-4e7d-a89d-a059090f8bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86214535 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.86214535
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.4148176843
Short name T707
Test name
Test status
Simulation time 260718053043 ps
CPU time 1167.77 seconds
Started Jan 14 01:50:16 PM PST 24
Finished Jan 14 02:09:45 PM PST 24
Peak memory 239992 kb
Host smart-9691a095-cdf4-43b1-a8da-c312b048e716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148176843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.4148176843
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.175935449
Short name T544
Test name
Test status
Simulation time 260195451 ps
CPU time 0.88 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 195872 kb
Host smart-329d77ea-56ca-47b6-b61e-38b1c0b6cb1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175935449 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.175935449
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1192109051
Short name T706
Test name
Test status
Simulation time 34645249543 ps
CPU time 366.78 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:56:19 PM PST 24
Peak memory 198804 kb
Host smart-771ac5e8-9c91-46d4-9ef6-8cf48b3a3800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192109051 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.1192109051
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2211097402
Short name T799
Test name
Test status
Simulation time 3985022581 ps
CPU time 49.02 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:51:01 PM PST 24
Peak memory 198876 kb
Host smart-a11cf1dd-66dd-44da-a3ad-867c0637d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211097402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2211097402
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1358878534
Short name T295
Test name
Test status
Simulation time 81570653 ps
CPU time 0.63 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 193180 kb
Host smart-e272ea5b-e373-43ca-8d06-de90cd9051e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358878534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1358878534
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1742319594
Short name T204
Test name
Test status
Simulation time 1235309873 ps
CPU time 37.78 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:53 PM PST 24
Peak memory 207040 kb
Host smart-e5e1e0cf-f028-41fc-9231-f86a946bfe9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742319594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1742319594
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1515438366
Short name T548
Test name
Test status
Simulation time 447927504 ps
CPU time 19.22 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:50:40 PM PST 24
Peak memory 198820 kb
Host smart-fa24fb7c-e252-426a-a5ec-758cd6922561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515438366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1515438366
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1945860994
Short name T262
Test name
Test status
Simulation time 885682262 ps
CPU time 10.75 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:26 PM PST 24
Peak memory 198744 kb
Host smart-4092ad0c-d3c1-4d7d-ae80-4f36e7ee3b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945860994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1945860994
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2332331512
Short name T319
Test name
Test status
Simulation time 92304613471 ps
CPU time 61.88 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:51:23 PM PST 24
Peak memory 198872 kb
Host smart-a3b41808-8d29-48c2-9d71-b55aeebc1e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332331512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2332331512
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1145064678
Short name T786
Test name
Test status
Simulation time 300877841 ps
CPU time 15.12 seconds
Started Jan 14 01:50:15 PM PST 24
Finished Jan 14 01:50:32 PM PST 24
Peak memory 198852 kb
Host smart-dc22ad09-d5cc-40ca-9d9c-469ca28c3fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145064678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1145064678
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1789075164
Short name T340
Test name
Test status
Simulation time 228218762 ps
CPU time 1 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 197428 kb
Host smart-f993d7b6-7a50-4ba1-ae45-f579f9109a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789075164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1789075164
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1354373148
Short name T506
Test name
Test status
Simulation time 115548402586 ps
CPU time 686.81 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 02:01:42 PM PST 24
Peak memory 220824 kb
Host smart-c327198a-b56b-4257-b39f-9723f639529d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354373148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1354373148
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1866144586
Short name T824
Test name
Test status
Simulation time 478160521815 ps
CPU time 1499.28 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 02:15:21 PM PST 24
Peak memory 247604 kb
Host smart-f73be51b-ff6e-4a4d-a799-198bcd161dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866144586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1866144586
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2485187871
Short name T52
Test name
Test status
Simulation time 96826225 ps
CPU time 0.9 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 196028 kb
Host smart-e646db8a-e770-4680-bf6e-202013458581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485187871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2485187871
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3623787161
Short name T451
Test name
Test status
Simulation time 34633065859 ps
CPU time 444.1 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:57:36 PM PST 24
Peak memory 198824 kb
Host smart-e4a6d87b-6341-44cf-96f6-2d651d551214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623787161 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3623787161
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3595588391
Short name T591
Test name
Test status
Simulation time 1149767994 ps
CPU time 50.52 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:51:06 PM PST 24
Peak memory 198820 kb
Host smart-5cac1bd4-451c-4508-a6ce-bbd0ba985641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595588391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3595588391
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1297992400
Short name T744
Test name
Test status
Simulation time 12267409 ps
CPU time 0.56 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:50:16 PM PST 24
Peak memory 193136 kb
Host smart-ffa6e672-3261-4640-8575-b218856cea5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297992400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1297992400
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2613479402
Short name T439
Test name
Test status
Simulation time 1695044496 ps
CPU time 26.01 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:41 PM PST 24
Peak memory 215056 kb
Host smart-01449e8a-0803-4d3b-a10f-638531db07b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613479402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2613479402
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1230761882
Short name T497
Test name
Test status
Simulation time 581744142 ps
CPU time 9.04 seconds
Started Jan 14 01:50:19 PM PST 24
Finished Jan 14 01:50:29 PM PST 24
Peak memory 198824 kb
Host smart-8e184a11-3b73-4647-8a88-88e7c0d936d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230761882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1230761882
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.382278048
Short name T274
Test name
Test status
Simulation time 1364517430 ps
CPU time 37.95 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:50:50 PM PST 24
Peak memory 198772 kb
Host smart-2a6e1685-6f56-41c6-86bd-95c7b43920f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382278048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.382278048
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2628209563
Short name T731
Test name
Test status
Simulation time 8691631886 ps
CPU time 35.35 seconds
Started Jan 14 01:50:15 PM PST 24
Finished Jan 14 01:50:52 PM PST 24
Peak memory 198916 kb
Host smart-f485644d-618a-4113-9777-3f195ed5557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628209563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2628209563
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.901620633
Short name T546
Test name
Test status
Simulation time 6533580860 ps
CPU time 123.44 seconds
Started Jan 14 01:50:08 PM PST 24
Finished Jan 14 01:52:15 PM PST 24
Peak memory 198916 kb
Host smart-63fed4f0-f38c-484a-9adf-19da3e1bdf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901620633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.901620633
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.8512760
Short name T2
Test name
Test status
Simulation time 122211376 ps
CPU time 2.78 seconds
Started Jan 14 01:50:16 PM PST 24
Finished Jan 14 01:50:20 PM PST 24
Peak memory 198904 kb
Host smart-eb432772-b7c9-44a5-a9fe-8b3282fbf777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8512760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.8512760
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3886192490
Short name T592
Test name
Test status
Simulation time 766017904557 ps
CPU time 2310.87 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 02:28:46 PM PST 24
Peak memory 198844 kb
Host smart-f557508f-e0a8-4aac-a195-558349bc5255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886192490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3886192490
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.2368660576
Short name T59
Test name
Test status
Simulation time 135750765543 ps
CPU time 1403.11 seconds
Started Jan 14 01:50:19 PM PST 24
Finished Jan 14 02:13:43 PM PST 24
Peak memory 244020 kb
Host smart-4eaa8791-ae11-4eca-9460-dcc5a65bafe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368660576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.2368660576
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1341438815
Short name T616
Test name
Test status
Simulation time 83313140 ps
CPU time 0.96 seconds
Started Jan 14 01:50:15 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 196440 kb
Host smart-32576186-9183-44dd-96eb-221a9f72c9e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341438815 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1341438815
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.183076532
Short name T567
Test name
Test status
Simulation time 41840443199 ps
CPU time 461.93 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:58:03 PM PST 24
Peak memory 198464 kb
Host smart-36190eef-8f45-406c-8e71-320f391e15a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183076532 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.183076532
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.224961895
Short name T33
Test name
Test status
Simulation time 577600569 ps
CPU time 7.25 seconds
Started Jan 14 01:50:15 PM PST 24
Finished Jan 14 01:50:25 PM PST 24
Peak memory 198832 kb
Host smart-97931739-0af3-4aca-8980-5fd299ebbb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224961895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.224961895
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3644844516
Short name T618
Test name
Test status
Simulation time 13036547 ps
CPU time 0.55 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 193156 kb
Host smart-7216d75e-12e3-4b2f-976c-d0b16b416f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644844516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3644844516
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1980872202
Short name T682
Test name
Test status
Simulation time 1613538314 ps
CPU time 30.25 seconds
Started Jan 14 01:50:14 PM PST 24
Finished Jan 14 01:50:47 PM PST 24
Peak memory 223392 kb
Host smart-a48e5bfa-3edd-4f3f-a9a3-c82b86e8cfc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980872202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1980872202
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1476603261
Short name T339
Test name
Test status
Simulation time 784206946 ps
CPU time 35.73 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:50:52 PM PST 24
Peak memory 198796 kb
Host smart-9dd08fdc-4eed-4d25-9d4a-fb053580cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476603261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1476603261
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2966673515
Short name T238
Test name
Test status
Simulation time 2385906273 ps
CPU time 118.03 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:52:14 PM PST 24
Peak memory 198812 kb
Host smart-725d5df1-6635-4618-a694-9c1a32ad6cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966673515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2966673515
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3287948647
Short name T321
Test name
Test status
Simulation time 16490167156 ps
CPU time 188.4 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:53:24 PM PST 24
Peak memory 198884 kb
Host smart-374b1b0d-e6cf-48bc-892d-8eceae1abfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287948647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3287948647
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3835027118
Short name T297
Test name
Test status
Simulation time 2136398303 ps
CPU time 26.12 seconds
Started Jan 14 01:50:14 PM PST 24
Finished Jan 14 01:50:42 PM PST 24
Peak memory 198856 kb
Host smart-57eb801c-8968-4317-a074-2009cbb26e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835027118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3835027118
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2171557365
Short name T630
Test name
Test status
Simulation time 85727427 ps
CPU time 2.18 seconds
Started Jan 14 01:50:11 PM PST 24
Finished Jan 14 01:50:17 PM PST 24
Peak memory 198704 kb
Host smart-af520536-c107-4954-9f46-85b5a77b66b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171557365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2171557365
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3083923783
Short name T476
Test name
Test status
Simulation time 41183106305 ps
CPU time 452.23 seconds
Started Jan 14 01:50:13 PM PST 24
Finished Jan 14 01:57:48 PM PST 24
Peak memory 198888 kb
Host smart-a64defc9-7450-4c53-8afe-91d48f2e2db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083923783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3083923783
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.2848968235
Short name T851
Test name
Test status
Simulation time 140329437722 ps
CPU time 1665.46 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 02:18:06 PM PST 24
Peak memory 256008 kb
Host smart-aca5f9db-4a76-45ed-8fc1-ab9513f88c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848968235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.2848968235
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.638091194
Short name T792
Test name
Test status
Simulation time 32635969 ps
CPU time 1.04 seconds
Started Jan 14 01:50:19 PM PST 24
Finished Jan 14 01:50:21 PM PST 24
Peak memory 197448 kb
Host smart-d16c1145-02cb-4c79-8a5d-5498648b62bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638091194 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.638091194
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3174215146
Short name T566
Test name
Test status
Simulation time 27230739629 ps
CPU time 441.53 seconds
Started Jan 14 01:50:20 PM PST 24
Finished Jan 14 01:57:43 PM PST 24
Peak memory 198840 kb
Host smart-4a3c6b59-811c-4bd5-a424-8591ddc3c98b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174215146 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3174215146
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2007609467
Short name T202
Test name
Test status
Simulation time 2715239877 ps
CPU time 51.67 seconds
Started Jan 14 01:50:12 PM PST 24
Finished Jan 14 01:51:07 PM PST 24
Peak memory 198872 kb
Host smart-a65acb21-4e1f-46cb-80b1-ae8ddde91beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007609467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2007609467
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3915206201
Short name T337
Test name
Test status
Simulation time 41537758 ps
CPU time 0.57 seconds
Started Jan 14 01:50:26 PM PST 24
Finished Jan 14 01:50:29 PM PST 24
Peak memory 193188 kb
Host smart-b9deb53e-86f2-47a8-be9b-3492f379c0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915206201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3915206201
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1553649666
Short name T284
Test name
Test status
Simulation time 118918700 ps
CPU time 3.28 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:50:28 PM PST 24
Peak memory 198712 kb
Host smart-8e1f82c6-21c9-4173-8ad1-fa1dd5b76ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553649666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1553649666
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2248485643
Short name T499
Test name
Test status
Simulation time 2089642990 ps
CPU time 27.6 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:50:52 PM PST 24
Peak memory 198780 kb
Host smart-e54c1e0e-ad57-4b1b-9807-219b14af9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248485643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2248485643
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.407896414
Short name T667
Test name
Test status
Simulation time 8456876415 ps
CPU time 87.66 seconds
Started Jan 14 01:50:22 PM PST 24
Finished Jan 14 01:51:50 PM PST 24
Peak memory 198800 kb
Host smart-e6d6a3a2-0374-47ed-a812-498aa6f86162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407896414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.407896414
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2107846693
Short name T185
Test name
Test status
Simulation time 1736754984 ps
CPU time 27.17 seconds
Started Jan 14 01:50:21 PM PST 24
Finished Jan 14 01:50:49 PM PST 24
Peak memory 198644 kb
Host smart-0a1f51a3-effa-4a53-8644-fa39a183ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107846693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2107846693
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3489729657
Short name T264
Test name
Test status
Simulation time 15117408882 ps
CPU time 106.06 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:52:12 PM PST 24
Peak memory 198892 kb
Host smart-c68773d2-fe04-4710-9418-35395805227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489729657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3489729657
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.908918322
Short name T367
Test name
Test status
Simulation time 163811495 ps
CPU time 2.2 seconds
Started Jan 14 01:50:09 PM PST 24
Finished Jan 14 01:50:14 PM PST 24
Peak memory 198620 kb
Host smart-43412620-9697-4fa4-b670-36e6bec2f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908918322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.908918322
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.117043720
Short name T454
Test name
Test status
Simulation time 32670703744 ps
CPU time 734.89 seconds
Started Jan 14 01:50:22 PM PST 24
Finished Jan 14 02:02:38 PM PST 24
Peak memory 231636 kb
Host smart-0b245855-f560-48f3-a7c1-1994fd626f3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117043720 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.117043720
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.2654366590
Short name T89
Test name
Test status
Simulation time 254630462809 ps
CPU time 1170.42 seconds
Started Jan 14 01:50:25 PM PST 24
Finished Jan 14 02:09:57 PM PST 24
Peak memory 253488 kb
Host smart-3d791c7b-17f6-4422-87cb-b20171339a84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654366590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.2654366590
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.103061227
Short name T408
Test name
Test status
Simulation time 176710612 ps
CPU time 0.95 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:50:30 PM PST 24
Peak memory 196468 kb
Host smart-8c2be055-d736-4b85-97c3-b8c8355192c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103061227 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.103061227
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3052560026
Short name T11
Test name
Test status
Simulation time 116732898640 ps
CPU time 448.47 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:57:55 PM PST 24
Peak memory 198780 kb
Host smart-a6477ac9-ebce-4db9-ada6-22d2c23f1d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052560026 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.3052560026
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3530799256
Short name T420
Test name
Test status
Simulation time 3382617526 ps
CPU time 49.97 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:51:15 PM PST 24
Peak memory 198816 kb
Host smart-7153a120-4b4f-4bf7-b3d9-6c35b559a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530799256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3530799256
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.498438426
Short name T547
Test name
Test status
Simulation time 12634845 ps
CPU time 0.6 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:50:34 PM PST 24
Peak memory 194212 kb
Host smart-8ea99b03-b65d-40d5-98dd-47309b6b30d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498438426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.498438426
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.342196939
Short name T475
Test name
Test status
Simulation time 2586994786 ps
CPU time 22.48 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:50:51 PM PST 24
Peak memory 217196 kb
Host smart-1f42085f-2c34-4f3b-b40f-07ee75cf244f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342196939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.342196939
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.233014002
Short name T400
Test name
Test status
Simulation time 299663228 ps
CPU time 12.78 seconds
Started Jan 14 01:50:28 PM PST 24
Finished Jan 14 01:50:48 PM PST 24
Peak memory 198788 kb
Host smart-d073f24f-d09b-42ef-b362-59464f029feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233014002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.233014002
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4191741992
Short name T665
Test name
Test status
Simulation time 2872814387 ps
CPU time 144.49 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:52:58 PM PST 24
Peak memory 198840 kb
Host smart-efce7ee8-69f7-4f1f-9362-fc922c45a427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191741992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4191741992
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1785148420
Short name T648
Test name
Test status
Simulation time 35951023286 ps
CPU time 157.24 seconds
Started Jan 14 01:50:26 PM PST 24
Finished Jan 14 01:53:06 PM PST 24
Peak memory 198892 kb
Host smart-7b4abbdb-52db-42f5-a7dc-27299b1fd9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785148420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1785148420
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.288344117
Short name T535
Test name
Test status
Simulation time 1007500084 ps
CPU time 17.27 seconds
Started Jan 14 01:50:23 PM PST 24
Finished Jan 14 01:50:41 PM PST 24
Peak memory 198728 kb
Host smart-395a6460-1a21-4929-b787-8b257db2ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288344117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.288344117
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1964870481
Short name T368
Test name
Test status
Simulation time 148454311 ps
CPU time 3.55 seconds
Started Jan 14 01:50:24 PM PST 24
Finished Jan 14 01:50:29 PM PST 24
Peak memory 198712 kb
Host smart-620ea616-bdd8-4d18-844c-1e8678822897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964870481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1964870481
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.347492430
Short name T307
Test name
Test status
Simulation time 210867316065 ps
CPU time 810.55 seconds
Started Jan 14 01:50:23 PM PST 24
Finished Jan 14 02:03:54 PM PST 24
Peak memory 198896 kb
Host smart-36dba105-658b-49be-b655-803a11723e63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347492430 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.347492430
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.3699046550
Short name T309
Test name
Test status
Simulation time 91454098716 ps
CPU time 206.21 seconds
Started Jan 14 01:50:31 PM PST 24
Finished Jan 14 01:54:03 PM PST 24
Peak memory 215356 kb
Host smart-27f8df12-9f38-480f-aed2-079fc15f9283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699046550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.3699046550
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2907088729
Short name T243
Test name
Test status
Simulation time 31905536 ps
CPU time 1.14 seconds
Started Jan 14 01:50:25 PM PST 24
Finished Jan 14 01:50:28 PM PST 24
Peak memory 197872 kb
Host smart-d287176e-b47b-40e9-8b2a-46dbf565d3e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907088729 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2907088729
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3940767033
Short name T819
Test name
Test status
Simulation time 35563849730 ps
CPU time 442.97 seconds
Started Jan 14 01:50:25 PM PST 24
Finished Jan 14 01:57:50 PM PST 24
Peak memory 198840 kb
Host smart-926bb944-6034-4877-82ff-da6a59ca54f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940767033 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3940767033
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1126794716
Short name T705
Test name
Test status
Simulation time 737264510 ps
CPU time 7.24 seconds
Started Jan 14 01:50:28 PM PST 24
Finished Jan 14 01:50:43 PM PST 24
Peak memory 198784 kb
Host smart-bd871fe8-9d4a-4e25-b7e1-9c6d8ea292c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126794716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1126794716
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3525393030
Short name T402
Test name
Test status
Simulation time 37120134 ps
CPU time 0.55 seconds
Started Jan 14 01:50:35 PM PST 24
Finished Jan 14 01:50:39 PM PST 24
Peak memory 193124 kb
Host smart-d072071f-f210-4d87-8289-3bba7d7d9dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525393030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3525393030
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1192658180
Short name T617
Test name
Test status
Simulation time 6732472879 ps
CPU time 40.64 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:51:13 PM PST 24
Peak memory 223664 kb
Host smart-c1af4c80-30a6-4f83-94ca-6702569ed5ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192658180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1192658180
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3623489751
Short name T573
Test name
Test status
Simulation time 1995160722 ps
CPU time 9.13 seconds
Started Jan 14 01:50:27 PM PST 24
Finished Jan 14 01:50:42 PM PST 24
Peak memory 198772 kb
Host smart-e2d83d1f-33a8-423c-82aa-344df1038039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623489751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3623489751
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.690692242
Short name T201
Test name
Test status
Simulation time 1922563517 ps
CPU time 91.54 seconds
Started Jan 14 01:50:30 PM PST 24
Finished Jan 14 01:52:08 PM PST 24
Peak memory 198808 kb
Host smart-5bcb5040-c4dc-40e5-8774-e0a742215ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690692242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.690692242
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4203282685
Short name T442
Test name
Test status
Simulation time 3388578922 ps
CPU time 41.89 seconds
Started Jan 14 01:50:28 PM PST 24
Finished Jan 14 01:51:18 PM PST 24
Peak memory 198844 kb
Host smart-adc0f305-3a9d-4dd4-9939-a157626a0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203282685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4203282685
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1037575122
Short name T615
Test name
Test status
Simulation time 8046343822 ps
CPU time 29.31 seconds
Started Jan 14 01:50:29 PM PST 24
Finished Jan 14 01:51:06 PM PST 24
Peak memory 198844 kb
Host smart-066f2325-8909-4966-8ac0-9e6744e1f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037575122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1037575122
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2206074106
Short name T467
Test name
Test status
Simulation time 570475043 ps
CPU time 4.33 seconds
Started Jan 14 01:50:34 PM PST 24
Finished Jan 14 01:50:41 PM PST 24
Peak memory 198580 kb
Host smart-ffbc8bc8-22b0-4d62-88c0-ba2e91a6f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206074106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2206074106
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3935902447
Short name T280
Test name
Test status
Simulation time 6875718913 ps
CPU time 94.46 seconds
Started Jan 14 01:50:35 PM PST 24
Finished Jan 14 01:52:14 PM PST 24
Peak memory 198888 kb
Host smart-b132ed6b-d05a-454d-aa3a-b742824f87e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935902447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3935902447
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3838703957
Short name T654
Test name
Test status
Simulation time 255933850 ps
CPU time 1.18 seconds
Started Jan 14 01:50:38 PM PST 24
Finished Jan 14 01:50:43 PM PST 24
Peak memory 197556 kb
Host smart-9ee37637-5694-4e8a-b3e3-7f3384690f11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838703957 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3838703957
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3064974718
Short name T730
Test name
Test status
Simulation time 44597955070 ps
CPU time 410.19 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:57:31 PM PST 24
Peak memory 198884 kb
Host smart-5ee4c52c-8071-4eb2-b7ab-a7be92271c46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064974718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.3064974718
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1512227101
Short name T556
Test name
Test status
Simulation time 22396894054 ps
CPU time 67.21 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:51:48 PM PST 24
Peak memory 198880 kb
Host smart-6198e706-a2f6-4dcf-923f-bdd8a16e44b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512227101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1512227101
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2648927532
Short name T288
Test name
Test status
Simulation time 31640478 ps
CPU time 0.57 seconds
Started Jan 14 01:50:44 PM PST 24
Finished Jan 14 01:50:45 PM PST 24
Peak memory 193144 kb
Host smart-3cb20bde-14cb-4f2d-aea5-921d28be3a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648927532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2648927532
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3284722855
Short name T767
Test name
Test status
Simulation time 1969340823 ps
CPU time 32.63 seconds
Started Jan 14 01:50:37 PM PST 24
Finished Jan 14 01:51:14 PM PST 24
Peak memory 225484 kb
Host smart-aaac33e5-1aeb-44ab-a617-a7082e736eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284722855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3284722855
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.4121306380
Short name T278
Test name
Test status
Simulation time 7843498554 ps
CPU time 37.19 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:51:18 PM PST 24
Peak memory 198920 kb
Host smart-25bfa12c-6a14-476d-9e5a-7447cdd750b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121306380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.4121306380
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1672079945
Short name T815
Test name
Test status
Simulation time 4014982008 ps
CPU time 52.1 seconds
Started Jan 14 01:50:37 PM PST 24
Finished Jan 14 01:51:33 PM PST 24
Peak memory 198872 kb
Host smart-c59a5dd6-a29a-4d0f-92e3-1f4bd5b2bc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672079945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1672079945
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.738743280
Short name T636
Test name
Test status
Simulation time 3850448600 ps
CPU time 97.62 seconds
Started Jan 14 01:50:41 PM PST 24
Finished Jan 14 01:52:21 PM PST 24
Peak memory 198964 kb
Host smart-c5a79bc6-2817-4c6a-9dec-b5911e11ab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738743280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.738743280
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3473330762
Short name T416
Test name
Test status
Simulation time 31816570 ps
CPU time 1.52 seconds
Started Jan 14 01:50:38 PM PST 24
Finished Jan 14 01:50:43 PM PST 24
Peak memory 198840 kb
Host smart-d588a0e8-af3a-429d-a3be-0cbd9fc641f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473330762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3473330762
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1757764555
Short name T723
Test name
Test status
Simulation time 194256439 ps
CPU time 2.95 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:50:44 PM PST 24
Peak memory 198556 kb
Host smart-2f65c071-637b-4907-b8c6-35e7b6fc116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757764555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1757764555
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2249216540
Short name T620
Test name
Test status
Simulation time 954364828 ps
CPU time 43.95 seconds
Started Jan 14 01:50:42 PM PST 24
Finished Jan 14 01:51:28 PM PST 24
Peak memory 198844 kb
Host smart-a958f1c5-4919-42fa-bf98-a71c16978f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249216540 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2249216540
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3190053722
Short name T237
Test name
Test status
Simulation time 20183132744 ps
CPU time 304.68 seconds
Started Jan 14 01:50:37 PM PST 24
Finished Jan 14 01:55:46 PM PST 24
Peak memory 226672 kb
Host smart-d7191015-8862-4c56-bf72-b49a340428ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190053722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.3190053722
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.285948046
Short name T236
Test name
Test status
Simulation time 133985834 ps
CPU time 1.22 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:50:42 PM PST 24
Peak memory 197196 kb
Host smart-354c446a-72d0-4982-861f-6c248a41da88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285948046 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_hmac_vectors.285948046
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2872828452
Short name T510
Test name
Test status
Simulation time 164172444482 ps
CPU time 487.1 seconds
Started Jan 14 01:50:37 PM PST 24
Finished Jan 14 01:58:49 PM PST 24
Peak memory 198696 kb
Host smart-e3516d79-540e-44a7-b5ad-b5a0b3d12537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872828452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.2872828452
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3043384995
Short name T186
Test name
Test status
Simulation time 478394784 ps
CPU time 4.83 seconds
Started Jan 14 01:50:35 PM PST 24
Finished Jan 14 01:50:44 PM PST 24
Peak memory 198540 kb
Host smart-6d17fc48-2db3-4ff8-b81d-db3546f80ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043384995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3043384995
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3279709907
Short name T785
Test name
Test status
Simulation time 49687403 ps
CPU time 0.6 seconds
Started Jan 14 01:48:13 PM PST 24
Finished Jan 14 01:48:15 PM PST 24
Peak memory 193180 kb
Host smart-c94b2837-553e-410b-8d4f-9be3da75aa00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279709907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3279709907
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3024269872
Short name T304
Test name
Test status
Simulation time 1850419095 ps
CPU time 28.5 seconds
Started Jan 14 01:48:08 PM PST 24
Finished Jan 14 01:48:37 PM PST 24
Peak memory 217168 kb
Host smart-14184eb6-b7ae-4b66-a4e0-a57257dd0342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024269872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3024269872
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3298184635
Short name T751
Test name
Test status
Simulation time 3083661736 ps
CPU time 42.4 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:48:55 PM PST 24
Peak memory 198916 kb
Host smart-0200d30d-5fc2-4873-980a-896cfba57604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298184635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3298184635
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1091007336
Short name T820
Test name
Test status
Simulation time 918263511 ps
CPU time 45.83 seconds
Started Jan 14 01:48:09 PM PST 24
Finished Jan 14 01:48:56 PM PST 24
Peak memory 198684 kb
Host smart-48e99951-d43d-4373-bd97-30471de03856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091007336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1091007336
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.102808821
Short name T552
Test name
Test status
Simulation time 6413045958 ps
CPU time 82.74 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 198888 kb
Host smart-8abbcaa1-a902-4abf-9299-a7b621f19c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102808821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.102808821
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2697350110
Short name T832
Test name
Test status
Simulation time 4695223941 ps
CPU time 25.67 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:48:38 PM PST 24
Peak memory 198840 kb
Host smart-43117dbd-afed-48a9-bdfc-0c9e744d4f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697350110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2697350110
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.3134421041
Short name T214
Test name
Test status
Simulation time 1047576956 ps
CPU time 1.58 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:48:14 PM PST 24
Peak memory 198560 kb
Host smart-c2f7d3eb-90ad-4416-866d-87fc63f7b6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134421041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3134421041
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.255737617
Short name T814
Test name
Test status
Simulation time 148898123786 ps
CPU time 601.11 seconds
Started Jan 14 01:48:09 PM PST 24
Finished Jan 14 01:58:11 PM PST 24
Peak memory 198856 kb
Host smart-652f1078-4bbb-4f7b-ba77-68e93cc8fcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255737617 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.255737617
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1812800285
Short name T314
Test name
Test status
Simulation time 50915658698 ps
CPU time 2562.22 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 02:30:54 PM PST 24
Peak memory 240908 kb
Host smart-566e77b1-cd33-43b3-8d46-f32cf32ee9b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812800285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1812800285
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3156455491
Short name T512
Test name
Test status
Simulation time 861749984 ps
CPU time 1.19 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:48:13 PM PST 24
Peak memory 197208 kb
Host smart-24abc322-0f47-4470-ae4d-d90ae7786283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156455491 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3156455491
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2412154085
Short name T260
Test name
Test status
Simulation time 31033362012 ps
CPU time 441.88 seconds
Started Jan 14 01:48:09 PM PST 24
Finished Jan 14 01:55:32 PM PST 24
Peak memory 198796 kb
Host smart-28debfb6-56a4-423f-bfb5-225a5583ea5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412154085 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.2412154085
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2073314017
Short name T650
Test name
Test status
Simulation time 4838559519 ps
CPU time 32.55 seconds
Started Jan 14 01:48:12 PM PST 24
Finished Jan 14 01:48:45 PM PST 24
Peak memory 198836 kb
Host smart-b7e17d55-4cf7-4854-b916-a2bf12508801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073314017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2073314017
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4009578909
Short name T270
Test name
Test status
Simulation time 43097396 ps
CPU time 0.54 seconds
Started Jan 14 01:50:50 PM PST 24
Finished Jan 14 01:50:53 PM PST 24
Peak memory 193108 kb
Host smart-1b322dc5-eecd-4be0-8e9b-c5efeacf1352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009578909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4009578909
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2025644659
Short name T110
Test name
Test status
Simulation time 1061049958 ps
CPU time 31.59 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:51:12 PM PST 24
Peak memory 211176 kb
Host smart-6b415d30-7981-4bc8-bbe1-ef00969fa940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025644659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2025644659
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2201685468
Short name T581
Test name
Test status
Simulation time 26804882770 ps
CPU time 46.89 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:51:31 PM PST 24
Peak memory 198864 kb
Host smart-31179a7b-4b7c-4eb4-a61b-210bff45dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201685468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2201685468
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2672396694
Short name T643
Test name
Test status
Simulation time 2482067915 ps
CPU time 65.24 seconds
Started Jan 14 01:50:39 PM PST 24
Finished Jan 14 01:51:47 PM PST 24
Peak memory 198864 kb
Host smart-ce3505bd-171e-4923-8336-694650c1f4e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672396694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2672396694
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.563202601
Short name T433
Test name
Test status
Simulation time 552980167 ps
CPU time 9.24 seconds
Started Jan 14 01:50:44 PM PST 24
Finished Jan 14 01:50:54 PM PST 24
Peak memory 198764 kb
Host smart-4313dde1-1b88-49ef-a67d-1f94d1a83ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563202601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.563202601
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.336882588
Short name T357
Test name
Test status
Simulation time 13709161165 ps
CPU time 54.99 seconds
Started Jan 14 01:50:36 PM PST 24
Finished Jan 14 01:51:35 PM PST 24
Peak memory 198804 kb
Host smart-ab8f2878-1ef8-4a5b-a9af-b1dc901dcedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336882588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.336882588
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2083912557
Short name T373
Test name
Test status
Simulation time 79966837 ps
CPU time 1.29 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:50:45 PM PST 24
Peak memory 198752 kb
Host smart-893b7877-e03d-4749-a790-d452bf6d211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083912557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2083912557
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3164874350
Short name T787
Test name
Test status
Simulation time 16958739082 ps
CPU time 415.04 seconds
Started Jan 14 01:50:42 PM PST 24
Finished Jan 14 01:57:39 PM PST 24
Peak memory 198832 kb
Host smart-774fdd60-b555-484a-a888-40e2c0ea3584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164874350 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3164874350
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.2156410985
Short name T637
Test name
Test status
Simulation time 287936162729 ps
CPU time 2657.17 seconds
Started Jan 14 01:50:49 PM PST 24
Finished Jan 14 02:35:09 PM PST 24
Peak memory 242864 kb
Host smart-2b9615ae-2646-4ee4-82a7-2b9a527d4c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156410985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.2156410985
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.552427563
Short name T189
Test name
Test status
Simulation time 161656320 ps
CPU time 0.92 seconds
Started Jan 14 01:50:42 PM PST 24
Finished Jan 14 01:50:45 PM PST 24
Peak memory 196764 kb
Host smart-5486d6a1-794a-4d1a-81fa-6a207bd8106d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552427563 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.552427563
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.714908744
Short name T219
Test name
Test status
Simulation time 44116705070 ps
CPU time 505.65 seconds
Started Jan 14 01:50:46 PM PST 24
Finished Jan 14 01:59:12 PM PST 24
Peak memory 198836 kb
Host smart-e8775f5d-62e0-458d-8b07-4af866f8e1c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714908744 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_sha_vectors.714908744
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.528538388
Short name T197
Test name
Test status
Simulation time 3266963340 ps
CPU time 37.58 seconds
Started Jan 14 01:50:37 PM PST 24
Finished Jan 14 01:51:19 PM PST 24
Peak memory 198836 kb
Host smart-6dcb12bd-75b6-4e60-bc80-bf153ea968a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528538388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.528538388
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1739356224
Short name T449
Test name
Test status
Simulation time 37372718 ps
CPU time 0.57 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:50:45 PM PST 24
Peak memory 193192 kb
Host smart-d61d1166-bb43-42f7-9297-89ae1c4fc75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739356224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1739356224
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1862087592
Short name T249
Test name
Test status
Simulation time 467396135 ps
CPU time 14.4 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:16 PM PST 24
Peak memory 206892 kb
Host smart-79a58401-36b3-4c7e-86ec-5b5f0ad40edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862087592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1862087592
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1791625916
Short name T658
Test name
Test status
Simulation time 1178122932 ps
CPU time 38.85 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:51:49 PM PST 24
Peak memory 198660 kb
Host smart-8622dedb-3dca-4a92-ac43-1914bfb2faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791625916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1791625916
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2554223731
Short name T474
Test name
Test status
Simulation time 1726035637 ps
CPU time 22.79 seconds
Started Jan 14 01:50:50 PM PST 24
Finished Jan 14 01:51:15 PM PST 24
Peak memory 198756 kb
Host smart-89b41a7a-f101-4498-97a5-b83645f85217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554223731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2554223731
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3178419051
Short name T562
Test name
Test status
Simulation time 81795055700 ps
CPU time 121.79 seconds
Started Jan 14 01:50:56 PM PST 24
Finished Jan 14 01:52:59 PM PST 24
Peak memory 198824 kb
Host smart-c3e48e5d-9107-45bd-8517-11e703e207d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178419051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3178419051
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3674354101
Short name T241
Test name
Test status
Simulation time 2788703826 ps
CPU time 49.98 seconds
Started Jan 14 01:50:44 PM PST 24
Finished Jan 14 01:51:35 PM PST 24
Peak memory 198904 kb
Host smart-46111a64-f5db-4d0d-913a-11c40ba69306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674354101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3674354101
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1704305998
Short name T356
Test name
Test status
Simulation time 448016086 ps
CPU time 4.7 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:50:49 PM PST 24
Peak memory 198784 kb
Host smart-d3b9cf37-6ef4-4a37-b6cb-cf4ab35679dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704305998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1704305998
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4215058758
Short name T626
Test name
Test status
Simulation time 3907889255 ps
CPU time 55.55 seconds
Started Jan 14 01:50:57 PM PST 24
Finished Jan 14 01:51:54 PM PST 24
Peak memory 198780 kb
Host smart-b00fb5cd-9a88-49ec-bfa6-d7a78135e9c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215058758 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4215058758
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1971811826
Short name T781
Test name
Test status
Simulation time 42062454652 ps
CPU time 1645.13 seconds
Started Jan 14 01:50:56 PM PST 24
Finished Jan 14 02:18:22 PM PST 24
Peak memory 247396 kb
Host smart-e2d8d98b-5ba4-41a8-a126-3593fa53e16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971811826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1971811826
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2896482232
Short name T823
Test name
Test status
Simulation time 117560797 ps
CPU time 1.04 seconds
Started Jan 14 01:50:45 PM PST 24
Finished Jan 14 01:50:47 PM PST 24
Peak memory 197148 kb
Host smart-050b3eea-7a36-4952-add7-b0c4a9c21af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896482232 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2896482232
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2087209255
Short name T378
Test name
Test status
Simulation time 36830585704 ps
CPU time 443.31 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:58:26 PM PST 24
Peak memory 198804 kb
Host smart-358feff3-7ca9-49d4-8239-b85c22dcc25e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087209255 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.2087209255
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3275984027
Short name T252
Test name
Test status
Simulation time 7735456562 ps
CPU time 93.22 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:52:36 PM PST 24
Peak memory 198876 kb
Host smart-e6268be2-d46e-4992-9de3-d8fb8070a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275984027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3275984027
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2163891216
Short name T570
Test name
Test status
Simulation time 12664155 ps
CPU time 0.64 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:51:11 PM PST 24
Peak memory 193020 kb
Host smart-3f2a90b7-1044-41c7-b5fe-041066c7979d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163891216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2163891216
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.728170494
Short name T840
Test name
Test status
Simulation time 706329565 ps
CPU time 23.41 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:25 PM PST 24
Peak memory 199712 kb
Host smart-285a8928-2bba-4fff-a3ff-0777f43c01db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728170494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.728170494
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2294693108
Short name T251
Test name
Test status
Simulation time 14014804661 ps
CPU time 54.02 seconds
Started Jan 14 01:50:46 PM PST 24
Finished Jan 14 01:51:40 PM PST 24
Peak memory 198888 kb
Host smart-b3e12a88-97e0-4074-88ed-b2f6773ff07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294693108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2294693108
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1224152391
Short name T285
Test name
Test status
Simulation time 9491867480 ps
CPU time 133.73 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:53:24 PM PST 24
Peak memory 198708 kb
Host smart-4854aaba-cadc-4b1a-bd5c-1e1ed75a614f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224152391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1224152391
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1367800537
Short name T470
Test name
Test status
Simulation time 125005161802 ps
CPU time 225.27 seconds
Started Jan 14 01:50:57 PM PST 24
Finished Jan 14 01:54:44 PM PST 24
Peak memory 198788 kb
Host smart-1e503ab9-409e-44c6-a350-160b1976924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367800537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1367800537
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1182886319
Short name T426
Test name
Test status
Simulation time 4002976773 ps
CPU time 50.49 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:51:35 PM PST 24
Peak memory 198736 kb
Host smart-025262a2-d0e2-4be8-9951-d0010eb5d93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182886319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1182886319
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2616094557
Short name T619
Test name
Test status
Simulation time 1782300465 ps
CPU time 2.73 seconds
Started Jan 14 01:50:48 PM PST 24
Finished Jan 14 01:50:53 PM PST 24
Peak memory 198816 kb
Host smart-6cb97868-1928-4c24-9677-702637ec05c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616094557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2616094557
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1050441830
Short name T269
Test name
Test status
Simulation time 66092233394 ps
CPU time 796.01 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 02:04:26 PM PST 24
Peak memory 235620 kb
Host smart-bf74c85f-9755-4b11-8f07-128f998e516b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050441830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1050441830
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.336269146
Short name T353
Test name
Test status
Simulation time 81464674610 ps
CPU time 1149.43 seconds
Started Jan 14 01:50:48 PM PST 24
Finished Jan 14 02:10:00 PM PST 24
Peak memory 247704 kb
Host smart-8956f84b-8500-4583-86fc-07dedf0fcd18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336269146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.336269146
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2938740341
Short name T773
Test name
Test status
Simulation time 33565118 ps
CPU time 1.08 seconds
Started Jan 14 01:50:49 PM PST 24
Finished Jan 14 01:50:52 PM PST 24
Peak memory 196832 kb
Host smart-20ac8834-40b6-4cbc-85a9-cae428796ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938740341 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2938740341
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3178595342
Short name T272
Test name
Test status
Simulation time 88347288188 ps
CPU time 431.68 seconds
Started Jan 14 01:50:43 PM PST 24
Finished Jan 14 01:57:56 PM PST 24
Peak memory 198844 kb
Host smart-a07c0a58-31e4-400a-9a57-00dd2cdb6b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178595342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.3178595342
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.896017258
Short name T409
Test name
Test status
Simulation time 2992745963 ps
CPU time 51.42 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:52:02 PM PST 24
Peak memory 198760 kb
Host smart-7990bd0d-30d5-45ed-80b9-6803f3e5139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896017258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.896017258
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1555433890
Short name T324
Test name
Test status
Simulation time 14288609 ps
CPU time 0.53 seconds
Started Jan 14 01:50:48 PM PST 24
Finished Jan 14 01:50:50 PM PST 24
Peak memory 193152 kb
Host smart-b7a62725-732e-4a95-85a1-53a6b8efc13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555433890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1555433890
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1824487607
Short name T279
Test name
Test status
Simulation time 2883581149 ps
CPU time 21.83 seconds
Started Jan 14 01:50:47 PM PST 24
Finished Jan 14 01:51:11 PM PST 24
Peak memory 214976 kb
Host smart-7ba64dfb-b020-4ed7-899d-61a54fb0a838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824487607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1824487607
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.984907177
Short name T482
Test name
Test status
Simulation time 500474939 ps
CPU time 21.55 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:51:31 PM PST 24
Peak memory 198656 kb
Host smart-80e1d868-46fd-47e5-a325-1dafb0c10698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984907177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.984907177
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.739365139
Short name T749
Test name
Test status
Simulation time 22877789493 ps
CPU time 109.8 seconds
Started Jan 14 01:50:53 PM PST 24
Finished Jan 14 01:52:45 PM PST 24
Peak memory 198840 kb
Host smart-f1f97c48-7f65-4ef0-a08a-96223cd2b46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739365139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.739365139
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3135061054
Short name T446
Test name
Test status
Simulation time 250100608 ps
CPU time 12.02 seconds
Started Jan 14 01:50:55 PM PST 24
Finished Jan 14 01:51:08 PM PST 24
Peak memory 198700 kb
Host smart-663bb7a7-f0e4-4a0e-882c-aa55c5348566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135061054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3135061054
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1407949412
Short name T771
Test name
Test status
Simulation time 887954779 ps
CPU time 46.46 seconds
Started Jan 14 01:50:47 PM PST 24
Finished Jan 14 01:51:36 PM PST 24
Peak memory 198796 kb
Host smart-f0aa6e5e-c699-42a1-b5e3-d016ad00d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407949412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1407949412
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3260753717
Short name T656
Test name
Test status
Simulation time 309665308 ps
CPU time 1.08 seconds
Started Jan 14 01:50:45 PM PST 24
Finished Jan 14 01:50:47 PM PST 24
Peak memory 198760 kb
Host smart-bed25ed3-83de-4298-9e7c-f0a9f4055b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260753717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3260753717
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3340526626
Short name T800
Test name
Test status
Simulation time 2950480661 ps
CPU time 99.2 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:52:49 PM PST 24
Peak memory 215084 kb
Host smart-353d89e2-c429-4dd4-9617-606d5832b543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340526626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3340526626
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.4040745979
Short name T842
Test name
Test status
Simulation time 1705064800734 ps
CPU time 3469.25 seconds
Started Jan 14 01:50:56 PM PST 24
Finished Jan 14 02:48:46 PM PST 24
Peak memory 240924 kb
Host smart-cce82f9f-35bb-4961-92c1-485365fbc8df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040745979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.4040745979
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1183765345
Short name T458
Test name
Test status
Simulation time 27807945 ps
CPU time 0.98 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:51:11 PM PST 24
Peak memory 195916 kb
Host smart-79135a99-fc2d-4079-a5a1-79945662d47d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183765345 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1183765345
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1026210029
Short name T551
Test name
Test status
Simulation time 32232281648 ps
CPU time 371.25 seconds
Started Jan 14 01:50:49 PM PST 24
Finished Jan 14 01:57:02 PM PST 24
Peak memory 198860 kb
Host smart-908b4768-3e6b-4c28-9382-d3279ea27ff2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026210029 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.1026210029
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.242801549
Short name T329
Test name
Test status
Simulation time 23395596 ps
CPU time 0.73 seconds
Started Jan 14 01:50:54 PM PST 24
Finished Jan 14 01:50:56 PM PST 24
Peak memory 194652 kb
Host smart-75e86bd5-0ed8-4110-813d-68aff2e33771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242801549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.242801549
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1223275061
Short name T669
Test name
Test status
Simulation time 19052161 ps
CPU time 0.59 seconds
Started Jan 14 01:50:57 PM PST 24
Finished Jan 14 01:50:59 PM PST 24
Peak memory 194164 kb
Host smart-1259d3a7-bf6b-4be6-9533-ce51d64ab2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223275061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1223275061
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.417491726
Short name T232
Test name
Test status
Simulation time 5609618611 ps
CPU time 48.57 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:49 PM PST 24
Peak memory 239620 kb
Host smart-a2a88897-3bdf-4fc5-a6ce-4ffba26d55db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417491726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.417491726
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3067139933
Short name T600
Test name
Test status
Simulation time 1035685350 ps
CPU time 47.39 seconds
Started Jan 14 01:50:58 PM PST 24
Finished Jan 14 01:51:47 PM PST 24
Peak memory 198828 kb
Host smart-933aa814-305f-4d83-9499-cf70cf136cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067139933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3067139933
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1103886549
Short name T588
Test name
Test status
Simulation time 33747761 ps
CPU time 0.85 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:51:03 PM PST 24
Peak memory 195300 kb
Host smart-3d02e2be-2942-4a43-9af0-e22fea7f1610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103886549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1103886549
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.225245187
Short name T681
Test name
Test status
Simulation time 6485261702 ps
CPU time 79.2 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:52:20 PM PST 24
Peak memory 198860 kb
Host smart-5cdd7e7c-8cd1-4fc8-85aa-4bf098408961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225245187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.225245187
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4175031036
Short name T569
Test name
Test status
Simulation time 6504442002 ps
CPU time 17.29 seconds
Started Jan 14 01:51:09 PM PST 24
Finished Jan 14 01:51:28 PM PST 24
Peak memory 198720 kb
Host smart-6641ec7a-9500-4737-ae0f-a339aceb897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175031036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4175031036
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.77589736
Short name T742
Test name
Test status
Simulation time 389953102 ps
CPU time 3.84 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:51:06 PM PST 24
Peak memory 198708 kb
Host smart-5064afa0-1ccd-4d6d-ab9e-183b3d883614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77589736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.77589736
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.846078523
Short name T557
Test name
Test status
Simulation time 211942737078 ps
CPU time 478.8 seconds
Started Jan 14 01:51:04 PM PST 24
Finished Jan 14 01:59:04 PM PST 24
Peak memory 198896 kb
Host smart-515a3ed4-6c6c-4c6d-a7ed-f8c80e90892c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846078523 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.846078523
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.2461663266
Short name T277
Test name
Test status
Simulation time 59611269926 ps
CPU time 1136.39 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 02:09:58 PM PST 24
Peak memory 248136 kb
Host smart-f323f26c-f60b-455b-80c1-0e0d443b9e2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461663266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.2461663266
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2728369611
Short name T583
Test name
Test status
Simulation time 45952251 ps
CPU time 0.98 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:01 PM PST 24
Peak memory 195892 kb
Host smart-e30bed34-0744-4e5d-8f84-74aee3daa5a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728369611 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2728369611
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3565849678
Short name T453
Test name
Test status
Simulation time 11011942669 ps
CPU time 383.54 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:57:25 PM PST 24
Peak memory 198748 kb
Host smart-b8b72389-4a63-4ae6-8c40-cebc6b043d9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565849678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.3565849678
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2889196266
Short name T555
Test name
Test status
Simulation time 3114206405 ps
CPU time 39.8 seconds
Started Jan 14 01:51:01 PM PST 24
Finished Jan 14 01:51:43 PM PST 24
Peak memory 198912 kb
Host smart-80c97b73-f9a5-4648-970d-8ea46c2569d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889196266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2889196266
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.943231193
Short name T480
Test name
Test status
Simulation time 50667362 ps
CPU time 0.57 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:16 PM PST 24
Peak memory 193120 kb
Host smart-c505bd0c-1eb9-4430-9c23-53dcff5d989d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943231193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.943231193
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2210111648
Short name T215
Test name
Test status
Simulation time 5855276889 ps
CPU time 70.08 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:52:11 PM PST 24
Peak memory 240908 kb
Host smart-1a38f343-6fb1-4e75-b8a4-2deffd60ad5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210111648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2210111648
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1339955800
Short name T541
Test name
Test status
Simulation time 3290821850 ps
CPU time 30.33 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:30 PM PST 24
Peak memory 198892 kb
Host smart-b5c0c4e3-14dd-4c7e-9033-b06935ce2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339955800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1339955800
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3121009484
Short name T258
Test name
Test status
Simulation time 19157847887 ps
CPU time 81.16 seconds
Started Jan 14 01:51:01 PM PST 24
Finished Jan 14 01:52:24 PM PST 24
Peak memory 198880 kb
Host smart-ff251ff1-2e12-4eec-8943-6d0f1e82a025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3121009484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3121009484
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4219852626
Short name T844
Test name
Test status
Simulation time 15892005547 ps
CPU time 180.4 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:54:03 PM PST 24
Peak memory 198896 kb
Host smart-39d5bcee-b264-4dcb-b57e-406d359b5931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219852626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4219852626
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.29136650
Short name T509
Test name
Test status
Simulation time 2855626182 ps
CPU time 49.27 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:51 PM PST 24
Peak memory 198848 kb
Host smart-f8a1029f-e5c6-4b57-931f-d330eea94232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29136650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.29136650
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1512647454
Short name T370
Test name
Test status
Simulation time 23112207 ps
CPU time 0.84 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:51:04 PM PST 24
Peak memory 196192 kb
Host smart-38cc4cd2-f36e-40c9-b66c-22cd37e86c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512647454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1512647454
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3313246299
Short name T346
Test name
Test status
Simulation time 53601566012 ps
CPU time 654.69 seconds
Started Jan 14 01:50:57 PM PST 24
Finished Jan 14 02:01:53 PM PST 24
Peak memory 215284 kb
Host smart-ed549f30-11a7-4fa2-a9ea-76993de54cae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313246299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3313246299
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.834720089
Short name T833
Test name
Test status
Simulation time 87450481008 ps
CPU time 1732.73 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 02:20:08 PM PST 24
Peak memory 229776 kb
Host smart-775928b0-4d1e-4c64-9aed-1dddd913aec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834720089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.834720089
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3477666816
Short name T769
Test name
Test status
Simulation time 67304004 ps
CPU time 1.11 seconds
Started Jan 14 01:50:59 PM PST 24
Finished Jan 14 01:51:03 PM PST 24
Peak memory 197272 kb
Host smart-361eadfc-95bd-4596-a171-c187540af106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477666816 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3477666816
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.827463045
Short name T491
Test name
Test status
Simulation time 58146211231 ps
CPU time 439.89 seconds
Started Jan 14 01:51:00 PM PST 24
Finished Jan 14 01:58:23 PM PST 24
Peak memory 198840 kb
Host smart-3d6a9b62-42c1-468a-b1cc-838bd1ae7186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827463045 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.hmac_test_sha_vectors.827463045
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3930572932
Short name T300
Test name
Test status
Simulation time 724488953 ps
CPU time 31.29 seconds
Started Jan 14 01:50:57 PM PST 24
Finished Jan 14 01:51:29 PM PST 24
Peak memory 198760 kb
Host smart-b11c316b-36a6-4cf1-8a71-8ddceb400ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930572932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3930572932
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1461370249
Short name T383
Test name
Test status
Simulation time 38242822 ps
CPU time 0.56 seconds
Started Jan 14 01:51:26 PM PST 24
Finished Jan 14 01:51:27 PM PST 24
Peak memory 193020 kb
Host smart-bf62f93f-d47c-4935-ab8d-42a9f9c8e227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461370249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1461370249
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.27836347
Short name T289
Test name
Test status
Simulation time 4719630196 ps
CPU time 45.21 seconds
Started Jan 14 01:51:13 PM PST 24
Finished Jan 14 01:52:00 PM PST 24
Peak memory 231596 kb
Host smart-6e876f13-600e-4d30-9a9e-7baa06d570ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27836347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.27836347
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1762387842
Short name T205
Test name
Test status
Simulation time 1537975233 ps
CPU time 28.55 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:44 PM PST 24
Peak memory 198784 kb
Host smart-ea4e567d-8cdc-433d-8cc5-7b45ebb0f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762387842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1762387842
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1025482525
Short name T554
Test name
Test status
Simulation time 2255124003 ps
CPU time 55.07 seconds
Started Jan 14 01:51:18 PM PST 24
Finished Jan 14 01:52:14 PM PST 24
Peak memory 198868 kb
Host smart-560ee999-de72-435a-b90c-a31d8900d26e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025482525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1025482525
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1149367735
Short name T540
Test name
Test status
Simulation time 7719394427 ps
CPU time 44.71 seconds
Started Jan 14 01:51:17 PM PST 24
Finished Jan 14 01:52:03 PM PST 24
Peak memory 198736 kb
Host smart-ebda3f70-7efa-4c71-99c5-ba196c11169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149367735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1149367735
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2251877635
Short name T760
Test name
Test status
Simulation time 1159028006 ps
CPU time 61.84 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:52:18 PM PST 24
Peak memory 198796 kb
Host smart-1be22c3f-6e78-43df-855b-5a751b2abb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251877635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2251877635
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3311619864
Short name T385
Test name
Test status
Simulation time 361713743 ps
CPU time 3.01 seconds
Started Jan 14 01:51:13 PM PST 24
Finished Jan 14 01:51:17 PM PST 24
Peak memory 198592 kb
Host smart-be1f0e0e-9eb6-409e-b6ce-a8412428b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311619864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3311619864
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2080479217
Short name T1
Test name
Test status
Simulation time 33651506129 ps
CPU time 412.42 seconds
Started Jan 14 01:51:12 PM PST 24
Finished Jan 14 01:58:05 PM PST 24
Peak memory 198836 kb
Host smart-158a6570-9648-4d4e-b864-a48993a6dc4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080479217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2080479217
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.1653192527
Short name T515
Test name
Test status
Simulation time 21819329588 ps
CPU time 284.08 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:56:01 PM PST 24
Peak memory 212968 kb
Host smart-1521f483-dd30-4116-afe9-ec7fe8e5ead9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653192527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.1653192527
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.147622297
Short name T584
Test name
Test status
Simulation time 46020329 ps
CPU time 0.86 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:17 PM PST 24
Peak memory 196612 kb
Host smart-c7245080-25a8-4547-9898-7f57290e3770
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147622297 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.147622297
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2077044257
Short name T635
Test name
Test status
Simulation time 59322604198 ps
CPU time 431.64 seconds
Started Jan 14 01:51:12 PM PST 24
Finished Jan 14 01:58:25 PM PST 24
Peak memory 198768 kb
Host smart-262e765f-e6af-4cfd-8148-c9c8d7a16d0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077044257 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.2077044257
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4231146890
Short name T745
Test name
Test status
Simulation time 1717032851 ps
CPU time 21.66 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:51:39 PM PST 24
Peak memory 198768 kb
Host smart-0936ab88-d32d-4d48-ad64-db570778070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231146890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4231146890
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2045308546
Short name T472
Test name
Test status
Simulation time 14512932 ps
CPU time 0.58 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:17 PM PST 24
Peak memory 193172 kb
Host smart-68f21d9d-33e3-4a03-89b0-dd202d923066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045308546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2045308546
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2552091896
Short name T640
Test name
Test status
Simulation time 957658376 ps
CPU time 33.72 seconds
Started Jan 14 01:51:12 PM PST 24
Finished Jan 14 01:51:47 PM PST 24
Peak memory 223408 kb
Host smart-94aafac0-36b3-446c-a606-e4384bb129ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552091896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2552091896
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1748298394
Short name T292
Test name
Test status
Simulation time 7844754622 ps
CPU time 53.62 seconds
Started Jan 14 01:51:18 PM PST 24
Finished Jan 14 01:52:13 PM PST 24
Peak memory 198852 kb
Host smart-69716eec-37ac-40c6-9d59-c05a99ec12df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748298394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1748298394
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.618812754
Short name T212
Test name
Test status
Simulation time 3375470052 ps
CPU time 42.41 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:58 PM PST 24
Peak memory 198828 kb
Host smart-99ce3113-e080-463d-8da2-5fce6392f8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618812754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.618812754
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1893708465
Short name T829
Test name
Test status
Simulation time 87670447 ps
CPU time 4.52 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:51:21 PM PST 24
Peak memory 198620 kb
Host smart-53c8fb7c-ec8c-4d1c-955a-be1050bd915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893708465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1893708465
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3397246666
Short name T287
Test name
Test status
Simulation time 17804274494 ps
CPU time 78.99 seconds
Started Jan 14 01:51:11 PM PST 24
Finished Jan 14 01:52:31 PM PST 24
Peak memory 198824 kb
Host smart-f8ce1c88-af66-4aa7-ba04-9aff36aac46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397246666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3397246666
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2713744968
Short name T431
Test name
Test status
Simulation time 170858236 ps
CPU time 4 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:20 PM PST 24
Peak memory 197848 kb
Host smart-460f9773-064e-4372-83ff-22f357927edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713744968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2713744968
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.793339445
Short name T784
Test name
Test status
Simulation time 141479343 ps
CPU time 0.88 seconds
Started Jan 14 01:51:11 PM PST 24
Finished Jan 14 01:51:13 PM PST 24
Peak memory 195908 kb
Host smart-19c726ac-3383-4ca7-a472-2f619e7e53e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793339445 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.793339445
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.208387251
Short name T647
Test name
Test status
Simulation time 56611639235 ps
CPU time 1651.01 seconds
Started Jan 14 01:51:11 PM PST 24
Finished Jan 14 02:18:44 PM PST 24
Peak memory 255756 kb
Host smart-7bba789a-e77c-49d7-82b0-3ce669dc8daa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208387251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.208387251
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2705239365
Short name T233
Test name
Test status
Simulation time 82040894 ps
CPU time 0.99 seconds
Started Jan 14 01:51:12 PM PST 24
Finished Jan 14 01:51:14 PM PST 24
Peak memory 197228 kb
Host smart-8a38bba1-96ca-40d8-b6c9-130f4ad843be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705239365 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2705239365
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1534790649
Short name T757
Test name
Test status
Simulation time 150174102555 ps
CPU time 380.06 seconds
Started Jan 14 01:51:11 PM PST 24
Finished Jan 14 01:57:32 PM PST 24
Peak memory 198784 kb
Host smart-8ea4b68c-c5d0-4f19-9472-fa3a1990f7d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534790649 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.1534790649
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.980291069
Short name T311
Test name
Test status
Simulation time 4860804054 ps
CPU time 22.09 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:37 PM PST 24
Peak memory 198848 kb
Host smart-ff8c33c5-0085-4d4b-99db-20cdb8a3ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980291069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.980291069
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3054234674
Short name T437
Test name
Test status
Simulation time 83455322 ps
CPU time 0.54 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:51:18 PM PST 24
Peak memory 193040 kb
Host smart-8ad4eade-d025-4eea-be83-1dfc74e0b2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054234674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3054234674
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.444146486
Short name T813
Test name
Test status
Simulation time 3261435054 ps
CPU time 24.8 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:40 PM PST 24
Peak memory 223436 kb
Host smart-512ffba7-f636-4058-a7eb-615b8410b957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444146486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.444146486
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4276673841
Short name T98
Test name
Test status
Simulation time 15805383371 ps
CPU time 42.23 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:51:58 PM PST 24
Peak memory 198636 kb
Host smart-3f09436c-e4e8-45f4-a4e5-898726b9385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276673841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4276673841
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3915072405
Short name T481
Test name
Test status
Simulation time 29477047073 ps
CPU time 113.99 seconds
Started Jan 14 01:51:12 PM PST 24
Finished Jan 14 01:53:07 PM PST 24
Peak memory 198900 kb
Host smart-6e16da6e-4484-48be-9a48-378f787a904b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915072405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3915072405
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2598726701
Short name T789
Test name
Test status
Simulation time 3746268710 ps
CPU time 56.85 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 01:52:13 PM PST 24
Peak memory 198852 kb
Host smart-7ddab3a5-b44d-4daa-8158-ffac3d74fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598726701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2598726701
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1014846310
Short name T574
Test name
Test status
Simulation time 4495693096 ps
CPU time 66.89 seconds
Started Jan 14 01:51:11 PM PST 24
Finished Jan 14 01:52:19 PM PST 24
Peak memory 198780 kb
Host smart-57f85876-6135-4592-ad65-86d45d47d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014846310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1014846310
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.829868309
Short name T479
Test name
Test status
Simulation time 80297432 ps
CPU time 0.74 seconds
Started Jan 14 01:51:13 PM PST 24
Finished Jan 14 01:51:15 PM PST 24
Peak memory 194588 kb
Host smart-f65f3098-8755-4fa8-9ae4-c1d468e75c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829868309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.829868309
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1604148962
Short name T222
Test name
Test status
Simulation time 23910260982 ps
CPU time 1189.1 seconds
Started Jan 14 01:51:14 PM PST 24
Finished Jan 14 02:11:05 PM PST 24
Peak memory 223896 kb
Host smart-229b98fc-16ba-40c7-bcf5-81fa3dab52bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604148962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1604148962
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.2843643336
Short name T424
Test name
Test status
Simulation time 69553683194 ps
CPU time 3083.11 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 02:42:40 PM PST 24
Peak memory 228476 kb
Host smart-afadbefa-c410-426d-9cf8-45fe29daf8a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843643336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.2843643336
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2332833662
Short name T686
Test name
Test status
Simulation time 261140137 ps
CPU time 1.08 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:51:18 PM PST 24
Peak memory 197172 kb
Host smart-8ff78f9d-9110-4379-842d-c30e6d894796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332833662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2332833662
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2973467428
Short name T464
Test name
Test status
Simulation time 12807997052 ps
CPU time 383.08 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:57:39 PM PST 24
Peak memory 198812 kb
Host smart-ac02cdf7-fbc5-4c68-b370-348eafa6f8a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973467428 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.2973467428
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2318160114
Short name T427
Test name
Test status
Simulation time 9136091809 ps
CPU time 40.83 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 01:51:57 PM PST 24
Peak memory 198880 kb
Host smart-23b056e1-eda0-448d-a6ae-c4b12554836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318160114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2318160114
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.385207438
Short name T375
Test name
Test status
Simulation time 31918702 ps
CPU time 0.56 seconds
Started Jan 14 01:51:20 PM PST 24
Finished Jan 14 01:51:22 PM PST 24
Peak memory 193184 kb
Host smart-7b1132d6-2981-4087-82f1-fbe83882ff01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385207438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.385207438
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1283460730
Short name T220
Test name
Test status
Simulation time 2363786106 ps
CPU time 16.09 seconds
Started Jan 14 01:51:20 PM PST 24
Finished Jan 14 01:51:37 PM PST 24
Peak memory 198844 kb
Host smart-c9f1c411-3999-4fa8-b237-ab4128358022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283460730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1283460730
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1713929575
Short name T422
Test name
Test status
Simulation time 5103084388 ps
CPU time 58.72 seconds
Started Jan 14 01:51:17 PM PST 24
Finished Jan 14 01:52:17 PM PST 24
Peak memory 198892 kb
Host smart-e679fe40-0948-4f9c-940d-579b5aedd519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713929575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1713929575
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1857139214
Short name T494
Test name
Test status
Simulation time 6585296859 ps
CPU time 69.89 seconds
Started Jan 14 01:51:17 PM PST 24
Finished Jan 14 01:52:28 PM PST 24
Peak memory 198844 kb
Host smart-2e69079b-b572-4d78-bf91-696a0ecd0c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857139214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1857139214
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1562070213
Short name T516
Test name
Test status
Simulation time 39859935545 ps
CPU time 160.1 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:53:58 PM PST 24
Peak memory 198840 kb
Host smart-d0ccf2a1-62ab-4e9c-9266-6f204e103630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562070213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1562070213
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1345459937
Short name T695
Test name
Test status
Simulation time 1712402294 ps
CPU time 12.63 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:51:30 PM PST 24
Peak memory 198716 kb
Host smart-6a48e660-1f6c-45ba-b7fe-13306d6deae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345459937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1345459937
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3590809583
Short name T698
Test name
Test status
Simulation time 289097503 ps
CPU time 3.91 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:51:22 PM PST 24
Peak memory 198768 kb
Host smart-e5ec9608-f5ce-4910-8df1-1b8ac035d1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590809583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3590809583
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.918169898
Short name T34
Test name
Test status
Simulation time 1231377245901 ps
CPU time 1505 seconds
Started Jan 14 01:51:15 PM PST 24
Finished Jan 14 02:16:22 PM PST 24
Peak memory 229456 kb
Host smart-aad33660-a39d-44b6-b956-3f8a32aac739
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918169898 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.918169898
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2051068609
Short name T754
Test name
Test status
Simulation time 55777734924 ps
CPU time 719.23 seconds
Started Jan 14 01:51:18 PM PST 24
Finished Jan 14 02:03:18 PM PST 24
Peak memory 215316 kb
Host smart-27a4108c-c6b1-4706-9eec-b9eaea422f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051068609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.2051068609
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2840932580
Short name T327
Test name
Test status
Simulation time 53382377 ps
CPU time 1.05 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 01:51:34 PM PST 24
Peak memory 197196 kb
Host smart-b0afc813-446e-40ab-b49f-616808fc76d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840932580 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2840932580
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2082151662
Short name T290
Test name
Test status
Simulation time 8255981750 ps
CPU time 407.98 seconds
Started Jan 14 01:51:17 PM PST 24
Finished Jan 14 01:58:07 PM PST 24
Peak memory 198848 kb
Host smart-e73ad09c-7c78-480e-94cf-0aab9e5bb082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082151662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.2082151662
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3974911579
Short name T580
Test name
Test status
Simulation time 4684618892 ps
CPU time 49.78 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:52:08 PM PST 24
Peak memory 198916 kb
Host smart-dd0efee4-fbc9-44d7-babe-9167cc171dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974911579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3974911579
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.291795615
Short name T430
Test name
Test status
Simulation time 38994017 ps
CPU time 0.58 seconds
Started Jan 14 01:48:21 PM PST 24
Finished Jan 14 01:48:23 PM PST 24
Peak memory 193152 kb
Host smart-bacb02f2-9b49-4c4c-bc7f-82d7bf78c63c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291795615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.291795615
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.309199073
Short name T798
Test name
Test status
Simulation time 2012945633 ps
CPU time 14.28 seconds
Started Jan 14 01:48:15 PM PST 24
Finished Jan 14 01:48:30 PM PST 24
Peak memory 214740 kb
Host smart-6d8fd434-889e-468b-9e2b-26695616eac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309199073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.309199073
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1374007044
Short name T812
Test name
Test status
Simulation time 1869707141 ps
CPU time 31.78 seconds
Started Jan 14 01:48:07 PM PST 24
Finished Jan 14 01:48:40 PM PST 24
Peak memory 198736 kb
Host smart-ef7d8318-a82c-4ccf-84bd-fd84dcb0f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374007044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1374007044
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4178007541
Short name T436
Test name
Test status
Simulation time 524272724 ps
CPU time 25.51 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:48:37 PM PST 24
Peak memory 198788 kb
Host smart-2a1274be-c091-4103-881f-7d4a31c9b419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178007541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4178007541
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1738817157
Short name T846
Test name
Test status
Simulation time 3602632842 ps
CPU time 46.25 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:48:57 PM PST 24
Peak memory 198732 kb
Host smart-a30e4e6c-48d8-42e1-9203-58fb916cdd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738817157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1738817157
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4293037178
Short name T417
Test name
Test status
Simulation time 5250811912 ps
CPU time 91.19 seconds
Started Jan 14 01:48:10 PM PST 24
Finished Jan 14 01:49:42 PM PST 24
Peak memory 198864 kb
Host smart-37518883-2448-44ec-935c-3f12a55c9d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293037178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4293037178
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3152186620
Short name T525
Test name
Test status
Simulation time 162643986 ps
CPU time 2.22 seconds
Started Jan 14 01:48:11 PM PST 24
Finished Jan 14 01:48:15 PM PST 24
Peak memory 198792 kb
Host smart-dc7d9192-3336-42c7-af71-87eeebbb5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152186620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3152186620
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4139875056
Short name T845
Test name
Test status
Simulation time 265208624714 ps
CPU time 1494.84 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 02:13:26 PM PST 24
Peak memory 207120 kb
Host smart-bb5fa75f-7a2d-4b8f-b18f-1d3515e9f1d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139875056 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4139875056
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3905584512
Short name T468
Test name
Test status
Simulation time 84131852433 ps
CPU time 866.13 seconds
Started Jan 14 01:48:21 PM PST 24
Finished Jan 14 02:02:49 PM PST 24
Peak memory 248060 kb
Host smart-499e2a1d-4f84-4ff7-92f4-4270200cebaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905584512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3905584512
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2460944714
Short name T184
Test name
Test status
Simulation time 90050931 ps
CPU time 0.91 seconds
Started Jan 14 01:48:20 PM PST 24
Finished Jan 14 01:48:21 PM PST 24
Peak memory 196524 kb
Host smart-b34d6e8f-50fa-48b7-aa0a-d285611b1a8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460944714 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2460944714
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.905024315
Short name T517
Test name
Test status
Simulation time 37705895371 ps
CPU time 470.94 seconds
Started Jan 14 01:48:22 PM PST 24
Finished Jan 14 01:56:14 PM PST 24
Peak memory 198688 kb
Host smart-8cbbe067-469a-4d93-949b-e8e1bf3a0b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905024315 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.hmac_test_sha_vectors.905024315
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1425255702
Short name T703
Test name
Test status
Simulation time 24501490421 ps
CPU time 72.87 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 01:49:44 PM PST 24
Peak memory 198884 kb
Host smart-1fc043ca-dfe0-4b7b-9c14-8024d94bf46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425255702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1425255702
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1692484425
Short name T394
Test name
Test status
Simulation time 51183712106 ps
CPU time 231.18 seconds
Started Jan 14 01:51:16 PM PST 24
Finished Jan 14 01:55:09 PM PST 24
Peak memory 215364 kb
Host smart-9eae8956-0658-4c38-b526-f4be03dee306
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692484425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1692484425
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.84563984
Short name T298
Test name
Test status
Simulation time 219649614714 ps
CPU time 1578.31 seconds
Started Jan 14 01:51:20 PM PST 24
Finished Jan 14 02:17:39 PM PST 24
Peak memory 242884 kb
Host smart-728bd8f2-e025-4b3c-8dc0-b0ca6c844127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84563984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.84563984
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.2436693246
Short name T539
Test name
Test status
Simulation time 154050683341 ps
CPU time 640.3 seconds
Started Jan 14 01:51:17 PM PST 24
Finished Jan 14 02:01:58 PM PST 24
Peak memory 210088 kb
Host smart-ebfcb4e5-9c17-4ca7-954f-fe85598b540e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436693246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.2436693246
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2459892338
Short name T694
Test name
Test status
Simulation time 61149558086 ps
CPU time 594.63 seconds
Started Jan 14 01:51:27 PM PST 24
Finished Jan 14 02:01:23 PM PST 24
Peak memory 242968 kb
Host smart-91b07fa8-7a5f-45d0-9007-69af079c4415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459892338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2459892338
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3813285432
Short name T716
Test name
Test status
Simulation time 270702009260 ps
CPU time 2706.41 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:36:36 PM PST 24
Peak memory 256360 kb
Host smart-d4e3e045-69db-47a9-887e-edc45bb697b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813285432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.3813285432
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.1769868820
Short name T372
Test name
Test status
Simulation time 244094754332 ps
CPU time 1158.72 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:10:48 PM PST 24
Peak memory 241884 kb
Host smart-aaa42ff5-5341-4a0d-8260-c34647740725
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769868820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.1769868820
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3895996006
Short name T111
Test name
Test status
Simulation time 359162092843 ps
CPU time 1854.08 seconds
Started Jan 14 01:51:22 PM PST 24
Finished Jan 14 02:22:17 PM PST 24
Peak memory 231756 kb
Host smart-266c7152-3f0a-4e57-8ad2-0df1264f2a95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895996006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.3895996006
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.3193561671
Short name T559
Test name
Test status
Simulation time 416436420701 ps
CPU time 1681.84 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:19:31 PM PST 24
Peak memory 245924 kb
Host smart-d54995d0-3654-4f27-aa14-7b1401d37243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193561671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.3193561671
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.3621456721
Short name T107
Test name
Test status
Simulation time 112751613488 ps
CPU time 4852.11 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 03:12:22 PM PST 24
Peak memory 258904 kb
Host smart-ad79a047-360c-4f98-9e21-aa8f2e98d70d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621456721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.3621456721
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.1836102403
Short name T336
Test name
Test status
Simulation time 67890035109 ps
CPU time 161.77 seconds
Started Jan 14 01:51:31 PM PST 24
Finished Jan 14 01:54:13 PM PST 24
Peak memory 214924 kb
Host smart-6c6d2b1d-cfa4-4636-a478-892ed18fd507
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836102403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.1836102403
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.93961259
Short name T434
Test name
Test status
Simulation time 39166475 ps
CPU time 0.54 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 01:48:29 PM PST 24
Peak memory 193160 kb
Host smart-46b2a92d-0e7d-45f6-9fa2-5b8804d6948f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93961259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.93961259
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1636601778
Short name T246
Test name
Test status
Simulation time 879798812 ps
CPU time 7.14 seconds
Started Jan 14 01:48:24 PM PST 24
Finished Jan 14 01:48:32 PM PST 24
Peak memory 214236 kb
Host smart-9ae281ee-0835-4f47-8b13-61c2144842b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636601778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1636601778
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.270529806
Short name T594
Test name
Test status
Simulation time 3489278962 ps
CPU time 13.83 seconds
Started Jan 14 01:48:21 PM PST 24
Finished Jan 14 01:48:35 PM PST 24
Peak memory 198868 kb
Host smart-dd107cb4-dbe7-4d9d-bbcc-014b9fa5c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270529806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.270529806
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2511294972
Short name T209
Test name
Test status
Simulation time 5173976270 ps
CPU time 55.28 seconds
Started Jan 14 01:48:20 PM PST 24
Finished Jan 14 01:49:16 PM PST 24
Peak memory 198844 kb
Host smart-5854f3a2-5d6f-4e45-8f24-c3b8bf5b34d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511294972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2511294972
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3522480354
Short name T770
Test name
Test status
Simulation time 779998306 ps
CPU time 39.75 seconds
Started Jan 14 01:48:22 PM PST 24
Finished Jan 14 01:49:02 PM PST 24
Peak memory 198664 kb
Host smart-7a5b5e8c-320f-463f-ab09-81b4c1e5efe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522480354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3522480354
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2538804845
Short name T558
Test name
Test status
Simulation time 7482162613 ps
CPU time 30.83 seconds
Started Jan 14 01:48:16 PM PST 24
Finished Jan 14 01:48:47 PM PST 24
Peak memory 198876 kb
Host smart-bfa64e30-5a76-409a-8dca-0e437470aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538804845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2538804845
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2059548623
Short name T191
Test name
Test status
Simulation time 1456733352 ps
CPU time 4.12 seconds
Started Jan 14 01:48:19 PM PST 24
Finished Jan 14 01:48:23 PM PST 24
Peak memory 198700 kb
Host smart-cfef6824-25c3-4b09-b504-7f9ab69088e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059548623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2059548623
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3909096412
Short name T582
Test name
Test status
Simulation time 57190719451 ps
CPU time 622.74 seconds
Started Jan 14 01:48:22 PM PST 24
Finished Jan 14 01:58:46 PM PST 24
Peak memory 223368 kb
Host smart-17d81b52-977d-4058-8783-fa708bc5472e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909096412 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3909096412
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4002786262
Short name T629
Test name
Test status
Simulation time 92976493223 ps
CPU time 343.31 seconds
Started Jan 14 01:48:17 PM PST 24
Finished Jan 14 01:54:01 PM PST 24
Peak memory 223588 kb
Host smart-e3ba3559-44c0-4ab2-b805-83c562f05453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002786262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4002786262
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3755911352
Short name T843
Test name
Test status
Simulation time 98201511 ps
CPU time 0.91 seconds
Started Jan 14 01:48:20 PM PST 24
Finished Jan 14 01:48:21 PM PST 24
Peak memory 196228 kb
Host smart-f1fb81d6-ad7b-49ad-b830-971ace91beaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755911352 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3755911352
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2206199790
Short name T530
Test name
Test status
Simulation time 15148669971 ps
CPU time 381.66 seconds
Started Jan 14 01:48:19 PM PST 24
Finished Jan 14 01:54:41 PM PST 24
Peak memory 198788 kb
Host smart-b25e8b88-f7fe-4cb4-9960-c71b60cdc8a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206199790 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.2206199790
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4118918330
Short name T577
Test name
Test status
Simulation time 3211085013 ps
CPU time 70.75 seconds
Started Jan 14 01:48:16 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 198884 kb
Host smart-40d2ff23-27b9-41ca-bb85-7c6e6dd501da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118918330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4118918330
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.964571609
Short name T240
Test name
Test status
Simulation time 78513344109 ps
CPU time 1783.65 seconds
Started Jan 14 01:51:25 PM PST 24
Finished Jan 14 02:21:10 PM PST 24
Peak memory 256356 kb
Host smart-4f948909-fd69-4077-9e6d-6732d7f9b429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964571609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.964571609
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.1068098082
Short name T834
Test name
Test status
Simulation time 117557611125 ps
CPU time 547.51 seconds
Started Jan 14 01:51:29 PM PST 24
Finished Jan 14 02:00:38 PM PST 24
Peak memory 209424 kb
Host smart-af7f665a-f98a-4b02-9d18-3b7fa29ef6ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068098082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.1068098082
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.414299172
Short name T664
Test name
Test status
Simulation time 239668868417 ps
CPU time 733.71 seconds
Started Jan 14 01:51:22 PM PST 24
Finished Jan 14 02:03:36 PM PST 24
Peak memory 215272 kb
Host smart-6b02ee77-e920-4a56-b485-8afa39ea5edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414299172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.414299172
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2329286416
Short name T457
Test name
Test status
Simulation time 89137048574 ps
CPU time 1670.75 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:19:20 PM PST 24
Peak memory 239936 kb
Host smart-e7a66905-dcb1-4b80-a1fc-b6a0c7135a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329286416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2329286416
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.4086542131
Short name T638
Test name
Test status
Simulation time 875760071120 ps
CPU time 1873.27 seconds
Started Jan 14 01:51:26 PM PST 24
Finished Jan 14 02:22:41 PM PST 24
Peak memory 257276 kb
Host smart-9edfd911-5831-4693-ab2d-16eea7632360
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086542131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.4086542131
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.2003128216
Short name T478
Test name
Test status
Simulation time 121597498870 ps
CPU time 1131.65 seconds
Started Jan 14 01:51:25 PM PST 24
Finished Jan 14 02:10:18 PM PST 24
Peak memory 245088 kb
Host smart-cb7c37ea-39db-451c-ab96-2d4e7d922259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003128216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.2003128216
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.3329021725
Short name T192
Test name
Test status
Simulation time 60538350358 ps
CPU time 1070.95 seconds
Started Jan 14 01:51:27 PM PST 24
Finished Jan 14 02:09:19 PM PST 24
Peak memory 233664 kb
Host smart-7a170d94-9908-41fd-8371-1762a346c72a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329021725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.3329021725
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.2662721120
Short name T99
Test name
Test status
Simulation time 396052528067 ps
CPU time 1162.13 seconds
Started Jan 14 01:51:27 PM PST 24
Finished Jan 14 02:10:51 PM PST 24
Peak memory 241996 kb
Host smart-94f379a7-5df4-4c08-8d76-16f0a02a9633
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662721120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.2662721120
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.4015659603
Short name T429
Test name
Test status
Simulation time 66259862333 ps
CPU time 978.08 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:07:48 PM PST 24
Peak memory 233988 kb
Host smart-af3d6b22-028e-4469-ac2d-57ac40668879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015659603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.4015659603
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1867172236
Short name T788
Test name
Test status
Simulation time 29144715 ps
CPU time 0.53 seconds
Started Jan 14 01:48:24 PM PST 24
Finished Jan 14 01:48:25 PM PST 24
Peak memory 193140 kb
Host smart-e1ba1313-8829-446b-b75c-0fd482ad63a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867172236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1867172236
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2804780495
Short name T207
Test name
Test status
Simulation time 1999817995 ps
CPU time 8.56 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:48:39 PM PST 24
Peak memory 198744 kb
Host smart-52f9c760-4efe-4a9b-ac2b-f4b8de553261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804780495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2804780495
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.302977792
Short name T782
Test name
Test status
Simulation time 259182222 ps
CPU time 11.55 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:41 PM PST 24
Peak memory 198804 kb
Host smart-9223a4cc-4f2a-414b-94d3-df8687e51a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302977792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.302977792
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1222309253
Short name T603
Test name
Test status
Simulation time 11684992436 ps
CPU time 116.83 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:50:26 PM PST 24
Peak memory 198800 kb
Host smart-84f5ddcf-907c-4db5-a3ef-4254bd483a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222309253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1222309253
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1215394710
Short name T587
Test name
Test status
Simulation time 11186457899 ps
CPU time 43.56 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 01:49:11 PM PST 24
Peak memory 198824 kb
Host smart-049c11cd-2c6b-4ada-a7c3-b5dcd7ce21c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215394710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1215394710
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2175949390
Short name T841
Test name
Test status
Simulation time 14983123912 ps
CPU time 69.9 seconds
Started Jan 14 01:48:17 PM PST 24
Finished Jan 14 01:49:28 PM PST 24
Peak memory 198876 kb
Host smart-c9a7cedc-3974-4e3b-b113-e18a7b317917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175949390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2175949390
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3978554341
Short name T347
Test name
Test status
Simulation time 33074559 ps
CPU time 0.91 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:48:32 PM PST 24
Peak memory 195736 kb
Host smart-d5421d1e-a2d6-43b1-bf10-f221ada68117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978554341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3978554341
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3413182142
Short name T522
Test name
Test status
Simulation time 734951236067 ps
CPU time 1971.25 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 02:21:21 PM PST 24
Peak memory 231196 kb
Host smart-53fada26-a360-4ea9-b3c5-4f2b36814f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413182142 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3413182142
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3156894420
Short name T585
Test name
Test status
Simulation time 55323948414 ps
CPU time 1113.99 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 02:07:05 PM PST 24
Peak memory 226624 kb
Host smart-ef932fe9-c5de-4e62-83df-e503a8405aad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156894420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3156894420
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3756474962
Short name T708
Test name
Test status
Simulation time 31926548 ps
CPU time 1.16 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 01:48:29 PM PST 24
Peak memory 197772 kb
Host smart-54b63793-b59e-460e-b4b6-1b8259e4b0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756474962 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3756474962
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2322612849
Short name T679
Test name
Test status
Simulation time 54959763634 ps
CPU time 473.41 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:56:24 PM PST 24
Peak memory 198808 kb
Host smart-cf6dea8a-443a-4c19-ac21-cdae70fca76f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322612849 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.2322612849
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.758200800
Short name T376
Test name
Test status
Simulation time 1167536149 ps
CPU time 9.41 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:39 PM PST 24
Peak memory 198800 kb
Host smart-4b46e881-6f49-47c5-b97c-41232549cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758200800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.758200800
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.3087426092
Short name T103
Test name
Test status
Simulation time 68755861428 ps
CPU time 2476.99 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:32:47 PM PST 24
Peak memory 258584 kb
Host smart-4962c0be-86c7-4dd9-90a4-81a673952397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087426092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.3087426092
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.271882541
Short name T379
Test name
Test status
Simulation time 535775285063 ps
CPU time 1863.06 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 02:22:32 PM PST 24
Peak memory 263380 kb
Host smart-59f14410-6f3b-45b5-8ba1-98591f2604ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271882541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.271882541
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.1527839112
Short name T247
Test name
Test status
Simulation time 101928458490 ps
CPU time 99 seconds
Started Jan 14 01:51:25 PM PST 24
Finished Jan 14 01:53:05 PM PST 24
Peak memory 215340 kb
Host smart-110d821b-8a09-48d4-8251-e0115b590e66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527839112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.1527839112
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.1957507424
Short name T753
Test name
Test status
Simulation time 151477301779 ps
CPU time 421.61 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 01:58:31 PM PST 24
Peak memory 215092 kb
Host smart-7a04c365-f40b-4132-b2a4-8b3b98974dde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957507424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.1957507424
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.2133887367
Short name T641
Test name
Test status
Simulation time 14324802277 ps
CPU time 213.02 seconds
Started Jan 14 01:51:26 PM PST 24
Finished Jan 14 01:54:59 PM PST 24
Peak memory 247600 kb
Host smart-330f09a4-c73b-42f2-a431-8e4d313b2483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133887367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.2133887367
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.334190201
Short name T306
Test name
Test status
Simulation time 24034637712 ps
CPU time 311.78 seconds
Started Jan 14 01:51:28 PM PST 24
Finished Jan 14 01:56:41 PM PST 24
Peak memory 214432 kb
Host smart-55b73882-4f5f-4868-8840-f5b3f00473ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334190201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.334190201
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.232021695
Short name T291
Test name
Test status
Simulation time 38520600731 ps
CPU time 486.56 seconds
Started Jan 14 01:51:26 PM PST 24
Finished Jan 14 01:59:34 PM PST 24
Peak memory 223552 kb
Host smart-4076624f-6266-4330-9e6d-25b16deeb59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232021695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.232021695
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.3378189490
Short name T104
Test name
Test status
Simulation time 61008514944 ps
CPU time 1308.13 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 02:13:21 PM PST 24
Peak memory 248028 kb
Host smart-fb94ad8a-5dc1-41a6-aaf6-a3ba6e44d096
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378189490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.3378189490
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.75608014
Short name T579
Test name
Test status
Simulation time 35250274 ps
CPU time 0.57 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:30 PM PST 24
Peak memory 193180 kb
Host smart-2d5afcb0-ccfa-4476-bb81-8b9b66c0ffbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75608014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.75608014
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3057056308
Short name T216
Test name
Test status
Simulation time 602726275 ps
CPU time 5.51 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:48:35 PM PST 24
Peak memory 214312 kb
Host smart-4bbb0c68-ed9c-4b5d-87d0-c53a9a7d9f01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057056308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3057056308
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2758364458
Short name T3
Test name
Test status
Simulation time 1301241443 ps
CPU time 31.19 seconds
Started Jan 14 01:48:25 PM PST 24
Finished Jan 14 01:48:57 PM PST 24
Peak memory 198776 kb
Host smart-6d0e1e14-af3d-41db-8e33-5cbaac957a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758364458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2758364458
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2926797370
Short name T838
Test name
Test status
Simulation time 2337438176 ps
CPU time 121.69 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 01:50:29 PM PST 24
Peak memory 198816 kb
Host smart-5ff3e2f4-dc72-432f-a3f2-957b2c1158ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926797370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2926797370
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.698949763
Short name T188
Test name
Test status
Simulation time 11940071391 ps
CPU time 66.37 seconds
Started Jan 14 01:48:22 PM PST 24
Finished Jan 14 01:49:30 PM PST 24
Peak memory 198880 kb
Host smart-6db48937-3696-4a0f-945f-1b601bd0fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698949763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.698949763
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.333110014
Short name T597
Test name
Test status
Simulation time 15437692510 ps
CPU time 83.32 seconds
Started Jan 14 01:48:31 PM PST 24
Finished Jan 14 01:49:55 PM PST 24
Peak memory 198928 kb
Host smart-39c74ae3-f4c5-4cf8-ad32-1d2cb272271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333110014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.333110014
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.666975586
Short name T234
Test name
Test status
Simulation time 153993289 ps
CPU time 1.88 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:31 PM PST 24
Peak memory 198664 kb
Host smart-59e23752-ab0f-40cb-8d59-a2b70540a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666975586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.666975586
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1478380863
Short name T108
Test name
Test status
Simulation time 391561870007 ps
CPU time 1629.44 seconds
Started Jan 14 01:48:27 PM PST 24
Finished Jan 14 02:15:38 PM PST 24
Peak memory 198892 kb
Host smart-7f4f54dc-69ec-463f-85f2-440b8d953f10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478380863 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1478380863
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3658958780
Short name T364
Test name
Test status
Simulation time 141738371330 ps
CPU time 2479.72 seconds
Started Jan 14 01:48:32 PM PST 24
Finished Jan 14 02:29:52 PM PST 24
Peak memory 245676 kb
Host smart-cee30d86-111e-40e0-870a-bc6cf1f08927
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658958780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3658958780
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.646938349
Short name T312
Test name
Test status
Simulation time 33871466 ps
CPU time 0.87 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 01:48:32 PM PST 24
Peak memory 195816 kb
Host smart-d509a74f-c02d-45cd-8615-b10fd2bf29bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646938349 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.646938349
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.163799953
Short name T802
Test name
Test status
Simulation time 38580726590 ps
CPU time 409.69 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:55:18 PM PST 24
Peak memory 198776 kb
Host smart-cb55e0d3-1a89-4897-92e7-e478a9af162b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163799953 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_sha_vectors.163799953
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3472068460
Short name T208
Test name
Test status
Simulation time 242034430 ps
CPU time 11.33 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:41 PM PST 24
Peak memory 198792 kb
Host smart-6092843b-e7dc-41b5-a8e0-95d10507295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472068460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3472068460
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.3195861622
Short name T310
Test name
Test status
Simulation time 13251528325 ps
CPU time 98.72 seconds
Started Jan 14 01:51:31 PM PST 24
Finished Jan 14 01:53:10 PM PST 24
Peak memory 198884 kb
Host smart-f43fd3b7-8e10-4d98-9d7a-a9ff017faf2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195861622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.3195861622
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1515013056
Short name T461
Test name
Test status
Simulation time 120859314803 ps
CPU time 4716.32 seconds
Started Jan 14 01:51:35 PM PST 24
Finished Jan 14 03:10:13 PM PST 24
Peak memory 264052 kb
Host smart-cca0dac0-5143-4a6c-8004-a8bf859b1e69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515013056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.1515013056
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.354389588
Short name T4
Test name
Test status
Simulation time 29764414065 ps
CPU time 378.64 seconds
Started Jan 14 01:51:38 PM PST 24
Finished Jan 14 01:57:59 PM PST 24
Peak memory 239724 kb
Host smart-eb0c93dc-b5b3-47f6-9b36-ccd4c0a57dc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354389588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.354389588
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.1547959157
Short name T334
Test name
Test status
Simulation time 214148295702 ps
CPU time 2681.61 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:36:16 PM PST 24
Peak memory 245968 kb
Host smart-b1ee499d-30ec-4283-979f-d3365a64a1fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547959157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.1547959157
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1971215065
Short name T690
Test name
Test status
Simulation time 248453366731 ps
CPU time 2574.47 seconds
Started Jan 14 01:51:38 PM PST 24
Finished Jan 14 02:34:35 PM PST 24
Peak memory 248088 kb
Host smart-f56420aa-d2ed-47a4-95e8-e85a6e3b178d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971215065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.1971215065
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.682991627
Short name T88
Test name
Test status
Simulation time 69628848011 ps
CPU time 1377.45 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:14:32 PM PST 24
Peak memory 239940 kb
Host smart-d717d891-6bee-4108-af78-cddf0229f3e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682991627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.682991627
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.1430510113
Short name T521
Test name
Test status
Simulation time 12193894129 ps
CPU time 138.83 seconds
Started Jan 14 01:51:30 PM PST 24
Finished Jan 14 01:53:50 PM PST 24
Peak memory 207152 kb
Host smart-59b8c715-a5fb-425d-93e3-1ad3f70c790c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430510113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.1430510113
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2829732467
Short name T670
Test name
Test status
Simulation time 29647622993 ps
CPU time 586.51 seconds
Started Jan 14 01:51:29 PM PST 24
Finished Jan 14 02:01:17 PM PST 24
Peak memory 231048 kb
Host smart-735557c5-f1ca-4bfb-a560-b30bc99a58e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829732467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.2829732467
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3546270032
Short name T495
Test name
Test status
Simulation time 62179364636 ps
CPU time 2065.18 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:26:00 PM PST 24
Peak memory 223540 kb
Host smart-f76d7ef9-7a8e-4197-8b5d-ca6b03a86453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546270032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.3546270032
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.2377326484
Short name T254
Test name
Test status
Simulation time 593194576081 ps
CPU time 1670.6 seconds
Started Jan 14 01:51:34 PM PST 24
Finished Jan 14 02:19:26 PM PST 24
Peak memory 248168 kb
Host smart-980a7873-d872-4351-b07c-551c36d23137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377326484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.2377326484
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2577974995
Short name T560
Test name
Test status
Simulation time 82836531 ps
CPU time 0.54 seconds
Started Jan 14 01:48:33 PM PST 24
Finished Jan 14 01:48:35 PM PST 24
Peak memory 193188 kb
Host smart-df69b29c-c776-415a-9446-26e1cb76da09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577974995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2577974995
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2794948477
Short name T53
Test name
Test status
Simulation time 1217291364 ps
CPU time 18.57 seconds
Started Jan 14 01:48:40 PM PST 24
Finished Jan 14 01:48:59 PM PST 24
Peak memory 214388 kb
Host smart-e6e3e274-23fd-4bde-a469-b23e6039b355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794948477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2794948477
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2273049245
Short name T245
Test name
Test status
Simulation time 1427906362 ps
CPU time 24.91 seconds
Started Jan 14 01:48:34 PM PST 24
Finished Jan 14 01:49:00 PM PST 24
Peak memory 198816 kb
Host smart-f01474f1-4d89-4306-8f7b-223dedfed773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273049245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2273049245
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3562433957
Short name T348
Test name
Test status
Simulation time 3980238484 ps
CPU time 106.82 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 01:50:18 PM PST 24
Peak memory 198856 kb
Host smart-d25c7a6f-c189-4aa9-a862-4f9ad83bced7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562433957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3562433957
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2504004012
Short name T676
Test name
Test status
Simulation time 7222898694 ps
CPU time 54.35 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:49:23 PM PST 24
Peak memory 198824 kb
Host smart-29748b91-1d4b-4e5e-8168-9754c77fb9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504004012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2504004012
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1470185577
Short name T318
Test name
Test status
Simulation time 3913224257 ps
CPU time 53.1 seconds
Started Jan 14 01:48:33 PM PST 24
Finished Jan 14 01:49:27 PM PST 24
Peak memory 198888 kb
Host smart-2145dccd-5dc9-40b8-9571-ec8324981930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470185577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1470185577
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.102409453
Short name T465
Test name
Test status
Simulation time 1213117965 ps
CPU time 3.9 seconds
Started Jan 14 01:48:33 PM PST 24
Finished Jan 14 01:48:38 PM PST 24
Peak memory 198580 kb
Host smart-f86546ee-7f6d-4117-b754-12e4224a8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102409453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.102409453
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3590534165
Short name T625
Test name
Test status
Simulation time 2822213399 ps
CPU time 115.64 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:50:26 PM PST 24
Peak memory 233600 kb
Host smart-a3ec416d-14ba-4c4d-a767-4abf74d5e54c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590534165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3590534165
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.23274741
Short name T631
Test name
Test status
Simulation time 174664249806 ps
CPU time 1565.98 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 02:14:36 PM PST 24
Peak memory 231700 kb
Host smart-aa07b8f4-573f-4197-a92c-dbfdc49ec510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23274741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.23274741
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.4238260024
Short name T520
Test name
Test status
Simulation time 32038898 ps
CPU time 1.06 seconds
Started Jan 14 01:48:28 PM PST 24
Finished Jan 14 01:48:30 PM PST 24
Peak memory 197440 kb
Host smart-718babad-01e8-47f1-9d5d-a7e21d29213b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238260024 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.4238260024
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.643924420
Short name T253
Test name
Test status
Simulation time 159179545210 ps
CPU time 406.07 seconds
Started Jan 14 01:48:30 PM PST 24
Finished Jan 14 01:55:17 PM PST 24
Peak memory 198856 kb
Host smart-4bc7c4ed-b3c5-4f24-9f48-b47ae950759c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643924420 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.643924420
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.364127118
Short name T407
Test name
Test status
Simulation time 14471198117 ps
CPU time 72.82 seconds
Started Jan 14 01:48:29 PM PST 24
Finished Jan 14 01:49:43 PM PST 24
Peak memory 198768 kb
Host smart-d69378e4-eaf8-4183-8ba3-fcb5bbf98be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364127118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.364127118
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3100731930
Short name T511
Test name
Test status
Simulation time 26632394823 ps
CPU time 487.19 seconds
Started Jan 14 01:51:38 PM PST 24
Finished Jan 14 01:59:48 PM PST 24
Peak memory 215064 kb
Host smart-223ac3f7-3306-4a64-8e20-147853b8444c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100731930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.3100731930
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.1603416264
Short name T836
Test name
Test status
Simulation time 426128603658 ps
CPU time 3322.36 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:46:57 PM PST 24
Peak memory 256316 kb
Host smart-a9984c9e-f3a8-49c9-99d6-789ebe2710ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603416264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.1603416264
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.3433324430
Short name T668
Test name
Test status
Simulation time 498643594525 ps
CPU time 1794.1 seconds
Started Jan 14 01:51:34 PM PST 24
Finished Jan 14 02:21:30 PM PST 24
Peak memory 224584 kb
Host smart-aec3e64a-368e-4799-afa6-194173092ac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433324430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.3433324430
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.3195702298
Short name T816
Test name
Test status
Simulation time 36557922514 ps
CPU time 1636.85 seconds
Started Jan 14 01:51:34 PM PST 24
Finished Jan 14 02:18:53 PM PST 24
Peak memory 218448 kb
Host smart-5ed947f7-78ac-4143-9469-1369b9853e2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195702298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.3195702298
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.2711573458
Short name T589
Test name
Test status
Simulation time 29696146353 ps
CPU time 1425.86 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 02:15:18 PM PST 24
Peak memory 236848 kb
Host smart-bad51d83-a748-42d7-a2d3-8794c7e2025f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711573458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.2711573458
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1089815037
Short name T381
Test name
Test status
Simulation time 1463402468667 ps
CPU time 3657.29 seconds
Started Jan 14 01:51:34 PM PST 24
Finished Jan 14 02:52:33 PM PST 24
Peak memory 244916 kb
Host smart-d88b8de2-5b0b-4997-bca6-7d45471d7b76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089815037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.1089815037
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3922132651
Short name T614
Test name
Test status
Simulation time 2893742961786 ps
CPU time 2242.04 seconds
Started Jan 14 01:51:33 PM PST 24
Finished Jan 14 02:28:56 PM PST 24
Peak memory 241980 kb
Host smart-6fc59dd2-58e5-4c2e-8074-c415c1a5e7c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922132651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.3922132651
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2194760470
Short name T553
Test name
Test status
Simulation time 496253475992 ps
CPU time 1375.55 seconds
Started Jan 14 01:51:32 PM PST 24
Finished Jan 14 02:14:28 PM PST 24
Peak memory 253212 kb
Host smart-72b42b53-3704-4408-ac11-24d81bff7dcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194760470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.2194760470
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2077610181
Short name T355
Test name
Test status
Simulation time 545121528191 ps
CPU time 2549.45 seconds
Started Jan 14 01:51:31 PM PST 24
Finished Jan 14 02:34:02 PM PST 24
Peak memory 240800 kb
Host smart-cbba45eb-1817-4ce6-9069-289236fd5460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077610181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.2077610181
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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