Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	39442423	1			T12	8		T17	8		T21	1
all_values[1]	39442423	1			T12	8		T17	8		T21	1
all_values[2]	39442423	1			T12	8		T17	8		T21	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135419

1

T12

10

T17

14

T21

3

auto[1]

118191850

1

T12

14

T17

10

T30

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85806770

1

T12

16

T17

13

T21

3

auto[1]

32520499

1

T12

8

T17

11

T30

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40407	1			T12	3		T17	1		T21	1
all_values[0]	auto[0]	auto[1]	1275	1			T12	1		T17	1		T30	2
all_values[0]	auto[1]	auto[0]	39234076	1			T12	2		T17	1		T45	2
all_values[0]	auto[1]	auto[1]	166665	1			T12	2		T17	5		T30	2
all_values[1]	auto[0]	auto[0]	25487	1			T12	1		T17	5		T21	1
all_values[1]	auto[0]	auto[1]	18592	1			T12	1		T30	3		T122	1
all_values[1]	auto[1]	auto[0]	22111583	1			T12	6		T17	2		T30	1
all_values[1]	auto[1]	auto[1]	17286761	1			T17	1		T45	1		T122	1
all_values[2]	auto[0]	auto[0]	34661	1			T12	2		T17	4		T21	1
all_values[2]	auto[0]	auto[1]	14997	1			T12	2		T17	3		T63	1
all_values[2]	auto[1]	auto[0]	24360556	1			T12	2		T30	1		T45	2
all_values[2]	auto[1]	auto[1]	15032209	1			T12	2		T17	1		T30	3