Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19890757

1

T1

50

T2

3769

T3

4623

auto[1]

9746183

1

T1

30

T2

3119

T3

5814

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9711726

1

T1

59

T2

3162

T3

5207

auto[1]

19925214

1

T1

21

T2

3726

T3

5230

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17477071

1

T1

35

T2

4493

T3

5283

auto[1]

12159869

1

T1

45

T2

2395

T3

5154

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16290074	1			T1	62		T2	5972		T3	3728
fifo_depth[1]	1475725	1			T1	8		T2	335		T3	751
fifo_depth[2]	1338350	1			T1	6		T2	254		T3	800
fifo_depth[3]	1141804	1			T1	2		T2	123		T3	739
fifo_depth[4]	1124713	1			T1	1		T2	117		T3	765
fifo_depth[5]	958747	1			T1	1		T2	36		T3	750
fifo_depth[6]	1002333	1			T2	20		T3	684		T8	1104
fifo_depth[7]	852854	1			T2	7		T3	685		T8	957
fifo_depth[8]	1044159	1			T2	21		T3	558		T8	812
fifo_depth[9]	605192	1			T2	1		T3	435		T8	594
fifo_depth[10]	628175	1			T2	1		T3	261		T8	409
fifo_depth[11]	383194	1			T2	1		T3	145		T8	231
fifo_depth[12]	653134	1			T3	89		T8	125		T4	139
fifo_depth[13]	288997	1			T3	29		T8	52		T4	59
fifo_depth[14]	482603	1			T3	14		T8	19		T4	26
fifo_depth[15]	273388	1			T3	3		T8	7		T4	10
fifo_depth[16]	1093498	1			T3	1		T8	4		T4	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13346866

1

T1

18

T2

916

T3

6709

auto[1]

16290074

1

T1

62

T2

5972

T3

3728

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28543442

1

T1

80

T2

6888

T3

10436

auto[1]

1093498

1

T3

1

T8

4

T4

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1052952

1

T2

51

T3

460

T4

1653

auto[0]

auto[0]

auto[0]

auto[1]

1014863

1

T2

183

T3

953

T4

1047

auto[0]

auto[0]

auto[1]

auto[0]

3454680

1

T2

153

T3

1139

T4

444

auto[0]

auto[0]

auto[1]

auto[1]

1085186

1

T2

80

T3

806

T4

2221

auto[0]

auto[1]

auto[0]

auto[0]

1683261

1

T1

4

T2

103

T3

588

auto[0]

auto[1]

auto[0]

auto[1]

1691795

1

T1

3

T2

93

T3

1344

auto[0]

auto[1]

auto[1]

auto[0]

1671633

1

T1

5

T2

71

T3

792

auto[0]

auto[1]

auto[1]

auto[1]

1692496

1

T1

6

T2

182

T3

627

auto[1]

auto[0]

auto[0]

auto[0]

794079

1

T1

27

T2

330

T3

281

auto[1]

auto[0]

auto[0]

auto[1]

774338

1

T1

8

T2

1283

T3

548

auto[1]

auto[0]

auto[1]

auto[0]

8496618

1

T2

1994

T3

645

T6

24

auto[1]

auto[0]

auto[1]

auto[1]

804355

1

T2

419

T3

451

T6

46

auto[1]

auto[1]

auto[0]

auto[0]

1359304

1

T1

11

T2

658

T3

304

auto[1]

auto[1]

auto[0]

auto[1]

1341134

1

T1

6

T2

461

T3

729

auto[1]

auto[1]

auto[1]

auto[0]

1378230

1

T1

3

T2

409

T3

414

auto[1]

auto[1]

auto[1]

auto[1]

1342016

1

T1

7

T2

418

T3

356

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1701266

1

T1

27

T2

381

T3

741

auto[0]

auto[0]

auto[0]

auto[1]

1665531

1

T1

8

T2

1466

T3

1500

auto[0]

auto[0]

auto[1]

auto[0]

11813209

1

T2

2147

T3

1784

T6

24

auto[0]

auto[0]

auto[1]

auto[1]

1739529

1

T2

499

T3

1257

T6

46

auto[0]

auto[1]

auto[0]

auto[0]

2914417

1

T1

15

T2

761

T3

892

auto[0]

auto[1]

auto[0]

auto[1]

2883248

1

T1

9

T2

554

T3

2073

auto[0]

auto[1]

auto[1]

auto[0]

2929452

1

T1

8

T2

480

T3

1206

auto[0]

auto[1]

auto[1]

auto[1]

2896790

1

T1

13

T2

600

T3

983

auto[1]

auto[0]

auto[0]

auto[0]

145765

1

T31

1508

T33

1505

T34

2874

auto[1]

auto[0]

auto[0]

auto[1]

123670

1

T3

1

T31

1433

T32

1

auto[1]

auto[0]

auto[1]

auto[0]

138089

1

T31

2107

T33

5995

T34

2818

auto[1]

auto[0]

auto[1]

auto[1]

150012

1

T31

1749

T33

3497

T34

1822

auto[1]

auto[1]

auto[0]

auto[0]

128148

1

T8

2

T4

1

T31

2038

auto[1]

auto[1]

auto[0]

auto[1]

149681

1

T11

3

T31

2082

T33

1501

auto[1]

auto[1]

auto[1]

auto[0]

120411

1

T8

1

T4

2

T31

1143

auto[1]

auto[1]

auto[1]

auto[1]

137722

1

T8

1

T31

1170

T32

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	794079	1			T1	27		T2	330		T3	281
fifo_depth[0]	auto[0]	auto[0]	auto[1]	774338	1			T1	8		T2	1283		T3	548
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8496618	1			T2	1994		T3	645		T6	24
fifo_depth[0]	auto[0]	auto[1]	auto[1]	804355	1			T2	419		T3	451		T6	46
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1359304	1			T1	11		T2	658		T3	304
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1341134	1			T1	6		T2	461		T3	729
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1378230	1			T1	3		T2	409		T3	414
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1342016	1			T1	7		T2	418		T3	356
fifo_depth[1]	auto[0]	auto[0]	auto[0]	75236	1			T2	22		T3	46		T4	193
fifo_depth[1]	auto[0]	auto[0]	auto[1]	73858	1			T2	80		T3	119		T4	181
fifo_depth[1]	auto[0]	auto[1]	auto[0]	614033	1			T2	74		T3	117		T4	47
fifo_depth[1]	auto[0]	auto[1]	auto[1]	75901	1			T2	26		T3	102		T4	287
fifo_depth[1]	auto[1]	auto[0]	auto[0]	161647	1			T1	1		T2	39		T3	65
fifo_depth[1]	auto[1]	auto[0]	auto[1]	157223	1			T1	1		T2	28		T3	144
fifo_depth[1]	auto[1]	auto[1]	auto[0]	159631	1			T1	3		T2	30		T3	85
fifo_depth[1]	auto[1]	auto[1]	auto[1]	158196	1			T1	3		T2	36		T3	73
fifo_depth[2]	auto[0]	auto[0]	auto[0]	71946	1			T2	16		T3	52		T4	188
fifo_depth[2]	auto[0]	auto[0]	auto[1]	70270	1			T2	61		T3	108		T4	179
fifo_depth[2]	auto[0]	auto[1]	auto[0]	523443	1			T2	38		T3	129		T4	49
fifo_depth[2]	auto[0]	auto[1]	auto[1]	71858	1			T2	19		T3	97		T4	300
fifo_depth[2]	auto[1]	auto[0]	auto[0]	154499	1			T1	2		T2	39		T3	70
fifo_depth[2]	auto[1]	auto[0]	auto[1]	147228	1			T1	1		T2	17		T3	164
fifo_depth[2]	auto[1]	auto[1]	auto[0]	150866	1			T1	2		T2	24		T3	93
fifo_depth[2]	auto[1]	auto[1]	auto[1]	148240	1			T1	1		T2	40		T3	87
fifo_depth[3]	auto[0]	auto[0]	auto[0]	62508	1			T2	11		T3	48		T4	178
fifo_depth[3]	auto[0]	auto[0]	auto[1]	61824	1			T2	26		T3	108		T4	129
fifo_depth[3]	auto[0]	auto[1]	auto[0]	415056	1			T2	18		T3	128		T4	49
fifo_depth[3]	auto[0]	auto[1]	auto[1]	63349	1			T2	11		T3	94		T4	264
fifo_depth[3]	auto[1]	auto[0]	auto[0]	138966	1			T2	14		T3	55		T8	477
fifo_depth[3]	auto[1]	auto[0]	auto[1]	132019	1			T2	10		T3	155		T8	143
fifo_depth[3]	auto[1]	auto[1]	auto[0]	135048	1			T2	13		T3	73		T8	142
fifo_depth[3]	auto[1]	auto[1]	auto[1]	133034	1			T1	2		T2	20		T3	78
fifo_depth[4]	auto[0]	auto[0]	auto[0]	74373	1			T2	1		T3	60		T4	202
fifo_depth[4]	auto[0]	auto[0]	auto[1]	72819	1			T2	9		T3	108		T4	136
fifo_depth[4]	auto[0]	auto[1]	auto[0]	332027	1			T2	21		T3	138		T4	51
fifo_depth[4]	auto[0]	auto[1]	auto[1]	74880	1			T2	9		T3	86		T4	250
fifo_depth[4]	auto[1]	auto[0]	auto[0]	146325	1			T1	1		T2	9		T3	66
fifo_depth[4]	auto[1]	auto[0]	auto[1]	138096	1			T2	34		T3	161		T8	163
fifo_depth[4]	auto[1]	auto[1]	auto[0]	144607	1			T2	4		T3	81		T8	116
fifo_depth[4]	auto[1]	auto[1]	auto[1]	141586	1			T2	30		T3	65		T8	301
fifo_depth[5]	auto[0]	auto[0]	auto[0]	60209	1			T3	65		T4	185		T5	28
fifo_depth[5]	auto[0]	auto[0]	auto[1]	60052	1			T2	6		T3	126		T4	117
fifo_depth[5]	auto[0]	auto[1]	auto[0]	270744	1			T2	2		T3	134		T4	47
fifo_depth[5]	auto[0]	auto[1]	auto[1]	60234	1			T2	5		T3	89		T4	243
fifo_depth[5]	auto[1]	auto[0]	auto[0]	130417	1			T2	2		T3	60		T8	460
fifo_depth[5]	auto[1]	auto[0]	auto[1]	123772	1			T1	1		T2	3		T3	144
fifo_depth[5]	auto[1]	auto[1]	auto[0]	127756	1			T3	82		T8	139		T4	303
fifo_depth[5]	auto[1]	auto[1]	auto[1]	125563	1			T2	18		T3	50		T8	330
fifo_depth[6]	auto[0]	auto[0]	auto[0]	70205	1			T2	1		T3	43		T4	177
fifo_depth[6]	auto[0]	auto[0]	auto[1]	68249	1			T2	1		T3	87		T4	100
fifo_depth[6]	auto[0]	auto[1]	auto[0]	251957	1			T3	124		T4	50		T5	32
fifo_depth[6]	auto[0]	auto[1]	auto[1]	72601	1			T2	6		T3	80		T4	234
fifo_depth[6]	auto[1]	auto[0]	auto[0]	137445	1			T3	62		T8	486		T4	47
fifo_depth[6]	auto[1]	auto[0]	auto[1]	131159	1			T3	134		T8	159		T4	340
fifo_depth[6]	auto[1]	auto[1]	auto[0]	136694	1			T3	90		T8	131		T4	282
fifo_depth[6]	auto[1]	auto[1]	auto[1]	134023	1			T2	12		T3	64		T8	328
fifo_depth[7]	auto[0]	auto[0]	auto[0]	58424	1			T3	45		T4	147		T5	9
fifo_depth[7]	auto[0]	auto[0]	auto[1]	58325	1			T3	90		T4	80		T5	6
fifo_depth[7]	auto[0]	auto[1]	auto[0]	200806	1			T3	112		T4	43		T5	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	60399	1			T2	1		T3	82		T4	225
fifo_depth[7]	auto[1]	auto[0]	auto[0]	120740	1			T3	58		T8	434		T4	44
fifo_depth[7]	auto[1]	auto[0]	auto[1]	116557	1			T3	144		T8	118		T4	283
fifo_depth[7]	auto[1]	auto[1]	auto[0]	120251	1			T3	95		T8	124		T4	291
fifo_depth[7]	auto[1]	auto[1]	auto[1]	117352	1			T2	6		T3	59		T8	281
fifo_depth[8]	auto[0]	auto[0]	auto[0]	93630	1			T3	36		T4	152		T5	12
fifo_depth[8]	auto[0]	auto[0]	auto[1]	89934	1			T3	82		T4	54		T5	4
fifo_depth[8]	auto[0]	auto[1]	auto[0]	195265	1			T3	85		T4	36		T5	13
fifo_depth[8]	auto[0]	auto[1]	auto[1]	96642	1			T2	3		T3	62		T4	154
fifo_depth[8]	auto[1]	auto[0]	auto[0]	140427	1			T3	63		T8	367		T4	43
fifo_depth[8]	auto[1]	auto[0]	auto[1]	140879	1			T2	1		T3	110		T8	114
fifo_depth[8]	auto[1]	auto[1]	auto[0]	143325	1			T3	66		T8	109		T4	254
fifo_depth[8]	auto[1]	auto[1]	auto[1]	144057	1			T2	17		T3	54		T8	222
fifo_depth[9]	auto[0]	auto[0]	auto[0]	46614	1			T3	23		T4	85		T31	360
fifo_depth[9]	auto[0]	auto[0]	auto[1]	47332	1			T3	58		T4	25		T5	2
fifo_depth[9]	auto[0]	auto[1]	auto[0]	117367	1			T3	80		T4	28		T5	1
fifo_depth[9]	auto[0]	auto[1]	auto[1]	48937	1			T3	49		T4	123		T31	432
fifo_depth[9]	auto[1]	auto[0]	auto[0]	85231	1			T3	39		T8	278		T4	33
fifo_depth[9]	auto[1]	auto[0]	auto[1]	85038	1			T3	86		T8	70		T4	205
fifo_depth[9]	auto[1]	auto[1]	auto[0]	86929	1			T3	55		T8	75		T4	193
fifo_depth[9]	auto[1]	auto[1]	auto[1]	87744	1			T2	1		T3	45		T8	171
fifo_depth[10]	auto[0]	auto[0]	auto[0]	58119	1			T3	20		T4	72		T31	497
fifo_depth[10]	auto[0]	auto[0]	auto[1]	59455	1			T3	26		T4	18		T31	532
fifo_depth[10]	auto[0]	auto[1]	auto[0]	105049	1			T3	49		T4	27		T5	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	62320	1			T3	35		T4	81		T31	426
fifo_depth[10]	auto[1]	auto[0]	auto[0]	82670	1			T3	22		T8	171		T4	25
fifo_depth[10]	auto[1]	auto[0]	auto[1]	86920	1			T3	49		T8	58		T4	115
fifo_depth[10]	auto[1]	auto[1]	auto[0]	84598	1			T3	34		T8	63		T4	106
fifo_depth[10]	auto[1]	auto[1]	auto[1]	89044	1			T2	1		T3	26		T8	117
fifo_depth[11]	auto[0]	auto[0]	auto[0]	35423	1			T3	10		T4	39		T31	329
fifo_depth[11]	auto[0]	auto[0]	auto[1]	37032	1			T3	20		T4	12		T31	331
fifo_depth[11]	auto[0]	auto[1]	auto[0]	62883	1			T3	24		T4	13		T9	149
fifo_depth[11]	auto[0]	auto[1]	auto[1]	39320	1			T3	18		T4	42		T31	308
fifo_depth[11]	auto[1]	auto[0]	auto[0]	49370	1			T3	12		T8	100		T4	13
fifo_depth[11]	auto[1]	auto[0]	auto[1]	52815	1			T3	30		T8	35		T4	64
fifo_depth[11]	auto[1]	auto[1]	auto[0]	52271	1			T3	19		T8	30		T4	59
fifo_depth[11]	auto[1]	auto[1]	auto[1]	54080	1			T2	1		T3	12		T8	66
fifo_depth[12]	auto[0]	auto[0]	auto[0]	76643	1			T3	10		T4	22		T31	956
fifo_depth[12]	auto[0]	auto[0]	auto[1]	71608	1			T3	12		T4	9		T31	911
fifo_depth[12]	auto[0]	auto[1]	auto[0]	87930	1			T3	17		T4	2		T9	82
fifo_depth[12]	auto[0]	auto[1]	auto[1]	80927	1			T3	11		T4	12		T31	1901
fifo_depth[12]	auto[1]	auto[0]	auto[0]	80860	1			T3	9		T8	60		T4	8
fifo_depth[12]	auto[1]	auto[0]	auto[1]	87481	1			T3	12		T8	11		T4	38
fifo_depth[12]	auto[1]	auto[1]	auto[0]	83160	1			T3	11		T8	22		T4	38
fifo_depth[12]	auto[1]	auto[1]	auto[1]	84525	1			T3	7		T8	32		T4	10
fifo_depth[13]	auto[0]	auto[0]	auto[0]	33160	1			T4	7		T31	244		T32	10
fifo_depth[13]	auto[0]	auto[0]	auto[1]	33507	1			T3	6		T4	4		T31	367
fifo_depth[13]	auto[0]	auto[1]	auto[0]	40243	1			T3	2		T4	2		T9	34
fifo_depth[13]	auto[0]	auto[1]	auto[1]	34511	1			T3	1		T4	4		T31	293
fifo_depth[13]	auto[1]	auto[0]	auto[0]	33537	1			T3	6		T8	32		T4	4
fifo_depth[13]	auto[1]	auto[0]	auto[1]	39864	1			T3	7		T8	4		T4	13
fifo_depth[13]	auto[1]	auto[1]	auto[0]	35428	1			T3	3		T8	5		T4	16
fifo_depth[13]	auto[1]	auto[1]	auto[1]	38747	1			T3	4		T8	11		T4	9
fifo_depth[14]	auto[0]	auto[0]	auto[0]	58321	1			T3	1		T4	4		T31	695
fifo_depth[14]	auto[0]	auto[0]	auto[1]	55133	1			T3	2		T31	701		T32	3
fifo_depth[14]	auto[0]	auto[1]	auto[0]	63664	1			T9	12		T31	739		T32	4
fifo_depth[14]	auto[0]	auto[1]	auto[1]	60044	1			T4	1		T31	1545		T32	4
fifo_depth[14]	auto[1]	auto[0]	auto[0]	59863	1			T8	12		T4	1		T11	4
fifo_depth[14]	auto[1]	auto[0]	auto[1]	65161	1			T3	3		T4	8		T11	6
fifo_depth[14]	auto[1]	auto[1]	auto[0]	57982	1			T3	5		T8	4		T4	6
fifo_depth[14]	auto[1]	auto[1]	auto[1]	62435	1			T3	3		T8	3		T4	6
fifo_depth[15]	auto[0]	auto[0]	auto[0]	32376	1			T3	1		T4	2		T31	169
fifo_depth[15]	auto[0]	auto[0]	auto[1]	31795	1			T4	3		T31	276		T32	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	36124	1			T9	4		T31	213		T32	1
fifo_depth[15]	auto[0]	auto[1]	auto[1]	33251	1			T4	1		T31	708		T32	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	33116	1			T3	1		T8	3		T4	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	37902	1			T3	1		T8	2		T4	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	32676	1			T8	1		T4	1		T31	423
fifo_depth[15]	auto[1]	auto[1]	auto[1]	36148	1			T8	1		T4	1		T31	342
fifo_depth[16]	auto[0]	auto[0]	auto[0]	145765	1			T31	1508		T33	1505		T34	2874
fifo_depth[16]	auto[0]	auto[0]	auto[1]	123670	1			T3	1		T31	1433		T32	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	138089	1			T31	2107		T33	5995		T34	2818
fifo_depth[16]	auto[0]	auto[1]	auto[1]	150012	1			T31	1749		T33	3497		T34	1822
fifo_depth[16]	auto[1]	auto[0]	auto[0]	128148	1			T8	2		T4	1		T31	2038
fifo_depth[16]	auto[1]	auto[0]	auto[1]	149681	1			T11	3		T31	2082		T33	1501
fifo_depth[16]	auto[1]	auto[1]	auto[0]	120411	1			T8	1		T4	2		T31	1143
fifo_depth[16]	auto[1]	auto[1]	auto[1]	137722	1			T8	1		T31	1170		T32	1