Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	39442423	1			T12	8		T17	8		T21	1
all_pins[1]	39442423	1			T12	8		T17	8		T21	1
all_pins[2]	39442423	1			T12	8		T17	8		T21	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85617890	1			T12	20		T17	17		T21	3
values[0x1]	32709379	1			T12	4		T17	7		T30	5
transitions[0x0=>0x1]	28757493	1			T12	3		T17	5		T30	4
transitions[0x1=>0x0]	28757524	1			T12	3		T17	5		T30	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	39271901	1			T12	6		T17	3		T21	1
all_pins[0]	values[0x1]	170522	1			T12	2		T17	5		T30	2
all_pins[0]	transitions[0x0=>0x1]	170265	1			T12	1		T17	4		T30	1
all_pins[0]	transitions[0x1=>0x0]	15031983	1			T12	1		T30	3		T122	1
all_pins[1]	values[0x0]	21935775	1			T12	8		T17	7		T21	1
all_pins[1]	values[0x1]	17506648	1			T17	1		T45	1		T122	1
all_pins[1]	transitions[0x0=>0x1]	17373426	1			T45	1		T122	1		T123	2
all_pins[1]	transitions[0x1=>0x0]	37300	1			T12	2		T17	4		T30	2
all_pins[2]	values[0x0]	24410214	1			T12	6		T17	7		T21	1
all_pins[2]	values[0x1]	15032209	1			T12	2		T17	1		T30	3
all_pins[2]	transitions[0x0=>0x1]	11213802	1			T12	2		T17	1		T30	3
all_pins[2]	transitions[0x1=>0x0]	13688241	1			T17	1		T45	1		T122	1