Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4242 1 T12 7 T17 7 T30 4
all_values[1] 4242 1 T12 7 T17 7 T30 4
all_values[2] 4242 1 T12 7 T17 7 T30 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6116 1 T12 13 T17 11 T30 8
auto[1] 6610 1 T12 8 T17 10 T30 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4758 1 T12 10 T17 8 T30 2
auto[1] 7968 1 T12 11 T17 13 T30 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7244 1 T12 14 T17 15 T30 7
auto[1] 5482 1 T12 7 T17 6 T30 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 736 1 T12 3 T17 1 T45 1
all_values[0] auto[0] auto[0] auto[1] 422 1 T12 1 T30 2 T63 2
all_values[0] auto[0] auto[1] auto[0] 882 1 T45 1 T122 1 T123 1
all_values[0] auto[0] auto[1] auto[1] 401 1 T12 1 T17 5 T30 1
all_values[0] auto[1] auto[0] auto[1] 883 1 T12 1 T17 1 T30 1
all_values[0] auto[1] auto[1] auto[1] 918 1 T12 1 T45 1 T63 1
all_values[1] auto[0] auto[0] auto[0] 732 1 T12 3 T17 2 T30 1
all_values[1] auto[0] auto[0] auto[1] 432 1 T30 1 T124 2 T125 1
all_values[1] auto[0] auto[1] auto[0] 865 1 T12 3 T17 2 T45 1
all_values[1] auto[0] auto[1] auto[1] 386 1 T17 1 T45 1 T123 1
all_values[1] auto[1] auto[0] auto[1] 869 1 T17 1 T30 2 T45 1
all_values[1] auto[1] auto[1] auto[1] 958 1 T12 1 T17 1 T122 1
all_values[2] auto[0] auto[0] auto[0] 724 1 T12 1 T17 3 T30 1
all_values[2] auto[0] auto[0] auto[1] 423 1 T12 1 T17 1 T122 1
all_values[2] auto[0] auto[1] auto[0] 819 1 T45 2 T63 1 T126 1
all_values[2] auto[0] auto[1] auto[1] 422 1 T12 1 T30 1 T123 1
all_values[2] auto[1] auto[0] auto[1] 895 1 T12 3 T17 2 T45 1
all_values[2] auto[1] auto[1] auto[1] 959 1 T12 1 T17 1 T30 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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