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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.60 99.53 98.58 100.00 100.00 99.76 99.49 99.86


Total test records in report: 906
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T757 /workspace/coverage/default/12.hmac_error.2010469246 Jan 17 12:50:17 PM PST 24 Jan 17 12:51:43 PM PST 24 6469694375 ps
T758 /workspace/coverage/default/21.hmac_test_hmac_vectors.1253691324 Jan 17 12:50:49 PM PST 24 Jan 17 12:50:51 PM PST 24 79881439 ps
T759 /workspace/coverage/default/26.hmac_wipe_secret.3629686315 Jan 17 12:50:56 PM PST 24 Jan 17 12:51:41 PM PST 24 14812162644 ps
T760 /workspace/coverage/default/10.hmac_wipe_secret.226148968 Jan 17 12:51:00 PM PST 24 Jan 17 12:51:57 PM PST 24 1505424505 ps
T761 /workspace/coverage/default/1.hmac_wipe_secret.3405174322 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:59 PM PST 24 16617477489 ps
T762 /workspace/coverage/default/28.hmac_back_pressure.1784299153 Jan 17 12:51:10 PM PST 24 Jan 17 12:51:51 PM PST 24 4427436086 ps
T763 /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.1552530116 Jan 17 12:52:05 PM PST 24 Jan 17 12:57:52 PM PST 24 73384251614 ps
T764 /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.1436897377 Jan 17 12:50:52 PM PST 24 Jan 17 01:14:25 PM PST 24 76946688076 ps
T765 /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.1816572255 Jan 17 12:50:20 PM PST 24 Jan 17 01:11:38 PM PST 24 295444562638 ps
T766 /workspace/coverage/default/29.hmac_test_sha_vectors.3456861378 Jan 17 12:51:08 PM PST 24 Jan 17 12:58:56 PM PST 24 181430600168 ps
T767 /workspace/coverage/default/15.hmac_datapath_stress.937900737 Jan 17 12:50:31 PM PST 24 Jan 17 12:52:50 PM PST 24 5134241156 ps
T768 /workspace/coverage/default/36.hmac_stress_all.1295759823 Jan 17 12:51:34 PM PST 24 Jan 17 01:02:39 PM PST 24 56483272788 ps
T769 /workspace/coverage/default/21.hmac_stress_all.3952061830 Jan 17 12:50:45 PM PST 24 Jan 17 12:52:36 PM PST 24 19628721120 ps
T770 /workspace/coverage/default/6.hmac_smoke.2546741273 Jan 17 12:50:14 PM PST 24 Jan 17 12:50:27 PM PST 24 435304199 ps
T771 /workspace/coverage/default/49.hmac_test_sha_vectors.2677267229 Jan 17 12:52:13 PM PST 24 Jan 17 12:58:57 PM PST 24 7867091309 ps
T772 /workspace/coverage/default/27.hmac_stress_all.3253845939 Jan 17 12:51:01 PM PST 24 Jan 17 12:59:48 PM PST 24 59952028569 ps
T773 /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.554617962 Jan 17 12:52:36 PM PST 24 Jan 17 01:48:15 PM PST 24 66489560051 ps
T774 /workspace/coverage/default/35.hmac_burst_wr.795133708 Jan 17 12:51:24 PM PST 24 Jan 17 12:52:34 PM PST 24 5844837158 ps
T775 /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.1506019564 Jan 17 12:52:31 PM PST 24 Jan 17 01:39:49 PM PST 24 258262230122 ps
T776 /workspace/coverage/default/22.hmac_burst_wr.2841745912 Jan 17 12:50:46 PM PST 24 Jan 17 12:51:05 PM PST 24 1231132586 ps
T777 /workspace/coverage/default/26.hmac_back_pressure.3390611778 Jan 17 12:51:05 PM PST 24 Jan 17 12:51:45 PM PST 24 2826876638 ps
T778 /workspace/coverage/default/8.hmac_wipe_secret.2688807927 Jan 17 12:50:17 PM PST 24 Jan 17 12:51:27 PM PST 24 6101624773 ps
T779 /workspace/coverage/default/17.hmac_error.4161214205 Jan 17 12:50:31 PM PST 24 Jan 17 12:53:04 PM PST 24 12554179113 ps
T780 /workspace/coverage/default/25.hmac_test_hmac_vectors.3069896325 Jan 17 12:50:52 PM PST 24 Jan 17 12:50:55 PM PST 24 169039605 ps
T781 /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.132183184 Jan 17 12:52:34 PM PST 24 Jan 17 01:04:49 PM PST 24 27919190686 ps
T782 /workspace/coverage/default/42.hmac_error.26705567 Jan 17 12:51:43 PM PST 24 Jan 17 12:51:56 PM PST 24 213014082 ps
T783 /workspace/coverage/default/1.hmac_alert_test.1964582172 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:11 PM PST 24 33695579 ps
T784 /workspace/coverage/default/2.hmac_wipe_secret.1875498135 Jan 17 12:50:06 PM PST 24 Jan 17 12:50:51 PM PST 24 5879958023 ps
T116 /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.2776025761 Jan 17 12:52:11 PM PST 24 Jan 17 01:09:16 PM PST 24 950342598528 ps
T785 /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2859269208 Jan 17 12:50:18 PM PST 24 Jan 17 01:45:21 PM PST 24 263754454794 ps
T786 /workspace/coverage/default/22.hmac_datapath_stress.1881606940 Jan 17 12:50:48 PM PST 24 Jan 17 12:52:47 PM PST 24 2261483602 ps
T787 /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.4074247288 Jan 17 12:52:35 PM PST 24 Jan 17 01:53:17 PM PST 24 85303400649 ps
T788 /workspace/coverage/default/13.hmac_datapath_stress.209378448 Jan 17 12:50:16 PM PST 24 Jan 17 12:51:31 PM PST 24 5750259589 ps
T789 /workspace/coverage/default/10.hmac_datapath_stress.3517811823 Jan 17 12:50:10 PM PST 24 Jan 17 12:51:30 PM PST 24 1315728297 ps
T790 /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1491142142 Jan 17 12:52:17 PM PST 24 Jan 17 01:00:11 PM PST 24 107880043744 ps
T791 /workspace/coverage/default/8.hmac_stress_all.4143005412 Jan 17 12:50:16 PM PST 24 Jan 17 01:19:35 PM PST 24 109259336451 ps
T792 /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.2249709448 Jan 17 12:52:35 PM PST 24 Jan 17 01:13:47 PM PST 24 327703869756 ps
T793 /workspace/coverage/default/27.hmac_datapath_stress.2957144231 Jan 17 12:50:57 PM PST 24 Jan 17 12:53:07 PM PST 24 18128240644 ps
T794 /workspace/coverage/default/42.hmac_datapath_stress.327983158 Jan 17 12:51:45 PM PST 24 Jan 17 12:53:52 PM PST 24 9380035437 ps
T795 /workspace/coverage/default/42.hmac_test_hmac_vectors.2913233355 Jan 17 12:51:42 PM PST 24 Jan 17 12:51:46 PM PST 24 41277722 ps
T796 /workspace/coverage/default/4.hmac_smoke.4074718232 Jan 17 12:50:08 PM PST 24 Jan 17 12:50:14 PM PST 24 165491926 ps
T797 /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.1576240753 Jan 17 12:52:17 PM PST 24 Jan 17 01:35:26 PM PST 24 80925415775 ps
T798 /workspace/coverage/default/20.hmac_smoke.3011197572 Jan 17 12:50:39 PM PST 24 Jan 17 12:50:44 PM PST 24 267684031 ps
T799 /workspace/coverage/default/48.hmac_test_sha_vectors.2099225455 Jan 17 12:52:08 PM PST 24 Jan 17 12:58:38 PM PST 24 20959780841 ps
T800 /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3370590162 Jan 17 12:52:29 PM PST 24 Jan 17 01:05:30 PM PST 24 210652583028 ps
T801 /workspace/coverage/default/26.hmac_burst_wr.599028850 Jan 17 12:50:59 PM PST 24 Jan 17 12:51:20 PM PST 24 14499442798 ps
T802 /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.3777361459 Jan 17 12:52:43 PM PST 24 Jan 17 12:58:46 PM PST 24 28105673432 ps
T803 /workspace/coverage/default/41.hmac_test_sha_vectors.2176171728 Jan 17 12:51:31 PM PST 24 Jan 17 12:59:25 PM PST 24 196168110620 ps
T804 /workspace/coverage/default/12.hmac_smoke.1775627800 Jan 17 12:50:18 PM PST 24 Jan 17 12:50:26 PM PST 24 169366017 ps
T805 /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3346004874 Jan 17 12:52:14 PM PST 24 Jan 17 01:31:59 PM PST 24 49420925795 ps
T806 /workspace/coverage/default/35.hmac_stress_all.1145237129 Jan 17 12:51:26 PM PST 24 Jan 17 12:52:53 PM PST 24 3387756152 ps
T807 /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.1842026908 Jan 17 12:52:12 PM PST 24 Jan 17 01:11:34 PM PST 24 62696212154 ps
T808 /workspace/coverage/default/24.hmac_long_msg.952307233 Jan 17 12:50:51 PM PST 24 Jan 17 12:51:57 PM PST 24 1243398632 ps
T809 /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2893149656 Jan 17 12:50:17 PM PST 24 Jan 17 01:22:15 PM PST 24 221931922658 ps
T810 /workspace/coverage/default/45.hmac_wipe_secret.2698760430 Jan 17 12:51:57 PM PST 24 Jan 17 12:52:44 PM PST 24 12534480277 ps
T811 /workspace/coverage/default/30.hmac_stress_all.3091253191 Jan 17 12:51:04 PM PST 24 Jan 17 12:51:45 PM PST 24 2157661465 ps
T812 /workspace/coverage/default/44.hmac_alert_test.4192558905 Jan 17 12:51:55 PM PST 24 Jan 17 12:51:57 PM PST 24 12355156 ps
T813 /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.4020217971 Jan 17 12:52:23 PM PST 24 Jan 17 12:56:46 PM PST 24 15353107715 ps
T814 /workspace/coverage/default/4.hmac_alert_test.254664137 Jan 17 12:50:08 PM PST 24 Jan 17 12:50:12 PM PST 24 12799550 ps
T815 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.1475598206 Jan 17 12:52:21 PM PST 24 Jan 17 01:15:08 PM PST 24 144217964294 ps
T816 /workspace/coverage/default/46.hmac_alert_test.809850941 Jan 17 12:52:01 PM PST 24 Jan 17 12:52:04 PM PST 24 11473885 ps
T817 /workspace/coverage/default/6.hmac_error.1390341936 Jan 17 12:50:29 PM PST 24 Jan 17 12:52:15 PM PST 24 13466268968 ps
T818 /workspace/coverage/default/13.hmac_burst_wr.657644209 Jan 17 12:50:19 PM PST 24 Jan 17 12:51:02 PM PST 24 1643249950 ps
T819 /workspace/coverage/default/43.hmac_alert_test.3027643560 Jan 17 12:51:48 PM PST 24 Jan 17 12:51:57 PM PST 24 31189585 ps
T117 /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.192420344 Jan 17 12:52:06 PM PST 24 Jan 17 01:36:22 PM PST 24 108608492008 ps
T820 /workspace/coverage/default/16.hmac_error.2849946761 Jan 17 12:50:37 PM PST 24 Jan 17 12:50:56 PM PST 24 977857099 ps
T821 /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3312558177 Jan 17 12:52:44 PM PST 24 Jan 17 01:02:42 PM PST 24 44893875128 ps
T822 /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.654802036 Jan 17 12:52:13 PM PST 24 Jan 17 01:10:49 PM PST 24 71146776950 ps
T823 /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.366554718 Jan 17 12:50:05 PM PST 24 Jan 17 01:13:24 PM PST 24 95344211594 ps
T824 /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.1134301174 Jan 17 12:51:28 PM PST 24 Jan 17 01:02:28 PM PST 24 523392658794 ps
T825 /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.708619381 Jan 17 12:52:26 PM PST 24 Jan 17 01:52:24 PM PST 24 97507497580 ps
T826 /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2482721257 Jan 17 12:52:22 PM PST 24 Jan 17 01:10:40 PM PST 24 1122060105542 ps
T827 /workspace/coverage/default/16.hmac_datapath_stress.2591766663 Jan 17 12:50:38 PM PST 24 Jan 17 12:53:19 PM PST 24 11236848328 ps
T828 /workspace/coverage/default/2.hmac_long_msg.3889089848 Jan 17 12:50:04 PM PST 24 Jan 17 12:52:11 PM PST 24 9619495859 ps
T829 /workspace/coverage/default/1.hmac_datapath_stress.3732289968 Jan 17 12:50:11 PM PST 24 Jan 17 12:50:33 PM PST 24 199366466 ps
T830 /workspace/coverage/default/17.hmac_wipe_secret.1261614097 Jan 17 12:50:31 PM PST 24 Jan 17 12:51:40 PM PST 24 14116388988 ps
T831 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1197154857 Jan 17 12:52:25 PM PST 24 Jan 17 01:43:59 PM PST 24 139831707536 ps
T832 /workspace/coverage/default/43.hmac_test_hmac_vectors.3531174568 Jan 17 12:51:46 PM PST 24 Jan 17 12:51:57 PM PST 24 66484985 ps
T833 /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.223396572 Jan 17 12:52:16 PM PST 24 Jan 17 01:20:06 PM PST 24 532866459975 ps
T834 /workspace/coverage/default/15.hmac_long_msg.3899361429 Jan 17 12:50:32 PM PST 24 Jan 17 12:51:27 PM PST 24 2107388307 ps
T835 /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.1673048689 Jan 17 12:52:43 PM PST 24 Jan 17 01:45:02 PM PST 24 187210619679 ps
T836 /workspace/coverage/default/41.hmac_burst_wr.1861081652 Jan 17 12:51:34 PM PST 24 Jan 17 12:52:33 PM PST 24 4585068483 ps
T837 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.1165285239 Jan 17 12:52:36 PM PST 24 Jan 17 01:03:39 PM PST 24 12688370246 ps
T838 /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2117133907 Jan 17 12:52:10 PM PST 24 Jan 17 01:07:27 PM PST 24 101347985525 ps
T839 /workspace/coverage/default/10.hmac_alert_test.2179214898 Jan 17 12:50:17 PM PST 24 Jan 17 12:50:26 PM PST 24 13979998 ps
T840 /workspace/coverage/default/33.hmac_alert_test.1276648310 Jan 17 12:51:21 PM PST 24 Jan 17 12:51:22 PM PST 24 22542092 ps
T841 /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.1636325175 Jan 17 12:52:15 PM PST 24 Jan 17 01:10:08 PM PST 24 44727620803 ps
T842 /workspace/coverage/default/47.hmac_datapath_stress.2104489328 Jan 17 12:52:00 PM PST 24 Jan 17 12:52:22 PM PST 24 719667984 ps
T843 /workspace/coverage/default/45.hmac_test_hmac_vectors.187158439 Jan 17 12:51:57 PM PST 24 Jan 17 12:51:59 PM PST 24 64962259 ps
T844 /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.3867369482 Jan 17 12:52:25 PM PST 24 Jan 17 01:36:10 PM PST 24 51358194019 ps
T845 /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.363062131 Jan 17 12:52:15 PM PST 24 Jan 17 01:05:44 PM PST 24 42442075698 ps
T846 /workspace/coverage/default/46.hmac_test_sha_vectors.1977353104 Jan 17 12:52:03 PM PST 24 Jan 17 12:58:09 PM PST 24 62506376365 ps
T847 /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3964631057 Jan 17 12:52:08 PM PST 24 Jan 17 01:17:38 PM PST 24 338893731935 ps
T848 /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.1203874644 Jan 17 12:50:31 PM PST 24 Jan 17 01:34:38 PM PST 24 54955837901 ps
T849 /workspace/coverage/default/32.hmac_test_sha_vectors.1569078853 Jan 17 12:51:27 PM PST 24 Jan 17 12:59:57 PM PST 24 39906634076 ps
T850 /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.142847662 Jan 17 12:52:16 PM PST 24 Jan 17 12:58:07 PM PST 24 150155181843 ps
T851 /workspace/coverage/default/8.hmac_alert_test.2381025092 Jan 17 12:50:07 PM PST 24 Jan 17 12:50:11 PM PST 24 13714971 ps
T852 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1721004085 Jan 17 12:32:14 PM PST 24 Jan 17 12:32:18 PM PST 24 31485080 ps
T853 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2888662871 Jan 17 12:32:15 PM PST 24 Jan 17 12:32:19 PM PST 24 22484209 ps
T854 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3560894093 Jan 17 12:32:37 PM PST 24 Jan 17 12:32:41 PM PST 24 11613675 ps
T855 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.872441989 Jan 17 12:32:15 PM PST 24 Jan 17 12:32:22 PM PST 24 206303505 ps
T856 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1245476722 Jan 17 12:32:42 PM PST 24 Jan 17 12:32:44 PM PST 24 16100399 ps
T857 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2497422161 Jan 17 12:32:49 PM PST 24 Jan 17 12:32:58 PM PST 24 182679323 ps
T858 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1420287921 Jan 17 12:32:19 PM PST 24 Jan 17 12:32:27 PM PST 24 15100777 ps
T859 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1000936818 Jan 17 12:32:36 PM PST 24 Jan 17 12:32:41 PM PST 24 36506293 ps
T860 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3469747955 Jan 17 12:32:34 PM PST 24 Jan 17 12:48:43 PM PST 24 122276524633 ps
T82 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4127457272 Jan 17 12:32:42 PM PST 24 Jan 17 12:32:44 PM PST 24 38115975 ps
T861 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.312094508 Jan 17 12:32:14 PM PST 24 Jan 17 12:32:18 PM PST 24 35148257 ps
T129 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3367495381 Jan 17 12:32:19 PM PST 24 Jan 17 12:32:29 PM PST 24 169231975 ps
T862 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2244944565 Jan 17 12:32:24 PM PST 24 Jan 17 12:32:28 PM PST 24 18639842 ps
T863 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1779336362 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:20 PM PST 24 25296661 ps
T864 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3469691748 Jan 17 12:33:50 PM PST 24 Jan 17 12:33:53 PM PST 24 14327969 ps
T865 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3570132679 Jan 17 12:32:12 PM PST 24 Jan 17 12:40:13 PM PST 24 36973814408 ps
T866 /workspace/coverage/cover_reg_top/47.hmac_intr_test.403682047 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:20 PM PST 24 12623025 ps
T867 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1741207314 Jan 17 12:32:09 PM PST 24 Jan 17 12:32:12 PM PST 24 54924666 ps
T868 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1437944836 Jan 17 12:32:37 PM PST 24 Jan 17 12:32:41 PM PST 24 86341004 ps
T869 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.985017315 Jan 17 12:32:08 PM PST 24 Jan 17 12:32:11 PM PST 24 101988720 ps
T870 /workspace/coverage/cover_reg_top/13.hmac_intr_test.357837737 Jan 17 12:32:20 PM PST 24 Jan 17 12:32:28 PM PST 24 19810652 ps
T871 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3519521594 Jan 17 12:32:42 PM PST 24 Jan 17 12:32:44 PM PST 24 48373336 ps
T872 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1423698885 Jan 17 12:32:12 PM PST 24 Jan 17 12:32:15 PM PST 24 365227605 ps
T873 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1526703747 Jan 17 12:32:30 PM PST 24 Jan 17 12:32:32 PM PST 24 72471069 ps
T874 /workspace/coverage/cover_reg_top/11.hmac_intr_test.735700778 Jan 17 12:32:17 PM PST 24 Jan 17 12:32:20 PM PST 24 20862575 ps
T875 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1420071247 Jan 17 12:32:28 PM PST 24 Jan 17 12:32:31 PM PST 24 247733151 ps
T876 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3373055154 Jan 17 12:32:27 PM PST 24 Jan 17 12:32:30 PM PST 24 16580349 ps
T877 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4192470784 Jan 17 12:32:12 PM PST 24 Jan 17 12:32:20 PM PST 24 1814645066 ps
T61 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1435250056 Jan 17 12:32:19 PM PST 24 Jan 17 12:32:28 PM PST 24 405052067 ps
T878 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2436094928 Jan 17 12:36:06 PM PST 24 Jan 17 12:36:11 PM PST 24 148466153 ps
T879 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4282943885 Jan 17 12:32:15 PM PST 24 Jan 17 12:32:24 PM PST 24 643865929 ps
T880 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2484875949 Jan 17 12:32:20 PM PST 24 Jan 17 12:32:29 PM PST 24 23526485 ps
T881 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3775582888 Jan 17 12:32:21 PM PST 24 Jan 17 12:32:29 PM PST 24 13380112 ps
T882 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1403117704 Jan 17 12:32:32 PM PST 24 Jan 17 12:32:35 PM PST 24 108719679 ps
T883 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3751965942 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:20 PM PST 24 41786274 ps
T884 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3682994352 Jan 17 12:32:42 PM PST 24 Jan 17 12:32:45 PM PST 24 32569937 ps
T885 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.549428247 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:27 PM PST 24 21290220 ps
T886 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.737218271 Jan 17 12:32:16 PM PST 24 Jan 17 12:32:19 PM PST 24 53686493 ps
T887 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2365475885 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:20 PM PST 24 30350479 ps
T888 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3905964785 Jan 17 12:32:19 PM PST 24 Jan 17 12:32:28 PM PST 24 233012394 ps
T130 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3043916461 Jan 17 12:32:22 PM PST 24 Jan 17 12:32:29 PM PST 24 110294397 ps
T889 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2329735320 Jan 17 12:32:24 PM PST 24 Jan 17 12:32:29 PM PST 24 103689662 ps
T890 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.341333250 Jan 17 12:32:42 PM PST 24 Jan 17 12:32:44 PM PST 24 33364170 ps
T891 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2826428104 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:20 PM PST 24 19081801 ps
T892 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3634284668 Jan 17 12:32:08 PM PST 24 Jan 17 12:32:11 PM PST 24 202411121 ps
T893 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2443476084 Jan 17 12:32:20 PM PST 24 Jan 17 12:32:28 PM PST 24 15696857 ps
T894 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3263320747 Jan 17 12:32:36 PM PST 24 Jan 17 12:32:39 PM PST 24 686547569 ps
T895 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.612613923 Jan 17 12:32:13 PM PST 24 Jan 17 12:32:17 PM PST 24 42331378 ps
T896 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3789665293 Jan 17 12:32:18 PM PST 24 Jan 17 12:32:26 PM PST 24 421703253 ps
T897 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.446439489 Jan 17 12:32:30 PM PST 24 Jan 17 12:32:32 PM PST 24 31232030 ps
T898 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1010092236 Jan 17 12:32:27 PM PST 24 Jan 17 12:32:30 PM PST 24 69029228 ps
T899 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.939401305 Jan 17 12:32:29 PM PST 24 Jan 17 12:32:32 PM PST 24 43430811 ps
T900 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1756640309 Jan 17 12:32:13 PM PST 24 Jan 17 12:32:17 PM PST 24 93977814 ps
T901 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1416002522 Jan 17 12:32:08 PM PST 24 Jan 17 12:32:12 PM PST 24 210548275 ps
T902 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1821995491 Jan 17 12:32:19 PM PST 24 Jan 17 12:32:27 PM PST 24 15593501 ps
T903 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3342517829 Jan 17 12:32:09 PM PST 24 Jan 17 12:32:13 PM PST 24 535621943 ps
T904 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1196363429 Jan 17 12:32:29 PM PST 24 Jan 17 12:32:31 PM PST 24 42107791 ps
T905 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4041780140 Jan 17 12:32:30 PM PST 24 Jan 17 12:32:32 PM PST 24 17147299 ps
T906 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1533372078 Jan 17 12:32:37 PM PST 24 Jan 17 12:32:40 PM PST 24 106751078 ps

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2181206303
Short name T12
Test name
Test status
Simulation time 41686939 ps
CPU time 0.56 seconds
Started Jan 17 12:32:24 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193100 kb
Host smart-a5908e7c-38d7-442d-97f1-d0055618a5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181206303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2181206303
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.3568930019
Short name T5
Test name
Test status
Simulation time 108790743977 ps
CPU time 1664.8 seconds
Started Jan 17 12:52:10 PM PST 24
Finished Jan 17 01:19:56 PM PST 24
Peak memory 248028 kb
Host smart-e9c7772c-78bb-495e-9995-66abede9903b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568930019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.3568930019
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4273965218
Short name T16
Test name
Test status
Simulation time 113087985014 ps
CPU time 903.7 seconds
Started Jan 17 12:36:06 PM PST 24
Finished Jan 17 12:51:14 PM PST 24
Peak memory 211688 kb
Host smart-ca3a56cb-73c7-43e6-9085-c5ec5552bc2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273965218 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4273965218
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.2116344620
Short name T33
Test name
Test status
Simulation time 235894559046 ps
CPU time 5814.75 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 02:29:00 PM PST 24
Peak memory 264928 kb
Host smart-8285f569-2734-4063-badd-8c56f7dd9069
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116344620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.2116344620
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.290311251
Short name T128
Test name
Test status
Simulation time 478121672 ps
CPU time 1.87 seconds
Started Jan 17 12:32:29 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 198276 kb
Host smart-8d4657cf-3a5e-4bb9-ae27-92cbd3bee995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290311251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.290311251
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.265937633
Short name T14
Test name
Test status
Simulation time 51089770 ps
CPU time 0.64 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 194708 kb
Host smart-9446f1de-d48d-4dbc-bbe1-c31149de0ab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265937633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.265937633
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.1312586342
Short name T89
Test name
Test status
Simulation time 90264032105 ps
CPU time 2405.7 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:32:39 PM PST 24
Peak memory 248040 kb
Host smart-50dfa1e0-3c44-43bd-897d-f8afd06388ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312586342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.1312586342
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3363286479
Short name T46
Test name
Test status
Simulation time 67799472 ps
CPU time 0.78 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 215660 kb
Host smart-64b2fd9e-e00b-4751-8f7d-bab45ef7054d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363286479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3363286479
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3388162434
Short name T124
Test name
Test status
Simulation time 20559168 ps
CPU time 0.6 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193032 kb
Host smart-d7205f68-38e3-4a51-8b74-7cfbf218ac18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388162434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3388162434
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3473736712
Short name T90
Test name
Test status
Simulation time 625388719818 ps
CPU time 3399.91 seconds
Started Jan 17 12:52:38 PM PST 24
Finished Jan 17 01:49:19 PM PST 24
Peak memory 264424 kb
Host smart-e1dc318b-afab-4828-962d-c4074618de95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473736712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3473736712
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1452687087
Short name T103
Test name
Test status
Simulation time 167849021675 ps
CPU time 3661.12 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:53:30 PM PST 24
Peak memory 263964 kb
Host smart-d1518311-5d1a-49fd-9618-cdcbcec25d0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452687087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.1452687087
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1435250056
Short name T61
Test name
Test status
Simulation time 405052067 ps
CPU time 1.73 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198388 kb
Host smart-014808f1-6825-4b0e-8133-76e1eaa32ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435250056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1435250056
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3367495381
Short name T129
Test name
Test status
Simulation time 169231975 ps
CPU time 2.4 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198408 kb
Host smart-a3089346-0bbe-40e3-a5aa-8cc968069b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367495381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3367495381
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2131149195
Short name T107
Test name
Test status
Simulation time 105989670211 ps
CPU time 4967.71 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 02:15:31 PM PST 24
Peak memory 264392 kb
Host smart-94034778-02ba-4852-9d28-89e9749c883a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131149195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2131149195
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3056692556
Short name T240
Test name
Test status
Simulation time 15235553 ps
CPU time 0.57 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:50:42 PM PST 24
Peak memory 193024 kb
Host smart-7ed44231-e591-454a-a56a-68fc9ff8a6ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056692556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3056692556
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1503458341
Short name T137
Test name
Test status
Simulation time 13625960 ps
CPU time 0.58 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:25 PM PST 24
Peak memory 193176 kb
Host smart-2ce9cece-6c45-4d70-9879-afa2846b7a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503458341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1503458341
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.1903662620
Short name T534
Test name
Test status
Simulation time 74173864551 ps
CPU time 2131.43 seconds
Started Jan 17 12:52:31 PM PST 24
Finished Jan 17 01:28:08 PM PST 24
Peak memory 241720 kb
Host smart-f8669eed-504b-4ccb-9555-18d5ccbfe29b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903662620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.1903662620
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.569619178
Short name T36
Test name
Test status
Simulation time 166458108499 ps
CPU time 3115.8 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 01:42:21 PM PST 24
Peak memory 254020 kb
Host smart-57d70114-420d-49ab-9916-5262fe62c8ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569619178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.569619178
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.82926760
Short name T115
Test name
Test status
Simulation time 3428729711 ps
CPU time 54.4 seconds
Started Jan 17 12:51:44 PM PST 24
Finished Jan 17 12:52:40 PM PST 24
Peak memory 227540 kb
Host smart-8b4a4d65-6cd1-46e6-af53-98b6df7b974d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82926760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.82926760
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1739780891
Short name T29
Test name
Test status
Simulation time 539205174 ps
CPU time 2.55 seconds
Started Jan 17 12:32:12 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 196956 kb
Host smart-967599e6-02e5-4bcb-88b2-db103cc0ad11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739780891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1739780891
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4085845966
Short name T141
Test name
Test status
Simulation time 260425343 ps
CPU time 5.69 seconds
Started Jan 17 12:32:03 PM PST 24
Finished Jan 17 12:32:10 PM PST 24
Peak memory 192264 kb
Host smart-6e9e580c-6c44-4799-ab16-57fae55bd134
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085845966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4085845966
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1468461167
Short name T170
Test name
Test status
Simulation time 16550397 ps
CPU time 0.64 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193876 kb
Host smart-9659e6db-c79c-4fa1-ae42-72bffb45a8a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468461167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1468461167
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3100882693
Short name T177
Test name
Test status
Simulation time 29601742 ps
CPU time 1.45 seconds
Started Jan 17 12:31:53 PM PST 24
Finished Jan 17 12:31:56 PM PST 24
Peak memory 198624 kb
Host smart-6fafd5d1-78c1-4245-88bc-4dd5a0cac666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100882693 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3100882693
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1779336362
Short name T863
Test name
Test status
Simulation time 25296661 ps
CPU time 0.75 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 194584 kb
Host smart-ffd57edf-e4bc-47f2-b480-ef8ec60e2a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779336362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1779336362
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3446158859
Short name T145
Test name
Test status
Simulation time 41724325 ps
CPU time 0.56 seconds
Started Jan 17 12:32:09 PM PST 24
Finished Jan 17 12:32:10 PM PST 24
Peak memory 193096 kb
Host smart-d7f817b8-2587-4de5-bc4f-48cbd232cd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446158859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3446158859
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.127546450
Short name T166
Test name
Test status
Simulation time 25421216 ps
CPU time 1.04 seconds
Started Jan 17 12:32:08 PM PST 24
Finished Jan 17 12:32:10 PM PST 24
Peak memory 192260 kb
Host smart-4e2bb8c1-8b66-47b5-bde4-dab262db2f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127546450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.127546450
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2928457134
Short name T21
Test name
Test status
Simulation time 842368840 ps
CPU time 2.9 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 198660 kb
Host smart-3b141419-3455-4115-89f5-b2345f1861f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928457134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2928457134
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1216057768
Short name T80
Test name
Test status
Simulation time 23019437 ps
CPU time 1.13 seconds
Started Jan 17 12:32:08 PM PST 24
Finished Jan 17 12:32:10 PM PST 24
Peak memory 184008 kb
Host smart-7103ae93-ecb2-475d-aa7a-06fd973dd81a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216057768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1216057768
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1706993569
Short name T77
Test name
Test status
Simulation time 343166347 ps
CPU time 3.62 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:31 PM PST 24
Peak memory 192248 kb
Host smart-7b71c1d1-6a57-46a0-82cb-402a794d9145
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706993569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1706993569
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3314284975
Short name T181
Test name
Test status
Simulation time 30972985 ps
CPU time 0.66 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 194024 kb
Host smart-4728ed80-d7b1-4359-8b73-8221e5be0312
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314284975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3314284975
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2682400193
Short name T27
Test name
Test status
Simulation time 91824789 ps
CPU time 2.32 seconds
Started Jan 17 12:32:09 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 198604 kb
Host smart-806c2789-ede1-4bf5-a0b8-bb4a7a528be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682400193 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2682400193
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.612613923
Short name T895
Test name
Test status
Simulation time 42331378 ps
CPU time 0.79 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:17 PM PST 24
Peak memory 194528 kb
Host smart-26760bd7-04f4-4f03-a7bf-9c8b7ea48a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612613923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.612613923
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.158991686
Short name T163
Test name
Test status
Simulation time 28230190 ps
CPU time 0.58 seconds
Started Jan 17 12:32:00 PM PST 24
Finished Jan 17 12:32:02 PM PST 24
Peak memory 193032 kb
Host smart-35ce78c6-c076-4f63-98b4-174b2624a190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158991686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.158991686
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3519521594
Short name T871
Test name
Test status
Simulation time 48373336 ps
CPU time 0.8 seconds
Started Jan 17 12:32:42 PM PST 24
Finished Jan 17 12:32:44 PM PST 24
Peak memory 195740 kb
Host smart-6cc709f9-4239-4a46-a4a9-df3daf25fc3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519521594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3519521594
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1416002522
Short name T901
Test name
Test status
Simulation time 210548275 ps
CPU time 2.23 seconds
Started Jan 17 12:32:08 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 198700 kb
Host smart-efb89615-42b5-4ff5-9e17-8337ceb97c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416002522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1416002522
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3634284668
Short name T892
Test name
Test status
Simulation time 202411121 ps
CPU time 1.75 seconds
Started Jan 17 12:32:08 PM PST 24
Finished Jan 17 12:32:11 PM PST 24
Peak memory 198212 kb
Host smart-9f78f08b-58c6-406c-82e6-aa8cb35a127b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634284668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3634284668
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3364778858
Short name T143
Test name
Test status
Simulation time 20106040 ps
CPU time 0.95 seconds
Started Jan 17 12:32:22 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198624 kb
Host smart-05030b76-2893-462f-a243-2e7ea55ceeef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364778858 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3364778858
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4127457272
Short name T82
Test name
Test status
Simulation time 38115975 ps
CPU time 0.67 seconds
Started Jan 17 12:32:42 PM PST 24
Finished Jan 17 12:32:44 PM PST 24
Peak memory 194656 kb
Host smart-2c82db44-9235-4691-a2db-8fb87a0bcdad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127457272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4127457272
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.372049967
Short name T154
Test name
Test status
Simulation time 15595657 ps
CPU time 0.59 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 193020 kb
Host smart-8c699391-2f02-4469-afd8-9a19bec1ba7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372049967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.372049967
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1573868103
Short name T134
Test name
Test status
Simulation time 47029367 ps
CPU time 1.17 seconds
Started Jan 17 12:32:10 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 197172 kb
Host smart-89c6b9f2-b616-4ca8-ab3a-e3bf5b682ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573868103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1573868103
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.939401305
Short name T899
Test name
Test status
Simulation time 43430811 ps
CPU time 2.36 seconds
Started Jan 17 12:32:29 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 198724 kb
Host smart-e2782505-ed0b-48ca-bb37-f0b5f0bda7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939401305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.939401305
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2703401595
Short name T168
Test name
Test status
Simulation time 61887489 ps
CPU time 1.25 seconds
Started Jan 17 12:32:12 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 198376 kb
Host smart-3d8bc0a5-a4e8-4740-8b4d-9c64b849bdc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703401595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2703401595
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.341333250
Short name T890
Test name
Test status
Simulation time 33364170 ps
CPU time 1.04 seconds
Started Jan 17 12:32:42 PM PST 24
Finished Jan 17 12:32:44 PM PST 24
Peak memory 198556 kb
Host smart-d6f9ba3d-f98a-489c-b79a-adcec107c052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341333250 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.341333250
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1721004085
Short name T852
Test name
Test status
Simulation time 31485080 ps
CPU time 0.71 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 194596 kb
Host smart-3aeb15e5-ee10-4ab3-a92c-2e01e8579a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721004085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1721004085
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.735700778
Short name T874
Test name
Test status
Simulation time 20862575 ps
CPU time 0.54 seconds
Started Jan 17 12:32:17 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193092 kb
Host smart-8ec0220e-2a85-436a-b86a-a416448ef4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735700778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.735700778
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2081225044
Short name T159
Test name
Test status
Simulation time 18655603 ps
CPU time 0.75 seconds
Started Jan 17 12:32:25 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 192112 kb
Host smart-be86fff4-71b5-4afe-87bb-d9b2289d745a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081225044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2081225044
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3789665293
Short name T896
Test name
Test status
Simulation time 421703253 ps
CPU time 1.61 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:26 PM PST 24
Peak memory 198604 kb
Host smart-c57429aa-4a89-4ab7-9a04-887c8b0e3664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789665293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3789665293
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2336598417
Short name T171
Test name
Test status
Simulation time 44244891 ps
CPU time 2.12 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198668 kb
Host smart-7674f4d5-6f67-477c-81ab-9b35857fda4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336598417 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2336598417
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.312094508
Short name T861
Test name
Test status
Simulation time 35148257 ps
CPU time 0.59 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 193892 kb
Host smart-22058f45-d319-44b1-b0ab-f90deba4ccef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312094508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.312094508
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2365475885
Short name T887
Test name
Test status
Simulation time 30350479 ps
CPU time 0.58 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 192284 kb
Host smart-175515bb-a77f-45b1-bbfd-76a2bbc5b9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365475885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2365475885
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1526703747
Short name T873
Test name
Test status
Simulation time 72471069 ps
CPU time 0.78 seconds
Started Jan 17 12:32:30 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 195380 kb
Host smart-3b5f662d-1648-4fa0-97f1-25eafdaa0942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526703747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1526703747
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2835383279
Short name T169
Test name
Test status
Simulation time 298993242 ps
CPU time 3.38 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 198464 kb
Host smart-5c8cfa29-7c32-454c-8e23-2138445746d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835383279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2835383279
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1010092236
Short name T898
Test name
Test status
Simulation time 69029228 ps
CPU time 1.13 seconds
Started Jan 17 12:32:27 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 197708 kb
Host smart-56ce2f71-dfdf-420c-af00-2a0570bd00b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010092236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1010092236
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4029526495
Short name T22
Test name
Test status
Simulation time 124156518 ps
CPU time 2.11 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 198688 kb
Host smart-38f21f88-684f-4d08-9496-a62a4b2a6410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029526495 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4029526495
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1809090618
Short name T76
Test name
Test status
Simulation time 25729347 ps
CPU time 0.74 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 194760 kb
Host smart-32f0997d-4382-4b51-b183-5d5de11166f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809090618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1809090618
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.357837737
Short name T870
Test name
Test status
Simulation time 19810652 ps
CPU time 0.57 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193100 kb
Host smart-d08fac6a-027d-4c0f-862c-627e58e3cdc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357837737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.357837737
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1420071247
Short name T875
Test name
Test status
Simulation time 247733151 ps
CPU time 1.1 seconds
Started Jan 17 12:32:28 PM PST 24
Finished Jan 17 12:32:31 PM PST 24
Peak memory 192180 kb
Host smart-5dfab19e-45cd-473a-98b6-9e9b686fbac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420071247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1420071247
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3682994352
Short name T884
Test name
Test status
Simulation time 32569937 ps
CPU time 1.73 seconds
Started Jan 17 12:32:42 PM PST 24
Finished Jan 17 12:32:45 PM PST 24
Peak memory 198776 kb
Host smart-f0a48442-c075-4021-a733-c6545aca3c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682994352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3682994352
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3091194840
Short name T71
Test name
Test status
Simulation time 462430628 ps
CPU time 1.83 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198356 kb
Host smart-7d4f9437-b266-4989-8fbe-65f8a3ac9be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091194840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3091194840
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1756640309
Short name T900
Test name
Test status
Simulation time 93977814 ps
CPU time 1.76 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:17 PM PST 24
Peak memory 198652 kb
Host smart-61675462-c062-475e-8ff3-1d92babfbb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756640309 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1756640309
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3187310576
Short name T62
Test name
Test status
Simulation time 35400803 ps
CPU time 0.72 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 194712 kb
Host smart-aba1904e-2ad2-431f-ae37-c2ca9e989b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187310576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3187310576
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3853808677
Short name T174
Test name
Test status
Simulation time 69537722 ps
CPU time 0.62 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 193024 kb
Host smart-491dc34c-bfb0-4ad7-b571-55226dcc6a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853808677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3853808677
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1645036529
Short name T85
Test name
Test status
Simulation time 161986845 ps
CPU time 1.37 seconds
Started Jan 17 12:32:21 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 192224 kb
Host smart-764b9243-1dca-4120-817d-929b2f481e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645036529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1645036529
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4272918947
Short name T161
Test name
Test status
Simulation time 42005913 ps
CPU time 2.18 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:22 PM PST 24
Peak memory 198720 kb
Host smart-3bb42d77-9a94-435e-97ec-a62b45f354f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272918947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4272918947
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2267363755
Short name T127
Test name
Test status
Simulation time 77773970 ps
CPU time 1.74 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198188 kb
Host smart-ca84bac3-0c07-4245-926c-b63897616d05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267363755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2267363755
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.549428247
Short name T885
Test name
Test status
Simulation time 21290220 ps
CPU time 1.02 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 198520 kb
Host smart-04275374-88f4-4f35-a173-05cf51e93328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549428247 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.549428247
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.993431501
Short name T144
Test name
Test status
Simulation time 28358788 ps
CPU time 0.76 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 192156 kb
Host smart-0258713a-9a9b-43c8-9269-4fceface01a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993431501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.993431501
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.77622259
Short name T60
Test name
Test status
Simulation time 47540870 ps
CPU time 2.64 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 198620 kb
Host smart-1fb24c5e-dde2-4951-b5de-1bf92b53f6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77622259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.77622259
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2484875949
Short name T880
Test name
Test status
Simulation time 23526485 ps
CPU time 1.56 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198636 kb
Host smart-717d73a3-569e-4bc0-aaa4-9b0091e365da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484875949 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2484875949
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.737218271
Short name T886
Test name
Test status
Simulation time 53686493 ps
CPU time 0.69 seconds
Started Jan 17 12:32:16 PM PST 24
Finished Jan 17 12:32:19 PM PST 24
Peak memory 194520 kb
Host smart-08995fed-5b5f-4af9-9af0-a2b5c5df14df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737218271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.737218271
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3836392830
Short name T165
Test name
Test status
Simulation time 58438025 ps
CPU time 0.95 seconds
Started Jan 17 12:32:26 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 196872 kb
Host smart-48ec21ee-b7f8-4dcc-9783-7d18662e2af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836392830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3836392830
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1403117704
Short name T882
Test name
Test status
Simulation time 108719679 ps
CPU time 2.3 seconds
Started Jan 17 12:32:32 PM PST 24
Finished Jan 17 12:32:35 PM PST 24
Peak memory 198664 kb
Host smart-29b46b07-fad4-44df-845c-0f402f088df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403117704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1403117704
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1295579409
Short name T68
Test name
Test status
Simulation time 217405486 ps
CPU time 1.29 seconds
Started Jan 17 12:32:16 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 198068 kb
Host smart-935d60f2-d4ef-437e-af28-746d74085705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295579409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1295579409
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3469747955
Short name T860
Test name
Test status
Simulation time 122276524633 ps
CPU time 968.59 seconds
Started Jan 17 12:32:34 PM PST 24
Finished Jan 17 12:48:43 PM PST 24
Peak memory 211192 kb
Host smart-db3eeb9e-5578-4eb9-a971-3d805d38970b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469747955 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3469747955
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.446439489
Short name T897
Test name
Test status
Simulation time 31232030 ps
CPU time 0.63 seconds
Started Jan 17 12:32:30 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 193740 kb
Host smart-eef03e70-2488-4e09-abc5-bbf21a32448a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446439489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.446439489
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2908889144
Short name T176
Test name
Test status
Simulation time 17412322 ps
CPU time 0.61 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 193080 kb
Host smart-fe8e4b8c-3e08-484b-b750-756d578c11b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908889144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2908889144
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2285575208
Short name T84
Test name
Test status
Simulation time 106145836 ps
CPU time 0.82 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 192096 kb
Host smart-d0e81819-66c6-4148-9ac4-20aab3930fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285575208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2285575208
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2497422161
Short name T857
Test name
Test status
Simulation time 182679323 ps
CPU time 3 seconds
Started Jan 17 12:32:49 PM PST 24
Finished Jan 17 12:32:58 PM PST 24
Peak memory 198724 kb
Host smart-10eb317b-81bc-4fc9-bc9a-d7e8597359d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497422161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2497422161
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3263320747
Short name T894
Test name
Test status
Simulation time 686547569 ps
CPU time 2.63 seconds
Started Jan 17 12:32:36 PM PST 24
Finished Jan 17 12:32:39 PM PST 24
Peak memory 198284 kb
Host smart-f996ed72-1f3e-49b4-9f32-4ba6e891a487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263320747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3263320747
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1000936818
Short name T859
Test name
Test status
Simulation time 36506293 ps
CPU time 3.03 seconds
Started Jan 17 12:32:36 PM PST 24
Finished Jan 17 12:32:41 PM PST 24
Peak memory 198672 kb
Host smart-e5cfb70c-fa72-46a5-a19d-f99189a24a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000936818 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1000936818
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1245476722
Short name T856
Test name
Test status
Simulation time 16100399 ps
CPU time 0.69 seconds
Started Jan 17 12:32:42 PM PST 24
Finished Jan 17 12:32:44 PM PST 24
Peak memory 194548 kb
Host smart-73245913-9bae-4b1c-a330-24e0c3b3bd15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245476722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1245476722
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3345211274
Short name T175
Test name
Test status
Simulation time 130702597 ps
CPU time 0.59 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:40 PM PST 24
Peak memory 193028 kb
Host smart-7a151939-d9a7-484c-8d02-a5c24b390ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345211274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3345211274
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1533372078
Short name T906
Test name
Test status
Simulation time 106751078 ps
CPU time 0.78 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:40 PM PST 24
Peak memory 195320 kb
Host smart-1fa26c2f-b2cf-468f-aa39-26212f09346e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533372078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1533372078
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1227570386
Short name T153
Test name
Test status
Simulation time 288223193 ps
CPU time 2.33 seconds
Started Jan 17 12:32:27 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 198672 kb
Host smart-e6e0a22b-4f82-4388-a3f5-b439da345982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227570386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1227570386
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.250498479
Short name T70
Test name
Test status
Simulation time 375884041 ps
CPU time 1.73 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198316 kb
Host smart-4bea4b2e-daf8-46be-a508-8e426964c5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250498479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.250498479
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.189169002
Short name T79
Test name
Test status
Simulation time 18923294 ps
CPU time 0.61 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 194200 kb
Host smart-ebaaea69-e56e-4f26-9475-ad5e99d855d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189169002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.189169002
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3810642935
Short name T155
Test name
Test status
Simulation time 59818086 ps
CPU time 0.6 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:40 PM PST 24
Peak memory 193028 kb
Host smart-92a267fc-8c3f-43b2-bdf2-3989fab044fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810642935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3810642935
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2436094928
Short name T878
Test name
Test status
Simulation time 148466153 ps
CPU time 1.12 seconds
Started Jan 17 12:36:06 PM PST 24
Finished Jan 17 12:36:11 PM PST 24
Peak memory 192132 kb
Host smart-b193ff1b-c0c0-4db6-8c9d-959df888e0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436094928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2436094928
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1604173763
Short name T26
Test name
Test status
Simulation time 69911273 ps
CPU time 1.96 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:41 PM PST 24
Peak memory 198656 kb
Host smart-3389d94c-a987-43e6-a882-95a1ad453966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604173763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1604173763
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2936459854
Short name T156
Test name
Test status
Simulation time 980559661 ps
CPU time 1.83 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198608 kb
Host smart-cf5ef8f5-900a-4894-af26-3ce6836fbed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936459854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2936459854
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3600166509
Short name T72
Test name
Test status
Simulation time 1677734271 ps
CPU time 1.81 seconds
Started Jan 17 12:32:15 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 184056 kb
Host smart-3531045c-79b6-42b4-b4bf-8f8c3065716b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600166509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3600166509
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4192470784
Short name T877
Test name
Test status
Simulation time 1814645066 ps
CPU time 6.43 seconds
Started Jan 17 12:32:12 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 192240 kb
Host smart-776f9742-b0c2-4976-a652-b51b14be6ca5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192470784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4192470784
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3175743009
Short name T81
Test name
Test status
Simulation time 47672582 ps
CPU time 0.7 seconds
Started Jan 17 12:32:10 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 194792 kb
Host smart-919988ad-b485-4fcf-8278-49a270597070
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175743009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3175743009
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1420287921
Short name T858
Test name
Test status
Simulation time 15100777 ps
CPU time 0.88 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 198484 kb
Host smart-d97990eb-a61d-4d12-893a-93626be6b790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420287921 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1420287921
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.930580780
Short name T138
Test name
Test status
Simulation time 75420944 ps
CPU time 0.66 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 194736 kb
Host smart-157ed50a-8e80-4bbb-b842-721652e8d142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930580780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.930580780
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3029087578
Short name T158
Test name
Test status
Simulation time 33416950 ps
CPU time 0.56 seconds
Started Jan 17 12:32:03 PM PST 24
Finished Jan 17 12:32:04 PM PST 24
Peak memory 193024 kb
Host smart-49038ecc-63e4-4df8-8bd1-add3986515b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029087578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3029087578
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4024326815
Short name T65
Test name
Test status
Simulation time 199917388 ps
CPU time 0.82 seconds
Started Jan 17 12:32:07 PM PST 24
Finished Jan 17 12:32:09 PM PST 24
Peak memory 195508 kb
Host smart-3c7136ce-317b-45e4-9473-e0cde51f0844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024326815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.4024326815
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1079269140
Short name T23
Test name
Test status
Simulation time 88828860 ps
CPU time 1.51 seconds
Started Jan 17 12:32:24 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198552 kb
Host smart-356edf0d-d854-4660-93c8-adfa68e82c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079269140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1079269140
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2645142460
Short name T59
Test name
Test status
Simulation time 78994765 ps
CPU time 1.78 seconds
Started Jan 17 12:32:06 PM PST 24
Finished Jan 17 12:32:09 PM PST 24
Peak memory 198328 kb
Host smart-cf60886d-8120-482a-b067-d29cd5d0aa53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645142460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2645142460
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1680843858
Short name T30
Test name
Test status
Simulation time 11874250 ps
CPU time 0.56 seconds
Started Jan 17 12:36:06 PM PST 24
Finished Jan 17 12:36:10 PM PST 24
Peak memory 192996 kb
Host smart-7e6bc796-e9b5-4d16-a750-4d3407195b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680843858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1680843858
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2888662871
Short name T853
Test name
Test status
Simulation time 22484209 ps
CPU time 0.59 seconds
Started Jan 17 12:32:15 PM PST 24
Finished Jan 17 12:32:19 PM PST 24
Peak memory 193044 kb
Host smart-7186306a-f3b9-4a68-afa6-ad6a33631ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888662871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2888662871
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2175470677
Short name T123
Test name
Test status
Simulation time 32447588 ps
CPU time 0.55 seconds
Started Jan 17 12:32:38 PM PST 24
Finished Jan 17 12:32:42 PM PST 24
Peak memory 193032 kb
Host smart-5ee90a37-f84c-4698-b73d-dcc8e88f9620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175470677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2175470677
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1393314544
Short name T148
Test name
Test status
Simulation time 24750872 ps
CPU time 0.62 seconds
Started Jan 17 12:35:47 PM PST 24
Finished Jan 17 12:35:49 PM PST 24
Peak memory 192024 kb
Host smart-84a1cbe5-8c83-4151-8a03-8f518f1388e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393314544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1393314544
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2192846827
Short name T122
Test name
Test status
Simulation time 15860529 ps
CPU time 0.57 seconds
Started Jan 17 12:32:28 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 193044 kb
Host smart-0955d3ff-5140-4fec-9287-4a871fc51429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192846827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2192846827
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3133187989
Short name T167
Test name
Test status
Simulation time 17026638 ps
CPU time 0.54 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193104 kb
Host smart-1674c9b7-1d42-492f-9371-4e4b7bfe059b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133187989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3133187989
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2004188630
Short name T63
Test name
Test status
Simulation time 21873485 ps
CPU time 0.55 seconds
Started Jan 17 12:32:39 PM PST 24
Finished Jan 17 12:32:43 PM PST 24
Peak memory 193044 kb
Host smart-926cdb65-32b5-4773-8f48-d17994ead48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004188630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2004188630
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1721033238
Short name T146
Test name
Test status
Simulation time 16056249 ps
CPU time 0.61 seconds
Started Jan 17 12:32:40 PM PST 24
Finished Jan 17 12:32:43 PM PST 24
Peak memory 193044 kb
Host smart-7d90c8df-5930-49d4-9c2c-7cfcf6b6be84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721033238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1721033238
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3560894093
Short name T854
Test name
Test status
Simulation time 11613675 ps
CPU time 0.6 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:41 PM PST 24
Peak memory 193068 kb
Host smart-e67a49e8-d914-4ef2-9e15-e6401e5d3491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560894093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3560894093
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2248009751
Short name T136
Test name
Test status
Simulation time 30078002 ps
CPU time 0.6 seconds
Started Jan 17 12:32:39 PM PST 24
Finished Jan 17 12:32:43 PM PST 24
Peak memory 193040 kb
Host smart-e2fffe62-a9c2-4a32-b969-aa0c08f7d2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248009751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2248009751
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1423698885
Short name T872
Test name
Test status
Simulation time 365227605 ps
CPU time 1.92 seconds
Started Jan 17 12:32:12 PM PST 24
Finished Jan 17 12:32:15 PM PST 24
Peak memory 195836 kb
Host smart-e33309f1-564f-473c-83ba-431fbe00d099
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423698885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1423698885
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4282943885
Short name T879
Test name
Test status
Simulation time 643865929 ps
CPU time 6.57 seconds
Started Jan 17 12:32:15 PM PST 24
Finished Jan 17 12:32:24 PM PST 24
Peak memory 192348 kb
Host smart-11d64301-4b5b-4f91-95c8-a2c83319ded9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282943885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4282943885
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2016184574
Short name T64
Test name
Test status
Simulation time 27809610 ps
CPU time 0.77 seconds
Started Jan 17 12:32:04 PM PST 24
Finished Jan 17 12:32:07 PM PST 24
Peak memory 194292 kb
Host smart-b264c487-6720-4c3f-897f-725d43fbb167
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016184574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2016184574
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2002489968
Short name T24
Test name
Test status
Simulation time 33869754 ps
CPU time 2.23 seconds
Started Jan 17 12:32:05 PM PST 24
Finished Jan 17 12:32:08 PM PST 24
Peak memory 198672 kb
Host smart-3f5c3584-e430-414e-b363-30f83bf172df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002489968 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2002489968
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2826428104
Short name T891
Test name
Test status
Simulation time 19081801 ps
CPU time 0.67 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 194448 kb
Host smart-604f28e6-ac69-4750-9789-706878583de6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826428104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2826428104
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3469691748
Short name T864
Test name
Test status
Simulation time 14327969 ps
CPU time 0.56 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 193092 kb
Host smart-08483951-932f-4a17-ab0a-7c47561c46cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469691748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3469691748
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3709843258
Short name T160
Test name
Test status
Simulation time 295459042 ps
CPU time 1.43 seconds
Started Jan 17 12:32:06 PM PST 24
Finished Jan 17 12:32:08 PM PST 24
Peak memory 197136 kb
Host smart-a0bad8dc-f542-4d9e-8ba9-3fc71001b854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709843258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3709843258
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.985017315
Short name T869
Test name
Test status
Simulation time 101988720 ps
CPU time 1.37 seconds
Started Jan 17 12:32:08 PM PST 24
Finished Jan 17 12:32:11 PM PST 24
Peak memory 198628 kb
Host smart-686f6a49-692c-4ce3-bfe2-7ef82ce74a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985017315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.985017315
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3217441803
Short name T131
Test name
Test status
Simulation time 63977987 ps
CPU time 1.23 seconds
Started Jan 17 12:32:07 PM PST 24
Finished Jan 17 12:32:10 PM PST 24
Peak memory 198200 kb
Host smart-3e90db58-339c-49d6-a77e-1751dae6f5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217441803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3217441803
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3132034603
Short name T125
Test name
Test status
Simulation time 162855701 ps
CPU time 0.58 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 193200 kb
Host smart-55417b2e-7475-4ae9-8d41-54b8edcf47fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132034603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3132034603
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1809924414
Short name T162
Test name
Test status
Simulation time 12314196 ps
CPU time 0.61 seconds
Started Jan 17 12:32:40 PM PST 24
Finished Jan 17 12:32:43 PM PST 24
Peak memory 193040 kb
Host smart-8e757bc4-dce7-47be-8ea2-689a36f12648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809924414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1809924414
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3775582888
Short name T881
Test name
Test status
Simulation time 13380112 ps
CPU time 0.56 seconds
Started Jan 17 12:32:21 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 193052 kb
Host smart-9e921656-4cd7-4a90-a6da-84cf6dc6b870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775582888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3775582888
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3751965942
Short name T883
Test name
Test status
Simulation time 41786274 ps
CPU time 0.62 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193056 kb
Host smart-574ccd82-4bb7-411d-a1f9-8d3810f25350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751965942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3751965942
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1821995491
Short name T902
Test name
Test status
Simulation time 15593501 ps
CPU time 0.56 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 193104 kb
Host smart-760ddd32-89f9-4ea6-9ebf-cad11e5dbb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821995491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1821995491
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2500871556
Short name T133
Test name
Test status
Simulation time 16042761 ps
CPU time 0.61 seconds
Started Jan 17 12:32:26 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 193152 kb
Host smart-e318e6a1-8623-4f1b-b753-ee771cf5d6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500871556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2500871556
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2184162287
Short name T135
Test name
Test status
Simulation time 18436289 ps
CPU time 0.55 seconds
Started Jan 17 12:32:43 PM PST 24
Finished Jan 17 12:32:44 PM PST 24
Peak memory 193056 kb
Host smart-7bb1e89e-60ec-468c-81cf-59653af0d459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184162287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2184162287
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2244944565
Short name T862
Test name
Test status
Simulation time 18639842 ps
CPU time 0.6 seconds
Started Jan 17 12:32:24 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193052 kb
Host smart-2ee6830d-36a6-4b01-845c-c25f11938856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244944565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2244944565
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2158676255
Short name T152
Test name
Test status
Simulation time 17356588 ps
CPU time 0.64 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 193040 kb
Host smart-4d487395-b573-4949-9ffe-5ca7f3bfa867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158676255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2158676255
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1150183340
Short name T78
Test name
Test status
Simulation time 50762771 ps
CPU time 2.28 seconds
Started Jan 17 12:32:11 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 192200 kb
Host smart-9f66b63f-818d-45c7-b7df-9d388600883a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150183340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1150183340
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2687931193
Short name T19
Test name
Test status
Simulation time 3884055016 ps
CPU time 9.07 seconds
Started Jan 17 12:32:16 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 192296 kb
Host smart-0192c717-2635-4878-a6b9-38c2d659594b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687931193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2687931193
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3964688634
Short name T74
Test name
Test status
Simulation time 28897930 ps
CPU time 0.67 seconds
Started Jan 17 12:32:14 PM PST 24
Finished Jan 17 12:32:18 PM PST 24
Peak memory 194240 kb
Host smart-8d0f1dd1-08f7-4261-bed2-cbcbab4fe9e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964688634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3964688634
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2329735320
Short name T889
Test name
Test status
Simulation time 103689662 ps
CPU time 2.09 seconds
Started Jan 17 12:32:24 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198632 kb
Host smart-8cdaafdf-5dbb-4634-804f-66047c766491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329735320 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2329735320
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2599161147
Short name T18
Test name
Test status
Simulation time 99335364 ps
CPU time 0.65 seconds
Started Jan 17 12:32:21 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 194068 kb
Host smart-942e62fb-0e9e-4f16-9f4c-20a10a87e7f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599161147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2599161147
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1417959796
Short name T126
Test name
Test status
Simulation time 41986885 ps
CPU time 0.58 seconds
Started Jan 17 12:32:17 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193152 kb
Host smart-a9bf2885-9a50-4a5c-9be0-8ac2d3aa05ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417959796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1417959796
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3911173779
Short name T173
Test name
Test status
Simulation time 354587710 ps
CPU time 1.06 seconds
Started Jan 17 12:32:16 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 196348 kb
Host smart-f663522f-4418-4f9d-9a47-649468b611dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911173779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3911173779
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3431596142
Short name T150
Test name
Test status
Simulation time 69600928 ps
CPU time 3.78 seconds
Started Jan 17 12:32:21 PM PST 24
Finished Jan 17 12:32:31 PM PST 24
Peak memory 198604 kb
Host smart-d4204a6e-3d8c-47cc-94c4-9749edbbb35c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431596142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3431596142
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2438788621
Short name T13
Test name
Test status
Simulation time 138357817 ps
CPU time 2.17 seconds
Started Jan 17 12:32:01 PM PST 24
Finished Jan 17 12:32:04 PM PST 24
Peak memory 198476 kb
Host smart-951b18dd-8f6f-464a-ab45-75219d5ffc88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438788621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2438788621
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1196363429
Short name T904
Test name
Test status
Simulation time 42107791 ps
CPU time 0.59 seconds
Started Jan 17 12:32:29 PM PST 24
Finished Jan 17 12:32:31 PM PST 24
Peak memory 193076 kb
Host smart-4ddcde86-c440-4b92-b62a-c464e4bfb2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196363429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1196363429
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3242313275
Short name T140
Test name
Test status
Simulation time 15525395 ps
CPU time 0.6 seconds
Started Jan 17 12:32:27 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 193076 kb
Host smart-e7354bfc-dc09-4973-8d01-f178c0aa754f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242313275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3242313275
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3130604289
Short name T149
Test name
Test status
Simulation time 50258889 ps
CPU time 0.6 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 192864 kb
Host smart-728dc95e-4da3-40da-94eb-d8ec3d48f404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130604289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3130604289
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.784886347
Short name T132
Test name
Test status
Simulation time 36937527 ps
CPU time 0.62 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193052 kb
Host smart-5859c491-9e8e-44c8-a38a-e77b6b403010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784886347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.784886347
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2558810964
Short name T164
Test name
Test status
Simulation time 107366020 ps
CPU time 0.58 seconds
Started Jan 17 12:32:21 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193052 kb
Host smart-9dd4cd7e-8960-4876-b662-f30bb894ad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558810964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2558810964
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2443476084
Short name T893
Test name
Test status
Simulation time 15696857 ps
CPU time 0.57 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 193068 kb
Host smart-717d5b3d-e8a9-4bde-9934-a6d04eb9ea44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443476084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2443476084
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3289974869
Short name T157
Test name
Test status
Simulation time 109447698 ps
CPU time 0.6 seconds
Started Jan 17 12:32:28 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 193076 kb
Host smart-06c647dc-e2f6-4391-bfd2-578959274129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289974869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3289974869
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.403682047
Short name T866
Test name
Test status
Simulation time 12623025 ps
CPU time 0.53 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193092 kb
Host smart-3d2b48d8-6ec5-4ade-8353-61fd0feef149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403682047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.403682047
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2648706476
Short name T142
Test name
Test status
Simulation time 17674960 ps
CPU time 0.58 seconds
Started Jan 17 12:32:29 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 193072 kb
Host smart-299a1a04-1598-4602-a35b-6ae3e6aa3479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648706476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2648706476
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1943719006
Short name T17
Test name
Test status
Simulation time 17743269 ps
CPU time 0.59 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:26 PM PST 24
Peak memory 193080 kb
Host smart-c587b360-5e93-4e56-9a2d-6d840cb05230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943719006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1943719006
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2274431865
Short name T20
Test name
Test status
Simulation time 18301971 ps
CPU time 0.95 seconds
Started Jan 17 12:32:22 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198540 kb
Host smart-4bbcdb3f-b78d-47e6-b5a1-b3a1fd367aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274431865 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2274431865
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3167737696
Short name T87
Test name
Test status
Simulation time 20982295 ps
CPU time 0.68 seconds
Started Jan 17 12:32:36 PM PST 24
Finished Jan 17 12:32:37 PM PST 24
Peak memory 194904 kb
Host smart-6fcc2190-169a-40de-9585-411d20146262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167737696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3167737696
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3373055154
Short name T876
Test name
Test status
Simulation time 16580349 ps
CPU time 0.59 seconds
Started Jan 17 12:32:27 PM PST 24
Finished Jan 17 12:32:30 PM PST 24
Peak memory 193084 kb
Host smart-e1bb0f3c-47e0-42a5-b9e8-748e10a3a83c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373055154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3373055154
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3157739823
Short name T86
Test name
Test status
Simulation time 184232221 ps
CPU time 1.11 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 196192 kb
Host smart-99a2bf10-2abe-4d7e-84d4-52c1259b0334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157739823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3157739823
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3342517829
Short name T903
Test name
Test status
Simulation time 535621943 ps
CPU time 2.2 seconds
Started Jan 17 12:32:09 PM PST 24
Finished Jan 17 12:32:13 PM PST 24
Peak memory 198584 kb
Host smart-14373b82-0369-413c-91e9-d29612ab8f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342517829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3342517829
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.535942524
Short name T69
Test name
Test status
Simulation time 1250851781 ps
CPU time 2.37 seconds
Started Jan 17 12:32:30 PM PST 24
Finished Jan 17 12:32:33 PM PST 24
Peak memory 198416 kb
Host smart-148ce266-cf45-4d94-8dde-5b096fb4220f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535942524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.535942524
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1640132731
Short name T139
Test name
Test status
Simulation time 36390318 ps
CPU time 2.87 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198684 kb
Host smart-671e3f4d-d0f4-4dc6-a952-04dc7dfb39e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640132731 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1640132731
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1945072859
Short name T73
Test name
Test status
Simulation time 16810885 ps
CPU time 0.73 seconds
Started Jan 17 12:32:13 PM PST 24
Finished Jan 17 12:32:16 PM PST 24
Peak memory 194652 kb
Host smart-191a08f1-bf7a-4832-9416-4f812a78db47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945072859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1945072859
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3553213535
Short name T45
Test name
Test status
Simulation time 13634536 ps
CPU time 0.57 seconds
Started Jan 17 12:32:32 PM PST 24
Finished Jan 17 12:32:33 PM PST 24
Peak memory 193088 kb
Host smart-4f7824d5-cd97-4e89-920b-1cff2591a45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553213535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3553213535
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2850519259
Short name T179
Test name
Test status
Simulation time 56464230 ps
CPU time 0.83 seconds
Started Jan 17 12:32:10 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 195632 kb
Host smart-0f43138d-3c54-474e-82b2-c18e2d6d622a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850519259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2850519259
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2838998800
Short name T28
Test name
Test status
Simulation time 64943080 ps
CPU time 1.68 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 197916 kb
Host smart-6a572259-2980-4bc0-a591-1e7a56568038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838998800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2838998800
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3517387681
Short name T15
Test name
Test status
Simulation time 2972389230 ps
CPU time 2.42 seconds
Started Jan 17 12:32:40 PM PST 24
Finished Jan 17 12:32:45 PM PST 24
Peak memory 198692 kb
Host smart-58210acf-4a63-490b-9f3e-afdb908d6902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517387681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3517387681
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3570132679
Short name T865
Test name
Test status
Simulation time 36973814408 ps
CPU time 478.7 seconds
Started Jan 17 12:32:12 PM PST 24
Finished Jan 17 12:40:13 PM PST 24
Peak memory 210408 kb
Host smart-ec802701-a9fd-465b-a41e-42bff0639879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570132679 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3570132679
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2397799740
Short name T182
Test name
Test status
Simulation time 14636583 ps
CPU time 0.7 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 194608 kb
Host smart-5e682500-b8b3-461b-b13e-dda85d119fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397799740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2397799740
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3948128632
Short name T147
Test name
Test status
Simulation time 15120847 ps
CPU time 0.57 seconds
Started Jan 17 12:32:15 PM PST 24
Finished Jan 17 12:32:19 PM PST 24
Peak memory 193004 kb
Host smart-bc073de4-da7d-479a-8c7d-c52cec54789a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948128632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3948128632
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2878046399
Short name T66
Test name
Test status
Simulation time 269976631 ps
CPU time 1.35 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:21 PM PST 24
Peak memory 192200 kb
Host smart-67e3130f-aa27-4ac4-a5ff-7cf9003b18a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878046399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2878046399
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.872441989
Short name T855
Test name
Test status
Simulation time 206303505 ps
CPU time 3.59 seconds
Started Jan 17 12:32:15 PM PST 24
Finished Jan 17 12:32:22 PM PST 24
Peak memory 198644 kb
Host smart-65686948-540e-44ff-8d8a-d5beed08af1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872441989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.872441989
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.909871289
Short name T67
Test name
Test status
Simulation time 129199811 ps
CPU time 1.27 seconds
Started Jan 17 12:32:16 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 197924 kb
Host smart-02b86ad5-93a3-4b5a-8f36-71ac95fcb4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909871289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.909871289
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3751175994
Short name T178
Test name
Test status
Simulation time 20585066 ps
CPU time 1.41 seconds
Started Jan 17 12:32:24 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198744 kb
Host smart-3348fafb-32ac-4221-b43a-cf3862388e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751175994 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3751175994
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2262627293
Short name T83
Test name
Test status
Simulation time 15305854 ps
CPU time 0.71 seconds
Started Jan 17 12:32:28 PM PST 24
Finished Jan 17 12:32:31 PM PST 24
Peak memory 195180 kb
Host smart-c75c04d6-0658-47e7-b3f0-0e15f85a414c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262627293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2262627293
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2262130211
Short name T180
Test name
Test status
Simulation time 10932492 ps
CPU time 0.58 seconds
Started Jan 17 12:32:18 PM PST 24
Finished Jan 17 12:32:20 PM PST 24
Peak memory 193124 kb
Host smart-5ae5346c-4c0f-40c1-a8cf-165d0a766854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262130211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2262130211
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4041780140
Short name T905
Test name
Test status
Simulation time 17147299 ps
CPU time 0.87 seconds
Started Jan 17 12:32:30 PM PST 24
Finished Jan 17 12:32:32 PM PST 24
Peak memory 195348 kb
Host smart-913d696a-fe0c-4cbf-b132-32e597ac9b58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041780140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4041780140
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2989509254
Short name T25
Test name
Test status
Simulation time 226197173 ps
CPU time 2.1 seconds
Started Jan 17 12:32:20 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198696 kb
Host smart-a0409a16-17e4-4fc5-b389-634dc7492265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989509254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2989509254
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1741207314
Short name T867
Test name
Test status
Simulation time 54924666 ps
CPU time 1.12 seconds
Started Jan 17 12:32:09 PM PST 24
Finished Jan 17 12:32:12 PM PST 24
Peak memory 197700 kb
Host smart-5989ed17-1de9-4272-8b68-250ab1424729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741207314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1741207314
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3905964785
Short name T888
Test name
Test status
Simulation time 233012394 ps
CPU time 1.38 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 198612 kb
Host smart-ca690118-7ef4-4575-936f-61e39fa01c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905964785 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3905964785
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3462714188
Short name T75
Test name
Test status
Simulation time 68856460 ps
CPU time 0.61 seconds
Started Jan 17 12:32:23 PM PST 24
Finished Jan 17 12:32:28 PM PST 24
Peak memory 194440 kb
Host smart-3e10101b-e9de-4f9c-a3c1-7664ceba58ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462714188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3462714188
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.587904059
Short name T172
Test name
Test status
Simulation time 29364860 ps
CPU time 0.57 seconds
Started Jan 17 12:32:19 PM PST 24
Finished Jan 17 12:32:27 PM PST 24
Peak memory 193020 kb
Host smart-fc3e6a35-18d5-4343-943c-4b91ea566388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587904059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.587904059
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1437944836
Short name T868
Test name
Test status
Simulation time 86341004 ps
CPU time 1.4 seconds
Started Jan 17 12:32:37 PM PST 24
Finished Jan 17 12:32:41 PM PST 24
Peak memory 192300 kb
Host smart-ba27c7dc-f24a-4fdd-8d3e-0811cafbebef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437944836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1437944836
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2558711086
Short name T151
Test name
Test status
Simulation time 705363210 ps
CPU time 3.22 seconds
Started Jan 17 12:32:30 PM PST 24
Finished Jan 17 12:32:34 PM PST 24
Peak memory 198588 kb
Host smart-5826b950-3ff9-4b5d-ba61-1068d88a6874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558711086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2558711086
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3043916461
Short name T130
Test name
Test status
Simulation time 110294397 ps
CPU time 2.28 seconds
Started Jan 17 12:32:22 PM PST 24
Finished Jan 17 12:32:29 PM PST 24
Peak memory 198424 kb
Host smart-6f3cf363-d9da-448a-a922-9e88a3a79da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043916461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3043916461
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4037006155
Short name T557
Test name
Test status
Simulation time 16699581 ps
CPU time 0.55 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 192864 kb
Host smart-30206c51-c7e4-4a7c-8e4c-ff09f72baa5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037006155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4037006155
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3960553818
Short name T190
Test name
Test status
Simulation time 1116829445 ps
CPU time 29.15 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:40 PM PST 24
Peak memory 217892 kb
Host smart-4a21c801-2bd9-4149-8ab6-86957ae95262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3960553818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3960553818
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2298052020
Short name T357
Test name
Test status
Simulation time 2507143552 ps
CPU time 55.2 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:51:15 PM PST 24
Peak memory 197976 kb
Host smart-c9b37ff7-e5f2-4b7b-8188-8703abcbd028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298052020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2298052020
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1328264430
Short name T8
Test name
Test status
Simulation time 1628683428 ps
CPU time 84.08 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 198664 kb
Host smart-e2992b51-9ee5-4461-9e91-3d6174e472c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328264430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1328264430
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4206004532
Short name T526
Test name
Test status
Simulation time 19076913524 ps
CPU time 153.17 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:52:55 PM PST 24
Peak memory 198828 kb
Host smart-841d7f85-4987-447c-8a6b-aa598342cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206004532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4206004532
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3269569415
Short name T432
Test name
Test status
Simulation time 17094153101 ps
CPU time 52.77 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198864 kb
Host smart-3fb778b1-4c3f-4a85-9cd9-f8c8ef41ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269569415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3269569415
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2531645458
Short name T718
Test name
Test status
Simulation time 400974863 ps
CPU time 2.87 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:13 PM PST 24
Peak memory 198484 kb
Host smart-64776580-5274-450e-ad3e-6f4016eb347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531645458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2531645458
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3161615774
Short name T547
Test name
Test status
Simulation time 15844890335 ps
CPU time 387.42 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:56:50 PM PST 24
Peak memory 198700 kb
Host smart-fb4230d2-28f4-4075-9f19-150a4432af23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161615774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3161615774
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1954914033
Short name T725
Test name
Test status
Simulation time 92767505 ps
CPU time 0.95 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 195916 kb
Host smart-a6daca1f-199d-4aa7-919d-edbaea3bf5c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954914033 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1954914033
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1546079465
Short name T406
Test name
Test status
Simulation time 37024710489 ps
CPU time 429.49 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:57:21 PM PST 24
Peak memory 198596 kb
Host smart-f3eff216-47ff-454d-bd41-7ea3452424c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546079465 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.1546079465
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.306075875
Short name T735
Test name
Test status
Simulation time 2984251622 ps
CPU time 46.97 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:57 PM PST 24
Peak memory 198756 kb
Host smart-b9d24910-cea6-4cbc-a998-cabbbdde2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306075875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.306075875
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1964582172
Short name T783
Test name
Test status
Simulation time 33695579 ps
CPU time 0.57 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:11 PM PST 24
Peak memory 193116 kb
Host smart-1659e4dc-1741-40c9-bfa6-23009b644e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964582172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1964582172
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3007837071
Short name T442
Test name
Test status
Simulation time 2950162565 ps
CPU time 23.65 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 211984 kb
Host smart-82321cce-aa65-4141-ae51-b8f4485f2fc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007837071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3007837071
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1949696913
Short name T617
Test name
Test status
Simulation time 524401433 ps
CPU time 23.43 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:31 PM PST 24
Peak memory 198628 kb
Host smart-a840a145-48ed-4c34-a545-02ad02d95265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949696913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1949696913
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3732289968
Short name T829
Test name
Test status
Simulation time 199366466 ps
CPU time 10.27 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:33 PM PST 24
Peak memory 198688 kb
Host smart-63d4c75b-041e-4dd5-8751-ff4cddb74c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732289968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3732289968
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2027713609
Short name T510
Test name
Test status
Simulation time 4231027851 ps
CPU time 52.17 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:51:03 PM PST 24
Peak memory 198788 kb
Host smart-d64fac1e-bd1b-4fd0-9069-c7a7a98e7247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027713609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2027713609
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3595406554
Short name T218
Test name
Test status
Simulation time 8242461961 ps
CPU time 41.16 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:52 PM PST 24
Peak memory 198812 kb
Host smart-59a436cc-8870-4ec7-91a3-2e9bb7c36d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595406554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3595406554
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2696041611
Short name T49
Test name
Test status
Simulation time 103166908 ps
CPU time 0.85 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 215564 kb
Host smart-2cd161db-f0c0-4265-919a-98dc656f23b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696041611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2696041611
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1369175872
Short name T370
Test name
Test status
Simulation time 252163742 ps
CPU time 2.9 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 198676 kb
Host smart-e49cc040-ffc6-49ad-8054-6b3ec9ff37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369175872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1369175872
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1430896382
Short name T351
Test name
Test status
Simulation time 98546864124 ps
CPU time 619.37 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 01:00:31 PM PST 24
Peak memory 198872 kb
Host smart-1a419d77-d8cd-4ef3-9cca-a9aa9836c1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430896382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1430896382
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3156058692
Short name T345
Test name
Test status
Simulation time 1301316117755 ps
CPU time 1885.44 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 01:21:37 PM PST 24
Peak memory 257272 kb
Host smart-1cb4c900-c5eb-4b7f-b648-22898698657b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156058692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3156058692
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.4271990915
Short name T416
Test name
Test status
Simulation time 50396860 ps
CPU time 0.97 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 197052 kb
Host smart-9579f4fd-5a66-4c9a-8a4a-1ce9a0bff755
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271990915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.4271990915
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3691430640
Short name T297
Test name
Test status
Simulation time 7870449183 ps
CPU time 382.46 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:56:33 PM PST 24
Peak memory 198648 kb
Host smart-fa9491d5-51b8-4d15-b195-7f343e40d4e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691430640 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.3691430640
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3405174322
Short name T761
Test name
Test status
Simulation time 16617477489 ps
CPU time 48.09 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:59 PM PST 24
Peak memory 198800 kb
Host smart-f7ff7af3-2693-4d0d-88b7-2a1438d45977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405174322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3405174322
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2179214898
Short name T839
Test name
Test status
Simulation time 13979998 ps
CPU time 0.58 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 193056 kb
Host smart-cc3c33da-e810-47fc-8eef-89032c6af7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179214898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2179214898
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.285920708
Short name T751
Test name
Test status
Simulation time 5415412824 ps
CPU time 34.94 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:51:00 PM PST 24
Peak memory 215168 kb
Host smart-138990ed-1762-49de-9512-3cf228e38131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285920708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.285920708
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.546066545
Short name T461
Test name
Test status
Simulation time 2860290621 ps
CPU time 48.95 seconds
Started Jan 17 12:51:00 PM PST 24
Finished Jan 17 12:51:53 PM PST 24
Peak memory 198688 kb
Host smart-be327b9e-6f3a-4a0a-ba26-762fd803bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546066545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.546066545
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3517811823
Short name T789
Test name
Test status
Simulation time 1315728297 ps
CPU time 67.4 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 198772 kb
Host smart-cc2d9cb4-c516-443d-98a4-9d869a7e1f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517811823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3517811823
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2880352381
Short name T750
Test name
Test status
Simulation time 691172773 ps
CPU time 32.98 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:50:58 PM PST 24
Peak memory 198564 kb
Host smart-2deb408e-e179-4e40-a440-97f0587a691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880352381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2880352381
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1658175299
Short name T58
Test name
Test status
Simulation time 2088657704 ps
CPU time 36.46 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:51:01 PM PST 24
Peak memory 198640 kb
Host smart-b6482954-c409-4b01-aa72-33891f4e5fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658175299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1658175299
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.436840920
Short name T417
Test name
Test status
Simulation time 165208934 ps
CPU time 3.79 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 197968 kb
Host smart-04fdb08a-6f2c-44ee-b623-253e2490dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436840920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.436840920
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2492662384
Short name T536
Test name
Test status
Simulation time 1490460308 ps
CPU time 12.84 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:36 PM PST 24
Peak memory 198692 kb
Host smart-91ff8758-8343-4b39-9fda-bfdcb6928baa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492662384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2492662384
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.880816986
Short name T410
Test name
Test status
Simulation time 315159976149 ps
CPU time 2801.61 seconds
Started Jan 17 12:50:30 PM PST 24
Finished Jan 17 01:37:13 PM PST 24
Peak memory 215280 kb
Host smart-677f3147-3cbc-469a-82ce-28f7182b9c70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880816986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.880816986
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1940351874
Short name T362
Test name
Test status
Simulation time 212286674 ps
CPU time 1.06 seconds
Started Jan 17 12:50:58 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 197168 kb
Host smart-2677502f-7921-4474-ac8b-a9b814c5e738
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940351874 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1940351874
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2460664637
Short name T9
Test name
Test status
Simulation time 7861182655 ps
CPU time 345 seconds
Started Jan 17 12:51:00 PM PST 24
Finished Jan 17 12:56:49 PM PST 24
Peak memory 198540 kb
Host smart-d808dad5-d21c-48a1-a8df-f1eb455d6139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460664637 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.2460664637
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.226148968
Short name T760
Test name
Test status
Simulation time 1505424505 ps
CPU time 52.76 seconds
Started Jan 17 12:51:00 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198612 kb
Host smart-2837fd42-6141-4d4a-aaa3-88f6f301da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226148968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.226148968
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3525526948
Short name T424
Test name
Test status
Simulation time 152542252249 ps
CPU time 3772.83 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:55:22 PM PST 24
Peak memory 254880 kb
Host smart-742fab3a-599d-46ed-9064-be4fb4038d86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525526948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.3525526948
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.3486386719
Short name T704
Test name
Test status
Simulation time 402766124029 ps
CPU time 1881.33 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:23:53 PM PST 24
Peak memory 256248 kb
Host smart-c8f9fc71-c7ad-4fa7-93ab-7b0088f52512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486386719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.3486386719
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.1827160690
Short name T742
Test name
Test status
Simulation time 37454247021 ps
CPU time 557.11 seconds
Started Jan 17 12:52:24 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 214000 kb
Host smart-59db7f9d-247f-4cb0-9b0f-29cbc1672d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827160690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.1827160690
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2975617939
Short name T265
Test name
Test status
Simulation time 10487082225 ps
CPU time 361.12 seconds
Started Jan 17 12:52:28 PM PST 24
Finished Jan 17 12:58:30 PM PST 24
Peak memory 238680 kb
Host smart-d097e5be-8762-4c21-8ed8-75450227ce9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975617939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.2975617939
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.2301262219
Short name T254
Test name
Test status
Simulation time 816712201390 ps
CPU time 2486.14 seconds
Started Jan 17 12:52:31 PM PST 24
Finished Jan 17 01:34:03 PM PST 24
Peak memory 248956 kb
Host smart-aafcac5d-caa4-4dfc-bbdd-af7641a6d6f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301262219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.2301262219
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1197154857
Short name T831
Test name
Test status
Simulation time 139831707536 ps
CPU time 3090.09 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:43:59 PM PST 24
Peak memory 263388 kb
Host smart-79831d10-e7b7-4dc5-abfb-798e0c352ef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197154857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.1197154857
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1771886793
Short name T396
Test name
Test status
Simulation time 29287665259 ps
CPU time 1211.57 seconds
Started Jan 17 12:52:24 PM PST 24
Finished Jan 17 01:12:40 PM PST 24
Peak memory 239892 kb
Host smart-290e03e6-817b-4ffb-ba95-f1cad06c6539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771886793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.1771886793
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.2436030764
Short name T347
Test name
Test status
Simulation time 108292040472 ps
CPU time 1990.71 seconds
Started Jan 17 12:52:22 PM PST 24
Finished Jan 17 01:25:39 PM PST 24
Peak memory 250752 kb
Host smart-ab1fa914-95bb-40be-bd47-8a424a6d137e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436030764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.2436030764
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2935082123
Short name T634
Test name
Test status
Simulation time 226151790067 ps
CPU time 926.03 seconds
Started Jan 17 12:52:23 PM PST 24
Finished Jan 17 01:07:55 PM PST 24
Peak memory 223484 kb
Host smart-3afabedc-3bc5-4841-b850-dd6bb3726070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935082123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.2935082123
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.4020217971
Short name T813
Test name
Test status
Simulation time 15353107715 ps
CPU time 257.63 seconds
Started Jan 17 12:52:23 PM PST 24
Finished Jan 17 12:56:46 PM PST 24
Peak memory 234680 kb
Host smart-9299518c-0947-4f60-8075-9d6275a25d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020217971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.4020217971
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4100475687
Short name T395
Test name
Test status
Simulation time 10255682 ps
CPU time 0.59 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 193088 kb
Host smart-c40a1d19-ea90-47fc-a1ff-1c4098fa7db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100475687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4100475687
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2685518846
Short name T210
Test name
Test status
Simulation time 1106995629 ps
CPU time 27.33 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:50:52 PM PST 24
Peak memory 215176 kb
Host smart-20bc385b-3409-4036-baaf-9a43f1953f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685518846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2685518846
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4145687924
Short name T360
Test name
Test status
Simulation time 1389194790 ps
CPU time 26.12 seconds
Started Jan 17 12:50:20 PM PST 24
Finished Jan 17 12:50:51 PM PST 24
Peak memory 198656 kb
Host smart-8179e269-fd27-434d-80c2-10ea89528654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145687924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4145687924
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3440617282
Short name T578
Test name
Test status
Simulation time 763281750 ps
CPU time 37.96 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:51:03 PM PST 24
Peak memory 198752 kb
Host smart-8dca35fa-2a68-4242-9e02-f3bd41facde9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440617282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3440617282
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.716861790
Short name T296
Test name
Test status
Simulation time 8772587502 ps
CPU time 140.69 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:52:46 PM PST 24
Peak memory 198604 kb
Host smart-db360cb8-ae99-413c-bee0-a67ede2c76ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716861790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.716861790
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2726167193
Short name T215
Test name
Test status
Simulation time 2494929993 ps
CPU time 42.08 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:51:07 PM PST 24
Peak memory 198488 kb
Host smart-9c60ffd7-77ca-4bfd-993c-56a5a9344f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726167193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2726167193
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.4257867191
Short name T324
Test name
Test status
Simulation time 1090096221 ps
CPU time 3.75 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 198636 kb
Host smart-41c595e2-ce2a-410f-b0bb-df5b4566f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257867191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.4257867191
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.770916564
Short name T489
Test name
Test status
Simulation time 2541381035 ps
CPU time 106.5 seconds
Started Jan 17 12:50:22 PM PST 24
Finished Jan 17 12:52:13 PM PST 24
Peak memory 198712 kb
Host smart-293d8eeb-5d48-492f-b752-d27f03b9377e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770916564 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.770916564
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.1816572255
Short name T765
Test name
Test status
Simulation time 295444562638 ps
CPU time 1272.96 seconds
Started Jan 17 12:50:20 PM PST 24
Finished Jan 17 01:11:38 PM PST 24
Peak memory 247996 kb
Host smart-263f2557-753f-455d-b1ce-6556550c2938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816572255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.1816572255
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2635376374
Short name T519
Test name
Test status
Simulation time 53763988 ps
CPU time 1.03 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 195984 kb
Host smart-a9a273be-fafc-494d-8249-4f23e1faddd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635376374 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2635376374
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3780966466
Short name T244
Test name
Test status
Simulation time 42729227928 ps
CPU time 498.28 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:58:43 PM PST 24
Peak memory 198692 kb
Host smart-432c0118-4762-43ac-b4c0-2bf09f1cc799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780966466 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.3780966466
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1905466578
Short name T458
Test name
Test status
Simulation time 7559053070 ps
CPU time 61.95 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 198608 kb
Host smart-77b0d9c1-ba28-4673-9bb0-fb6fdf79e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905466578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1905466578
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.831326595
Short name T728
Test name
Test status
Simulation time 107075335732 ps
CPU time 1804.26 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 01:22:33 PM PST 24
Peak memory 259876 kb
Host smart-ef5476f8-d549-4d06-b862-1c841286ad07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831326595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.831326595
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.3407865871
Short name T389
Test name
Test status
Simulation time 22297357786 ps
CPU time 325.23 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 12:57:54 PM PST 24
Peak memory 206932 kb
Host smart-bb9405bb-84b2-4ff7-a863-3fa0300c1506
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407865871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.3407865871
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.165579778
Short name T98
Test name
Test status
Simulation time 69401498149 ps
CPU time 1051.39 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:10:00 PM PST 24
Peak memory 245360 kb
Host smart-8b64edff-eca3-46b8-9542-c9e39573152b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165579778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.165579778
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1901612178
Short name T314
Test name
Test status
Simulation time 16717089298 ps
CPU time 319.13 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 12:57:48 PM PST 24
Peak memory 215236 kb
Host smart-9a083b74-1ab1-4c47-9c30-cced773b9b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901612178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1901612178
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.3800057886
Short name T499
Test name
Test status
Simulation time 60539841655 ps
CPU time 555.35 seconds
Started Jan 17 12:52:23 PM PST 24
Finished Jan 17 01:01:44 PM PST 24
Peak memory 239840 kb
Host smart-23508a05-629d-406c-bb54-6f26092001c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800057886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.3800057886
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.3022011185
Short name T99
Test name
Test status
Simulation time 42493447424 ps
CPU time 1697.62 seconds
Started Jan 17 12:52:28 PM PST 24
Finished Jan 17 01:20:47 PM PST 24
Peak memory 231552 kb
Host smart-233b25d5-5320-4a03-94fd-7a4ee0477b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022011185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.3022011185
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.1972823156
Short name T574
Test name
Test status
Simulation time 636081490265 ps
CPU time 1315.52 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 01:14:24 PM PST 24
Peak memory 226952 kb
Host smart-d50168e1-6bc5-4e45-b04b-b4cbc6f17f1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972823156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.1972823156
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.1225978982
Short name T522
Test name
Test status
Simulation time 187723034948 ps
CPU time 918.24 seconds
Started Jan 17 12:52:32 PM PST 24
Finished Jan 17 01:07:55 PM PST 24
Peak memory 248040 kb
Host smart-51e552cb-c786-4b67-9c2b-45abec653a0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225978982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.1225978982
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2555344436
Short name T425
Test name
Test status
Simulation time 11930653 ps
CPU time 0.6 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 193124 kb
Host smart-94e0b6ae-4811-4664-91ae-65250fd09602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555344436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2555344436
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2682854320
Short name T731
Test name
Test status
Simulation time 749874811 ps
CPU time 10.33 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:39 PM PST 24
Peak memory 223360 kb
Host smart-e08178b0-4023-4c01-8524-d0f7f1eb08db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682854320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2682854320
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1260230549
Short name T754
Test name
Test status
Simulation time 571906400 ps
CPU time 6.3 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:35 PM PST 24
Peak memory 198544 kb
Host smart-83975adf-5db4-4b83-9642-f735b15309f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260230549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1260230549
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3369141338
Short name T720
Test name
Test status
Simulation time 23930368063 ps
CPU time 74.77 seconds
Started Jan 17 12:50:20 PM PST 24
Finished Jan 17 12:51:40 PM PST 24
Peak memory 198756 kb
Host smart-ab100702-3401-4ff3-aa01-cd036ddd177b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369141338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3369141338
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2010469246
Short name T757
Test name
Test status
Simulation time 6469694375 ps
CPU time 78.36 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:51:43 PM PST 24
Peak memory 198752 kb
Host smart-5140c44c-8bce-45fb-8f16-7d3df6c1c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010469246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2010469246
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1902817827
Short name T3
Test name
Test status
Simulation time 1174109507 ps
CPU time 61.24 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 198572 kb
Host smart-5d1ab277-3e41-42b3-bde1-6627cfdbb987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902817827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1902817827
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1775627800
Short name T804
Test name
Test status
Simulation time 169366017 ps
CPU time 1.29 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 198084 kb
Host smart-a5687f35-355d-4afd-b79b-2dc192570ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775627800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1775627800
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2868940052
Short name T527
Test name
Test status
Simulation time 163461421585 ps
CPU time 989.61 seconds
Started Jan 17 12:50:22 PM PST 24
Finished Jan 17 01:06:56 PM PST 24
Peak memory 215128 kb
Host smart-f749d1ff-645e-4ff8-948f-b1360a4b1e4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868940052 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2868940052
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.3812458334
Short name T535
Test name
Test status
Simulation time 67255475577 ps
CPU time 402.14 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:57:07 PM PST 24
Peak memory 215280 kb
Host smart-ed123419-8045-4ad9-b8e1-aa2a1f81fc7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812458334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.3812458334
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1545623344
Short name T612
Test name
Test status
Simulation time 210141431 ps
CPU time 0.9 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 195692 kb
Host smart-c04d942d-ead0-4358-9681-428f0c6e25d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545623344 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1545623344
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2169526402
Short name T229
Test name
Test status
Simulation time 43822915504 ps
CPU time 503.73 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:58:49 PM PST 24
Peak memory 198692 kb
Host smart-9cbbf843-0752-4c50-8cb3-a014d94c8fce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169526402 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.2169526402
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.242918518
Short name T438
Test name
Test status
Simulation time 1584064457 ps
CPU time 27.73 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:56 PM PST 24
Peak memory 198600 kb
Host smart-537988e5-94ba-4b45-bc42-323f62871ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242918518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.242918518
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.1475598206
Short name T815
Test name
Test status
Simulation time 144217964294 ps
CPU time 1359.44 seconds
Started Jan 17 12:52:21 PM PST 24
Finished Jan 17 01:15:08 PM PST 24
Peak memory 211760 kb
Host smart-8f3121e8-3644-49de-9d1b-4e143cf336b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475598206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.1475598206
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.2102694103
Short name T468
Test name
Test status
Simulation time 54163114665 ps
CPU time 623.38 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:02:52 PM PST 24
Peak memory 231656 kb
Host smart-fa8bf45c-4ed3-4c72-b668-9baab3925d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102694103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.2102694103
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.419319297
Short name T723
Test name
Test status
Simulation time 25943021189 ps
CPU time 240.13 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 12:56:29 PM PST 24
Peak memory 198920 kb
Host smart-441f8fbd-d522-4190-a43d-14ecce45547f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419319297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.419319297
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.1184271847
Short name T239
Test name
Test status
Simulation time 118487067844 ps
CPU time 1540.03 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:18:09 PM PST 24
Peak memory 228744 kb
Host smart-8229ac8f-d424-4474-b36c-0b7137fee381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184271847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.1184271847
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2183623899
Short name T553
Test name
Test status
Simulation time 88589556323 ps
CPU time 4084.13 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 02:00:33 PM PST 24
Peak memory 256248 kb
Host smart-9e58caf8-d590-4d82-9b06-b2e3debe8211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183623899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.2183623899
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.2786368821
Short name T756
Test name
Test status
Simulation time 196689553661 ps
CPU time 2131.1 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:28:00 PM PST 24
Peak memory 255452 kb
Host smart-a504668e-01d1-46f3-867b-bcd25435da4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786368821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.2786368821
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.2149967375
Short name T749
Test name
Test status
Simulation time 87493975937 ps
CPU time 1554.5 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:18:23 PM PST 24
Peak memory 240756 kb
Host smart-7e28111c-2582-4818-8232-bf909fa0bb5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149967375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.2149967375
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4152707496
Short name T508
Test name
Test status
Simulation time 38435691 ps
CPU time 0.56 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 193124 kb
Host smart-2c304b5b-ffd4-4808-ab6e-66a3cdf33c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152707496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4152707496
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1464902476
Short name T203
Test name
Test status
Simulation time 3234265515 ps
CPU time 28.41 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 228456 kb
Host smart-60216384-fac9-439b-be4b-aa032301105a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464902476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1464902476
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.657644209
Short name T818
Test name
Test status
Simulation time 1643249950 ps
CPU time 36.63 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198508 kb
Host smart-9af84c3f-1f05-4678-9459-d1ac00251dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657644209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.657644209
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.209378448
Short name T788
Test name
Test status
Simulation time 5750259589 ps
CPU time 66.37 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 198772 kb
Host smart-9bde41ec-2f55-4e15-91ea-773a0fe6526b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209378448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.209378448
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2239765621
Short name T549
Test name
Test status
Simulation time 11817938205 ps
CPU time 133.92 seconds
Started Jan 17 12:50:24 PM PST 24
Finished Jan 17 12:52:41 PM PST 24
Peak memory 198772 kb
Host smart-a9be0b4b-e67b-4dd0-ad3a-b938c97d3091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239765621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2239765621
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2920571432
Short name T209
Test name
Test status
Simulation time 11705270620 ps
CPU time 80.1 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 198804 kb
Host smart-91a45536-737f-4abf-a007-d564b7d26067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920571432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2920571432
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3618114003
Short name T298
Test name
Test status
Simulation time 393592358 ps
CPU time 4.54 seconds
Started Jan 17 12:50:20 PM PST 24
Finished Jan 17 12:50:30 PM PST 24
Peak memory 198324 kb
Host smart-4499f624-13d7-4252-8f2a-1a3d7832a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618114003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3618114003
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.605800982
Short name T256
Test name
Test status
Simulation time 229927585264 ps
CPU time 1052.88 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 01:07:58 PM PST 24
Peak memory 231012 kb
Host smart-6a7286c0-c134-4e3a-b62c-b18da306dc22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605800982 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.605800982
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2859269208
Short name T785
Test name
Test status
Simulation time 263754454794 ps
CPU time 3295.79 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 01:45:21 PM PST 24
Peak memory 263736 kb
Host smart-d32ffd8b-b968-4f15-b865-3576b4746bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859269208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2859269208
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2932842691
Short name T404
Test name
Test status
Simulation time 29321379 ps
CPU time 1.04 seconds
Started Jan 17 12:50:25 PM PST 24
Finished Jan 17 12:50:28 PM PST 24
Peak memory 196660 kb
Host smart-37e13b8f-d336-4748-a7fc-7e8954b58f5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932842691 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2932842691
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.4126608792
Short name T335
Test name
Test status
Simulation time 170118648648 ps
CPU time 430.37 seconds
Started Jan 17 12:50:20 PM PST 24
Finished Jan 17 12:57:36 PM PST 24
Peak memory 198556 kb
Host smart-b6acf5e5-a218-4bf4-a832-268330698e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126608792 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.4126608792
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.218514404
Short name T591
Test name
Test status
Simulation time 2398001803 ps
CPU time 21.19 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:50:46 PM PST 24
Peak memory 198696 kb
Host smart-a2d68a93-f619-427c-84fe-76d55d9ddcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218514404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.218514404
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1929235582
Short name T91
Test name
Test status
Simulation time 151183621348 ps
CPU time 1784.57 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:22:14 PM PST 24
Peak memory 223952 kb
Host smart-16aa01f7-3a74-47ad-b90d-f29fd3262c0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929235582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1929235582
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.521458624
Short name T622
Test name
Test status
Simulation time 88720076095 ps
CPU time 1356.79 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:15:11 PM PST 24
Peak memory 248036 kb
Host smart-123d082f-c66a-4992-bf00-f43cc5a642af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521458624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.521458624
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.3867369482
Short name T844
Test name
Test status
Simulation time 51358194019 ps
CPU time 2620.86 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:36:10 PM PST 24
Peak memory 246692 kb
Host smart-cd66e2a2-5e25-49c7-bec2-437e26285763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867369482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.3867369482
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1344192936
Short name T109
Test name
Test status
Simulation time 233827350449 ps
CPU time 5681.58 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 02:27:11 PM PST 24
Peak memory 272596 kb
Host smart-7e7c3de6-9e26-41bf-97a0-e146b7dbc48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344192936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.1344192936
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.2070106542
Short name T450
Test name
Test status
Simulation time 37563502581 ps
CPU time 428.78 seconds
Started Jan 17 12:52:35 PM PST 24
Finished Jan 17 12:59:46 PM PST 24
Peak memory 215328 kb
Host smart-9e88c30a-3387-4fef-ba02-74c7b1be57ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070106542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.2070106542
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.1074280980
Short name T581
Test name
Test status
Simulation time 115854842493 ps
CPU time 1295.85 seconds
Started Jan 17 12:52:34 PM PST 24
Finished Jan 17 01:14:13 PM PST 24
Peak memory 256288 kb
Host smart-053a964d-2ab7-4cf7-9b63-d7b3fe8641d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074280980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.1074280980
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3378142684
Short name T358
Test name
Test status
Simulation time 63171184710 ps
CPU time 489.19 seconds
Started Jan 17 12:52:32 PM PST 24
Finished Jan 17 01:00:46 PM PST 24
Peak memory 247968 kb
Host smart-10e5757a-44a3-49d4-bb26-a1023f29c6f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378142684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3378142684
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.292059732
Short name T192
Test name
Test status
Simulation time 18441666700 ps
CPU time 865.24 seconds
Started Jan 17 12:52:34 PM PST 24
Finished Jan 17 01:07:02 PM PST 24
Peak memory 214872 kb
Host smart-cacd7d08-ef0b-4843-8fc9-c850d6f84dcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292059732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.292059732
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.1383947674
Short name T602
Test name
Test status
Simulation time 242766340041 ps
CPU time 1299.28 seconds
Started Jan 17 12:52:35 PM PST 24
Finished Jan 17 01:14:16 PM PST 24
Peak memory 256240 kb
Host smart-12bc153e-8614-4f52-8d41-fe487a0b441a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383947674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.1383947674
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.739034394
Short name T669
Test name
Test status
Simulation time 14278228 ps
CPU time 0.57 seconds
Started Jan 17 12:50:24 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 193104 kb
Host smart-f77dfd07-6983-41a4-8ad8-943d4c2322f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739034394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.739034394
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.313466639
Short name T512
Test name
Test status
Simulation time 865135107 ps
CPU time 26.58 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:50:52 PM PST 24
Peak memory 215156 kb
Host smart-25169a3d-f7a1-4ab4-b907-b5d478c0bc55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313466639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.313466639
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1930401054
Short name T729
Test name
Test status
Simulation time 1526569266 ps
CPU time 27.32 seconds
Started Jan 17 12:50:22 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 198684 kb
Host smart-d4f266fd-4a3f-4738-8eb2-888f14b16494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930401054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1930401054
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.693967106
Short name T242
Test name
Test status
Simulation time 5286656038 ps
CPU time 106.83 seconds
Started Jan 17 12:50:21 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 198704 kb
Host smart-b6bd1899-fb00-4dea-a2ff-0850207cf644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693967106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.693967106
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.630086868
Short name T739
Test name
Test status
Simulation time 4595411044 ps
CPU time 72.15 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:51:37 PM PST 24
Peak memory 198836 kb
Host smart-16de1abe-a6d1-415c-a64a-767db229fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630086868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.630086868
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1322147392
Short name T693
Test name
Test status
Simulation time 21024523513 ps
CPU time 106.04 seconds
Started Jan 17 12:50:21 PM PST 24
Finished Jan 17 12:52:11 PM PST 24
Peak memory 198696 kb
Host smart-da31969b-a5fc-4f60-bb0c-deeff15fe5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322147392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1322147392
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1240483175
Short name T241
Test name
Test status
Simulation time 70567847 ps
CPU time 1.96 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 198656 kb
Host smart-a86325ed-98dd-405c-80d1-52424d8df1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240483175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1240483175
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3438894558
Short name T439
Test name
Test status
Simulation time 47092568216 ps
CPU time 563.6 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:59:52 PM PST 24
Peak memory 233640 kb
Host smart-28c77076-5e77-45c3-8bcc-bf8dd1501c4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438894558 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3438894558
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.1203874644
Short name T848
Test name
Test status
Simulation time 54955837901 ps
CPU time 2646.54 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 01:34:38 PM PST 24
Peak memory 247612 kb
Host smart-39ee796a-519d-49ac-bf1e-31a58d766afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203874644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.1203874644
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2605780308
Short name T213
Test name
Test status
Simulation time 39489364 ps
CPU time 0.96 seconds
Started Jan 17 12:50:30 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 195876 kb
Host smart-a79fa49c-1768-4a26-a4a5-80e27ccd177a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605780308 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2605780308
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.281789071
Short name T594
Test name
Test status
Simulation time 7364986760 ps
CPU time 354.35 seconds
Started Jan 17 12:50:25 PM PST 24
Finished Jan 17 12:56:21 PM PST 24
Peak memory 198752 kb
Host smart-f371627b-8993-4307-a1ee-0452998e2e98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281789071 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.281789071
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3855060060
Short name T257
Test name
Test status
Simulation time 1217714535 ps
CPU time 4.77 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:50:33 PM PST 24
Peak memory 198740 kb
Host smart-2e1659ba-3c5e-4dbf-adb3-028333f2b747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855060060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3855060060
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.1971671015
Short name T614
Test name
Test status
Simulation time 70929843781 ps
CPU time 460.78 seconds
Started Jan 17 12:52:36 PM PST 24
Finished Jan 17 01:00:18 PM PST 24
Peak memory 240924 kb
Host smart-29ab0c68-360d-4cab-809e-65436291a34e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971671015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.1971671015
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.2398124407
Short name T316
Test name
Test status
Simulation time 93754034588 ps
CPU time 1875.37 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:23:44 PM PST 24
Peak memory 243904 kb
Host smart-ec30867d-a642-4edb-a9e8-88a529d55d04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398124407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.2398124407
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.1506019564
Short name T775
Test name
Test status
Simulation time 258262230122 ps
CPU time 2832.37 seconds
Started Jan 17 12:52:31 PM PST 24
Finished Jan 17 01:39:49 PM PST 24
Peak memory 247944 kb
Host smart-632a08b6-78b0-43f4-9ba7-abb6e9e06408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506019564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.1506019564
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.3024345229
Short name T680
Test name
Test status
Simulation time 74120222171 ps
CPU time 1028.72 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:09:42 PM PST 24
Peak memory 223816 kb
Host smart-380c6526-91dc-4718-805f-d7c3d08dea45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024345229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.3024345229
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.526114094
Short name T579
Test name
Test status
Simulation time 232048747049 ps
CPU time 675.81 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:03:45 PM PST 24
Peak memory 243672 kb
Host smart-edc9620e-5d2d-46d0-8214-a671146f35ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526114094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.526114094
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.2251260605
Short name T302
Test name
Test status
Simulation time 81579810425 ps
CPU time 1420.74 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:16:10 PM PST 24
Peak memory 247988 kb
Host smart-30c29a18-32eb-4d5e-8f4f-cb280088eaf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251260605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.2251260605
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.1165285239
Short name T837
Test name
Test status
Simulation time 12688370246 ps
CPU time 661.81 seconds
Started Jan 17 12:52:36 PM PST 24
Finished Jan 17 01:03:39 PM PST 24
Peak memory 239940 kb
Host smart-d44cd184-8a3a-40c4-8977-fae7d078d9fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165285239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.1165285239
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.1039260907
Short name T102
Test name
Test status
Simulation time 12762454608 ps
CPU time 404.06 seconds
Started Jan 17 12:52:32 PM PST 24
Finished Jan 17 12:59:20 PM PST 24
Peak memory 231628 kb
Host smart-06055caf-3687-4ece-b8ba-f39ef7d1e55b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039260907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.1039260907
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.708619381
Short name T825
Test name
Test status
Simulation time 97507497580 ps
CPU time 3595.11 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 01:52:24 PM PST 24
Peak memory 256900 kb
Host smart-ab169a15-7f83-4f22-b0d8-97fd2482c758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708619381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.708619381
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1485339473
Short name T105
Test name
Test status
Simulation time 130335124602 ps
CPU time 2241.19 seconds
Started Jan 17 12:52:36 PM PST 24
Finished Jan 17 01:29:58 PM PST 24
Peak memory 231344 kb
Host smart-851b215e-0174-4c93-a789-c9e1f3677e30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485339473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1485339473
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.139504752
Short name T310
Test name
Test status
Simulation time 14631214 ps
CPU time 0.56 seconds
Started Jan 17 12:50:30 PM PST 24
Finished Jan 17 12:50:31 PM PST 24
Peak memory 193080 kb
Host smart-811bfe2e-ada0-45dd-b9eb-936fcb557934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139504752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.139504752
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3240642513
Short name T700
Test name
Test status
Simulation time 3014616313 ps
CPU time 23.21 seconds
Started Jan 17 12:50:25 PM PST 24
Finished Jan 17 12:50:50 PM PST 24
Peak memory 198808 kb
Host smart-b173b631-5627-49de-923a-1c97250e24f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240642513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3240642513
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2747909889
Short name T748
Test name
Test status
Simulation time 6272702754 ps
CPU time 19.53 seconds
Started Jan 17 12:50:33 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 198792 kb
Host smart-efd69ca3-a454-4a18-b564-60e2e85c4df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747909889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2747909889
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.937900737
Short name T767
Test name
Test status
Simulation time 5134241156 ps
CPU time 138.13 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:52:50 PM PST 24
Peak memory 198784 kb
Host smart-c8e0570c-e460-48b3-8292-f097f4bbedb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937900737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.937900737
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3437867344
Short name T184
Test name
Test status
Simulation time 4020083862 ps
CPU time 63.54 seconds
Started Jan 17 12:50:29 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 198828 kb
Host smart-17aad4bb-c654-49f4-a6e2-113b7468fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437867344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3437867344
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3899361429
Short name T834
Test name
Test status
Simulation time 2107388307 ps
CPU time 53.67 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:51:27 PM PST 24
Peak memory 198732 kb
Host smart-285a06c2-8327-4737-a933-1e66ad6c7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899361429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3899361429
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2427766530
Short name T6
Test name
Test status
Simulation time 1301265644 ps
CPU time 3.16 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:50:36 PM PST 24
Peak memory 198716 kb
Host smart-c50ca2b5-3ae6-4b21-bc9b-21bac409f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427766530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2427766530
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2313591381
Short name T695
Test name
Test status
Simulation time 34471234553 ps
CPU time 390.27 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:57:03 PM PST 24
Peak memory 207000 kb
Host smart-675a8a38-ddd9-4fbd-a0ac-2358391678d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313591381 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2313591381
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.157074562
Short name T444
Test name
Test status
Simulation time 32564660577 ps
CPU time 314.63 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:55:49 PM PST 24
Peak memory 227572 kb
Host smart-8c083e40-3f68-422b-95b5-26c298928e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157074562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.157074562
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1102267304
Short name T561
Test name
Test status
Simulation time 373451436 ps
CPU time 0.9 seconds
Started Jan 17 12:50:24 PM PST 24
Finished Jan 17 12:50:28 PM PST 24
Peak memory 196512 kb
Host smart-b60d9195-b689-455e-bb6c-5e226978bc2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102267304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1102267304
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2102807582
Short name T349
Test name
Test status
Simulation time 8750824081 ps
CPU time 408.05 seconds
Started Jan 17 12:50:29 PM PST 24
Finished Jan 17 12:57:18 PM PST 24
Peak memory 198532 kb
Host smart-c2631b75-cacc-4dd8-867e-6cfc0227d812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102807582 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.2102807582
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3752333524
Short name T365
Test name
Test status
Simulation time 13378256192 ps
CPU time 14.5 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:49 PM PST 24
Peak memory 198748 kb
Host smart-acd745cb-889b-4e45-adec-18e10960daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752333524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3752333524
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.2249709448
Short name T792
Test name
Test status
Simulation time 327703869756 ps
CPU time 1270.45 seconds
Started Jan 17 12:52:35 PM PST 24
Finished Jan 17 01:13:47 PM PST 24
Peak memory 231712 kb
Host smart-8c62121e-85f8-4252-a2e4-d384d920e68c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249709448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.2249709448
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.554617962
Short name T773
Test name
Test status
Simulation time 66489560051 ps
CPU time 3337.23 seconds
Started Jan 17 12:52:36 PM PST 24
Finished Jan 17 01:48:15 PM PST 24
Peak memory 231716 kb
Host smart-06a06821-3a23-49dc-80e5-18405a9cc093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554617962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.554617962
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.453633263
Short name T697
Test name
Test status
Simulation time 111309680111 ps
CPU time 1071.36 seconds
Started Jan 17 12:52:30 PM PST 24
Finished Jan 17 01:10:27 PM PST 24
Peak memory 239904 kb
Host smart-fe3525d1-6c8d-478f-9abc-339bfdc52ac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453633263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.453633263
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1566256461
Short name T583
Test name
Test status
Simulation time 192132320468 ps
CPU time 1035.74 seconds
Started Jan 17 12:52:34 PM PST 24
Finished Jan 17 01:09:52 PM PST 24
Peak memory 235748 kb
Host smart-6774601b-b775-4083-b5d6-4bcb1eab11b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566256461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.1566256461
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1650088181
Short name T743
Test name
Test status
Simulation time 114424665893 ps
CPU time 1831.17 seconds
Started Jan 17 12:52:30 PM PST 24
Finished Jan 17 01:23:07 PM PST 24
Peak memory 247956 kb
Host smart-ac246af7-df76-4492-a2f0-46533aa2fcba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650088181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1650088181
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.1632417658
Short name T258
Test name
Test status
Simulation time 93972894795 ps
CPU time 348.88 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 12:58:18 PM PST 24
Peak memory 215128 kb
Host smart-75c6f989-47ca-4a14-87e9-4241292f1297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632417658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.1632417658
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.1830251449
Short name T589
Test name
Test status
Simulation time 615972319576 ps
CPU time 1813.94 seconds
Started Jan 17 12:52:38 PM PST 24
Finished Jan 17 01:22:53 PM PST 24
Peak memory 263268 kb
Host smart-999c5456-38e0-4c0a-b392-9d3884411ce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830251449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.1830251449
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.1576910929
Short name T485
Test name
Test status
Simulation time 21088499127 ps
CPU time 161.13 seconds
Started Jan 17 12:52:38 PM PST 24
Finished Jan 17 12:55:19 PM PST 24
Peak memory 207072 kb
Host smart-c1cf784c-2607-4038-a941-66ed16559f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576910929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.1576910929
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1758222354
Short name T419
Test name
Test status
Simulation time 394606767647 ps
CPU time 1688.33 seconds
Started Jan 17 12:52:39 PM PST 24
Finished Jan 17 01:20:48 PM PST 24
Peak memory 219860 kb
Host smart-bb719f53-6189-466a-9256-a892b4e8febb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758222354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1758222354
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1925701192
Short name T542
Test name
Test status
Simulation time 24692128 ps
CPU time 0.61 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 193044 kb
Host smart-f790cf9e-6d33-4d81-a293-d27b126d3c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925701192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1925701192
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3059687399
Short name T515
Test name
Test status
Simulation time 2701937048 ps
CPU time 36.74 seconds
Started Jan 17 12:50:23 PM PST 24
Finished Jan 17 12:51:03 PM PST 24
Peak memory 210044 kb
Host smart-288b2c8b-5063-41a0-89a9-d9a187e24275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059687399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3059687399
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3341664960
Short name T660
Test name
Test status
Simulation time 7193673920 ps
CPU time 24.39 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:51:07 PM PST 24
Peak memory 198656 kb
Host smart-9251ab8a-1c8c-457b-b355-de01fda609db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341664960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3341664960
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2591766663
Short name T827
Test name
Test status
Simulation time 11236848328 ps
CPU time 157.12 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:53:19 PM PST 24
Peak memory 198808 kb
Host smart-26133b2c-7ca0-468d-87c8-81d842ffe7cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591766663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2591766663
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2849946761
Short name T820
Test name
Test status
Simulation time 977857099 ps
CPU time 16.98 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 12:50:56 PM PST 24
Peak memory 198736 kb
Host smart-612a4c0e-63ba-4f57-b081-8bfb23f45ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849946761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2849946761
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1330647607
Short name T620
Test name
Test status
Simulation time 36534406071 ps
CPU time 90.7 seconds
Started Jan 17 12:50:36 PM PST 24
Finished Jan 17 12:52:08 PM PST 24
Peak memory 198740 kb
Host smart-1b1b8d4b-6380-4c8c-b322-9746ee399293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330647607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1330647607
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2797407296
Short name T708
Test name
Test status
Simulation time 1218774438 ps
CPU time 1.99 seconds
Started Jan 17 12:50:26 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 198656 kb
Host smart-63813630-c8b7-426b-9578-2c3a5371b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797407296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2797407296
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1664041324
Short name T188
Test name
Test status
Simulation time 11196882674 ps
CPU time 36.71 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 198792 kb
Host smart-35f92414-362f-4916-a165-a406d0223bf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664041324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1664041324
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.1583934216
Short name T101
Test name
Test status
Simulation time 147153564100 ps
CPU time 1393.03 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 01:13:46 PM PST 24
Peak memory 256220 kb
Host smart-46f6d304-d68f-42be-a223-173fc72feb27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583934216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.1583934216
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3315364354
Short name T284
Test name
Test status
Simulation time 946553559 ps
CPU time 1.09 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:30 PM PST 24
Peak memory 197436 kb
Host smart-e2e9035e-fd4b-4d57-9822-981e1464a0f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315364354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3315364354
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.218960209
Short name T740
Test name
Test status
Simulation time 27142412507 ps
CPU time 448.76 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:57:57 PM PST 24
Peak memory 198724 kb
Host smart-438e9796-01b6-46d6-982e-fcb2f5a70d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218960209 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_sha_vectors.218960209
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.23567436
Short name T467
Test name
Test status
Simulation time 1635406017 ps
CPU time 19.51 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198584 kb
Host smart-80eae310-7451-41bb-aeb5-c1fcc58a4328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23567436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.23567436
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.3858982453
Short name T300
Test name
Test status
Simulation time 152935430563 ps
CPU time 527.56 seconds
Started Jan 17 12:52:37 PM PST 24
Finished Jan 17 01:01:25 PM PST 24
Peak memory 226596 kb
Host smart-d3c30250-ac1c-4339-8d92-c80f5fc355f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858982453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.3858982453
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.132183184
Short name T781
Test name
Test status
Simulation time 27919190686 ps
CPU time 731.98 seconds
Started Jan 17 12:52:34 PM PST 24
Finished Jan 17 01:04:49 PM PST 24
Peak memory 207108 kb
Host smart-a4fece50-9b4a-4a13-afaa-591e464fae45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132183184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.132183184
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.2362338406
Short name T628
Test name
Test status
Simulation time 18916847082 ps
CPU time 247.97 seconds
Started Jan 17 12:52:39 PM PST 24
Finished Jan 17 12:56:47 PM PST 24
Peak memory 207076 kb
Host smart-9483fba8-312a-40c8-a0f0-e04dc4f16cd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362338406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.2362338406
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.4074247288
Short name T787
Test name
Test status
Simulation time 85303400649 ps
CPU time 3639.98 seconds
Started Jan 17 12:52:35 PM PST 24
Finished Jan 17 01:53:17 PM PST 24
Peak memory 256180 kb
Host smart-e9a99f9d-6c14-4228-a5a7-b50032ee3d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074247288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.4074247288
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1516565474
Short name T35
Test name
Test status
Simulation time 1868475561165 ps
CPU time 3546.14 seconds
Started Jan 17 12:52:37 PM PST 24
Finished Jan 17 01:51:44 PM PST 24
Peak memory 272660 kb
Host smart-13af0e91-859a-42e8-bf47-203e5c85873c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516565474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1516565474
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.3197431195
Short name T529
Test name
Test status
Simulation time 23494293518 ps
CPU time 115.42 seconds
Started Jan 17 12:52:34 PM PST 24
Finished Jan 17 12:54:32 PM PST 24
Peak memory 239908 kb
Host smart-6370ea31-45d5-4305-a77a-b75fc72ecb66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197431195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.3197431195
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.2336161355
Short name T493
Test name
Test status
Simulation time 1521053835791 ps
CPU time 2399.58 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 01:32:43 PM PST 24
Peak memory 260856 kb
Host smart-0018285e-82d5-4ea1-88b6-a423f1307bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336161355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.2336161355
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1455651024
Short name T642
Test name
Test status
Simulation time 69931955531 ps
CPU time 1287.09 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 01:14:09 PM PST 24
Peak memory 242364 kb
Host smart-af33a6ae-f03a-4790-a69d-71b4b146e6c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455651024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1455651024
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.3353370751
Short name T233
Test name
Test status
Simulation time 174374788304 ps
CPU time 449.85 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 01:00:12 PM PST 24
Peak memory 215260 kb
Host smart-cdf9ba2c-fac8-4383-8f0e-f9d8e1dc153a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353370751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.3353370751
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.119494644
Short name T674
Test name
Test status
Simulation time 954104578 ps
CPU time 12.61 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:42 PM PST 24
Peak memory 198812 kb
Host smart-dadd696e-3e7b-4dad-9895-3a5b809c9232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119494644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.119494644
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1716355294
Short name T56
Test name
Test status
Simulation time 668500836 ps
CPU time 29.54 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:50:58 PM PST 24
Peak memory 198840 kb
Host smart-328c846c-7e5f-468b-9ad6-dfeecb2a360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716355294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1716355294
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3851278149
Short name T247
Test name
Test status
Simulation time 2291198236 ps
CPU time 60.93 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:51:42 PM PST 24
Peak memory 198752 kb
Host smart-1d860c45-26f6-4d91-af2a-21ac0f69ea4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851278149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3851278149
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4161214205
Short name T779
Test name
Test status
Simulation time 12554179113 ps
CPU time 151.94 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:53:04 PM PST 24
Peak memory 198812 kb
Host smart-52e7e173-0a14-48a7-8a7e-ae05a9390231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161214205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4161214205
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.689088011
Short name T346
Test name
Test status
Simulation time 1495307123 ps
CPU time 65.32 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 198688 kb
Host smart-3d71117a-f236-4ae2-833c-1c5df3bcefbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689088011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.689088011
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2191932561
Short name T7
Test name
Test status
Simulation time 365572073 ps
CPU time 3.64 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:50:42 PM PST 24
Peak memory 198684 kb
Host smart-b2387bcf-5667-45ee-8a5e-931136293f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191932561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2191932561
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.791918208
Short name T37
Test name
Test status
Simulation time 20223724943 ps
CPU time 217.78 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:54:20 PM PST 24
Peak memory 198784 kb
Host smart-fcf8be57-3fca-4b0c-8fe3-68f9ff08d91a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791918208 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.791918208
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1935561321
Short name T414
Test name
Test status
Simulation time 25885024828 ps
CPU time 196.06 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:53:58 PM PST 24
Peak memory 227892 kb
Host smart-0c12d51e-8662-4a96-b495-72e7dba64283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935561321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.1935561321
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1572274886
Short name T372
Test name
Test status
Simulation time 376099047 ps
CPU time 0.95 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 12:50:40 PM PST 24
Peak memory 195944 kb
Host smart-1b7cf6b3-8c45-4900-8a31-4180b6a05aff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572274886 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1572274886
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3372979370
Short name T443
Test name
Test status
Simulation time 65511105619 ps
CPU time 399.4 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 12:57:18 PM PST 24
Peak memory 198756 kb
Host smart-09ea07e1-cd15-4401-8bcb-1792dd11bf45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372979370 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.3372979370
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1261614097
Short name T830
Test name
Test status
Simulation time 14116388988 ps
CPU time 67.38 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:51:40 PM PST 24
Peak memory 198784 kb
Host smart-1107998b-7f07-4ba1-8140-7fb2860a6bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261614097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1261614097
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.2277093634
Short name T88
Test name
Test status
Simulation time 63498831899 ps
CPU time 2140.57 seconds
Started Jan 17 12:52:46 PM PST 24
Finished Jan 17 01:28:27 PM PST 24
Peak memory 255472 kb
Host smart-06f013ec-3968-47f6-a39e-383bb04b8b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277093634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.2277093634
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.1558546881
Short name T111
Test name
Test status
Simulation time 45570060706 ps
CPU time 1160.52 seconds
Started Jan 17 12:52:46 PM PST 24
Finished Jan 17 01:12:07 PM PST 24
Peak memory 239712 kb
Host smart-8b7e330f-c57d-47d6-a59b-335b74346d10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558546881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.1558546881
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.985876499
Short name T52
Test name
Test status
Simulation time 36960025124 ps
CPU time 669.92 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 01:03:52 PM PST 24
Peak memory 215284 kb
Host smart-e1cccad8-1d9b-46ec-b6ac-f8fc2d191976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985876499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.985876499
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.3528461632
Short name T686
Test name
Test status
Simulation time 142077537706 ps
CPU time 846.64 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 01:06:49 PM PST 24
Peak memory 215208 kb
Host smart-aebae924-2d35-4f7d-8554-aaaae5275cb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528461632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.3528461632
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3052637156
Short name T677
Test name
Test status
Simulation time 166684697664 ps
CPU time 1464.44 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 01:17:06 PM PST 24
Peak memory 246744 kb
Host smart-17633e4e-176a-4c9c-b593-6f8bb9864690
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052637156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.3052637156
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3312558177
Short name T821
Test name
Test status
Simulation time 44893875128 ps
CPU time 597.42 seconds
Started Jan 17 12:52:44 PM PST 24
Finished Jan 17 01:02:42 PM PST 24
Peak memory 240972 kb
Host smart-2d6d0a3b-e669-4580-a5d4-977c76c0261b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312558177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.3312558177
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.1673048689
Short name T835
Test name
Test status
Simulation time 187210619679 ps
CPU time 3138.36 seconds
Started Jan 17 12:52:43 PM PST 24
Finished Jan 17 01:45:02 PM PST 24
Peak memory 264504 kb
Host smart-c1e61247-a838-4977-b6cd-e7d4993d3bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673048689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.1673048689
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2364107834
Short name T658
Test name
Test status
Simulation time 383244724681 ps
CPU time 1620.09 seconds
Started Jan 17 12:52:43 PM PST 24
Finished Jan 17 01:19:44 PM PST 24
Peak memory 226088 kb
Host smart-581a627e-3291-4e0d-9022-8105a35cf588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364107834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2364107834
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.225383524
Short name T541
Test name
Test status
Simulation time 423407713380 ps
CPU time 1931.53 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 01:24:55 PM PST 24
Peak memory 263636 kb
Host smart-fff5091d-e1eb-4a07-9b31-3552d1298875
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225383524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.225383524
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3965209771
Short name T201
Test name
Test status
Simulation time 136382142 ps
CPU time 0.54 seconds
Started Jan 17 12:50:34 PM PST 24
Finished Jan 17 12:50:35 PM PST 24
Peak memory 193108 kb
Host smart-0404fe0f-2612-455a-89c4-1e4fc4868da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965209771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3965209771
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.530713374
Short name T593
Test name
Test status
Simulation time 7037882704 ps
CPU time 58.14 seconds
Started Jan 17 12:50:39 PM PST 24
Finished Jan 17 12:51:40 PM PST 24
Peak memory 231560 kb
Host smart-3952c064-88ef-43eb-b986-1c4623cfa753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530713374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.530713374
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.60169071
Short name T537
Test name
Test status
Simulation time 4998209585 ps
CPU time 48.04 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 198816 kb
Host smart-a6791aeb-ba71-4911-a520-6557398593f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60169071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.60169071
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.214332474
Short name T408
Test name
Test status
Simulation time 24309398 ps
CPU time 0.68 seconds
Started Jan 17 12:50:42 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 194028 kb
Host smart-d71ec344-80ed-4159-93df-11e4f09ccae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214332474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.214332474
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1607012283
Short name T340
Test name
Test status
Simulation time 22684401627 ps
CPU time 135.31 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 198648 kb
Host smart-3d13004c-7c74-4fe1-81c8-5eb3ac3c0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607012283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1607012283
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1082219131
Short name T607
Test name
Test status
Simulation time 29236869859 ps
CPU time 82.39 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:52:04 PM PST 24
Peak memory 198764 kb
Host smart-bbef1dc9-8306-4131-be3e-6ad0d78fd9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082219131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1082219131
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2711942716
Short name T38
Test name
Test status
Simulation time 682057343 ps
CPU time 3.11 seconds
Started Jan 17 12:50:33 PM PST 24
Finished Jan 17 12:50:37 PM PST 24
Peak memory 198648 kb
Host smart-1e4de989-7d20-47a4-890e-de09196283da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711942716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2711942716
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2873009726
Short name T616
Test name
Test status
Simulation time 31016361043 ps
CPU time 700.97 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 206820 kb
Host smart-7639e8db-023e-4cd3-88fd-22a71dde3bf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873009726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2873009726
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.3791396795
Short name T613
Test name
Test status
Simulation time 351676248670 ps
CPU time 1632.95 seconds
Started Jan 17 12:50:43 PM PST 24
Finished Jan 17 01:17:57 PM PST 24
Peak memory 254316 kb
Host smart-6f9a41e2-960c-4abc-a598-7dcf6f67896f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791396795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.3791396795
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3957730273
Short name T747
Test name
Test status
Simulation time 60765241 ps
CPU time 1.15 seconds
Started Jan 17 12:50:43 PM PST 24
Finished Jan 17 12:50:45 PM PST 24
Peak memory 196856 kb
Host smart-0e9ea17c-2090-4d8f-a301-89b6fa891b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957730273 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3957730273
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3227832398
Short name T665
Test name
Test status
Simulation time 4636314357 ps
CPU time 58.55 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:51:40 PM PST 24
Peak memory 198720 kb
Host smart-aef19782-3373-46c1-8e38-8fa38fee5593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227832398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3227832398
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.678700408
Short name T319
Test name
Test status
Simulation time 64271610118 ps
CPU time 941.54 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 01:08:24 PM PST 24
Peak memory 225560 kb
Host smart-6f87ed52-c9fc-4969-b9e7-5502a21cd072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678700408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.678700408
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.2914668024
Short name T338
Test name
Test status
Simulation time 64562049405 ps
CPU time 689.92 seconds
Started Jan 17 12:52:40 PM PST 24
Finished Jan 17 01:04:11 PM PST 24
Peak memory 255464 kb
Host smart-f4622372-b684-42f8-8f0f-0f139a1fac47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914668024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.2914668024
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.1064278218
Short name T565
Test name
Test status
Simulation time 37940815963 ps
CPU time 508.61 seconds
Started Jan 17 12:52:44 PM PST 24
Finished Jan 17 01:01:13 PM PST 24
Peak memory 215280 kb
Host smart-553b4fd8-fab5-48fe-a0f7-bf5e56a31c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064278218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.1064278218
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.2999721927
Short name T715
Test name
Test status
Simulation time 168426219856 ps
CPU time 698.5 seconds
Started Jan 17 12:52:43 PM PST 24
Finished Jan 17 01:04:22 PM PST 24
Peak memory 242048 kb
Host smart-05281df4-db84-424a-b796-8809ec263d53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999721927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.2999721927
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.143578727
Short name T435
Test name
Test status
Simulation time 171939039140 ps
CPU time 827.41 seconds
Started Jan 17 12:52:48 PM PST 24
Finished Jan 17 01:06:36 PM PST 24
Peak memory 223480 kb
Host smart-56564606-c966-431e-a17f-e00f9db8491d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143578727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.143578727
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.1647068668
Short name T453
Test name
Test status
Simulation time 47607921415 ps
CPU time 1319.97 seconds
Started Jan 17 12:52:40 PM PST 24
Finished Jan 17 01:14:41 PM PST 24
Peak memory 255820 kb
Host smart-62c8a54c-1811-40d6-8e2c-06f5b906b6b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647068668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.1647068668
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.349868052
Short name T355
Test name
Test status
Simulation time 235888686478 ps
CPU time 1064.28 seconds
Started Jan 17 12:52:45 PM PST 24
Finished Jan 17 01:10:30 PM PST 24
Peak memory 223480 kb
Host smart-62d837db-9eeb-4ae6-a7dc-42ff6b1f3ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349868052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.349868052
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.1487188408
Short name T34
Test name
Test status
Simulation time 355340034496 ps
CPU time 4412.92 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 02:06:16 PM PST 24
Peak memory 253172 kb
Host smart-3f3aa706-a9cc-43dd-bd61-6c7b4c5e2b14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487188408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.1487188408
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.3632354427
Short name T685
Test name
Test status
Simulation time 186819555560 ps
CPU time 779.95 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 01:05:43 PM PST 24
Peak memory 211116 kb
Host smart-d22a9efb-7395-4e18-81e7-959925351062
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632354427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.3632354427
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.3023220165
Short name T701
Test name
Test status
Simulation time 172028182579 ps
CPU time 2517.72 seconds
Started Jan 17 12:52:43 PM PST 24
Finished Jan 17 01:34:41 PM PST 24
Peak memory 248048 kb
Host smart-2daf2b10-1e00-4dac-bf06-e09f7d6a71e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023220165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.3023220165
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.387333242
Short name T315
Test name
Test status
Simulation time 39837858 ps
CPU time 0.56 seconds
Started Jan 17 12:50:39 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 193128 kb
Host smart-44b7ac36-28c4-4e38-aa54-17d6cc27f38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387333242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.387333242
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2537959972
Short name T479
Test name
Test status
Simulation time 2577511183 ps
CPU time 21.73 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:50:50 PM PST 24
Peak memory 215188 kb
Host smart-104833ea-4621-471e-9924-94ef71187ae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537959972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2537959972
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3027770932
Short name T290
Test name
Test status
Simulation time 2359124601 ps
CPU time 32.65 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 12:51:01 PM PST 24
Peak memory 198772 kb
Host smart-5f7ae4d2-615f-41f1-b528-9197e057a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027770932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3027770932
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1469672006
Short name T211
Test name
Test status
Simulation time 1949328271 ps
CPU time 26.16 seconds
Started Jan 17 12:50:39 PM PST 24
Finished Jan 17 12:51:08 PM PST 24
Peak memory 198744 kb
Host smart-aef3307b-6196-4ce0-8e0e-30c52a9b69f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469672006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1469672006
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1845294032
Short name T379
Test name
Test status
Simulation time 1483187992 ps
CPU time 72.62 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 198632 kb
Host smart-0dc0f217-b6bf-4318-850d-a09385da66d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845294032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1845294032
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3033120650
Short name T648
Test name
Test status
Simulation time 1620419657 ps
CPU time 82.05 seconds
Started Jan 17 12:50:36 PM PST 24
Finished Jan 17 12:52:00 PM PST 24
Peak memory 198768 kb
Host smart-c77f6ea8-999b-4090-a30b-23ac278ad0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033120650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3033120650
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.816576761
Short name T273
Test name
Test status
Simulation time 552189231 ps
CPU time 3.15 seconds
Started Jan 17 12:50:30 PM PST 24
Finished Jan 17 12:50:34 PM PST 24
Peak memory 198576 kb
Host smart-1b985b23-0599-4c32-ab2e-05f8ada57a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816576761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.816576761
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.890339692
Short name T456
Test name
Test status
Simulation time 521923477847 ps
CPU time 2061.3 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 01:24:54 PM PST 24
Peak memory 198988 kb
Host smart-dffa713d-b319-4d8d-aa67-3c77f4012f96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890339692 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.890339692
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1170367254
Short name T626
Test name
Test status
Simulation time 49680352858 ps
CPU time 979.84 seconds
Started Jan 17 12:50:27 PM PST 24
Finished Jan 17 01:06:48 PM PST 24
Peak memory 231688 kb
Host smart-f4e32bf6-76e4-47f2-b1a0-7c4c67b8666b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170367254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1170367254
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1473694109
Short name T733
Test name
Test status
Simulation time 50038880 ps
CPU time 0.94 seconds
Started Jan 17 12:50:33 PM PST 24
Finished Jan 17 12:50:35 PM PST 24
Peak memory 196424 kb
Host smart-d0061308-490c-4db2-afc6-5a240e60aac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473694109 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1473694109
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2828493220
Short name T413
Test name
Test status
Simulation time 39737277465 ps
CPU time 415.86 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:57:27 PM PST 24
Peak memory 198744 kb
Host smart-db73c677-0cf6-450c-8afb-b7fc6706ecb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828493220 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.2828493220
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2456623623
Short name T724
Test name
Test status
Simulation time 22256106457 ps
CPU time 89.03 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:52:02 PM PST 24
Peak memory 198984 kb
Host smart-f77ed201-3a9b-4409-93d3-103b9784d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456623623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2456623623
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3190160235
Short name T588
Test name
Test status
Simulation time 183074375792 ps
CPU time 1406.13 seconds
Started Jan 17 12:52:44 PM PST 24
Finished Jan 17 01:16:11 PM PST 24
Peak memory 252976 kb
Host smart-d81f0fee-28c0-491b-ba96-5655f887e29f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190160235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.3190160235
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.223726066
Short name T687
Test name
Test status
Simulation time 77004678690 ps
CPU time 1074.18 seconds
Started Jan 17 12:52:39 PM PST 24
Finished Jan 17 01:10:35 PM PST 24
Peak memory 244020 kb
Host smart-310cea01-24dd-40a0-9168-d4eecc657c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223726066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.223726066
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.3777361459
Short name T802
Test name
Test status
Simulation time 28105673432 ps
CPU time 361.58 seconds
Started Jan 17 12:52:43 PM PST 24
Finished Jan 17 12:58:46 PM PST 24
Peak memory 207064 kb
Host smart-2e836a78-d3de-4488-9486-1cf79547f800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777361459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.3777361459
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.3843829529
Short name T451
Test name
Test status
Simulation time 567820406959 ps
CPU time 3695.04 seconds
Started Jan 17 12:52:45 PM PST 24
Finished Jan 17 01:54:21 PM PST 24
Peak memory 264428 kb
Host smart-862c60ab-8257-4641-b3e6-6ac5ba99a46f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843829529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.3843829529
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.1018836408
Short name T279
Test name
Test status
Simulation time 108950766963 ps
CPU time 1037.81 seconds
Started Jan 17 12:52:41 PM PST 24
Finished Jan 17 01:10:00 PM PST 24
Peak memory 231688 kb
Host smart-c8cf66a7-68f7-4726-b087-f29e0c098a31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018836408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.1018836408
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.1240154480
Short name T2
Test name
Test status
Simulation time 6587470547 ps
CPU time 128.51 seconds
Started Jan 17 12:52:42 PM PST 24
Finished Jan 17 12:54:52 PM PST 24
Peak memory 214624 kb
Host smart-9652ef0f-272b-4b6d-8374-c60dd2b060b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240154480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.1240154480
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.4093147303
Short name T657
Test name
Test status
Simulation time 710453570819 ps
CPU time 882 seconds
Started Jan 17 12:52:44 PM PST 24
Finished Jan 17 01:07:27 PM PST 24
Peak memory 247748 kb
Host smart-863e96bd-0fe6-4453-9f58-9594c3d2f90a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093147303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.4093147303
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3408231750
Short name T422
Test name
Test status
Simulation time 647375252451 ps
CPU time 1150.15 seconds
Started Jan 17 12:52:46 PM PST 24
Finished Jan 17 01:11:57 PM PST 24
Peak memory 223460 kb
Host smart-5d0150b7-4ed6-4366-9310-39ed11e19f66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408231750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3408231750
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.865968478
Short name T705
Test name
Test status
Simulation time 42964534 ps
CPU time 0.58 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:50:09 PM PST 24
Peak memory 193004 kb
Host smart-bb1f5198-f035-40af-8890-06fe0ff062dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865968478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.865968478
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.227335341
Short name T42
Test name
Test status
Simulation time 547451415 ps
CPU time 7.74 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:18 PM PST 24
Peak memory 214468 kb
Host smart-e7a0a5a3-9863-440e-8195-e27019b32a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227335341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.227335341
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3992281030
Short name T277
Test name
Test status
Simulation time 3152469935 ps
CPU time 42.32 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 198760 kb
Host smart-f11cc52b-a685-4e57-b223-51534b46dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992281030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3992281030
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1589838849
Short name T232
Test name
Test status
Simulation time 4711417236 ps
CPU time 57.97 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:51:09 PM PST 24
Peak memory 198816 kb
Host smart-ce3e780a-7eb6-48a6-a553-91b43cc329f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589838849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1589838849
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2876959295
Short name T630
Test name
Test status
Simulation time 18677466131 ps
CPU time 114.92 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 198764 kb
Host smart-1084ffd3-dbc5-44b4-b508-c8301903905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876959295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2876959295
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3889089848
Short name T828
Test name
Test status
Simulation time 9619495859 ps
CPU time 121.86 seconds
Started Jan 17 12:50:04 PM PST 24
Finished Jan 17 12:52:11 PM PST 24
Peak memory 198668 kb
Host smart-53a0a4e4-f842-42ce-ba29-2b25e8ee837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889089848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3889089848
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.465388304
Short name T50
Test name
Test status
Simulation time 217513104 ps
CPU time 0.9 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:23 PM PST 24
Peak memory 215984 kb
Host smart-19a7598b-a28e-4d5e-8fc3-5c814ff20956
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465388304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.465388304
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2695915657
Short name T562
Test name
Test status
Simulation time 21287824 ps
CPU time 0.83 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:21 PM PST 24
Peak memory 195068 kb
Host smart-1f96830c-87ca-4419-80cc-a264dd2533bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695915657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2695915657
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.637435417
Short name T200
Test name
Test status
Simulation time 7499712829 ps
CPU time 92.46 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198772 kb
Host smart-618ba12d-c635-4458-b72a-18e9c184af06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637435417 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.637435417
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.366554718
Short name T823
Test name
Test status
Simulation time 95344211594 ps
CPU time 1393.48 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 01:13:24 PM PST 24
Peak memory 240888 kb
Host smart-5048f0ff-c762-4e9a-ac4f-dd7698503daa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366554718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.366554718
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1588278555
Short name T312
Test name
Test status
Simulation time 77904726 ps
CPU time 1.14 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 197232 kb
Host smart-af86ac9b-aeac-4d11-9387-5259c9ca0d3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588278555 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1588278555
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2691952150
Short name T356
Test name
Test status
Simulation time 37213366986 ps
CPU time 417.07 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:57:22 PM PST 24
Peak memory 198696 kb
Host smart-48eef64c-f487-4820-9c78-92889942be12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691952150 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.2691952150
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1875498135
Short name T784
Test name
Test status
Simulation time 5879958023 ps
CPU time 40.94 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:51 PM PST 24
Peak memory 198772 kb
Host smart-ad9ae69a-0d03-4ef8-9f61-31b201f92f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875498135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1875498135
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.931435923
Short name T236
Test name
Test status
Simulation time 25140394 ps
CPU time 0.56 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 193120 kb
Host smart-7c35ec7c-1a82-4d37-b892-39b73a7e4541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931435923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.931435923
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1587032376
Short name T440
Test name
Test status
Simulation time 3340751667 ps
CPU time 26.99 seconds
Started Jan 17 12:50:29 PM PST 24
Finished Jan 17 12:50:57 PM PST 24
Peak memory 223440 kb
Host smart-c5ca407f-ff0a-4580-86fe-5f9c2f2250ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587032376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1587032376
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3522931845
Short name T202
Test name
Test status
Simulation time 5156881383 ps
CPU time 63.02 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 198844 kb
Host smart-b5b89632-6d9a-4179-aecf-357a6dc547d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522931845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3522931845
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.217889198
Short name T531
Test name
Test status
Simulation time 2522221797 ps
CPU time 131.66 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 198748 kb
Host smart-8e0d39e9-3911-4833-a613-a588eed98e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217889198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.217889198
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2920708940
Short name T573
Test name
Test status
Simulation time 7979704066 ps
CPU time 157.51 seconds
Started Jan 17 12:50:38 PM PST 24
Finished Jan 17 12:53:19 PM PST 24
Peak memory 198756 kb
Host smart-b9110be0-69ed-4c06-a9c6-f5e1f78345db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920708940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2920708940
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3861766335
Short name T736
Test name
Test status
Simulation time 918449162 ps
CPU time 30.34 seconds
Started Jan 17 12:50:39 PM PST 24
Finished Jan 17 12:51:12 PM PST 24
Peak memory 198720 kb
Host smart-c2b3638a-11b0-421c-8652-fbb145142039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861766335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3861766335
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3011197572
Short name T798
Test name
Test status
Simulation time 267684031 ps
CPU time 1.86 seconds
Started Jan 17 12:50:39 PM PST 24
Finished Jan 17 12:50:44 PM PST 24
Peak memory 198748 kb
Host smart-c78f9aaf-fdd9-4146-8678-67cd35881539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011197572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3011197572
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3186236769
Short name T726
Test name
Test status
Simulation time 8371194873 ps
CPU time 395.2 seconds
Started Jan 17 12:50:43 PM PST 24
Finished Jan 17 12:57:19 PM PST 24
Peak memory 198872 kb
Host smart-22bc77cd-b682-40b5-aa29-7f8bdf46bc52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186236769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3186236769
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3061121271
Short name T119
Test name
Test status
Simulation time 143523373111 ps
CPU time 3500.32 seconds
Started Jan 17 12:50:43 PM PST 24
Finished Jan 17 01:49:04 PM PST 24
Peak memory 251344 kb
Host smart-bcdb77f0-3061-40f2-bf78-5b600c2b306b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061121271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.3061121271
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3206953644
Short name T303
Test name
Test status
Simulation time 203805343 ps
CPU time 1.24 seconds
Started Jan 17 12:50:28 PM PST 24
Finished Jan 17 12:50:30 PM PST 24
Peak memory 196420 kb
Host smart-38855800-33b2-45de-90c4-759a9ffa4b64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206953644 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3206953644
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3423816304
Short name T57
Test name
Test status
Simulation time 92105917894 ps
CPU time 385.88 seconds
Started Jan 17 12:50:37 PM PST 24
Finished Jan 17 12:57:05 PM PST 24
Peak memory 198756 kb
Host smart-e3f99a18-7232-41bc-a3ec-565e96bba1c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423816304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3423816304
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.883805440
Short name T476
Test name
Test status
Simulation time 1628640897 ps
CPU time 51.88 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:51:24 PM PST 24
Peak memory 198812 kb
Host smart-4d20a93a-5ee2-43ce-8824-75981a272c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883805440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.883805440
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1619188495
Short name T227
Test name
Test status
Simulation time 37792313 ps
CPU time 0.59 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 193096 kb
Host smart-e637b7d2-3ed6-4f90-a33a-c6340dec9017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619188495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1619188495
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3821884553
Short name T448
Test name
Test status
Simulation time 988850506 ps
CPU time 27.57 seconds
Started Jan 17 12:50:42 PM PST 24
Finished Jan 17 12:51:11 PM PST 24
Peak memory 198648 kb
Host smart-b2cc78f0-866f-4d70-ab0c-426cda1f33fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821884553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3821884553
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1694433524
Short name T97
Test name
Test status
Simulation time 8802272468 ps
CPU time 37.78 seconds
Started Jan 17 12:50:47 PM PST 24
Finished Jan 17 12:51:25 PM PST 24
Peak memory 198828 kb
Host smart-6715cb02-304e-41b2-b261-9ba7fb3e2b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694433524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1694433524
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3908949919
Short name T11
Test name
Test status
Simulation time 1260686572 ps
CPU time 47.87 seconds
Started Jan 17 12:50:41 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 198700 kb
Host smart-aa3a0d70-b81e-421f-ba4c-93d05e88ce41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908949919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3908949919
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1401003666
Short name T528
Test name
Test status
Simulation time 11254008186 ps
CPU time 89.07 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:52:34 PM PST 24
Peak memory 198828 kb
Host smart-739b8398-09cb-453e-af32-b3f1d37d5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401003666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1401003666
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1254439701
Short name T380
Test name
Test status
Simulation time 2191823006 ps
CPU time 39.9 seconds
Started Jan 17 12:50:47 PM PST 24
Finished Jan 17 12:51:28 PM PST 24
Peak memory 198772 kb
Host smart-d15f2354-d2b7-4da0-9108-dfd7dc6c13ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254439701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1254439701
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.183306561
Short name T611
Test name
Test status
Simulation time 283562378 ps
CPU time 2.97 seconds
Started Jan 17 12:50:48 PM PST 24
Finished Jan 17 12:50:52 PM PST 24
Peak memory 198732 kb
Host smart-bb3d303d-7c77-4840-9240-443488978d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183306561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.183306561
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3952061830
Short name T769
Test name
Test status
Simulation time 19628721120 ps
CPU time 110.3 seconds
Started Jan 17 12:50:45 PM PST 24
Finished Jan 17 12:52:36 PM PST 24
Peak memory 223412 kb
Host smart-0838f3da-955b-430e-87e5-9b5ce93a772d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952061830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3952061830
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.1864565297
Short name T590
Test name
Test status
Simulation time 134368177047 ps
CPU time 581.99 seconds
Started Jan 17 12:50:47 PM PST 24
Finished Jan 17 01:00:30 PM PST 24
Peak memory 215308 kb
Host smart-9b7879ac-b09f-4afe-9f3b-5527bf40b3d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864565297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.1864565297
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1253691324
Short name T758
Test name
Test status
Simulation time 79881439 ps
CPU time 0.9 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:50:51 PM PST 24
Peak memory 195776 kb
Host smart-fa3acc9f-5984-4d5a-8125-75ad566e7d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253691324 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1253691324
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1936819770
Short name T575
Test name
Test status
Simulation time 13581626930 ps
CPU time 344.81 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:56:39 PM PST 24
Peak memory 198620 kb
Host smart-3a159ba3-d37b-4050-94cb-0131fdc393b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936819770 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.1936819770
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.159040874
Short name T337
Test name
Test status
Simulation time 1710482834 ps
CPU time 33.23 seconds
Started Jan 17 12:50:46 PM PST 24
Finished Jan 17 12:51:19 PM PST 24
Peak memory 198804 kb
Host smart-d36bc696-abc7-4329-a912-cde042642454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159040874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.159040874
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1515489036
Short name T220
Test name
Test status
Simulation time 31571279 ps
CPU time 0.57 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:50:54 PM PST 24
Peak memory 193292 kb
Host smart-2bd1618c-e310-4b0a-afdd-5c2b762e787e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515489036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1515489036
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2893884315
Short name T197
Test name
Test status
Simulation time 1168792525 ps
CPU time 42.22 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 228440 kb
Host smart-fa2a048a-47e8-4633-8b14-77df3e43ca81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893884315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2893884315
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2841745912
Short name T776
Test name
Test status
Simulation time 1231132586 ps
CPU time 18.76 seconds
Started Jan 17 12:50:46 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 198716 kb
Host smart-b0296022-c789-4d45-bc1a-f37a0d3c5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841745912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2841745912
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1881606940
Short name T786
Test name
Test status
Simulation time 2261483602 ps
CPU time 118.3 seconds
Started Jan 17 12:50:48 PM PST 24
Finished Jan 17 12:52:47 PM PST 24
Peak memory 198800 kb
Host smart-84986bed-4e5e-4b24-8866-0269a4ae09bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881606940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1881606940
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2181517250
Short name T212
Test name
Test status
Simulation time 2525714100 ps
CPU time 121.41 seconds
Started Jan 17 12:50:48 PM PST 24
Finished Jan 17 12:52:51 PM PST 24
Peak memory 198828 kb
Host smart-b1dfdf55-99d0-40d3-87c8-ea291fddd001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181517250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2181517250
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2359318312
Short name T681
Test name
Test status
Simulation time 29291303037 ps
CPU time 73.73 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 198748 kb
Host smart-9b52d78c-73f8-4b68-82e6-c2eb5e83921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359318312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2359318312
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3176564756
Short name T1
Test name
Test status
Simulation time 214858705 ps
CPU time 1.67 seconds
Started Jan 17 12:50:53 PM PST 24
Finished Jan 17 12:50:56 PM PST 24
Peak memory 198636 kb
Host smart-0a3ecf6d-a2b5-4bb1-8bb4-3b69a0998198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176564756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3176564756
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4125771966
Short name T670
Test name
Test status
Simulation time 49933084540 ps
CPU time 1200.46 seconds
Started Jan 17 12:50:48 PM PST 24
Finished Jan 17 01:10:50 PM PST 24
Peak memory 224296 kb
Host smart-ce058d01-6cb3-40d8-9a13-f599bc65aa3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125771966 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4125771966
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.273938619
Short name T521
Test name
Test status
Simulation time 70920773843 ps
CPU time 2975.81 seconds
Started Jan 17 12:50:47 PM PST 24
Finished Jan 17 01:40:24 PM PST 24
Peak memory 255648 kb
Host smart-73d49bd9-84ae-42f8-8289-f7bbf7e6b45d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273938619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.273938619
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2288870408
Short name T580
Test name
Test status
Simulation time 81082076 ps
CPU time 1.07 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 195972 kb
Host smart-40b3225c-2397-4151-a970-b904932d2e29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288870408 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2288870408
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1835497118
Short name T520
Test name
Test status
Simulation time 51155061719 ps
CPU time 369.46 seconds
Started Jan 17 12:50:47 PM PST 24
Finished Jan 17 12:56:57 PM PST 24
Peak memory 198768 kb
Host smart-c697d049-c216-4a4e-8430-34c9c6a7087e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835497118 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.1835497118
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2787813963
Short name T307
Test name
Test status
Simulation time 209601035 ps
CPU time 3.38 seconds
Started Jan 17 12:50:54 PM PST 24
Finished Jan 17 12:50:59 PM PST 24
Peak memory 198724 kb
Host smart-64891029-45a9-4333-ba3f-91375d22e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787813963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2787813963
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2675652541
Short name T501
Test name
Test status
Simulation time 32754858 ps
CPU time 0.55 seconds
Started Jan 17 12:50:59 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 193136 kb
Host smart-07ece088-9335-4c49-af60-6ea03a5b6933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675652541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2675652541
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3447263818
Short name T486
Test name
Test status
Simulation time 1386612045 ps
CPU time 43.15 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 217124 kb
Host smart-0bf235a0-45fb-463f-b67a-1dd84f1fbbf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447263818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3447263818
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3860087932
Short name T191
Test name
Test status
Simulation time 1616979485 ps
CPU time 39.03 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:51:29 PM PST 24
Peak memory 198740 kb
Host smart-a124b673-f6f3-4e2b-930b-096e1f12f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860087932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3860087932
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2163774631
Short name T719
Test name
Test status
Simulation time 522019699 ps
CPU time 27.94 seconds
Started Jan 17 12:50:58 PM PST 24
Finished Jan 17 12:51:32 PM PST 24
Peak memory 198704 kb
Host smart-2b2d3e86-27a7-4b3a-b9ae-5a4bb1f9669d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163774631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2163774631
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1034197018
Short name T587
Test name
Test status
Simulation time 12717071653 ps
CPU time 100.32 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:52:30 PM PST 24
Peak memory 198772 kb
Host smart-8426995c-bbbb-430c-b6c1-97290953210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034197018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1034197018
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1549154553
Short name T752
Test name
Test status
Simulation time 4238081324 ps
CPU time 18.27 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:51:11 PM PST 24
Peak memory 198748 kb
Host smart-8016faf3-c73a-4b8f-bb56-f32274040c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549154553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1549154553
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3372268402
Short name T465
Test name
Test status
Simulation time 112449892 ps
CPU time 3.07 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 198712 kb
Host smart-094e1f83-bffd-4e39-be2c-209b50f665b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372268402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3372268402
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1362731284
Short name T248
Test name
Test status
Simulation time 98493185637 ps
CPU time 1502.57 seconds
Started Jan 17 12:50:50 PM PST 24
Finished Jan 17 01:15:53 PM PST 24
Peak memory 219292 kb
Host smart-41ac1d7f-04ea-4f71-8ebf-5d6fc94fb862
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362731284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1362731284
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.3957496360
Short name T375
Test name
Test status
Simulation time 4937099009 ps
CPU time 119.21 seconds
Started Jan 17 12:50:59 PM PST 24
Finished Jan 17 12:53:03 PM PST 24
Peak memory 242416 kb
Host smart-32c6a9de-e383-4d96-bd0f-c3277e34a21c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957496360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.3957496360
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2825505753
Short name T186
Test name
Test status
Simulation time 28721660 ps
CPU time 0.96 seconds
Started Jan 17 12:50:58 PM PST 24
Finished Jan 17 12:51:05 PM PST 24
Peak memory 196968 kb
Host smart-93e7e297-85c0-4fad-8aae-a2ffd6d80e05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825505753 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2825505753
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1189921161
Short name T745
Test name
Test status
Simulation time 116853774731 ps
CPU time 358.16 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:57:02 PM PST 24
Peak memory 198708 kb
Host smart-5376acb2-3f1f-4439-8945-c1f61fcda754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189921161 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.1189921161
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2299831268
Short name T427
Test name
Test status
Simulation time 5983884242 ps
CPU time 76.44 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 198788 kb
Host smart-3df4083d-78b3-486c-9446-b3b4ed406b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299831268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2299831268
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2886915631
Short name T577
Test name
Test status
Simulation time 12356216 ps
CPU time 0.57 seconds
Started Jan 17 12:51:05 PM PST 24
Finished Jan 17 12:51:15 PM PST 24
Peak memory 193096 kb
Host smart-7d539c6b-cde1-45c3-84fe-314781efadee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886915631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2886915631
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1939939694
Short name T504
Test name
Test status
Simulation time 5782633113 ps
CPU time 48.74 seconds
Started Jan 17 12:50:49 PM PST 24
Finished Jan 17 12:51:39 PM PST 24
Peak memory 223428 kb
Host smart-c10cf396-3b23-4f0b-98bd-073cd911f852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939939694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1939939694
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2583477085
Short name T551
Test name
Test status
Simulation time 454579119 ps
CPU time 4.65 seconds
Started Jan 17 12:50:53 PM PST 24
Finished Jan 17 12:50:59 PM PST 24
Peak memory 198728 kb
Host smart-5c6d21da-6c10-417b-b63b-721897367441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583477085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2583477085
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3356378327
Short name T539
Test name
Test status
Simulation time 1445661026 ps
CPU time 73.3 seconds
Started Jan 17 12:50:50 PM PST 24
Finished Jan 17 12:52:04 PM PST 24
Peak memory 198764 kb
Host smart-fe1a89c6-7a90-44be-a68d-2e12172044d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356378327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3356378327
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1732052512
Short name T470
Test name
Test status
Simulation time 25660311103 ps
CPU time 69.68 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:52:14 PM PST 24
Peak memory 198792 kb
Host smart-75900fd1-f7ff-4bc4-901b-3379e1609ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732052512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1732052512
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.952307233
Short name T808
Test name
Test status
Simulation time 1243398632 ps
CPU time 64.92 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198712 kb
Host smart-c0078311-41ea-4dd0-beae-2ad82e88faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952307233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.952307233
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1811804784
Short name T540
Test name
Test status
Simulation time 946679291 ps
CPU time 3.33 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:51:08 PM PST 24
Peak memory 198784 kb
Host smart-dfa3e809-fc7a-4e22-80ff-87862a8fab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811804784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1811804784
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3629806985
Short name T287
Test name
Test status
Simulation time 56014426482 ps
CPU time 511.91 seconds
Started Jan 17 12:50:53 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 198796 kb
Host smart-72b0a808-e73b-4d66-a4f2-f42d8bc0b72d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629806985 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3629806985
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.1436897377
Short name T764
Test name
Test status
Simulation time 76946688076 ps
CPU time 1411.75 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 01:14:25 PM PST 24
Peak memory 233276 kb
Host smart-c41ddc9e-b361-4c32-8700-e098db7b9a73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436897377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.1436897377
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1522226382
Short name T496
Test name
Test status
Simulation time 26465245 ps
CPU time 0.89 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 196564 kb
Host smart-6ffcfcbf-6071-45c1-8251-a146590470ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522226382 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1522226382
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1328806244
Short name T455
Test name
Test status
Simulation time 27955672998 ps
CPU time 348.5 seconds
Started Jan 17 12:50:53 PM PST 24
Finished Jan 17 12:56:43 PM PST 24
Peak memory 198784 kb
Host smart-f5cf6e19-c76f-4ac1-b26d-c53adbf67ded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328806244 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.1328806244
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3674736529
Short name T317
Test name
Test status
Simulation time 3976714397 ps
CPU time 47.86 seconds
Started Jan 17 12:51:00 PM PST 24
Finished Jan 17 12:51:52 PM PST 24
Peak memory 198876 kb
Host smart-ddab2ddd-0b49-4696-844c-c92bf403ab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674736529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3674736529
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2697731813
Short name T291
Test name
Test status
Simulation time 31436705 ps
CPU time 0.56 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:50:54 PM PST 24
Peak memory 193108 kb
Host smart-fec6e92b-42ed-4659-abd1-64e16a9c818b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697731813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2697731813
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1420785494
Short name T689
Test name
Test status
Simulation time 6289716507 ps
CPU time 58.23 seconds
Started Jan 17 12:50:50 PM PST 24
Finished Jan 17 12:51:49 PM PST 24
Peak memory 229876 kb
Host smart-9bdd293a-ae85-4090-9a53-211995b21e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420785494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1420785494
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3084048124
Short name T329
Test name
Test status
Simulation time 5707081921 ps
CPU time 65.28 seconds
Started Jan 17 12:50:50 PM PST 24
Finished Jan 17 12:51:56 PM PST 24
Peak memory 198772 kb
Host smart-ea1cfca9-d622-4018-917b-a47ac187fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084048124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3084048124
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2364320119
Short name T625
Test name
Test status
Simulation time 1163151951 ps
CPU time 61.19 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 198712 kb
Host smart-5297c626-79f2-4af5-858a-59064566a2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364320119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2364320119
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1359322564
Short name T342
Test name
Test status
Simulation time 14029885572 ps
CPU time 178.28 seconds
Started Jan 17 12:50:53 PM PST 24
Finished Jan 17 12:53:52 PM PST 24
Peak memory 198820 kb
Host smart-89ac91af-0dc9-4836-a225-e8ae47b47ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359322564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1359322564
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1357164794
Short name T32
Test name
Test status
Simulation time 11013785986 ps
CPU time 76.65 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:52:22 PM PST 24
Peak memory 198788 kb
Host smart-34488966-f861-48a6-9c4b-0620afacb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357164794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1357164794
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2003391989
Short name T471
Test name
Test status
Simulation time 99564637 ps
CPU time 0.89 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 196672 kb
Host smart-7d522a35-c373-4018-a27d-0657710c3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003391989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2003391989
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2610051838
Short name T431
Test name
Test status
Simulation time 4910716334 ps
CPU time 180.25 seconds
Started Jan 17 12:50:50 PM PST 24
Finished Jan 17 12:53:51 PM PST 24
Peak memory 198688 kb
Host smart-5c3c3407-38f3-4ee5-ab33-e233a204e6b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610051838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2610051838
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.32693497
Short name T631
Test name
Test status
Simulation time 101190983638 ps
CPU time 1380.13 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 01:14:13 PM PST 24
Peak memory 230236 kb
Host smart-57b65145-db5d-43a7-997f-a286018274c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32693497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.32693497
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3069896325
Short name T780
Test name
Test status
Simulation time 169039605 ps
CPU time 1.23 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:50:55 PM PST 24
Peak memory 197564 kb
Host smart-95dbcf47-7fe1-405f-8a04-6c5f4be5896a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069896325 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3069896325
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.465671549
Short name T252
Test name
Test status
Simulation time 8452378090 ps
CPU time 392.69 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:57:26 PM PST 24
Peak memory 198728 kb
Host smart-35a0edbd-3e85-4221-ae92-6a5e5305e29e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465671549 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_sha_vectors.465671549
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.873294868
Short name T703
Test name
Test status
Simulation time 6332355527 ps
CPU time 42.13 seconds
Started Jan 17 12:50:51 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 198752 kb
Host smart-04e274d9-75ec-4f50-8a33-2722a0d40d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873294868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.873294868
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1589071753
Short name T445
Test name
Test status
Simulation time 82403971 ps
CPU time 0.61 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:51:03 PM PST 24
Peak memory 194148 kb
Host smart-221a6dea-2f51-4c8b-a56d-c805f2ca5476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589071753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1589071753
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3390611778
Short name T777
Test name
Test status
Simulation time 2826876638 ps
CPU time 31.37 seconds
Started Jan 17 12:51:05 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 207032 kb
Host smart-f65b1f1a-40f3-46f8-8036-6067c0e2602f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390611778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3390611778
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.599028850
Short name T801
Test name
Test status
Simulation time 14499442798 ps
CPU time 16.22 seconds
Started Jan 17 12:50:59 PM PST 24
Finished Jan 17 12:51:20 PM PST 24
Peak memory 198812 kb
Host smart-4e7b8830-69bf-48c3-9dd0-d91260b1e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599028850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.599028850
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2586009509
Short name T198
Test name
Test status
Simulation time 5201721371 ps
CPU time 65.61 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:52:10 PM PST 24
Peak memory 198828 kb
Host smart-7e0b1826-6a45-414b-9842-1dc65ea51bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586009509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2586009509
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.493880275
Short name T228
Test name
Test status
Simulation time 12150714547 ps
CPU time 50.47 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:51:54 PM PST 24
Peak memory 198740 kb
Host smart-d46a346e-ecc1-4f30-828d-9226327cdecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493880275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.493880275
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3934270606
Short name T194
Test name
Test status
Simulation time 24603496235 ps
CPU time 107.7 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:52:53 PM PST 24
Peak memory 198824 kb
Host smart-083af0c1-be69-49c6-9df1-8011abab6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934270606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3934270606
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4118039357
Short name T452
Test name
Test status
Simulation time 730714255 ps
CPU time 3.78 seconds
Started Jan 17 12:50:52 PM PST 24
Finished Jan 17 12:50:57 PM PST 24
Peak memory 198500 kb
Host smart-4ac0fc65-d252-4236-9561-ceea74e36831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118039357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4118039357
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1247554400
Short name T120
Test name
Test status
Simulation time 7561910215 ps
CPU time 125.05 seconds
Started Jan 17 12:51:07 PM PST 24
Finished Jan 17 12:53:20 PM PST 24
Peak memory 214788 kb
Host smart-76e237b4-c20d-4d71-807e-c311fbfae75a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247554400 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1247554400
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.206264165
Short name T661
Test name
Test status
Simulation time 67290910462 ps
CPU time 1192.82 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 01:10:56 PM PST 24
Peak memory 231696 kb
Host smart-666b0ff1-75a3-4da1-9670-04d3457085f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206264165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.206264165
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.151921306
Short name T403
Test name
Test status
Simulation time 258233656 ps
CPU time 1.13 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 197060 kb
Host smart-82f75e34-3366-4ac7-bd63-073e34429853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151921306 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.151921306
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2371551081
Short name T409
Test name
Test status
Simulation time 26772145874 ps
CPU time 332.04 seconds
Started Jan 17 12:51:07 PM PST 24
Finished Jan 17 12:56:47 PM PST 24
Peak memory 198700 kb
Host smart-9fa64e20-edb1-4997-ac33-2331c98b8dcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371551081 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2371551081
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3629686315
Short name T759
Test name
Test status
Simulation time 14812162644 ps
CPU time 40.7 seconds
Started Jan 17 12:50:56 PM PST 24
Finished Jan 17 12:51:41 PM PST 24
Peak memory 198736 kb
Host smart-0d76eed3-2b95-4b51-9317-8717fe4f4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629686315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3629686315
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2629189225
Short name T39
Test name
Test status
Simulation time 31211778 ps
CPU time 0.57 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 193120 kb
Host smart-e92b7373-2959-436e-a860-e5872f8ae162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629189225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2629189225
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4182307612
Short name T494
Test name
Test status
Simulation time 184183907 ps
CPU time 5.56 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:10 PM PST 24
Peak memory 198756 kb
Host smart-93d742f7-c438-4921-a392-ccc326cdbae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182307612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4182307612
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2316236797
Short name T361
Test name
Test status
Simulation time 3737311042 ps
CPU time 35.2 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:40 PM PST 24
Peak memory 198776 kb
Host smart-638b8aa9-da55-4b16-a8c6-369114cc36af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316236797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2316236797
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2957144231
Short name T793
Test name
Test status
Simulation time 18128240644 ps
CPU time 124.49 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:53:07 PM PST 24
Peak memory 198844 kb
Host smart-0b04a813-7ceb-44b4-bac5-40fcca050b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957144231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2957144231
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1176311218
Short name T596
Test name
Test status
Simulation time 4001913334 ps
CPU time 98.85 seconds
Started Jan 17 12:50:59 PM PST 24
Finished Jan 17 12:52:43 PM PST 24
Peak memory 198844 kb
Host smart-c49f4643-fb13-43ea-8014-fd687c14e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176311218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1176311218
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.309031451
Short name T560
Test name
Test status
Simulation time 20503843132 ps
CPU time 90.17 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:52:35 PM PST 24
Peak memory 198696 kb
Host smart-43e65dac-f3f6-4ce0-ac86-fbc4d273ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309031451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.309031451
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3819854636
Short name T343
Test name
Test status
Simulation time 870544487 ps
CPU time 1.61 seconds
Started Jan 17 12:50:56 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198808 kb
Host smart-11b11e86-a862-49a7-a807-86fc5ff0a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819854636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3819854636
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3253845939
Short name T772
Test name
Test status
Simulation time 59952028569 ps
CPU time 523.13 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:59:48 PM PST 24
Peak memory 226272 kb
Host smart-ef792f8d-8708-43f0-967b-818b8c955495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253845939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3253845939
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.1706738167
Short name T585
Test name
Test status
Simulation time 14612179306 ps
CPU time 141.34 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:53:26 PM PST 24
Peak memory 207120 kb
Host smart-0cc391b5-a877-45fc-9cb9-2e97258ade42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706738167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.1706738167
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.419518259
Short name T525
Test name
Test status
Simulation time 26487221 ps
CPU time 0.91 seconds
Started Jan 17 12:51:14 PM PST 24
Finished Jan 17 12:51:16 PM PST 24
Peak memory 196640 kb
Host smart-a4e485d3-444d-4171-809b-d394d4ce77df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419518259 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.419518259
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2202348230
Short name T253
Test name
Test status
Simulation time 163681551014 ps
CPU time 435.32 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:58:20 PM PST 24
Peak memory 198644 kb
Host smart-4b493c7e-cfb3-44bf-9eb9-c613ab518c78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202348230 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.2202348230
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1608230476
Short name T737
Test name
Test status
Simulation time 1361380962 ps
CPU time 23.8 seconds
Started Jan 17 12:50:58 PM PST 24
Finished Jan 17 12:51:28 PM PST 24
Peak memory 198628 kb
Host smart-8cf72595-502d-4530-be1d-9378fba405c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608230476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1608230476
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.358098947
Short name T663
Test name
Test status
Simulation time 47207049 ps
CPU time 0.58 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 193064 kb
Host smart-7d87a14c-7667-453e-a146-6325a71a08b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358098947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.358098947
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1784299153
Short name T762
Test name
Test status
Simulation time 4427436086 ps
CPU time 36.08 seconds
Started Jan 17 12:51:10 PM PST 24
Finished Jan 17 12:51:51 PM PST 24
Peak memory 215176 kb
Host smart-d0674358-b948-4714-9b30-849c3caeaeff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784299153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1784299153
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3062150105
Short name T446
Test name
Test status
Simulation time 12697756179 ps
CPU time 46.87 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:52 PM PST 24
Peak memory 198812 kb
Host smart-29b35964-9b04-4c2d-819b-8e88d552a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062150105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3062150105
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3218547407
Short name T558
Test name
Test status
Simulation time 1630974694 ps
CPU time 80.5 seconds
Started Jan 17 12:51:10 PM PST 24
Finished Jan 17 12:52:35 PM PST 24
Peak memory 198780 kb
Host smart-e8efb255-3899-47a0-bce7-1b1f632a12ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218547407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3218547407
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2071308584
Short name T629
Test name
Test status
Simulation time 2078205238 ps
CPU time 103.01 seconds
Started Jan 17 12:51:08 PM PST 24
Finished Jan 17 12:52:58 PM PST 24
Peak memory 198612 kb
Host smart-3569e53e-063f-4458-8b93-5d56b715ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071308584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2071308584
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3781969585
Short name T418
Test name
Test status
Simulation time 1568943120 ps
CPU time 15.21 seconds
Started Jan 17 12:51:01 PM PST 24
Finished Jan 17 12:51:20 PM PST 24
Peak memory 198632 kb
Host smart-892a80f0-2506-4509-b1c3-853087fa9697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781969585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3781969585
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3951962463
Short name T662
Test name
Test status
Simulation time 175045570 ps
CPU time 2.23 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:07 PM PST 24
Peak memory 198708 kb
Host smart-df9a711c-b8ec-4893-bae9-b2559dd002af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951962463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3951962463
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2941248774
Short name T572
Test name
Test status
Simulation time 144680641766 ps
CPU time 1852.64 seconds
Started Jan 17 12:51:14 PM PST 24
Finished Jan 17 01:22:08 PM PST 24
Peak memory 198732 kb
Host smart-0c278c2e-4fb3-4b2f-921d-35ce8bc5898f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941248774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2941248774
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.3354842783
Short name T31
Test name
Test status
Simulation time 91721862798 ps
CPU time 1539.04 seconds
Started Jan 17 12:51:08 PM PST 24
Finished Jan 17 01:16:54 PM PST 24
Peak memory 239824 kb
Host smart-1775848c-3e05-4ea9-8e46-8e7398146654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354842783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.3354842783
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.189437847
Short name T221
Test name
Test status
Simulation time 148949370 ps
CPU time 0.84 seconds
Started Jan 17 12:51:10 PM PST 24
Finished Jan 17 12:51:16 PM PST 24
Peak memory 195708 kb
Host smart-566ef81c-7b38-416f-bfc0-cb1f996ef294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189437847 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.189437847
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.210009576
Short name T193
Test name
Test status
Simulation time 39114972124 ps
CPU time 462.94 seconds
Started Jan 17 12:50:57 PM PST 24
Finished Jan 17 12:58:43 PM PST 24
Peak memory 198780 kb
Host smart-d70dc398-40c2-47d6-b0a3-2f720f7dbd5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210009576 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.210009576
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4096801632
Short name T690
Test name
Test status
Simulation time 152937814 ps
CPU time 2.54 seconds
Started Jan 17 12:51:10 PM PST 24
Finished Jan 17 12:51:17 PM PST 24
Peak memory 198692 kb
Host smart-d69d78b6-69d8-4b14-9193-17c9e7be7c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096801632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4096801632
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2467602640
Short name T623
Test name
Test status
Simulation time 13079624 ps
CPU time 0.59 seconds
Started Jan 17 12:51:09 PM PST 24
Finished Jan 17 12:51:15 PM PST 24
Peak memory 193144 kb
Host smart-864a37fe-e33d-48ba-8782-1b94cc86f882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467602640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2467602640
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3281621287
Short name T730
Test name
Test status
Simulation time 4620613381 ps
CPU time 67.05 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 239788 kb
Host smart-d7b339aa-ab8d-4f71-825b-8ff8953507d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281621287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3281621287
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.319270012
Short name T292
Test name
Test status
Simulation time 169759827 ps
CPU time 2.2 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:15 PM PST 24
Peak memory 198748 kb
Host smart-543b279a-248a-428d-a1e8-f45a57d058cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319270012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.319270012
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.202609182
Short name T189
Test name
Test status
Simulation time 2092913389 ps
CPU time 108.85 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 198720 kb
Host smart-26202a80-3466-4366-8a77-9cedd560c122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202609182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.202609182
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.84682831
Short name T313
Test name
Test status
Simulation time 51872513198 ps
CPU time 161.77 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:53:53 PM PST 24
Peak memory 198808 kb
Host smart-5830ebd0-e735-4de4-b049-14c6663a1763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84682831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.84682831
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3269393432
Short name T311
Test name
Test status
Simulation time 6260732103 ps
CPU time 21.44 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:26 PM PST 24
Peak memory 198768 kb
Host smart-f9d679d3-5d74-4902-bf07-386989a65205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269393432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3269393432
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4265541506
Short name T491
Test name
Test status
Simulation time 742842835 ps
CPU time 2.28 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:16 PM PST 24
Peak memory 198784 kb
Host smart-d6d7c85f-7d41-4909-a3c6-b5d5f67acb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265541506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4265541506
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.544944295
Short name T473
Test name
Test status
Simulation time 147867391870 ps
CPU time 607.35 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 01:01:13 PM PST 24
Peak memory 198824 kb
Host smart-39502f94-4c6f-4925-9150-72697b3dbe41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544944295 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.544944295
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.400813294
Short name T475
Test name
Test status
Simulation time 190576970022 ps
CPU time 2063.01 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 01:25:28 PM PST 24
Peak memory 225144 kb
Host smart-417be79f-4f15-400d-8d3d-7147e53a4fcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400813294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.400813294
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4026542126
Short name T568
Test name
Test status
Simulation time 207610038 ps
CPU time 1.19 seconds
Started Jan 17 12:51:13 PM PST 24
Finished Jan 17 12:51:16 PM PST 24
Peak memory 197872 kb
Host smart-9a6eed8f-9cc0-4ea7-89a2-542db3e19069
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026542126 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4026542126
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3456861378
Short name T766
Test name
Test status
Simulation time 181430600168 ps
CPU time 461.13 seconds
Started Jan 17 12:51:08 PM PST 24
Finished Jan 17 12:58:56 PM PST 24
Peak memory 198636 kb
Host smart-9325d1b1-0584-4f28-93c6-59519c350444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456861378 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3456861378
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2153003667
Short name T649
Test name
Test status
Simulation time 178918725 ps
CPU time 3.36 seconds
Started Jan 17 12:51:09 PM PST 24
Finished Jan 17 12:51:18 PM PST 24
Peak memory 198332 kb
Host smart-2387fcdf-5706-47dc-9119-0d4093f07c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153003667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2153003667
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1146903088
Short name T652
Test name
Test status
Simulation time 39316033 ps
CPU time 0.55 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:11 PM PST 24
Peak memory 193124 kb
Host smart-52a63fe1-d938-4ff3-b86c-123bde043b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146903088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1146903088
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3624640791
Short name T399
Test name
Test status
Simulation time 1802574735 ps
CPU time 39.21 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:51:04 PM PST 24
Peak memory 227292 kb
Host smart-772a5a6f-f809-41d3-b1d8-6bae5748abbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624640791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3624640791
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1184999391
Short name T682
Test name
Test status
Simulation time 8482566964 ps
CPU time 38.53 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:51:03 PM PST 24
Peak memory 198644 kb
Host smart-58a7d543-b595-4e9d-9b00-e63a59122e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184999391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1184999391
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1270790515
Short name T474
Test name
Test status
Simulation time 432705435 ps
CPU time 20.56 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:43 PM PST 24
Peak memory 198880 kb
Host smart-cbb971a3-fab9-4850-a6f4-0f2911151723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270790515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1270790515
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2453780401
Short name T600
Test name
Test status
Simulation time 9866395220 ps
CPU time 159.52 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:53:04 PM PST 24
Peak memory 198740 kb
Host smart-11224e53-03ee-4cc3-8934-f75b537c2377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453780401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2453780401
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3420257583
Short name T464
Test name
Test status
Simulation time 6212310011 ps
CPU time 104.4 seconds
Started Jan 17 12:50:05 PM PST 24
Finished Jan 17 12:51:54 PM PST 24
Peak memory 198764 kb
Host smart-ece09a86-8114-4938-9125-8ef072fccff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420257583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3420257583
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2165194811
Short name T47
Test name
Test status
Simulation time 965570898 ps
CPU time 1.12 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 215788 kb
Host smart-7d995622-4e66-4130-9dce-73b7f6fa502b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165194811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2165194811
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.327611460
Short name T207
Test name
Test status
Simulation time 217573545 ps
CPU time 2.78 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:28 PM PST 24
Peak memory 198688 kb
Host smart-b5e2a282-c092-4167-8024-65be7318638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327611460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.327611460
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1650398055
Short name T106
Test name
Test status
Simulation time 308897231468 ps
CPU time 1267.81 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 01:11:30 PM PST 24
Peak memory 227528 kb
Host smart-ddff7822-f3f9-4bde-932e-3c4c0ef88a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650398055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1650398055
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1797359725
Short name T371
Test name
Test status
Simulation time 80625874 ps
CPU time 1.17 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 196836 kb
Host smart-566235f9-7547-4d9e-a94d-4db331734b9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797359725 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1797359725
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3716730271
Short name T678
Test name
Test status
Simulation time 110551573311 ps
CPU time 517.29 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 198744 kb
Host smart-30055b2a-277a-4c2f-b33d-33c7692fb22c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716730271 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.3716730271
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3132629185
Short name T509
Test name
Test status
Simulation time 21763843 ps
CPU time 0.7 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 194480 kb
Host smart-c5ca6ed7-5610-43ef-99c0-ce3f147605d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132629185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3132629185
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3597408133
Short name T264
Test name
Test status
Simulation time 11852088 ps
CPU time 0.57 seconds
Started Jan 17 12:51:07 PM PST 24
Finished Jan 17 12:51:15 PM PST 24
Peak memory 193108 kb
Host smart-7aa390cf-113d-4f16-8869-fb2889d58750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597408133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3597408133
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2399957642
Short name T326
Test name
Test status
Simulation time 3343084812 ps
CPU time 28.06 seconds
Started Jan 17 12:51:13 PM PST 24
Finished Jan 17 12:51:43 PM PST 24
Peak memory 220084 kb
Host smart-e6ea2604-e4db-4e40-9a6b-d19af271955e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399957642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2399957642
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3729674989
Short name T462
Test name
Test status
Simulation time 9397865808 ps
CPU time 32.23 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:51:37 PM PST 24
Peak memory 198824 kb
Host smart-356c9192-8d61-4e79-a44c-46a085a4050f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729674989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3729674989
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.430335032
Short name T487
Test name
Test status
Simulation time 645797002 ps
CPU time 15.55 seconds
Started Jan 17 12:51:09 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 198656 kb
Host smart-a6511da4-1143-4557-9d1d-ee654629d867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430335032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.430335032
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.653394878
Short name T638
Test name
Test status
Simulation time 11652038717 ps
CPU time 95.14 seconds
Started Jan 17 12:51:08 PM PST 24
Finished Jan 17 12:52:50 PM PST 24
Peak memory 198808 kb
Host smart-8334660b-5f22-46da-8606-ca8cccf8d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653394878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.653394878
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1089638401
Short name T554
Test name
Test status
Simulation time 21449582752 ps
CPU time 84.85 seconds
Started Jan 17 12:51:07 PM PST 24
Finished Jan 17 12:52:40 PM PST 24
Peak memory 198800 kb
Host smart-3b7cc8c0-63b7-4800-82a8-500373ad660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089638401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1089638401
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.800206270
Short name T679
Test name
Test status
Simulation time 158726566 ps
CPU time 1.47 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 198716 kb
Host smart-cb9967dc-75bf-4be6-9593-8ad61000a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800206270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.800206270
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3091253191
Short name T811
Test name
Test status
Simulation time 2157661465 ps
CPU time 32.72 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 227532 kb
Host smart-5bd4a1ec-6e0b-4834-b2d3-9704144a9d8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091253191 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3091253191
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.143568636
Short name T113
Test name
Test status
Simulation time 89260348337 ps
CPU time 1683.7 seconds
Started Jan 17 12:51:02 PM PST 24
Finished Jan 17 01:19:09 PM PST 24
Peak memory 248016 kb
Host smart-2d0e1b6c-5030-436c-ac71-ed1c20a6028d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143568636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.143568636
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3792586351
Short name T262
Test name
Test status
Simulation time 167215943 ps
CPU time 1.02 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:06 PM PST 24
Peak memory 197248 kb
Host smart-241cb3a7-2939-4c93-9710-7d3c0682ddcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792586351 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3792586351
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3167341221
Short name T635
Test name
Test status
Simulation time 6625930027 ps
CPU time 331.47 seconds
Started Jan 17 12:51:13 PM PST 24
Finished Jan 17 12:56:46 PM PST 24
Peak memory 198580 kb
Host smart-4603598f-086b-4334-8fc0-bc88e291c3e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167341221 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.3167341221
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1204035633
Short name T434
Test name
Test status
Simulation time 16011368418 ps
CPU time 51.03 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198864 kb
Host smart-9cf633b0-8dd1-4d75-99e5-13c347decae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204035633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1204035633
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2784763000
Short name T320
Test name
Test status
Simulation time 15157235 ps
CPU time 0.57 seconds
Started Jan 17 12:51:26 PM PST 24
Finished Jan 17 12:51:29 PM PST 24
Peak memory 193120 kb
Host smart-1128084d-19e6-4dec-b194-f7158cafb2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784763000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2784763000
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3410605057
Short name T647
Test name
Test status
Simulation time 321634583 ps
CPU time 4.92 seconds
Started Jan 17 12:51:10 PM PST 24
Finished Jan 17 12:51:20 PM PST 24
Peak memory 198608 kb
Host smart-379fbd68-ed81-4346-940d-b6cd8e95345a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410605057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3410605057
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1011918797
Short name T691
Test name
Test status
Simulation time 868798115 ps
CPU time 39.59 seconds
Started Jan 17 12:51:05 PM PST 24
Finished Jan 17 12:51:54 PM PST 24
Peak memory 198776 kb
Host smart-c9d01b6f-afc6-47c6-b1a6-7248d27f9d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011918797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1011918797
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1950660444
Short name T466
Test name
Test status
Simulation time 1887963365 ps
CPU time 96.05 seconds
Started Jan 17 12:51:08 PM PST 24
Finished Jan 17 12:52:51 PM PST 24
Peak memory 198656 kb
Host smart-d513d8ae-38e1-46d7-908c-0bdfedf751a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1950660444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1950660444
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.538597569
Short name T694
Test name
Test status
Simulation time 52322216500 ps
CPU time 165.35 seconds
Started Jan 17 12:51:04 PM PST 24
Finished Jan 17 12:53:59 PM PST 24
Peak memory 198752 kb
Host smart-a1adfde3-93f0-43b1-9ba4-89742129c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538597569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.538597569
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.182949064
Short name T721
Test name
Test status
Simulation time 743941500 ps
CPU time 20.11 seconds
Started Jan 17 12:51:07 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 198672 kb
Host smart-61dece3e-6af1-4b73-a981-9cfd69a7a5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182949064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.182949064
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2145230329
Short name T636
Test name
Test status
Simulation time 73330336 ps
CPU time 1.74 seconds
Started Jan 17 12:51:03 PM PST 24
Finished Jan 17 12:51:07 PM PST 24
Peak memory 198676 kb
Host smart-7d5c24b9-b5ac-4b2f-9eb4-33f20a109282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145230329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2145230329
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1947203541
Short name T523
Test name
Test status
Simulation time 18953709642 ps
CPU time 815.76 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 01:04:58 PM PST 24
Peak memory 236656 kb
Host smart-4d1cabc6-216a-4f5f-8f2e-6a808050ec8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947203541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1947203541
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.1118420940
Short name T584
Test name
Test status
Simulation time 163994479656 ps
CPU time 1035.84 seconds
Started Jan 17 12:51:22 PM PST 24
Finished Jan 17 01:08:42 PM PST 24
Peak memory 256232 kb
Host smart-387fc762-9687-4ad9-aa64-ea447d0bcc68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118420940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.1118420940
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.219377665
Short name T472
Test name
Test status
Simulation time 264613117 ps
CPU time 0.84 seconds
Started Jan 17 12:51:17 PM PST 24
Finished Jan 17 12:51:19 PM PST 24
Peak memory 195716 kb
Host smart-ae9d3f25-cf70-4398-9185-fa123db13354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219377665 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.219377665
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4275726266
Short name T268
Test name
Test status
Simulation time 7610588973 ps
CPU time 357.04 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:57:19 PM PST 24
Peak memory 198720 kb
Host smart-60344faf-6c42-407b-8f91-7d87b416699e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275726266 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.4275726266
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3115838285
Short name T707
Test name
Test status
Simulation time 979728666 ps
CPU time 14.3 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:51:41 PM PST 24
Peak memory 198784 kb
Host smart-021e573e-2b1e-49be-8c60-bf0f6005179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115838285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3115838285
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3611160871
Short name T667
Test name
Test status
Simulation time 24586019 ps
CPU time 0.57 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:51:22 PM PST 24
Peak memory 193076 kb
Host smart-41f4860f-13cf-4fbd-bb84-c03386cfc45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611160871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3611160871
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.450998379
Short name T333
Test name
Test status
Simulation time 840078812 ps
CPU time 30.06 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:51:52 PM PST 24
Peak memory 230444 kb
Host smart-04f311fa-3c8b-47ff-80a4-159fe990c40a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450998379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.450998379
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1328306697
Short name T727
Test name
Test status
Simulation time 3061411745 ps
CPU time 48.45 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 12:52:19 PM PST 24
Peak memory 198764 kb
Host smart-389a14b7-821a-4d13-8336-22e772483758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328306697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1328306697
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.100247516
Short name T564
Test name
Test status
Simulation time 3729183512 ps
CPU time 93.21 seconds
Started Jan 17 12:51:15 PM PST 24
Finished Jan 17 12:52:49 PM PST 24
Peak memory 198732 kb
Host smart-01db191f-2909-4617-a85c-86e8b5504deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100247516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.100247516
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3409318711
Short name T104
Test name
Test status
Simulation time 2705631179 ps
CPU time 136.16 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:53:45 PM PST 24
Peak memory 198760 kb
Host smart-80f6c76c-857f-4456-887a-be17f3056cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409318711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3409318711
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2866446510
Short name T497
Test name
Test status
Simulation time 22491110104 ps
CPU time 107.06 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:53:16 PM PST 24
Peak memory 198840 kb
Host smart-51cd78be-1c16-44c5-afe3-c612f60343b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866446510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2866446510
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1957362828
Short name T350
Test name
Test status
Simulation time 266450789 ps
CPU time 1.27 seconds
Started Jan 17 12:51:20 PM PST 24
Finished Jan 17 12:51:22 PM PST 24
Peak memory 198244 kb
Host smart-1a7e1b6f-1b91-4303-bce3-17ee50e167c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957362828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1957362828
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1583062747
Short name T332
Test name
Test status
Simulation time 239855972623 ps
CPU time 1003.05 seconds
Started Jan 17 12:51:22 PM PST 24
Finished Jan 17 01:08:07 PM PST 24
Peak memory 198772 kb
Host smart-591be94d-e760-46b5-bb54-f0b15d915626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583062747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1583062747
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.1134301174
Short name T824
Test name
Test status
Simulation time 523392658794 ps
CPU time 658.18 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 215292 kb
Host smart-5bff21ee-27c4-4f9f-9ba1-6fdf67327a0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134301174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.1134301174
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2908895934
Short name T671
Test name
Test status
Simulation time 60368233 ps
CPU time 0.88 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:51:28 PM PST 24
Peak memory 196376 kb
Host smart-e341fcc5-a1f9-4188-bf31-6fb0ba435da1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908895934 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2908895934
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1569078853
Short name T849
Test name
Test status
Simulation time 39906634076 ps
CPU time 507.86 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:59:57 PM PST 24
Peak memory 198752 kb
Host smart-e437f161-73e3-4428-89b3-ab1ee1631b8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569078853 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.1569078853
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.4104207070
Short name T673
Test name
Test status
Simulation time 362462496 ps
CPU time 5.65 seconds
Started Jan 17 12:51:20 PM PST 24
Finished Jan 17 12:51:27 PM PST 24
Peak memory 198720 kb
Host smart-ccc924bb-4ce2-4080-b15b-5d67550864a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104207070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4104207070
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1276648310
Short name T840
Test name
Test status
Simulation time 22542092 ps
CPU time 0.61 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:51:22 PM PST 24
Peak memory 193080 kb
Host smart-70713789-5873-4538-b8c1-9a10a1dfe74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276648310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1276648310
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4022858406
Short name T219
Test name
Test status
Simulation time 7481606196 ps
CPU time 25.61 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:51:53 PM PST 24
Peak memory 214336 kb
Host smart-01d5c09d-7195-4a27-a97c-0bf0d510d101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022858406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4022858406
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.227391082
Short name T488
Test name
Test status
Simulation time 12846877845 ps
CPU time 45.59 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 198824 kb
Host smart-5281306b-5263-46d7-85ac-585e01b8c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227391082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.227391082
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3518527934
Short name T482
Test name
Test status
Simulation time 499511799 ps
CPU time 26.2 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:51:48 PM PST 24
Peak memory 198716 kb
Host smart-cc50956d-1d57-4b13-9270-c442d270664a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518527934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3518527934
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.60818737
Short name T267
Test name
Test status
Simulation time 10634676358 ps
CPU time 34.18 seconds
Started Jan 17 12:51:17 PM PST 24
Finished Jan 17 12:51:52 PM PST 24
Peak memory 198764 kb
Host smart-29767eed-2795-4fe0-9dc6-7ba05706db1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60818737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.60818737
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2936673737
Short name T637
Test name
Test status
Simulation time 4800588565 ps
CPU time 29.63 seconds
Started Jan 17 12:51:26 PM PST 24
Finished Jan 17 12:51:58 PM PST 24
Peak memory 198812 kb
Host smart-f4a48376-dfd0-4e57-aebb-e6ad7ea754f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936673737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2936673737
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1535922590
Short name T668
Test name
Test status
Simulation time 320565053 ps
CPU time 2.09 seconds
Started Jan 17 12:51:18 PM PST 24
Finished Jan 17 12:51:21 PM PST 24
Peak memory 198484 kb
Host smart-0ce4c5a9-64d4-4f1c-8e7e-8638940abb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535922590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1535922590
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.955797362
Short name T367
Test name
Test status
Simulation time 1558604507 ps
CPU time 35.01 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:52:10 PM PST 24
Peak memory 226276 kb
Host smart-a2c31fcd-ee60-458e-abde-df8f50f7b8fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955797362 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.955797362
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1653608902
Short name T269
Test name
Test status
Simulation time 97098229020 ps
CPU time 376.94 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:57:48 PM PST 24
Peak memory 226528 kb
Host smart-9b368954-72f1-4ff9-bd36-5c526f5a9219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653608902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1653608902
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3828247020
Short name T331
Test name
Test status
Simulation time 40403995 ps
CPU time 0.95 seconds
Started Jan 17 12:51:17 PM PST 24
Finished Jan 17 12:51:19 PM PST 24
Peak memory 196036 kb
Host smart-5c27756e-d9df-4d47-bcc2-a7afa8ac3b48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828247020 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3828247020
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3486176040
Short name T255
Test name
Test status
Simulation time 52424282435 ps
CPU time 395 seconds
Started Jan 17 12:51:24 PM PST 24
Finished Jan 17 12:58:03 PM PST 24
Peak memory 198772 kb
Host smart-d290bfd0-d51b-4270-b32a-dce0144aeb08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486176040 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3486176040
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2009214397
Short name T421
Test name
Test status
Simulation time 14781076 ps
CPU time 0.58 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:51:28 PM PST 24
Peak memory 193256 kb
Host smart-9caa4b34-b2f9-4749-a3e6-c46d6cfff277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009214397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2009214397
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3340965534
Short name T196
Test name
Test status
Simulation time 19103881 ps
CPU time 0.56 seconds
Started Jan 17 12:51:19 PM PST 24
Finished Jan 17 12:51:20 PM PST 24
Peak memory 193128 kb
Host smart-b34658b3-e058-46c3-87be-91fc33e5cb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340965534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3340965534
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3795051018
Short name T222
Test name
Test status
Simulation time 215985039 ps
CPU time 4.38 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 214196 kb
Host smart-89de14f6-f4e6-4b3d-a473-1e0572a28d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795051018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3795051018
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2249155992
Short name T428
Test name
Test status
Simulation time 7654012411 ps
CPU time 33.66 seconds
Started Jan 17 12:51:16 PM PST 24
Finished Jan 17 12:51:50 PM PST 24
Peak memory 198828 kb
Host smart-325dd2c5-4833-46a7-b2f7-f8aa4a70bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249155992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2249155992
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1055718010
Short name T305
Test name
Test status
Simulation time 16735425001 ps
CPU time 93.34 seconds
Started Jan 17 12:51:20 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 198852 kb
Host smart-2ab303e3-3e2d-41ad-9e8c-0080043c1b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055718010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1055718010
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1049146538
Short name T237
Test name
Test status
Simulation time 7099575764 ps
CPU time 64.29 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:52:32 PM PST 24
Peak memory 198468 kb
Host smart-5ae3293f-c369-4774-aa5d-f49b12fc67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049146538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1049146538
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3042287206
Short name T676
Test name
Test status
Simulation time 2294884878 ps
CPU time 58.37 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:52:25 PM PST 24
Peak memory 198788 kb
Host smart-a9c6a908-7cbb-4b1c-884c-cc2cff56bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042287206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3042287206
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2176541060
Short name T639
Test name
Test status
Simulation time 62021188 ps
CPU time 0.74 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 12:51:22 PM PST 24
Peak memory 194884 kb
Host smart-a6cd19f5-7a66-4420-91fd-87837ec60c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176541060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2176541060
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2599937976
Short name T603
Test name
Test status
Simulation time 128490399139 ps
CPU time 1048.64 seconds
Started Jan 17 12:51:21 PM PST 24
Finished Jan 17 01:08:50 PM PST 24
Peak memory 222428 kb
Host smart-1bf4b701-6e72-48bf-b1ec-3446f51f6fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599937976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2599937976
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.2163956497
Short name T460
Test name
Test status
Simulation time 38491831413 ps
CPU time 187.66 seconds
Started Jan 17 12:51:17 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 239852 kb
Host smart-d53c9406-de63-465a-b0c6-7b349bc8404a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163956497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.2163956497
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3787771316
Short name T717
Test name
Test status
Simulation time 29887562 ps
CPU time 0.96 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 12:51:32 PM PST 24
Peak memory 196096 kb
Host smart-5f8c80fd-d0ab-4048-93c8-279e1e876831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787771316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3787771316
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2467576697
Short name T330
Test name
Test status
Simulation time 105516626196 ps
CPU time 453.94 seconds
Started Jan 17 12:51:24 PM PST 24
Finished Jan 17 12:59:02 PM PST 24
Peak memory 198760 kb
Host smart-d12f6b00-2de0-468e-b60d-28593bf96921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467576697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.2467576697
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1800387122
Short name T328
Test name
Test status
Simulation time 1266929799 ps
CPU time 44.66 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:52:11 PM PST 24
Peak memory 198708 kb
Host smart-d3a84d6b-87c5-42ba-b001-7599c02fbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800387122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1800387122
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2026145262
Short name T402
Test name
Test status
Simulation time 23494342 ps
CPU time 0.57 seconds
Started Jan 17 12:51:35 PM PST 24
Finished Jan 17 12:51:36 PM PST 24
Peak memory 193104 kb
Host smart-cc3228d6-8793-4c69-a54b-161d7eca0efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026145262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2026145262
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2288575429
Short name T753
Test name
Test status
Simulation time 791637971 ps
CPU time 15.12 seconds
Started Jan 17 12:51:24 PM PST 24
Finished Jan 17 12:51:43 PM PST 24
Peak memory 215136 kb
Host smart-e1e76e21-934b-4c26-a58c-b5e058a35a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288575429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2288575429
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.795133708
Short name T774
Test name
Test status
Simulation time 5844837158 ps
CPU time 65.81 seconds
Started Jan 17 12:51:24 PM PST 24
Finished Jan 17 12:52:34 PM PST 24
Peak memory 198752 kb
Host smart-aa47a086-9961-4a26-8dd4-69664b3aff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795133708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.795133708
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2614896294
Short name T280
Test name
Test status
Simulation time 4216922172 ps
CPU time 111.67 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 12:53:23 PM PST 24
Peak memory 198816 kb
Host smart-ff7aa396-bf37-4612-83c7-34bbc4ed9d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614896294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2614896294
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3077708016
Short name T217
Test name
Test status
Simulation time 34618210463 ps
CPU time 141.81 seconds
Started Jan 17 12:51:23 PM PST 24
Finished Jan 17 12:53:50 PM PST 24
Peak memory 198740 kb
Host smart-db4b3253-d821-46d2-8e68-f0b44d3c52b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077708016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3077708016
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1147433327
Short name T711
Test name
Test status
Simulation time 399917224 ps
CPU time 5.78 seconds
Started Jan 17 12:51:24 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 198572 kb
Host smart-54b850f6-f76b-4dd8-80fd-326cbf0bdc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147433327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1147433327
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2523284605
Short name T374
Test name
Test status
Simulation time 219455851 ps
CPU time 3.12 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:32 PM PST 24
Peak memory 198244 kb
Host smart-f5cca5a2-60c0-4e8a-847f-eded4937e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523284605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2523284605
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1145237129
Short name T806
Test name
Test status
Simulation time 3387756152 ps
CPU time 84.38 seconds
Started Jan 17 12:51:26 PM PST 24
Finished Jan 17 12:52:53 PM PST 24
Peak memory 198820 kb
Host smart-2de65056-3062-40d2-980e-c7c7a8474fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145237129 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1145237129
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.3235729335
Short name T675
Test name
Test status
Simulation time 37716344585 ps
CPU time 520.83 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 01:00:10 PM PST 24
Peak memory 241852 kb
Host smart-fae8c2dd-0b68-434c-9b89-9843d793c742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235729335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.3235729335
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.789877356
Short name T306
Test name
Test status
Simulation time 121669247 ps
CPU time 1.2 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 196708 kb
Host smart-94318d49-4389-45bd-a74e-a3818fadd359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789877356 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.789877356
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3277219044
Short name T344
Test name
Test status
Simulation time 1684445635 ps
CPU time 28.13 seconds
Started Jan 17 12:51:36 PM PST 24
Finished Jan 17 12:52:05 PM PST 24
Peak memory 198636 kb
Host smart-40c7a427-34d6-48b1-89bb-896cf8a50c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277219044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3277219044
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1304248804
Short name T533
Test name
Test status
Simulation time 27313817 ps
CPU time 0.62 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:51:36 PM PST 24
Peak memory 194084 kb
Host smart-bca69e79-73f6-4251-9364-9d536a3e438a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304248804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1304248804
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4235679704
Short name T226
Test name
Test status
Simulation time 1335356461 ps
CPU time 45.38 seconds
Started Jan 17 12:51:39 PM PST 24
Finished Jan 17 12:52:28 PM PST 24
Peak memory 223152 kb
Host smart-94ced60c-871d-4a9d-bb46-40aae0e15c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235679704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4235679704
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.687823903
Short name T544
Test name
Test status
Simulation time 1461120336 ps
CPU time 32.18 seconds
Started Jan 17 12:51:35 PM PST 24
Finished Jan 17 12:52:08 PM PST 24
Peak memory 198740 kb
Host smart-e76ecb0c-3d80-4468-8e36-6fa0341d0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687823903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.687823903
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.335435251
Short name T650
Test name
Test status
Simulation time 815203144 ps
CPU time 40.95 seconds
Started Jan 17 12:51:37 PM PST 24
Finished Jan 17 12:52:19 PM PST 24
Peak memory 198804 kb
Host smart-de742e4f-424b-4534-9f36-5a6a5a050378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335435251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.335435251
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1105683052
Short name T308
Test name
Test status
Simulation time 9858526682 ps
CPU time 79.93 seconds
Started Jan 17 12:51:39 PM PST 24
Finished Jan 17 12:53:03 PM PST 24
Peak memory 198620 kb
Host smart-c4c52c88-1a26-4ead-abad-41b34ff7ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105683052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1105683052
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1882745118
Short name T706
Test name
Test status
Simulation time 17438369058 ps
CPU time 55.49 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:52:25 PM PST 24
Peak memory 198780 kb
Host smart-765540a3-daa5-45d5-ac4f-3ad8934c9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882745118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1882745118
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2710316549
Short name T397
Test name
Test status
Simulation time 878060768 ps
CPU time 4.41 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:51:49 PM PST 24
Peak memory 198072 kb
Host smart-946e0732-4544-4555-be97-2b62c80c7f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710316549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2710316549
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1295759823
Short name T768
Test name
Test status
Simulation time 56483272788 ps
CPU time 663.66 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 01:02:39 PM PST 24
Peak memory 198768 kb
Host smart-b7dfa920-b251-41a2-b77e-dff0becfde16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295759823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1295759823
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.1164439958
Short name T383
Test name
Test status
Simulation time 198885369230 ps
CPU time 3539.79 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 01:50:45 PM PST 24
Peak memory 264172 kb
Host smart-f7e75de1-437a-469c-8e1d-e415476ef3a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164439958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.1164439958
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1239092627
Short name T275
Test name
Test status
Simulation time 30934195 ps
CPU time 1.08 seconds
Started Jan 17 12:51:39 PM PST 24
Finished Jan 17 12:51:44 PM PST 24
Peak memory 196700 kb
Host smart-de99ba3e-c7d1-459d-a6a1-6317e6b958dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239092627 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1239092627
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1028487111
Short name T498
Test name
Test status
Simulation time 7600857927 ps
CPU time 359.77 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:57:44 PM PST 24
Peak memory 198756 kb
Host smart-b618dc8c-391d-40ab-9541-5d261a196f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028487111 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.1028487111
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2532582398
Short name T454
Test name
Test status
Simulation time 4181446093 ps
CPU time 69.08 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 198812 kb
Host smart-f46d5c46-cb92-4f55-af4f-4ca34b55ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532582398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2532582398
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3449415322
Short name T44
Test name
Test status
Simulation time 43646746 ps
CPU time 0.55 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:51:32 PM PST 24
Peak memory 193032 kb
Host smart-e3d81e06-a052-4a69-ac72-6c30e304837a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449415322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3449415322
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1404588194
Short name T429
Test name
Test status
Simulation time 47189267 ps
CPU time 1.68 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 198712 kb
Host smart-69ef1734-187b-4f11-bf9a-8a7da6d7270e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404588194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1404588194
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.820979115
Short name T205
Test name
Test status
Simulation time 6004596222 ps
CPU time 24.23 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 198872 kb
Host smart-2d02437e-9f48-4a94-8631-bdc7ed12d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820979115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.820979115
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1102911549
Short name T441
Test name
Test status
Simulation time 3983551643 ps
CPU time 37.36 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 198732 kb
Host smart-12912f44-efbe-41fc-aace-309d9e6ddd1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102911549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1102911549
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.899100924
Short name T376
Test name
Test status
Simulation time 18890369858 ps
CPU time 59.39 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:52:28 PM PST 24
Peak memory 198788 kb
Host smart-adc1338c-8152-49ac-b424-6d3ef8c3a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899100924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.899100924
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3592597414
Short name T503
Test name
Test status
Simulation time 108130148 ps
CPU time 5.3 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:51:37 PM PST 24
Peak memory 198608 kb
Host smart-c27bd0b8-efa7-47f8-8782-c17bfe05347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592597414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3592597414
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3323804333
Short name T457
Test name
Test status
Simulation time 207684634 ps
CPU time 0.76 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 194732 kb
Host smart-f59357b2-2d03-4726-ada3-09653df70d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323804333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3323804333
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2420040511
Short name T621
Test name
Test status
Simulation time 65635529343 ps
CPU time 527.45 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 01:00:18 PM PST 24
Peak memory 198864 kb
Host smart-bb69406e-7e60-4a0e-a403-4820ca943fa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420040511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2420040511
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.888714257
Short name T592
Test name
Test status
Simulation time 98206091610 ps
CPU time 779.93 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 01:04:29 PM PST 24
Peak memory 209976 kb
Host smart-771e1d19-48d4-4bb2-9b01-00cbd4446128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888714257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.888714257
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1016923455
Short name T714
Test name
Test status
Simulation time 365486001 ps
CPU time 0.95 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 196680 kb
Host smart-b65da5ab-bbfe-4d91-9cea-ec24bfcca0c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016923455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1016923455
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3675452352
Short name T666
Test name
Test status
Simulation time 48571575698 ps
CPU time 414.8 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 12:58:26 PM PST 24
Peak memory 198720 kb
Host smart-e4498148-6d0c-4856-8027-8e9a2cc91d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675452352 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3675452352
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.619866856
Short name T651
Test name
Test status
Simulation time 13237124787 ps
CPU time 69.7 seconds
Started Jan 17 12:51:32 PM PST 24
Finished Jan 17 12:52:42 PM PST 24
Peak memory 198796 kb
Host smart-5fffc789-88b2-4c8d-b578-5e94a45ae52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619866856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.619866856
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1618516827
Short name T633
Test name
Test status
Simulation time 34907863 ps
CPU time 0.57 seconds
Started Jan 17 12:51:26 PM PST 24
Finished Jan 17 12:51:29 PM PST 24
Peak memory 193116 kb
Host smart-e9a37a20-598f-41fb-9b10-1244d7d25837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618516827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1618516827
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3751469212
Short name T604
Test name
Test status
Simulation time 1215612938 ps
CPU time 36.8 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 203152 kb
Host smart-fde4c4ae-9297-4dfe-8353-a801d38d499e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751469212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3751469212
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1523706289
Short name T567
Test name
Test status
Simulation time 1612554662 ps
CPU time 35.64 seconds
Started Jan 17 12:51:32 PM PST 24
Finished Jan 17 12:52:09 PM PST 24
Peak memory 198668 kb
Host smart-099d2166-2422-4b5a-bc9a-ed69d1ece531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523706289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1523706289
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1441171995
Short name T235
Test name
Test status
Simulation time 984735151 ps
CPU time 24.63 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198912 kb
Host smart-2f8645be-edd3-4c10-b87a-0c12776a096b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441171995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1441171995
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.531229982
Short name T606
Test name
Test status
Simulation time 8179754358 ps
CPU time 130.76 seconds
Started Jan 17 12:51:25 PM PST 24
Finished Jan 17 12:53:39 PM PST 24
Peak memory 198628 kb
Host smart-e592db40-d85d-4d99-8b38-70965509ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531229982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.531229982
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3020537027
Short name T224
Test name
Test status
Simulation time 4270101190 ps
CPU time 37.07 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:52:11 PM PST 24
Peak memory 198824 kb
Host smart-30873f6b-8cc4-463c-9a28-3e966657dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020537027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3020537027
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2535328033
Short name T738
Test name
Test status
Simulation time 788030587 ps
CPU time 2.33 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 12:51:33 PM PST 24
Peak memory 198776 kb
Host smart-c812c3a6-7b6b-4dd0-962d-a67a2cf6787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535328033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2535328033
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2259418516
Short name T480
Test name
Test status
Simulation time 80977543055 ps
CPU time 1078.54 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 01:09:31 PM PST 24
Peak memory 224660 kb
Host smart-f08ee18c-66f0-49eb-9b09-bcfeb96e58e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259418516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2259418516
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.2059711183
Short name T627
Test name
Test status
Simulation time 42876494111 ps
CPU time 837.26 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 01:05:28 PM PST 24
Peak memory 247100 kb
Host smart-ce7e4082-6b90-4b55-878a-fb33afdd4584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059711183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.2059711183
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1391937101
Short name T359
Test name
Test status
Simulation time 41174866 ps
CPU time 0.95 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 196088 kb
Host smart-3750bbba-d8c4-4ca7-b278-dfffc95fc63c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391937101 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1391937101
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2681041525
Short name T641
Test name
Test status
Simulation time 31466317386 ps
CPU time 483.36 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:59:35 PM PST 24
Peak memory 198652 kb
Host smart-5fb9dca4-8393-4eb1-b9e4-62d5b4b74c8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681041525 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2681041525
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2483159080
Short name T655
Test name
Test status
Simulation time 5505709647 ps
CPU time 44.68 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:52:16 PM PST 24
Peak memory 198828 kb
Host smart-104924b2-4491-4096-8d35-bd831b36de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483159080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2483159080
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1996874641
Short name T469
Test name
Test status
Simulation time 15388405 ps
CPU time 0.58 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 192992 kb
Host smart-6de86f22-2938-4e2a-b4b2-845cc49e4eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996874641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1996874641
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.657975279
Short name T556
Test name
Test status
Simulation time 949054776 ps
CPU time 30.35 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:52:02 PM PST 24
Peak memory 221672 kb
Host smart-5c437491-a27f-4ff8-83c5-a6c7a32ff6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657975279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.657975279
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.835737189
Short name T513
Test name
Test status
Simulation time 8143645910 ps
CPU time 34.86 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:52:07 PM PST 24
Peak memory 198740 kb
Host smart-3dbdf5e3-81ec-4154-961f-cb27d7b527f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835737189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.835737189
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3170939027
Short name T734
Test name
Test status
Simulation time 10632327707 ps
CPU time 129.65 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:53:44 PM PST 24
Peak memory 198864 kb
Host smart-581a9169-4910-4f33-af92-5649d07ebd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170939027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3170939027
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.789211192
Short name T644
Test name
Test status
Simulation time 3664971542 ps
CPU time 21.71 seconds
Started Jan 17 12:51:35 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198816 kb
Host smart-cbe41766-eb00-49fc-9973-8408e420b53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789211192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.789211192
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2054580680
Short name T225
Test name
Test status
Simulation time 934349689 ps
CPU time 48.85 seconds
Started Jan 17 12:51:32 PM PST 24
Finished Jan 17 12:52:21 PM PST 24
Peak memory 198928 kb
Host smart-8623e8d0-d1a3-4cf1-8ccc-f816ba6ab0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054580680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2054580680
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.357979647
Short name T289
Test name
Test status
Simulation time 36998069 ps
CPU time 0.73 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 194596 kb
Host smart-3197434b-ae35-43e6-93c1-f494a7acfcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357979647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.357979647
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1284100384
Short name T366
Test name
Test status
Simulation time 49637585653 ps
CPU time 1154.06 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 01:10:48 PM PST 24
Peak memory 224436 kb
Host smart-ac4cae26-2819-44d0-b932-476e6e7d1a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284100384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1284100384
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.192277873
Short name T41
Test name
Test status
Simulation time 53075870568 ps
CPU time 1056.6 seconds
Started Jan 17 12:51:36 PM PST 24
Finished Jan 17 01:09:14 PM PST 24
Peak memory 247804 kb
Host smart-8c415b52-6e1a-4c8a-a1d3-806a61a370b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192277873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.192277873
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3355554202
Short name T490
Test name
Test status
Simulation time 306314629 ps
CPU time 0.88 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:51:34 PM PST 24
Peak memory 196584 kb
Host smart-4319557f-16bc-4c31-84b2-12dad1d34d9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355554202 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3355554202
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2829292786
Short name T278
Test name
Test status
Simulation time 31019497476 ps
CPU time 498.32 seconds
Started Jan 17 12:51:28 PM PST 24
Finished Jan 17 12:59:48 PM PST 24
Peak memory 198728 kb
Host smart-c3c7b6f9-a8c5-4323-9500-a83c7622090e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829292786 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.2829292786
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3878601327
Short name T511
Test name
Test status
Simulation time 5104065059 ps
CPU time 33.18 seconds
Started Jan 17 12:51:29 PM PST 24
Finished Jan 17 12:52:04 PM PST 24
Peak memory 198712 kb
Host smart-aa46e0b5-cd45-4d1f-92a6-337856e1a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878601327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3878601327
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.254664137
Short name T814
Test name
Test status
Simulation time 12799550 ps
CPU time 0.57 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:12 PM PST 24
Peak memory 193116 kb
Host smart-97fcdd1e-09cf-463d-8ac5-156ffcaa4630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254664137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.254664137
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.683888819
Short name T654
Test name
Test status
Simulation time 3744958289 ps
CPU time 42.99 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:51:08 PM PST 24
Peak memory 225496 kb
Host smart-a92daa1e-9f1d-4128-896b-b2f6d50115d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683888819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.683888819
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2241050002
Short name T716
Test name
Test status
Simulation time 1411286590 ps
CPU time 9.58 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:21 PM PST 24
Peak memory 198812 kb
Host smart-6898456a-b92a-4c1c-8284-c630eb826b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241050002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2241050002
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1280277457
Short name T696
Test name
Test status
Simulation time 2587744620 ps
CPU time 138.7 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:52:30 PM PST 24
Peak memory 198792 kb
Host smart-35fd112d-f513-4a8c-95a7-01fe721e2e6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1280277457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1280277457
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2826461948
Short name T597
Test name
Test status
Simulation time 50050271193 ps
CPU time 83.76 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 198736 kb
Host smart-e03a9bc8-aa53-466b-a1ec-614b32cbcf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826461948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2826461948
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3437611117
Short name T569
Test name
Test status
Simulation time 1635357930 ps
CPU time 85.75 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:51:36 PM PST 24
Peak memory 198708 kb
Host smart-b2bda2fb-c2a6-40fa-b85b-a48fbd6d3268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437611117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3437611117
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3400851969
Short name T48
Test name
Test status
Simulation time 88653955 ps
CPU time 0.99 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 217056 kb
Host smart-83362b1d-9de2-47f1-8b69-ecea2b547dfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400851969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3400851969
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4074718232
Short name T796
Test name
Test status
Simulation time 165491926 ps
CPU time 2.36 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:50:14 PM PST 24
Peak memory 198540 kb
Host smart-7eece0df-8420-403b-bb99-5b7f12597a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074718232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4074718232
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.178438053
Short name T502
Test name
Test status
Simulation time 13982433440 ps
CPU time 153.13 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:52:58 PM PST 24
Peak memory 198820 kb
Host smart-9dec5d73-82d9-44b3-90c8-4b7776c42e48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178438053 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.178438053
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1368136556
Short name T709
Test name
Test status
Simulation time 40380347887 ps
CPU time 373.15 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:56:35 PM PST 24
Peak memory 215268 kb
Host smart-d36f74a7-857f-40b2-ae5b-1ff4cc05a41d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368136556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1368136556
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2264601404
Short name T285
Test name
Test status
Simulation time 30397957 ps
CPU time 0.95 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:21 PM PST 24
Peak memory 197252 kb
Host smart-6c1ea8b4-50f4-42c1-8c31-a2857f970ceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264601404 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2264601404
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.662543264
Short name T615
Test name
Test status
Simulation time 41876618511 ps
CPU time 452.21 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:57:56 PM PST 24
Peak memory 198884 kb
Host smart-57ccba86-5e36-4be1-bcdf-ed058a86243d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662543264 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.hmac_test_sha_vectors.662543264
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.491533499
Short name T449
Test name
Test status
Simulation time 759951051 ps
CPU time 17.22 seconds
Started Jan 17 12:50:06 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 198744 kb
Host smart-135e4792-72eb-478c-ad5e-873d814ac878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491533499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.491533499
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.126417659
Short name T384
Test name
Test status
Simulation time 36285260 ps
CPU time 0.56 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 193060 kb
Host smart-85a61c93-3896-4eca-a7ed-8aea7db6c6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126417659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.126417659
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1848345264
Short name T388
Test name
Test status
Simulation time 959495746 ps
CPU time 30.98 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:52:16 PM PST 24
Peak memory 214676 kb
Host smart-472504ca-d912-4422-814b-ba1f211dc69b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848345264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1848345264
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.418426447
Short name T643
Test name
Test status
Simulation time 1986964990 ps
CPU time 21.97 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:51:53 PM PST 24
Peak memory 198760 kb
Host smart-bc790a4e-dcf7-4ff0-af86-851755ab98ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418426447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.418426447
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1569587939
Short name T538
Test name
Test status
Simulation time 1008611659 ps
CPU time 50.38 seconds
Started Jan 17 12:51:36 PM PST 24
Finished Jan 17 12:52:27 PM PST 24
Peak memory 198548 kb
Host smart-95f61487-a3ea-46dc-81db-5ff8065806a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569587939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1569587939
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3392374388
Short name T214
Test name
Test status
Simulation time 2609381268 ps
CPU time 130.18 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:53:45 PM PST 24
Peak memory 198768 kb
Host smart-3c62c7f1-dd9c-40c3-a3f2-d77e03c382b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392374388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3392374388
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.294650016
Short name T599
Test name
Test status
Simulation time 1699544666 ps
CPU time 86.71 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:52:59 PM PST 24
Peak memory 198952 kb
Host smart-d80b1941-3c7a-4214-9fdb-4a565dd1fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294650016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.294650016
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1369860
Short name T263
Test name
Test status
Simulation time 217524547 ps
CPU time 1.63 seconds
Started Jan 17 12:51:27 PM PST 24
Finished Jan 17 12:51:31 PM PST 24
Peak memory 198332 kb
Host smart-70adda19-2c75-4f9f-bba5-2740002b74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1369860
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.359587016
Short name T121
Test name
Test status
Simulation time 552283411914 ps
CPU time 1688.55 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 01:19:54 PM PST 24
Peak memory 198836 kb
Host smart-01978017-13d7-454e-aa63-c52a2011e3e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359587016 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.359587016
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.1805152188
Short name T118
Test name
Test status
Simulation time 102871392669 ps
CPU time 415.23 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 215292 kb
Host smart-ac6236e4-c592-4773-a111-f3073ed7634a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805152188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.1805152188
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.475755920
Short name T692
Test name
Test status
Simulation time 29607123 ps
CPU time 1.04 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 197176 kb
Host smart-2bdd6aac-cde4-45a8-94ca-5c19edcfdac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475755920 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.475755920
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.686546006
Short name T199
Test name
Test status
Simulation time 185868208721 ps
CPU time 507.26 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 01:00:12 PM PST 24
Peak memory 198740 kb
Host smart-7b7a6453-cb4e-4021-80d4-cc26c415482f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686546006 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_sha_vectors.686546006
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2880484819
Short name T387
Test name
Test status
Simulation time 4390095117 ps
CPU time 77.89 seconds
Started Jan 17 12:51:30 PM PST 24
Finished Jan 17 12:52:49 PM PST 24
Peak memory 198776 kb
Host smart-718ecd00-70fa-4a8d-9789-e17c2e9d4cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880484819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2880484819
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1624389354
Short name T10
Test name
Test status
Simulation time 54707570 ps
CPU time 0.57 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 193096 kb
Host smart-528ec43c-b181-461c-8a0e-b26d1e06702f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624389354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1624389354
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3197237847
Short name T741
Test name
Test status
Simulation time 279503664 ps
CPU time 9.15 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:51:53 PM PST 24
Peak memory 206492 kb
Host smart-a9395c55-1825-4856-a17c-9627ccb5c339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197237847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3197237847
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1861081652
Short name T836
Test name
Test status
Simulation time 4585068483 ps
CPU time 58.05 seconds
Started Jan 17 12:51:34 PM PST 24
Finished Jan 17 12:52:33 PM PST 24
Peak memory 198752 kb
Host smart-8a6b59bd-cece-4193-aff4-15f66201a993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861081652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1861081652
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1875237301
Short name T322
Test name
Test status
Simulation time 1209831491 ps
CPU time 14.82 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:51:49 PM PST 24
Peak memory 198768 kb
Host smart-2e7ddf62-ff27-484e-9d97-a476ec9897e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875237301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1875237301
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1538320944
Short name T548
Test name
Test status
Simulation time 30048816625 ps
CPU time 162.27 seconds
Started Jan 17 12:51:33 PM PST 24
Finished Jan 17 12:54:16 PM PST 24
Peak memory 198816 kb
Host smart-4a49bca7-5723-4cd6-988f-0ece93885166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538320944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1538320944
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.162309832
Short name T377
Test name
Test status
Simulation time 1588380665 ps
CPU time 75.95 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:53:00 PM PST 24
Peak memory 198304 kb
Host smart-98d1c6b3-863b-4a8b-9994-cd7556c8bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162309832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.162309832
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.835005523
Short name T187
Test name
Test status
Simulation time 132655210 ps
CPU time 1.32 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:51:33 PM PST 24
Peak memory 198220 kb
Host smart-8f48e980-7ba3-4819-8431-3cd45d4149bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835005523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.835005523
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1138847532
Short name T309
Test name
Test status
Simulation time 509203406701 ps
CPU time 502.66 seconds
Started Jan 17 12:51:32 PM PST 24
Finished Jan 17 12:59:56 PM PST 24
Peak memory 207016 kb
Host smart-cf399160-1ec6-4eb3-a8ff-e5151a498c14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138847532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1138847532
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2324492324
Short name T570
Test name
Test status
Simulation time 83130858051 ps
CPU time 4080.55 seconds
Started Jan 17 12:51:32 PM PST 24
Finished Jan 17 01:59:34 PM PST 24
Peak memory 248040 kb
Host smart-1c95d68c-b2aa-4039-a10b-4855cf9f1923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324492324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.2324492324
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1856776637
Short name T348
Test name
Test status
Simulation time 29432587 ps
CPU time 0.9 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:51:45 PM PST 24
Peak memory 195932 kb
Host smart-2398fbb9-cead-451d-86f0-54cf188c496d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856776637 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1856776637
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2176171728
Short name T803
Test name
Test status
Simulation time 196168110620 ps
CPU time 472.59 seconds
Started Jan 17 12:51:31 PM PST 24
Finished Jan 17 12:59:25 PM PST 24
Peak memory 198640 kb
Host smart-efb0d40f-4b31-4988-a5a3-15e62f3cf504
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176171728 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.2176171728
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.28397539
Short name T518
Test name
Test status
Simulation time 10440628290 ps
CPU time 29.82 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:52:14 PM PST 24
Peak memory 198776 kb
Host smart-6ccc8cf4-7c38-424d-9f2e-205e21165b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28397539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.28397539
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.415216854
Short name T381
Test name
Test status
Simulation time 11543953 ps
CPU time 0.59 seconds
Started Jan 17 12:51:45 PM PST 24
Finished Jan 17 12:51:56 PM PST 24
Peak memory 193116 kb
Host smart-e57c9bc5-6c1a-4d97-a333-d058c146fada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415216854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.415216854
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.173344794
Short name T373
Test name
Test status
Simulation time 2526937279 ps
CPU time 38.37 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:52:34 PM PST 24
Peak memory 207004 kb
Host smart-f1e2f554-4c65-4f89-b5fe-12089f31c586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173344794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.173344794
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.307544253
Short name T632
Test name
Test status
Simulation time 3355241431 ps
CPU time 44.59 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:52:29 PM PST 24
Peak memory 198796 kb
Host smart-27941d39-fcd8-45a1-a26e-ac897ae914fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307544253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.307544253
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.327983158
Short name T794
Test name
Test status
Simulation time 9380035437 ps
CPU time 116.91 seconds
Started Jan 17 12:51:45 PM PST 24
Finished Jan 17 12:53:52 PM PST 24
Peak memory 198756 kb
Host smart-fde84507-649e-4934-bcc9-ccc7285ca242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327983158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.327983158
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.26705567
Short name T782
Test name
Test status
Simulation time 213014082 ps
CPU time 10.61 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 12:51:56 PM PST 24
Peak memory 198672 kb
Host smart-adeff8ba-353c-4824-99eb-7815a70fbc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26705567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.26705567
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3839767494
Short name T96
Test name
Test status
Simulation time 1951870193 ps
CPU time 48.11 seconds
Started Jan 17 12:51:38 PM PST 24
Finished Jan 17 12:52:28 PM PST 24
Peak memory 198572 kb
Host smart-21b77a5b-2053-4bf4-a0c0-ce390d772301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839767494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3839767494
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1251915318
Short name T386
Test name
Test status
Simulation time 88969377 ps
CPU time 1.3 seconds
Started Jan 17 12:51:41 PM PST 24
Finished Jan 17 12:51:46 PM PST 24
Peak memory 197184 kb
Host smart-58ca9a36-86ec-4096-95a2-53d96e80d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251915318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1251915318
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2397086637
Short name T546
Test name
Test status
Simulation time 18036405721 ps
CPU time 199.81 seconds
Started Jan 17 12:51:47 PM PST 24
Finished Jan 17 12:55:16 PM PST 24
Peak memory 207060 kb
Host smart-cafcd963-0524-49f5-bd61-517c338e46cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397086637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2397086637
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.2831985092
Short name T301
Test name
Test status
Simulation time 144087509307 ps
CPU time 1629.02 seconds
Started Jan 17 12:51:47 PM PST 24
Finished Jan 17 01:19:05 PM PST 24
Peak memory 210452 kb
Host smart-db6fabbe-bd6e-4cd8-acd9-26d610a0e0d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831985092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.2831985092
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2913233355
Short name T795
Test name
Test status
Simulation time 41277722 ps
CPU time 1 seconds
Started Jan 17 12:51:42 PM PST 24
Finished Jan 17 12:51:46 PM PST 24
Peak memory 196640 kb
Host smart-af9085a5-050e-459c-9a03-c0f872fcf3fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913233355 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2913233355
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2070695747
Short name T339
Test name
Test status
Simulation time 35881600115 ps
CPU time 430.91 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:59:07 PM PST 24
Peak memory 198444 kb
Host smart-b4de70a2-c81a-4f04-b886-03bc6c5adacc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070695747 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2070695747
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.399682350
Short name T423
Test name
Test status
Simulation time 17026554808 ps
CPU time 71.46 seconds
Started Jan 17 12:51:48 PM PST 24
Finished Jan 17 12:53:07 PM PST 24
Peak memory 198828 kb
Host smart-ccfa69f2-6063-4ea2-aaf5-74a7be9f1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399682350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.399682350
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3027643560
Short name T819
Test name
Test status
Simulation time 31189585 ps
CPU time 0.58 seconds
Started Jan 17 12:51:48 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 193100 kb
Host smart-0aede4f5-001a-4325-936e-a69cb8d92703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027643560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3027643560
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1375785799
Short name T363
Test name
Test status
Simulation time 5744584460 ps
CPU time 49.36 seconds
Started Jan 17 12:51:44 PM PST 24
Finished Jan 17 12:52:35 PM PST 24
Peak memory 223404 kb
Host smart-f75e7a77-ba65-4563-a5ff-a6a7410e91f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375785799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1375785799
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1584713603
Short name T53
Test name
Test status
Simulation time 5415775528 ps
CPU time 22.49 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:52:18 PM PST 24
Peak memory 198720 kb
Host smart-f7c6783c-1450-43db-91f4-b7c4854d1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584713603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1584713603
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3647989285
Short name T656
Test name
Test status
Simulation time 140104567 ps
CPU time 3.51 seconds
Started Jan 17 12:51:47 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 198792 kb
Host smart-50ce7feb-5a16-4e99-afd5-8f15e8ae6676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647989285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3647989285
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1163535463
Short name T261
Test name
Test status
Simulation time 2597703371 ps
CPU time 34.97 seconds
Started Jan 17 12:51:45 PM PST 24
Finished Jan 17 12:52:30 PM PST 24
Peak memory 198812 kb
Host smart-527848ec-e062-4d2e-a93d-79927e56fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163535463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1163535463
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.370568443
Short name T514
Test name
Test status
Simulation time 3201320469 ps
CPU time 56.96 seconds
Started Jan 17 12:51:42 PM PST 24
Finished Jan 17 12:52:42 PM PST 24
Peak memory 198748 kb
Host smart-51618625-dd02-4e39-9107-58a2ee29f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370568443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.370568443
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.433181445
Short name T223
Test name
Test status
Simulation time 499484155 ps
CPU time 1.7 seconds
Started Jan 17 12:51:45 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198568 kb
Host smart-f3240b7d-37dd-4d5b-aee5-d93be4e33184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433181445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.433181445
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1960278372
Short name T478
Test name
Test status
Simulation time 104369577060 ps
CPU time 1257.24 seconds
Started Jan 17 12:51:43 PM PST 24
Finished Jan 17 01:12:42 PM PST 24
Peak memory 215220 kb
Host smart-2d3ebf5e-1a2c-4046-a738-1bde16c0404b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960278372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1960278372
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.1217183445
Short name T477
Test name
Test status
Simulation time 37114257048 ps
CPU time 1727.59 seconds
Started Jan 17 12:51:48 PM PST 24
Finished Jan 17 01:20:44 PM PST 24
Peak memory 215144 kb
Host smart-e3383e24-42af-4cf9-80a9-8112a261d53b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217183445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.1217183445
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3531174568
Short name T832
Test name
Test status
Simulation time 66484985 ps
CPU time 1.11 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 196264 kb
Host smart-24f6a366-cc93-4bf7-820e-5187d42dfcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531174568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3531174568
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1341097936
Short name T304
Test name
Test status
Simulation time 102792281717 ps
CPU time 400.44 seconds
Started Jan 17 12:51:49 PM PST 24
Finished Jan 17 12:58:36 PM PST 24
Peak memory 198920 kb
Host smart-b3e99c3b-e4cd-4ffa-be23-f8fa6e6ed68e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341097936 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.1341097936
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.234239786
Short name T92
Test name
Test status
Simulation time 1405040351 ps
CPU time 59.3 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:52:55 PM PST 24
Peak memory 198764 kb
Host smart-6bbea172-46ce-4cfc-ba1a-1c6195e52a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234239786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.234239786
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.4192558905
Short name T812
Test name
Test status
Simulation time 12355156 ps
CPU time 0.58 seconds
Started Jan 17 12:51:55 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 193020 kb
Host smart-fdde330f-9f5f-4a0d-a294-f982959074c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192558905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.4192558905
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1222619564
Short name T295
Test name
Test status
Simulation time 1290843813 ps
CPU time 12.23 seconds
Started Jan 17 12:51:49 PM PST 24
Finished Jan 17 12:52:08 PM PST 24
Peak memory 198752 kb
Host smart-604d56ba-39de-46dd-83fc-1099f6461613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222619564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1222619564
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1462947168
Short name T433
Test name
Test status
Simulation time 2568903225 ps
CPU time 130.06 seconds
Started Jan 17 12:51:47 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 198836 kb
Host smart-ac6283ee-4988-42f1-97b4-72176f7210ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462947168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1462947168
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.275591463
Short name T608
Test name
Test status
Simulation time 2573451879 ps
CPU time 122.72 seconds
Started Jan 17 12:51:45 PM PST 24
Finished Jan 17 12:53:58 PM PST 24
Peak memory 198696 kb
Host smart-b64e84a3-9725-4395-8bd2-156eacbab540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275591463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.275591463
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1439953267
Short name T430
Test name
Test status
Simulation time 3392363352 ps
CPU time 3.26 seconds
Started Jan 17 12:51:50 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 198744 kb
Host smart-0d8e7089-80c3-4ed8-a844-56c2e12688aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439953267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1439953267
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.575098134
Short name T272
Test name
Test status
Simulation time 675792461 ps
CPU time 3.18 seconds
Started Jan 17 12:51:46 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 198488 kb
Host smart-194067f1-e914-4241-a6fc-6d65c18f104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575098134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.575098134
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3353070364
Short name T108
Test name
Test status
Simulation time 128757744372 ps
CPU time 2070.61 seconds
Started Jan 17 12:51:55 PM PST 24
Finished Jan 17 01:26:28 PM PST 24
Peak memory 231616 kb
Host smart-3f61a8d0-bdcb-4b5d-b0d1-9a0a7a74e5fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353070364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3353070364
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.2109441782
Short name T415
Test name
Test status
Simulation time 365687432014 ps
CPU time 2957.21 seconds
Started Jan 17 12:51:54 PM PST 24
Finished Jan 17 01:41:14 PM PST 24
Peak memory 256496 kb
Host smart-1308e970-f8da-43c6-827c-451f8e929eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109441782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.2109441782
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3214271511
Short name T325
Test name
Test status
Simulation time 62303101 ps
CPU time 1.22 seconds
Started Jan 17 12:52:12 PM PST 24
Finished Jan 17 12:52:14 PM PST 24
Peak memory 197252 kb
Host smart-26227e06-5a8a-4b48-b447-80fabf00ad42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214271511 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3214271511
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.434063978
Short name T369
Test name
Test status
Simulation time 56737887620 ps
CPU time 487.43 seconds
Started Jan 17 12:51:49 PM PST 24
Finished Jan 17 01:00:03 PM PST 24
Peak memory 198716 kb
Host smart-385a6659-d906-43cc-ad9e-d441d4f4a1a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434063978 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.hmac_test_sha_vectors.434063978
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1396696040
Short name T390
Test name
Test status
Simulation time 6039618679 ps
CPU time 60.95 seconds
Started Jan 17 12:51:49 PM PST 24
Finished Jan 17 12:52:57 PM PST 24
Peak memory 198800 kb
Host smart-352b14d6-a99b-4908-8cad-36429d1539ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396696040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1396696040
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.518940827
Short name T249
Test name
Test status
Simulation time 31519727 ps
CPU time 0.58 seconds
Started Jan 17 12:51:59 PM PST 24
Finished Jan 17 12:52:00 PM PST 24
Peak memory 194108 kb
Host smart-efbfa8f4-f77c-4fd5-b7f5-218fee24ba32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518940827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.518940827
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3646840718
Short name T619
Test name
Test status
Simulation time 461734717 ps
CPU time 17.8 seconds
Started Jan 17 12:52:00 PM PST 24
Finished Jan 17 12:52:21 PM PST 24
Peak memory 231392 kb
Host smart-314211ba-aaf8-49e2-a9ed-9d571e0cd1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646840718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3646840718
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3183271150
Short name T550
Test name
Test status
Simulation time 1293923771 ps
CPU time 15.64 seconds
Started Jan 17 12:51:54 PM PST 24
Finished Jan 17 12:52:12 PM PST 24
Peak memory 198728 kb
Host smart-9730198c-7502-4cef-9510-ca1b21d4848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183271150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3183271150
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2863876792
Short name T353
Test name
Test status
Simulation time 230590532 ps
CPU time 3.28 seconds
Started Jan 17 12:51:56 PM PST 24
Finished Jan 17 12:52:01 PM PST 24
Peak memory 198724 kb
Host smart-16c1af4a-c27d-4016-ac6d-eacae0fa8a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863876792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2863876792
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2089605968
Short name T271
Test name
Test status
Simulation time 722298119 ps
CPU time 8.53 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:52:07 PM PST 24
Peak memory 198664 kb
Host smart-0f1f2e79-6895-454b-aeaa-0fba027005eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089605968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2089605968
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.469950789
Short name T672
Test name
Test status
Simulation time 16204678570 ps
CPU time 69.45 seconds
Started Jan 17 12:51:54 PM PST 24
Finished Jan 17 12:53:05 PM PST 24
Peak memory 198840 kb
Host smart-30409402-ebff-4917-86df-2ea06a87c410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469950789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.469950789
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2067892199
Short name T640
Test name
Test status
Simulation time 95833968 ps
CPU time 1.02 seconds
Started Jan 17 12:51:54 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 198128 kb
Host smart-70078080-8860-4252-8843-c39069955f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067892199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2067892199
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.863454317
Short name T646
Test name
Test status
Simulation time 13351590187 ps
CPU time 183.26 seconds
Started Jan 17 12:51:53 PM PST 24
Finished Jan 17 12:54:59 PM PST 24
Peak memory 207056 kb
Host smart-15e292bc-b6cd-4339-9f3a-a6d16632148d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863454317 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.863454317
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.187158439
Short name T843
Test name
Test status
Simulation time 64962259 ps
CPU time 0.88 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 195780 kb
Host smart-25db7f47-074a-4467-b251-db92c90ca4bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187158439 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.187158439
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2230904248
Short name T51
Test name
Test status
Simulation time 68334824301 ps
CPU time 367.31 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:58:05 PM PST 24
Peak memory 198836 kb
Host smart-99dd755a-252c-4e1b-907c-c1a1446555cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230904248 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.2230904248
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2698760430
Short name T810
Test name
Test status
Simulation time 12534480277 ps
CPU time 46.33 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:52:44 PM PST 24
Peak memory 198740 kb
Host smart-772c3884-afda-496f-948f-3a96ad6701fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698760430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2698760430
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.809850941
Short name T816
Test name
Test status
Simulation time 11473885 ps
CPU time 0.57 seconds
Started Jan 17 12:52:01 PM PST 24
Finished Jan 17 12:52:04 PM PST 24
Peak memory 193132 kb
Host smart-23a287b8-7133-42b4-98e3-4718dd9da314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809850941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.809850941
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2716230281
Short name T266
Test name
Test status
Simulation time 5126215905 ps
CPU time 31.09 seconds
Started Jan 17 12:51:58 PM PST 24
Finished Jan 17 12:52:30 PM PST 24
Peak memory 215204 kb
Host smart-65de94d5-dd1d-464a-a633-f659659eb32b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716230281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2716230281
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2680835888
Short name T683
Test name
Test status
Simulation time 487889749 ps
CPU time 17.1 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 12:52:22 PM PST 24
Peak memory 198640 kb
Host smart-4a881af4-a6f2-4aed-8711-b399d78502aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680835888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2680835888
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3557929419
Short name T95
Test name
Test status
Simulation time 1521722688 ps
CPU time 82.52 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 12:53:38 PM PST 24
Peak memory 198768 kb
Host smart-0e293876-ba94-473b-9418-9e6709eca917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557929419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3557929419
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.125147050
Short name T702
Test name
Test status
Simulation time 513070236 ps
CPU time 26.05 seconds
Started Jan 17 12:51:54 PM PST 24
Finished Jan 17 12:52:22 PM PST 24
Peak memory 198764 kb
Host smart-7eec700f-1bdc-46c8-8591-886fd60ea2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125147050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.125147050
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3672843961
Short name T505
Test name
Test status
Simulation time 1523569338 ps
CPU time 80.75 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:53:19 PM PST 24
Peak memory 198804 kb
Host smart-78f02511-3ac1-4164-aa69-c8eddb2733fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672843961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3672843961
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2239643658
Short name T495
Test name
Test status
Simulation time 44978127 ps
CPU time 1.02 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 12:52:04 PM PST 24
Peak memory 196176 kb
Host smart-01e0e736-3910-48e0-862f-358455036775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239643658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2239643658
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1318694511
Short name T293
Test name
Test status
Simulation time 65186662368 ps
CPU time 1052.99 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 01:09:37 PM PST 24
Peak memory 218408 kb
Host smart-c723e3dc-1037-45d9-8001-b4a3da30e6a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318694511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1318694511
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.3439098547
Short name T112
Test name
Test status
Simulation time 103122654012 ps
CPU time 465.85 seconds
Started Jan 17 12:52:03 PM PST 24
Finished Jan 17 12:59:50 PM PST 24
Peak memory 207360 kb
Host smart-9da908fa-71b6-4436-b9fe-54ac1966ad02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439098547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.3439098547
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1769303754
Short name T231
Test name
Test status
Simulation time 41280991 ps
CPU time 1.02 seconds
Started Jan 17 12:51:59 PM PST 24
Finished Jan 17 12:52:01 PM PST 24
Peak memory 195964 kb
Host smart-6f5766c2-69d9-448e-9f97-b25454ad3fe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769303754 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1769303754
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1977353104
Short name T846
Test name
Test status
Simulation time 62506376365 ps
CPU time 364.75 seconds
Started Jan 17 12:52:03 PM PST 24
Finished Jan 17 12:58:09 PM PST 24
Peak memory 198776 kb
Host smart-3eaa9754-1ee9-483e-9f3b-d6cc19358429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977353104 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1977353104
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.228172520
Short name T744
Test name
Test status
Simulation time 10607856247 ps
CPU time 46.53 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 12:52:50 PM PST 24
Peak memory 198736 kb
Host smart-6e2b3afb-0841-4a18-a247-19870b3bf7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228172520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.228172520
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.732308035
Short name T270
Test name
Test status
Simulation time 14163322 ps
CPU time 0.57 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 193068 kb
Host smart-2c2cdcd5-98ed-4ad9-9a72-a34dc8cc1a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732308035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.732308035
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3945718436
Short name T251
Test name
Test status
Simulation time 466440894 ps
CPU time 14.93 seconds
Started Jan 17 12:51:55 PM PST 24
Finished Jan 17 12:52:11 PM PST 24
Peak memory 215176 kb
Host smart-f6325860-04d4-4388-b9c1-a66f854166b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945718436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3945718436
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3478902148
Short name T483
Test name
Test status
Simulation time 22153378 ps
CPU time 0.62 seconds
Started Jan 17 12:51:55 PM PST 24
Finished Jan 17 12:51:57 PM PST 24
Peak memory 193448 kb
Host smart-338708d7-5a6b-490c-abd3-cb417af0e4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478902148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3478902148
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2104489328
Short name T842
Test name
Test status
Simulation time 719667984 ps
CPU time 18.53 seconds
Started Jan 17 12:52:00 PM PST 24
Finished Jan 17 12:52:22 PM PST 24
Peak memory 198788 kb
Host smart-4776a3f2-a6f3-41fa-ad08-3c8ca0706c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104489328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2104489328
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1038736273
Short name T506
Test name
Test status
Simulation time 2610362155 ps
CPU time 133.56 seconds
Started Jan 17 12:52:01 PM PST 24
Finished Jan 17 12:54:17 PM PST 24
Peak memory 198764 kb
Host smart-96b05e1f-4aae-4dc6-8ab0-b0be968f1191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038736273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1038736273
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3836009183
Short name T246
Test name
Test status
Simulation time 54869628936 ps
CPU time 82.06 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 12:53:25 PM PST 24
Peak memory 198812 kb
Host smart-abe2cd93-97c4-4fd0-adaa-96a4da1121a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836009183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3836009183
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1615943329
Short name T294
Test name
Test status
Simulation time 3272302212 ps
CPU time 3.03 seconds
Started Jan 17 12:51:57 PM PST 24
Finished Jan 17 12:52:01 PM PST 24
Peak memory 198708 kb
Host smart-4e2cc470-2293-4291-b566-65bd3e66da2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615943329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1615943329
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.504896141
Short name T195
Test name
Test status
Simulation time 124945222198 ps
CPU time 1000.31 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 01:08:44 PM PST 24
Peak memory 198824 kb
Host smart-0729086f-6b2c-4bd2-ba62-26ce1ac1509a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504896141 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.504896141
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.385181181
Short name T516
Test name
Test status
Simulation time 109721486067 ps
CPU time 424.99 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 12:59:10 PM PST 24
Peak memory 225416 kb
Host smart-19570696-c208-434a-a670-c6b229b299b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385181181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.385181181
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.307630497
Short name T318
Test name
Test status
Simulation time 75863866 ps
CPU time 1.03 seconds
Started Jan 17 12:52:00 PM PST 24
Finished Jan 17 12:52:03 PM PST 24
Peak memory 197392 kb
Host smart-1fb43712-cbb5-45f2-b9f0-c639a8df08e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307630497 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.307630497
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2444262802
Short name T55
Test name
Test status
Simulation time 24060210369 ps
CPU time 388.39 seconds
Started Jan 17 12:52:00 PM PST 24
Finished Jan 17 12:58:31 PM PST 24
Peak memory 198716 kb
Host smart-17a6b616-279f-417b-b593-ee39e4da0e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444262802 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2444262802
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2336454531
Short name T610
Test name
Test status
Simulation time 4695441441 ps
CPU time 36.4 seconds
Started Jan 17 12:52:01 PM PST 24
Finished Jan 17 12:52:39 PM PST 24
Peak memory 198816 kb
Host smart-5a33543b-cf03-4edd-8401-a9cfbbfd4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336454531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2336454531
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3896252447
Short name T576
Test name
Test status
Simulation time 11447668 ps
CPU time 0.62 seconds
Started Jan 17 12:52:06 PM PST 24
Finished Jan 17 12:52:08 PM PST 24
Peak memory 193112 kb
Host smart-31b8611e-f384-4fba-a1ff-a156bec9dfe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896252447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3896252447
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2097056657
Short name T500
Test name
Test status
Simulation time 1253627571 ps
CPU time 45.11 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 12:53:00 PM PST 24
Peak memory 231264 kb
Host smart-75aab15b-f8e9-41b7-9f1d-f49e1f60b5e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097056657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2097056657
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2644294424
Short name T559
Test name
Test status
Simulation time 13868293787 ps
CPU time 51.04 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 12:52:56 PM PST 24
Peak memory 198668 kb
Host smart-95db5bd1-0dc7-4a1d-b0e7-0724e69a72f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644294424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2644294424
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2712147963
Short name T185
Test name
Test status
Simulation time 517146295 ps
CPU time 26.37 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 12:52:32 PM PST 24
Peak memory 198676 kb
Host smart-5d94d1da-c778-4e4b-bd13-e9e036b23e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712147963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2712147963
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.765181250
Short name T400
Test name
Test status
Simulation time 1344798538 ps
CPU time 16.16 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 12:52:20 PM PST 24
Peak memory 198612 kb
Host smart-9685740f-b88b-4ae7-8190-25e0f8506b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765181250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.765181250
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.133522812
Short name T238
Test name
Test status
Simulation time 654110071 ps
CPU time 35.56 seconds
Started Jan 17 12:52:03 PM PST 24
Finished Jan 17 12:52:39 PM PST 24
Peak memory 198744 kb
Host smart-828b3571-f466-418b-aa0d-85f1bb874e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133522812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.133522812
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2586304913
Short name T230
Test name
Test status
Simulation time 389449086 ps
CPU time 2.88 seconds
Started Jan 17 12:52:02 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 198608 kb
Host smart-026b766d-6e7c-4585-b046-71d51574922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586304913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2586304913
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3153122188
Short name T334
Test name
Test status
Simulation time 33323027538 ps
CPU time 396.97 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 12:58:46 PM PST 24
Peak memory 227840 kb
Host smart-5349df3d-9826-4826-b29f-75fcf2857dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153122188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3153122188
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.192420344
Short name T117
Test name
Test status
Simulation time 108608492008 ps
CPU time 2654.8 seconds
Started Jan 17 12:52:06 PM PST 24
Finished Jan 17 01:36:22 PM PST 24
Peak memory 246228 kb
Host smart-e0e87bd9-6158-4f42-bc7c-4b287b5a7d2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192420344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.192420344
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3041503414
Short name T234
Test name
Test status
Simulation time 51840795 ps
CPU time 0.96 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 12:52:06 PM PST 24
Peak memory 195732 kb
Host smart-502298e1-8bfc-47e3-8150-aa17d71f0ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041503414 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3041503414
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2099225455
Short name T799
Test name
Test status
Simulation time 20959780841 ps
CPU time 388.99 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 198744 kb
Host smart-4aec5b30-cb07-4814-a190-7b3d61b1a8ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099225455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.2099225455
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.609492691
Short name T582
Test name
Test status
Simulation time 1293642812 ps
CPU time 11.36 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 12:52:20 PM PST 24
Peak memory 198704 kb
Host smart-4bfefe6c-118d-432b-a051-f4dda3221337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609492691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.609492691
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.802581797
Short name T407
Test name
Test status
Simulation time 13981304 ps
CPU time 0.58 seconds
Started Jan 17 12:52:07 PM PST 24
Finished Jan 17 12:52:09 PM PST 24
Peak memory 193080 kb
Host smart-82c1b7a7-1970-4121-a2e1-b009c80326bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802581797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.802581797
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1421783092
Short name T463
Test name
Test status
Simulation time 946363148 ps
CPU time 23.34 seconds
Started Jan 17 12:52:06 PM PST 24
Finished Jan 17 12:52:31 PM PST 24
Peak memory 198756 kb
Host smart-a5ad0c81-e22b-4468-af5a-fabae217c700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421783092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1421783092
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3778531295
Short name T352
Test name
Test status
Simulation time 2586011674 ps
CPU time 12.15 seconds
Started Jan 17 12:52:10 PM PST 24
Finished Jan 17 12:52:23 PM PST 24
Peak memory 198760 kb
Host smart-a69a5858-6e14-41e5-86ba-997eb7711e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778531295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3778531295
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.196508979
Short name T40
Test name
Test status
Simulation time 9325198063 ps
CPU time 100.65 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 12:53:46 PM PST 24
Peak memory 198708 kb
Host smart-8de39b0a-30da-4dea-a0b4-09dcc0d96b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196508979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.196508979
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.177910001
Short name T336
Test name
Test status
Simulation time 2518338559 ps
CPU time 28.5 seconds
Started Jan 17 12:52:03 PM PST 24
Finished Jan 17 12:52:32 PM PST 24
Peak memory 198900 kb
Host smart-99e895e2-477f-49bc-bc6b-0904be7c2738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177910001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.177910001
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1491962291
Short name T274
Test name
Test status
Simulation time 628908735 ps
CPU time 26.77 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 12:52:40 PM PST 24
Peak memory 198696 kb
Host smart-d1e0acc7-d2f3-49d6-a8ec-35c876447ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491962291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1491962291
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2679522682
Short name T354
Test name
Test status
Simulation time 24867872 ps
CPU time 0.79 seconds
Started Jan 17 12:52:11 PM PST 24
Finished Jan 17 12:52:13 PM PST 24
Peak memory 194636 kb
Host smart-8e043c53-b968-4bcf-9bf7-317e129e8d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679522682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2679522682
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1664851871
Short name T401
Test name
Test status
Simulation time 41849431244 ps
CPU time 503.1 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 01:00:38 PM PST 24
Peak memory 231576 kb
Host smart-8d2db400-25cf-43fc-a47d-0be1fe08c2df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664851871 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1664851871
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.3505407595
Short name T698
Test name
Test status
Simulation time 16651813177 ps
CPU time 701.34 seconds
Started Jan 17 12:52:10 PM PST 24
Finished Jan 17 01:03:53 PM PST 24
Peak memory 236236 kb
Host smart-c5822c39-cc7f-49c2-8a2c-0d8ebbf7b3cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505407595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.3505407595
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1530750618
Short name T183
Test name
Test status
Simulation time 26099688 ps
CPU time 0.92 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 12:52:07 PM PST 24
Peak memory 196456 kb
Host smart-9339cee9-84dc-4b26-a1e4-bcd7e8e7cc8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530750618 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1530750618
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2677267229
Short name T771
Test name
Test status
Simulation time 7867091309 ps
CPU time 403.48 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 12:58:57 PM PST 24
Peak memory 198720 kb
Host smart-fe81b144-3eec-4bbd-b76d-c90d5a3d6fac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677267229 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.2677267229
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.8050692
Short name T645
Test name
Test status
Simulation time 29094086963 ps
CPU time 46.13 seconds
Started Jan 17 12:52:04 PM PST 24
Finished Jan 17 12:52:51 PM PST 24
Peak memory 198180 kb
Host smart-12128e54-ce04-4638-80f3-7b8795c7aa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8050692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.8050692
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.294484557
Short name T327
Test name
Test status
Simulation time 11196336 ps
CPU time 0.59 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 193060 kb
Host smart-7d6ea6fb-c26c-446c-b59b-eb07058f1803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294484557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.294484557
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3579437195
Short name T250
Test name
Test status
Simulation time 1013633340 ps
CPU time 17.43 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 219384 kb
Host smart-de8c0d7d-6db2-496e-987d-7c5a6f7df8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579437195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3579437195
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3437355462
Short name T664
Test name
Test status
Simulation time 375461238 ps
CPU time 2.66 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 198720 kb
Host smart-87735b5d-4d64-441e-b89a-f4aaf98967fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437355462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3437355462
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.526850028
Short name T276
Test name
Test status
Simulation time 620635705 ps
CPU time 31.87 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:51 PM PST 24
Peak memory 198724 kb
Host smart-d3fb8d48-8469-496d-beeb-fc14410cd75a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526850028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.526850028
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2271896291
Short name T398
Test name
Test status
Simulation time 10053326740 ps
CPU time 127.08 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:52:32 PM PST 24
Peak memory 198868 kb
Host smart-c52b6d89-ad7b-42d1-a50a-64d22c504388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271896291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2271896291
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1046050765
Short name T484
Test name
Test status
Simulation time 2378964200 ps
CPU time 29.65 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 198820 kb
Host smart-1fff3a6d-b302-44c7-a9a8-d1a73b473bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046050765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1046050765
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4085874452
Short name T54
Test name
Test status
Simulation time 4916538415 ps
CPU time 4.21 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:29 PM PST 24
Peak memory 198728 kb
Host smart-2f8c129b-06cd-4f70-b854-a502134c1524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085874452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4085874452
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.258394145
Short name T385
Test name
Test status
Simulation time 4105046936 ps
CPU time 63.17 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:51:28 PM PST 24
Peak memory 198792 kb
Host smart-00d6254b-5a65-46bc-9913-bdaf47f45b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258394145 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.258394145
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3296481194
Short name T288
Test name
Test status
Simulation time 64260930592 ps
CPU time 1043.38 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 01:07:35 PM PST 24
Peak memory 248048 kb
Host smart-678dd2da-11ce-4549-9ad1-a3d517676870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296481194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3296481194
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2710276438
Short name T206
Test name
Test status
Simulation time 130884288 ps
CPU time 0.92 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 195940 kb
Host smart-e8a45232-b3bc-49aa-9cda-6b7d498b52ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710276438 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2710276438
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3153567616
Short name T341
Test name
Test status
Simulation time 30267963594 ps
CPU time 369.09 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:56:34 PM PST 24
Peak memory 198704 kb
Host smart-430b3ae9-e3a2-4c48-abd4-a96ab0d9eca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153567616 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.3153567616
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4112881284
Short name T755
Test name
Test status
Simulation time 1269887674 ps
CPU time 15.13 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:50:40 PM PST 24
Peak memory 198672 kb
Host smart-e81f326c-b0e4-427a-a896-6c42d2f400fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112881284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4112881284
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.2831338037
Short name T260
Test name
Test status
Simulation time 217875874451 ps
CPU time 2609.33 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 01:35:45 PM PST 24
Peak memory 250112 kb
Host smart-94566d36-df0a-4686-a79a-d36c31997419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831338037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.2831338037
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1070491140
Short name T391
Test name
Test status
Simulation time 331412798661 ps
CPU time 1830.06 seconds
Started Jan 17 12:52:07 PM PST 24
Finished Jan 17 01:22:38 PM PST 24
Peak memory 245988 kb
Host smart-3aec1bcd-4390-4d64-9f76-5104bbb3a045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070491140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.1070491140
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.1825474270
Short name T243
Test name
Test status
Simulation time 69774660669 ps
CPU time 654.19 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 01:03:08 PM PST 24
Peak memory 214380 kb
Host smart-4ff86e6b-365f-4f71-ab24-fdc279221a9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825474270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.1825474270
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3918458701
Short name T110
Test name
Test status
Simulation time 116113013669 ps
CPU time 561.77 seconds
Started Jan 17 12:54:35 PM PST 24
Finished Jan 17 01:03:57 PM PST 24
Peak memory 242952 kb
Host smart-2ee22ba3-1d98-44d3-ad20-6b792b32329f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918458701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.3918458701
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.859622140
Short name T94
Test name
Test status
Simulation time 211986174571 ps
CPU time 3216.08 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 01:45:45 PM PST 24
Peak memory 244844 kb
Host smart-45e5f423-9e79-468d-99db-c008a69108c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859622140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.859622140
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3346004874
Short name T805
Test name
Test status
Simulation time 49420925795 ps
CPU time 2382.08 seconds
Started Jan 17 12:52:14 PM PST 24
Finished Jan 17 01:31:59 PM PST 24
Peak memory 246784 kb
Host smart-a08a5788-c44b-4ccf-85d4-33b6463484ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346004874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.3346004874
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.914972587
Short name T653
Test name
Test status
Simulation time 1409476413240 ps
CPU time 2438.91 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 01:32:47 PM PST 24
Peak memory 255304 kb
Host smart-46fc57da-1aa1-4486-a032-cc62a05b77e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914972587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.914972587
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3964631057
Short name T847
Test name
Test status
Simulation time 338893731935 ps
CPU time 1528.5 seconds
Started Jan 17 12:52:08 PM PST 24
Finished Jan 17 01:17:38 PM PST 24
Peak memory 245176 kb
Host smart-a7d82d07-0749-43b3-ac5b-89b42a2cf22e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964631057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.3964631057
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1910013767
Short name T586
Test name
Test status
Simulation time 31667849 ps
CPU time 0.56 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 193112 kb
Host smart-1036eba2-fe12-4a3a-800e-32386dcad68c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910013767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1910013767
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3611857421
Short name T393
Test name
Test status
Simulation time 3309805670 ps
CPU time 21.58 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 12:50:47 PM PST 24
Peak memory 207948 kb
Host smart-938a6cd7-0d0a-4c1c-8391-ad89c0e0e0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611857421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3611857421
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1405605893
Short name T259
Test name
Test status
Simulation time 1337563730 ps
CPU time 57.86 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:51:21 PM PST 24
Peak memory 198920 kb
Host smart-e28e970d-3b42-42c8-952d-c45cef86d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405605893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1405605893
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.873078897
Short name T283
Test name
Test status
Simulation time 5308945358 ps
CPU time 67.23 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:51:32 PM PST 24
Peak memory 198792 kb
Host smart-3fd40114-937c-48fb-9f36-171393060552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873078897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.873078897
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1390341936
Short name T817
Test name
Test status
Simulation time 13466268968 ps
CPU time 104.85 seconds
Started Jan 17 12:50:29 PM PST 24
Finished Jan 17 12:52:15 PM PST 24
Peak memory 198788 kb
Host smart-aa5145a7-af73-49d0-b97e-6f0ef5a300ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390341936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1390341936
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1938029101
Short name T524
Test name
Test status
Simulation time 36546048633 ps
CPU time 78.07 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:51:43 PM PST 24
Peak memory 198796 kb
Host smart-0fae7665-ae5d-4de8-8b72-e7926cc9e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938029101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1938029101
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2546741273
Short name T770
Test name
Test status
Simulation time 435304199 ps
CPU time 1.89 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 197320 kb
Host smart-5126ff37-723f-48bf-9f7c-e9cabf49f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546741273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2546741273
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3301019693
Short name T459
Test name
Test status
Simulation time 446377756730 ps
CPU time 1305.37 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 01:12:10 PM PST 24
Peak memory 229504 kb
Host smart-c5713f7d-8cb6-4080-8be1-f165e76ade4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301019693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3301019693
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2893149656
Short name T809
Test name
Test status
Simulation time 221931922658 ps
CPU time 1910.17 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 01:22:15 PM PST 24
Peak memory 226756 kb
Host smart-0474602f-5354-4903-bea9-81dc2a3d2433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893149656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2893149656
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.377583943
Short name T530
Test name
Test status
Simulation time 191749331 ps
CPU time 1.12 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:50:34 PM PST 24
Peak memory 196084 kb
Host smart-202cb142-8f80-4f1f-8b3a-29a2ddf6dc9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377583943 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.377583943
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.4144718817
Short name T412
Test name
Test status
Simulation time 74598076746 ps
CPU time 448.53 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:57:54 PM PST 24
Peak memory 198588 kb
Host smart-b8287829-4eb6-4a14-bfb6-d1d8d88ecf5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144718817 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.4144718817
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2516224795
Short name T492
Test name
Test status
Simulation time 3350067485 ps
CPU time 28.96 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198796 kb
Host smart-69b44e78-9c50-4e43-bc57-71f609e2da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516224795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2516224795
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.2776025761
Short name T116
Test name
Test status
Simulation time 950342598528 ps
CPU time 1023.72 seconds
Started Jan 17 12:52:11 PM PST 24
Finished Jan 17 01:09:16 PM PST 24
Peak memory 252764 kb
Host smart-c9ec735c-a1e1-4074-8163-253df0e222c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776025761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.2776025761
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.1462631366
Short name T605
Test name
Test status
Simulation time 42268740766 ps
CPU time 298.82 seconds
Started Jan 17 12:52:06 PM PST 24
Finished Jan 17 12:57:06 PM PST 24
Peak memory 239924 kb
Host smart-bc52bd9a-330f-44e7-88b7-e2d955964897
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462631366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.1462631366
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.1552530116
Short name T763
Test name
Test status
Simulation time 73384251614 ps
CPU time 345.81 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 12:57:52 PM PST 24
Peak memory 246968 kb
Host smart-f6de0166-b110-4590-aabb-2e14d811a6b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552530116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.1552530116
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.1682952491
Short name T481
Test name
Test status
Simulation time 175536618420 ps
CPU time 848.66 seconds
Started Jan 17 12:52:05 PM PST 24
Finished Jan 17 01:06:15 PM PST 24
Peak memory 231660 kb
Host smart-bb6d5f23-8189-4185-aa2a-7bf9084e4404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682952491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.1682952491
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2117133907
Short name T838
Test name
Test status
Simulation time 101347985525 ps
CPU time 915.35 seconds
Started Jan 17 12:52:10 PM PST 24
Finished Jan 17 01:07:27 PM PST 24
Peak memory 231652 kb
Host smart-cf07a312-0643-4451-93b4-f9fe2c081431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117133907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2117133907
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.1842026908
Short name T807
Test name
Test status
Simulation time 62696212154 ps
CPU time 1161.35 seconds
Started Jan 17 12:52:12 PM PST 24
Finished Jan 17 01:11:34 PM PST 24
Peak memory 203260 kb
Host smart-0f6009f6-e892-4f60-b0ab-ca4ee66fc0af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842026908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.1842026908
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.1636325175
Short name T841
Test name
Test status
Simulation time 44727620803 ps
CPU time 1070.59 seconds
Started Jan 17 12:52:15 PM PST 24
Finished Jan 17 01:10:08 PM PST 24
Peak memory 231648 kb
Host smart-e21a083c-d1a4-4c6c-a221-829f634ed422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636325175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.1636325175
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1491142142
Short name T790
Test name
Test status
Simulation time 107880043744 ps
CPU time 470.97 seconds
Started Jan 17 12:52:17 PM PST 24
Finished Jan 17 01:00:11 PM PST 24
Peak memory 215296 kb
Host smart-eb461f9c-ce27-4d77-9ab2-f9de97dee7fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491142142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.1491142142
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.2817966624
Short name T4
Test name
Test status
Simulation time 26735944752 ps
CPU time 345.5 seconds
Started Jan 17 12:52:23 PM PST 24
Finished Jan 17 12:58:14 PM PST 24
Peak memory 215284 kb
Host smart-e5bc3c60-3a25-42b6-b2f9-f5cb6de08f18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817966624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.2817966624
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.1307173222
Short name T286
Test name
Test status
Simulation time 25495194063 ps
CPU time 597.88 seconds
Started Jan 17 12:52:15 PM PST 24
Finished Jan 17 01:02:15 PM PST 24
Peak memory 234748 kb
Host smart-d95f2ed6-8eef-476f-a1f2-8ca3f0dfb3de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307173222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.1307173222
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3368931570
Short name T552
Test name
Test status
Simulation time 122338370 ps
CPU time 0.59 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 192860 kb
Host smart-f7871509-673c-4fcd-95db-b64d84634dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368931570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3368931570
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2730470444
Short name T712
Test name
Test status
Simulation time 187769408 ps
CPU time 5.72 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:50:28 PM PST 24
Peak memory 198700 kb
Host smart-3c5e005b-1e60-46e2-aa15-014dc1196eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730470444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2730470444
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4208466545
Short name T659
Test name
Test status
Simulation time 3060351494 ps
CPU time 15.6 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:50:48 PM PST 24
Peak memory 198816 kb
Host smart-71570ad7-5e90-483f-89aa-43dd4323b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208466545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4208466545
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1345859807
Short name T507
Test name
Test status
Simulation time 1686084018 ps
CPU time 87.13 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:51:52 PM PST 24
Peak memory 198660 kb
Host smart-b67e8a34-089e-4936-8e67-f888acdbc1bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345859807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1345859807
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1006196461
Short name T299
Test name
Test status
Simulation time 1086948433 ps
CPU time 13.01 seconds
Started Jan 17 12:50:33 PM PST 24
Finished Jan 17 12:50:47 PM PST 24
Peak memory 198548 kb
Host smart-c80fcf41-441c-49e3-823f-25e3f5e3b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006196461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1006196461
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2534842088
Short name T555
Test name
Test status
Simulation time 864316212 ps
CPU time 7.07 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 198568 kb
Host smart-e81268d4-c6b0-4ee1-b645-e69d79d6ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534842088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2534842088
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3288342381
Short name T368
Test name
Test status
Simulation time 111558883 ps
CPU time 1.34 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 197936 kb
Host smart-1fd27f53-bdd9-4780-a28c-4268d8054c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288342381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3288342381
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1921548171
Short name T378
Test name
Test status
Simulation time 6030778061 ps
CPU time 243.13 seconds
Started Jan 17 12:50:31 PM PST 24
Finished Jan 17 12:54:35 PM PST 24
Peak memory 238924 kb
Host smart-06060db1-9262-4d5c-8224-e0b6ae3ed1f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921548171 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1921548171
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.4037122614
Short name T394
Test name
Test status
Simulation time 23164086206 ps
CPU time 449.6 seconds
Started Jan 17 12:50:10 PM PST 24
Finished Jan 17 12:57:53 PM PST 24
Peak memory 231968 kb
Host smart-91129f4c-d14e-4670-bfb6-ec2454c8f74d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037122614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4037122614
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2652045634
Short name T245
Test name
Test status
Simulation time 42918137 ps
CPU time 0.95 seconds
Started Jan 17 12:50:29 PM PST 24
Finished Jan 17 12:50:31 PM PST 24
Peak memory 195952 kb
Host smart-840fe7dc-5558-48e9-9362-5e849379866e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652045634 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2652045634
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3668206844
Short name T684
Test name
Test status
Simulation time 30872187547 ps
CPU time 389.56 seconds
Started Jan 17 12:50:22 PM PST 24
Finished Jan 17 12:56:56 PM PST 24
Peak memory 198636 kb
Host smart-e83b0666-c837-43ec-acb7-219da2f77f4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668206844 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.3668206844
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3634782240
Short name T699
Test name
Test status
Simulation time 25682487109 ps
CPU time 56.37 seconds
Started Jan 17 12:50:32 PM PST 24
Finished Jan 17 12:51:30 PM PST 24
Peak memory 198800 kb
Host smart-c9692328-a53c-43b8-9821-75eef0f3001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634782240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3634782240
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2556021507
Short name T517
Test name
Test status
Simulation time 387804979969 ps
CPU time 2892.98 seconds
Started Jan 17 12:52:14 PM PST 24
Finished Jan 17 01:40:30 PM PST 24
Peak memory 231680 kb
Host smart-71b839d6-f842-44d9-901e-e87a1c7bbd19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556021507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2556021507
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.4158448921
Short name T321
Test name
Test status
Simulation time 76868517309 ps
CPU time 3795.26 seconds
Started Jan 17 12:52:15 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 256216 kb
Host smart-e78aaf8e-4aeb-4101-a767-8da22fa36a74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158448921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.4158448921
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.534740881
Short name T323
Test name
Test status
Simulation time 6791776754 ps
CPU time 351.78 seconds
Started Jan 17 12:52:17 PM PST 24
Finished Jan 17 12:58:11 PM PST 24
Peak memory 207088 kb
Host smart-46c09960-d909-4392-b4c6-5c5a1f93beb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534740881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.534740881
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.1576240753
Short name T797
Test name
Test status
Simulation time 80925415775 ps
CPU time 2586.41 seconds
Started Jan 17 12:52:17 PM PST 24
Finished Jan 17 01:35:26 PM PST 24
Peak memory 248052 kb
Host smart-55be1a91-8f1e-4f90-b1d5-ae02c3bfe5c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576240753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.1576240753
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.20077131
Short name T364
Test name
Test status
Simulation time 406741182011 ps
CPU time 1328.64 seconds
Started Jan 17 12:52:11 PM PST 24
Finished Jan 17 01:14:21 PM PST 24
Peak memory 255972 kb
Host smart-8a3340c2-390a-4f3f-8b49-ed53ee086ddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20077131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.20077131
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.223396572
Short name T833
Test name
Test status
Simulation time 532866459975 ps
CPU time 1666.99 seconds
Started Jan 17 12:52:16 PM PST 24
Finished Jan 17 01:20:06 PM PST 24
Peak memory 215272 kb
Host smart-ccfe6f72-23c3-4f2f-b75b-4d5ee90f56f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223396572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.223396572
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3181546061
Short name T688
Test name
Test status
Simulation time 90388392074 ps
CPU time 1453.69 seconds
Started Jan 17 12:52:11 PM PST 24
Finished Jan 17 01:16:26 PM PST 24
Peak memory 215560 kb
Host smart-50293dc9-c663-4636-869e-ed0d3b5c6eec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181546061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3181546061
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.1583698343
Short name T216
Test name
Test status
Simulation time 106298087789 ps
CPU time 4957.92 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 02:14:52 PM PST 24
Peak memory 264332 kb
Host smart-2ba2cdd3-fc0f-4cf1-bcaa-9cfc242ea3ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583698343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.1583698343
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2381025092
Short name T851
Test name
Test status
Simulation time 13714971 ps
CPU time 0.56 seconds
Started Jan 17 12:50:07 PM PST 24
Finished Jan 17 12:50:11 PM PST 24
Peak memory 193112 kb
Host smart-646f2ebd-ba5f-45e3-b3c5-03ce06741432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381025092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2381025092
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.592726023
Short name T208
Test name
Test status
Simulation time 1632708460 ps
CPU time 43.65 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:51:09 PM PST 24
Peak memory 206692 kb
Host smart-95f89bd2-f791-4fcc-8dce-d51fc638e985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592726023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.592726023
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.568263748
Short name T543
Test name
Test status
Simulation time 52253287 ps
CPU time 2.41 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 198756 kb
Host smart-dde58fa4-131f-4476-9704-cb34692bccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568263748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.568263748
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1909810526
Short name T563
Test name
Test status
Simulation time 367424911 ps
CPU time 9.2 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 12:50:34 PM PST 24
Peak memory 198688 kb
Host smart-32912d68-fd9f-4587-bdad-cbe057c97fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909810526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1909810526
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4286570040
Short name T405
Test name
Test status
Simulation time 2293080592 ps
CPU time 58.02 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:51:23 PM PST 24
Peak memory 198708 kb
Host smart-94f94c85-5dff-4845-90d2-c1c8ac03925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286570040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4286570040
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1756224792
Short name T447
Test name
Test status
Simulation time 42762520919 ps
CPU time 69.94 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:51:35 PM PST 24
Peak memory 198676 kb
Host smart-fcca8b01-2a09-4a6b-afcc-e62bfe206d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756224792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1756224792
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.100106265
Short name T436
Test name
Test status
Simulation time 19213910 ps
CPU time 0.7 seconds
Started Jan 17 12:50:21 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 194208 kb
Host smart-7f830f53-df1e-4bef-a3a7-ca2993576522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100106265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.100106265
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.4143005412
Short name T791
Test name
Test status
Simulation time 109259336451 ps
CPU time 1749.63 seconds
Started Jan 17 12:50:16 PM PST 24
Finished Jan 17 01:19:35 PM PST 24
Peak memory 215220 kb
Host smart-d0a9c816-1b15-483e-8654-da570592bc6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143005412 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.4143005412
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1124201984
Short name T722
Test name
Test status
Simulation time 51660342 ps
CPU time 1.01 seconds
Started Jan 17 12:50:11 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 196596 kb
Host smart-d4ec0a26-cba9-4a89-8a89-c835134cb91c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124201984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1124201984
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1244262825
Short name T282
Test name
Test status
Simulation time 18961114388 ps
CPU time 361.81 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:56:27 PM PST 24
Peak memory 198700 kb
Host smart-e951168c-5dc1-4ad1-9c37-b1f1262f2361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244262825 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.1244262825
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2688807927
Short name T778
Test name
Test status
Simulation time 6101624773 ps
CPU time 61.9 seconds
Started Jan 17 12:50:17 PM PST 24
Finished Jan 17 12:51:27 PM PST 24
Peak memory 198652 kb
Host smart-4300d7b6-04b5-4fee-bc18-b51e44fbe9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688807927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2688807927
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2370723583
Short name T382
Test name
Test status
Simulation time 153989245192 ps
CPU time 3936.1 seconds
Started Jan 17 12:52:17 PM PST 24
Finished Jan 17 01:57:56 PM PST 24
Peak memory 263420 kb
Host smart-a97b6a9d-c9d8-41f4-8509-b61d12dd0ab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370723583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2370723583
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3738363522
Short name T746
Test name
Test status
Simulation time 41397135878 ps
CPU time 747.95 seconds
Started Jan 17 12:52:16 PM PST 24
Finished Jan 17 01:04:47 PM PST 24
Peak memory 249972 kb
Host smart-055cf6e0-32e2-4d59-a4ac-36e23af09686
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738363522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.3738363522
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.927703261
Short name T545
Test name
Test status
Simulation time 55478301890 ps
CPU time 412.16 seconds
Started Jan 17 12:52:20 PM PST 24
Finished Jan 17 12:59:13 PM PST 24
Peak memory 247208 kb
Host smart-1fcd7f20-174c-43d0-bd0f-9d5dd99f1e49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927703261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.927703261
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.654802036
Short name T822
Test name
Test status
Simulation time 71146776950 ps
CPU time 1115.27 seconds
Started Jan 17 12:52:13 PM PST 24
Finished Jan 17 01:10:49 PM PST 24
Peak memory 261460 kb
Host smart-f64c04a1-7716-416a-aa16-0615a03b7ec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654802036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.654802036
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3524562831
Short name T411
Test name
Test status
Simulation time 437439264940 ps
CPU time 1407.37 seconds
Started Jan 17 12:52:11 PM PST 24
Finished Jan 17 01:15:39 PM PST 24
Peak memory 255512 kb
Host smart-b0e93621-b14e-4f34-9772-ff6668b5db39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524562831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.3524562831
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3853576797
Short name T624
Test name
Test status
Simulation time 367910952 ps
CPU time 6.1 seconds
Started Jan 17 12:52:15 PM PST 24
Finished Jan 17 12:52:24 PM PST 24
Peak memory 198840 kb
Host smart-da99e6da-407d-446c-8565-69399195dd90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853576797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.3853576797
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.142847662
Short name T850
Test name
Test status
Simulation time 150155181843 ps
CPU time 348.2 seconds
Started Jan 17 12:52:16 PM PST 24
Finished Jan 17 12:58:07 PM PST 24
Peak memory 207040 kb
Host smart-f1dd2cc7-a954-42b6-917f-cdecdd4e598d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142847662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.142847662
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.363062131
Short name T845
Test name
Test status
Simulation time 42442075698 ps
CPU time 805.96 seconds
Started Jan 17 12:52:15 PM PST 24
Finished Jan 17 01:05:44 PM PST 24
Peak memory 201736 kb
Host smart-65ed62b0-b246-4304-ae15-bdb7a6917408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363062131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.363062131
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.1782953322
Short name T532
Test name
Test status
Simulation time 8930863127 ps
CPU time 450.85 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:00:00 PM PST 24
Peak memory 239064 kb
Host smart-da7b4bfa-52fe-4786-a20e-ef6781435ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782953322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.1782953322
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3370590162
Short name T800
Test name
Test status
Simulation time 210652583028 ps
CPU time 777.8 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:05:30 PM PST 24
Peak memory 248032 kb
Host smart-fe744dd9-f66a-4302-94b5-5a6a6e4887ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370590162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.3370590162
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4039970808
Short name T281
Test name
Test status
Simulation time 68766575 ps
CPU time 0.59 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:50:25 PM PST 24
Peak memory 193104 kb
Host smart-fe79a5f9-5ac0-4755-97a0-39b7d6fd8ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039970808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4039970808
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.125394535
Short name T420
Test name
Test status
Simulation time 961297463 ps
CPU time 27.39 seconds
Started Jan 17 12:50:15 PM PST 24
Finished Jan 17 12:50:53 PM PST 24
Peak memory 206724 kb
Host smart-75ad4e34-8d9c-4dbc-8d55-70a48c275fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125394535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.125394535
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2347439203
Short name T595
Test name
Test status
Simulation time 5795061134 ps
CPU time 37.49 seconds
Started Jan 17 12:50:12 PM PST 24
Finished Jan 17 12:51:02 PM PST 24
Peak memory 198812 kb
Host smart-7bef0c4c-9e4b-440f-8fab-35abb5b19c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347439203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2347439203
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3431434600
Short name T571
Test name
Test status
Simulation time 236934347 ps
CPU time 12.77 seconds
Started Jan 17 12:50:09 PM PST 24
Finished Jan 17 12:50:24 PM PST 24
Peak memory 198756 kb
Host smart-355395dd-b784-487c-81bb-ca732d9166c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431434600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3431434600
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2465936925
Short name T204
Test name
Test status
Simulation time 2144435980 ps
CPU time 6.72 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:50:32 PM PST 24
Peak memory 198688 kb
Host smart-bc49f90d-0bcd-4768-b7a2-77b0603134e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465936925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2465936925
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3225780693
Short name T618
Test name
Test status
Simulation time 73157240171 ps
CPU time 78.13 seconds
Started Jan 17 12:50:08 PM PST 24
Finished Jan 17 12:51:29 PM PST 24
Peak memory 198840 kb
Host smart-3b8a1048-975e-4291-a959-f25d95b438bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225780693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3225780693
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.443217893
Short name T732
Test name
Test status
Simulation time 1886907917 ps
CPU time 2.39 seconds
Started Jan 17 12:50:13 PM PST 24
Finished Jan 17 12:50:27 PM PST 24
Peak memory 198760 kb
Host smart-2be3375b-bd14-49ef-ae74-17b8de0b9976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443217893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.443217893
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1314312025
Short name T93
Test name
Test status
Simulation time 126716305270 ps
CPU time 1443.04 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 01:14:28 PM PST 24
Peak memory 239756 kb
Host smart-2187d7a6-9a92-4256-b7c2-d784096b1a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314312025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1314312025
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3450630411
Short name T566
Test name
Test status
Simulation time 67302827840 ps
CPU time 1092.79 seconds
Started Jan 17 12:50:19 PM PST 24
Finished Jan 17 01:08:38 PM PST 24
Peak memory 223452 kb
Host smart-ccaeb6aa-8dd4-4013-99e8-a8b3a3b62e5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450630411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3450630411
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3985413369
Short name T392
Test name
Test status
Simulation time 28703642 ps
CPU time 0.88 seconds
Started Jan 17 12:50:18 PM PST 24
Finished Jan 17 12:50:26 PM PST 24
Peak memory 196436 kb
Host smart-5e3cbea5-8f96-40e3-a44b-ec2373457273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985413369 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3985413369
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.143205726
Short name T710
Test name
Test status
Simulation time 15321471942 ps
CPU time 369.77 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:56:35 PM PST 24
Peak memory 198388 kb
Host smart-42157775-e769-4286-a041-23e6b0a3583b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143205726 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.143205726
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1600626444
Short name T609
Test name
Test status
Simulation time 4618976047 ps
CPU time 68.14 seconds
Started Jan 17 12:50:14 PM PST 24
Finished Jan 17 12:51:33 PM PST 24
Peak memory 198700 kb
Host smart-da44f600-aa61-47c2-bce3-b36bea4f614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600626444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1600626444
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2856625357
Short name T43
Test name
Test status
Simulation time 25942162697 ps
CPU time 214.52 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 12:56:03 PM PST 24
Peak memory 207040 kb
Host smart-29c62bb3-f211-419d-b1ca-6b35f6ca33d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856625357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.2856625357
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.437396937
Short name T426
Test name
Test status
Simulation time 277566235254 ps
CPU time 641.33 seconds
Started Jan 17 12:52:25 PM PST 24
Finished Jan 17 01:03:10 PM PST 24
Peak memory 256612 kb
Host smart-53cc1620-5cb0-43c7-b49f-0ece17f3fde8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437396937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.437396937
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.764639193
Short name T114
Test name
Test status
Simulation time 67234140064 ps
CPU time 251.03 seconds
Started Jan 17 12:52:26 PM PST 24
Finished Jan 17 12:56:40 PM PST 24
Peak memory 215316 kb
Host smart-3a4eafe7-86db-4c48-8eaa-9338e1b384f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764639193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.764639193
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2482721257
Short name T826
Test name
Test status
Simulation time 1122060105542 ps
CPU time 1090.89 seconds
Started Jan 17 12:52:22 PM PST 24
Finished Jan 17 01:10:40 PM PST 24
Peak memory 238100 kb
Host smart-608b96b2-235a-4142-83ee-15c5975246bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482721257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.2482721257
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.143262574
Short name T437
Test name
Test status
Simulation time 130401978980 ps
CPU time 1872.2 seconds
Started Jan 17 12:52:27 PM PST 24
Finished Jan 17 01:23:42 PM PST 24
Peak memory 256516 kb
Host smart-f8dd63cd-158b-4b7d-b2a4-f8f654946a6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143262574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.143262574
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2079379270
Short name T601
Test name
Test status
Simulation time 77302913737 ps
CPU time 3376.56 seconds
Started Jan 17 12:52:24 PM PST 24
Finished Jan 17 01:48:46 PM PST 24
Peak memory 256252 kb
Host smart-e09f2752-53a2-4845-9115-1fe3c0ce1956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079379270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.2079379270
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3051970934
Short name T100
Test name
Test status
Simulation time 73526502739 ps
CPU time 1282.8 seconds
Started Jan 17 12:52:29 PM PST 24
Finished Jan 17 01:13:56 PM PST 24
Peak memory 225948 kb
Host smart-1254ccc3-b3c9-468a-8818-300cb0f30cc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051970934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.3051970934
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.1107047167
Short name T713
Test name
Test status
Simulation time 91354425112 ps
CPU time 1066.76 seconds
Started Jan 17 12:52:23 PM PST 24
Finished Jan 17 01:10:16 PM PST 24
Peak memory 225920 kb
Host smart-33a24a2c-038c-4524-ba56-a67cfe75628e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107047167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.1107047167
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2179507624
Short name T598
Test name
Test status
Simulation time 57318386645 ps
CPU time 1088.55 seconds
Started Jan 17 12:52:31 PM PST 24
Finished Jan 17 01:10:45 PM PST 24
Peak memory 248016 kb
Host smart-90d697ad-f977-459f-bfc7-4eed1d83fc0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179507624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.2179507624
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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