Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	36220331	1			T12	10		T13	11		T15	1
all_values[1]	36220331	1			T12	10		T13	11		T15	1
all_values[2]	36220331	1			T12	10		T13	11		T15	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125659

1

T12

15

T13

17

T15

3

auto[1]

108535334

1

T12

15

T13

16

T19

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78607987

1

T12

23

T13

27

T15

3

auto[1]

30053006

1

T12

7

T13

6

T19

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	42143	1			T12	5		T13	1		T15	1
all_values[0]	auto[0]	auto[1]	1287	1			T12	2		T28	2		T108	1
all_values[0]	auto[1]	auto[0]	36021531	1			T12	3		T13	8		T19	2
all_values[0]	auto[1]	auto[1]	155370	1			T13	2		T19	3		T28	2
all_values[1]	auto[0]	auto[0]	20879	1			T12	4		T13	6		T15	1
all_values[1]	auto[0]	auto[1]	15417	1			T12	1		T13	1		T28	3
all_values[1]	auto[1]	auto[0]	20055728	1			T12	4		T13	3		T19	2
all_values[1]	auto[1]	auto[1]	16128307	1			T12	1		T13	1		T28	3
all_values[2]	auto[0]	auto[0]	33145	1			T12	1		T13	7		T15	1
all_values[2]	auto[0]	auto[1]	12788	1			T12	2		T13	2		T19	1
all_values[2]	auto[1]	auto[0]	22434561	1			T12	6		T13	2		T19	1
all_values[2]	auto[1]	auto[1]	13739837	1			T12	1		T28	2		T78	3