Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.69 100.00 100.00 99.76 99.49 99.86


Total tests in report: 904
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.49 52.49 34.16 34.16 31.87 31.87 85.68 85.68 100.00 100.00 23.53 23.53 79.55 79.55 12.65 12.65 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1442400977
85.97 33.48 92.06 57.90 77.66 45.78 90.20 4.52 100.00 0.00 92.24 68.71 92.68 13.13 56.95 44.29 /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.403319222
94.65 8.68 98.83 6.77 94.09 16.43 98.24 8.04 100.00 0.00 98.35 6.12 93.69 1.01 79.37 22.42 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1533729926
96.98 2.33 99.07 0.23 94.85 0.77 98.24 0.00 100.00 0.00 98.82 0.47 95.71 2.02 92.16 12.79 /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.318401986
98.00 1.02 99.07 0.00 97.70 2.85 99.50 1.26 100.00 0.00 99.29 0.47 96.46 0.76 93.95 1.79 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4242266421
98.21 0.22 99.07 0.00 97.70 0.00 99.50 0.00 100.00 0.00 99.29 0.00 96.46 0.00 95.46 1.51 /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1637591551
98.41 0.19 99.07 0.00 97.70 0.00 99.50 0.00 100.00 0.00 99.29 0.00 96.72 0.25 96.56 1.10 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1606496590
98.59 0.18 99.53 0.47 98.03 0.33 99.50 0.00 100.00 0.00 99.76 0.47 96.72 0.00 96.56 0.00 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4003429310
98.77 0.18 99.53 0.00 98.03 0.00 99.50 0.00 100.00 0.00 99.76 0.00 97.98 1.26 96.56 0.00 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3949363357
98.94 0.18 99.53 0.00 98.25 0.22 100.00 0.50 100.00 0.00 99.76 0.00 98.23 0.25 96.84 0.28 /workspace/coverage/default/4.hmac_sec_cm.1891171204
99.04 0.10 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 97.52 0.69 /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1790314045
99.10 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 97.94 0.41 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.235934749
99.16 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 98.35 0.41 /workspace/coverage/default/0.hmac_stress_all.2490839450
99.22 0.06 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 98.76 0.41 /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1413293960
99.26 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.23 0.00 99.04 0.28 /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.945018630
99.30 0.04 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.25 99.04 0.00 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.289416863
99.33 0.03 99.53 0.00 98.47 0.22 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.04 0.00 /workspace/coverage/default/14.hmac_alert_test.626202675
99.35 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.14 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1729571166
99.37 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/default/0.hmac_wipe_secret.3086576789
99.39 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1331312898
99.41 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.3641110773
99.42 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/18.hmac_error.1776560908
99.44 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1988519385
99.46 0.02 99.53 0.00 98.58 0.11 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.00 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.7216757
99.48 0.02 99.53 0.00 98.69 0.11 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.00 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4088650956

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4058509450
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1348381040
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3646877272
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3521330926
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.181956908
/workspace/coverage/cover_reg_top/0.hmac_intr_test.237751104
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.391714026
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.330405584
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.176473898
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2914272597
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2914541316
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1798609159
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.634731809
/workspace/coverage/cover_reg_top/1.hmac_intr_test.2382150290
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3641310398
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.2859481124
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3137654368
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.3323968706
/workspace/coverage/cover_reg_top/10.hmac_intr_test.2614563844
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.881101316
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.742099927
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.564303951
/workspace/coverage/cover_reg_top/11.hmac_intr_test.590197161
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4237952298
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.3602150517
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1378702271
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.2255105031
/workspace/coverage/cover_reg_top/12.hmac_intr_test.3481764957
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.231052442
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.25873911
/workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1565735486
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1245151754
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.479638916
/workspace/coverage/cover_reg_top/13.hmac_intr_test.21871211
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.650103271
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.3484559604
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4258863765
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1097226127
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.178446289
/workspace/coverage/cover_reg_top/14.hmac_intr_test.2981961221
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1744686614
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.1344967860
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4078177448
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.169973211
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.3415151078
/workspace/coverage/cover_reg_top/15.hmac_intr_test.3112939822
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1862168630
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.4226626454
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1944082628
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.1606773890
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1652003908
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.3976472383
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2119200201
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.556609404
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1131324635
/workspace/coverage/cover_reg_top/17.hmac_intr_test.2713439106
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.26720792
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.4204326613
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.136932862
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.950150803
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.4172938300
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3047758365
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.2180301874
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.911151859
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1000514616
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.847015662
/workspace/coverage/cover_reg_top/19.hmac_intr_test.3810222574
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3130371282
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.2255782848
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3917757987
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2577016214
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2804008244
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1740741368
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1588877403
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.1528724279
/workspace/coverage/cover_reg_top/2.hmac_intr_test.2132537574
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.845857235
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.897279912
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.560786922
/workspace/coverage/cover_reg_top/20.hmac_intr_test.3157686602
/workspace/coverage/cover_reg_top/21.hmac_intr_test.3461636349
/workspace/coverage/cover_reg_top/22.hmac_intr_test.3550277710
/workspace/coverage/cover_reg_top/23.hmac_intr_test.3203486910
/workspace/coverage/cover_reg_top/25.hmac_intr_test.3114874658
/workspace/coverage/cover_reg_top/26.hmac_intr_test.2498634083
/workspace/coverage/cover_reg_top/27.hmac_intr_test.692323649
/workspace/coverage/cover_reg_top/28.hmac_intr_test.2787220722
/workspace/coverage/cover_reg_top/29.hmac_intr_test.1799597839
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2943135703
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1133371588
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3117156162
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.553333777
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.3698149966
/workspace/coverage/cover_reg_top/3.hmac_intr_test.500705069
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2153634327
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.1267648617
/workspace/coverage/cover_reg_top/30.hmac_intr_test.3525141997
/workspace/coverage/cover_reg_top/31.hmac_intr_test.2093415145
/workspace/coverage/cover_reg_top/32.hmac_intr_test.4236674467
/workspace/coverage/cover_reg_top/33.hmac_intr_test.3830207933
/workspace/coverage/cover_reg_top/34.hmac_intr_test.4268714765
/workspace/coverage/cover_reg_top/35.hmac_intr_test.438975393
/workspace/coverage/cover_reg_top/36.hmac_intr_test.2489873330
/workspace/coverage/cover_reg_top/37.hmac_intr_test.3053115954
/workspace/coverage/cover_reg_top/38.hmac_intr_test.407858825
/workspace/coverage/cover_reg_top/39.hmac_intr_test.3870445537
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.547330273
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4159783817
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3697648859
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.957750450
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.380331215
/workspace/coverage/cover_reg_top/4.hmac_intr_test.2529952463
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4217187565
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.2207936786
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2428306643
/workspace/coverage/cover_reg_top/40.hmac_intr_test.2132329209
/workspace/coverage/cover_reg_top/41.hmac_intr_test.398560255
/workspace/coverage/cover_reg_top/42.hmac_intr_test.1386115699
/workspace/coverage/cover_reg_top/43.hmac_intr_test.406294668
/workspace/coverage/cover_reg_top/44.hmac_intr_test.1995077956
/workspace/coverage/cover_reg_top/45.hmac_intr_test.3151750813
/workspace/coverage/cover_reg_top/46.hmac_intr_test.235085256
/workspace/coverage/cover_reg_top/47.hmac_intr_test.2497659937
/workspace/coverage/cover_reg_top/48.hmac_intr_test.1625764622
/workspace/coverage/cover_reg_top/49.hmac_intr_test.1369932685
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2240681807
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.145378850
/workspace/coverage/cover_reg_top/5.hmac_intr_test.2722764271
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3890351090
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.879609253
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1404818821
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3761565228
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.2531622
/workspace/coverage/cover_reg_top/6.hmac_intr_test.3969649623
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2859779312
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.1852483963
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2570691189
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1726011613
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2588112296
/workspace/coverage/cover_reg_top/7.hmac_intr_test.4093468684
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.951181862
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.814703721
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.689930816
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.1900301354
/workspace/coverage/cover_reg_top/8.hmac_intr_test.404732206
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4008188946
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.276359591
/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3691886285
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1209761626
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.1014153010
/workspace/coverage/cover_reg_top/9.hmac_intr_test.1675492049
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4098096075
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.589840338
/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2030682047
/workspace/coverage/default/0.hmac_alert_test.1012740116
/workspace/coverage/default/0.hmac_back_pressure.1479950846
/workspace/coverage/default/0.hmac_burst_wr.546656207
/workspace/coverage/default/0.hmac_datapath_stress.3342065187
/workspace/coverage/default/0.hmac_error.2344787134
/workspace/coverage/default/0.hmac_long_msg.3570648450
/workspace/coverage/default/0.hmac_sec_cm.2582417949
/workspace/coverage/default/0.hmac_smoke.2941705377
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3810242247
/workspace/coverage/default/0.hmac_test_hmac_vectors.2015069224
/workspace/coverage/default/0.hmac_test_sha_vectors.3222547766
/workspace/coverage/default/1.hmac_alert_test.2699125347
/workspace/coverage/default/1.hmac_back_pressure.3881213945
/workspace/coverage/default/1.hmac_burst_wr.1994458366
/workspace/coverage/default/1.hmac_datapath_stress.2304136193
/workspace/coverage/default/1.hmac_error.684898341
/workspace/coverage/default/1.hmac_long_msg.3540648259
/workspace/coverage/default/1.hmac_sec_cm.1394586793
/workspace/coverage/default/1.hmac_smoke.542573832
/workspace/coverage/default/1.hmac_stress_all.4110102397
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2739070275
/workspace/coverage/default/1.hmac_test_hmac_vectors.984477206
/workspace/coverage/default/1.hmac_test_sha_vectors.1394465695
/workspace/coverage/default/1.hmac_wipe_secret.1206773569
/workspace/coverage/default/10.hmac_alert_test.1238277063
/workspace/coverage/default/10.hmac_back_pressure.3478496552
/workspace/coverage/default/10.hmac_burst_wr.604737029
/workspace/coverage/default/10.hmac_datapath_stress.1095952690
/workspace/coverage/default/10.hmac_error.1886490387
/workspace/coverage/default/10.hmac_long_msg.317964774
/workspace/coverage/default/10.hmac_smoke.3963995797
/workspace/coverage/default/10.hmac_stress_all.2801085472
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2622612920
/workspace/coverage/default/10.hmac_test_hmac_vectors.3630482747
/workspace/coverage/default/10.hmac_test_sha_vectors.952357759
/workspace/coverage/default/10.hmac_wipe_secret.985579701
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3732832246
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2545144552
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.1561928706
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.310220122
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2571714513
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3704659424
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.474145680
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.1927276991
/workspace/coverage/default/11.hmac_alert_test.1275146997
/workspace/coverage/default/11.hmac_back_pressure.2791585433
/workspace/coverage/default/11.hmac_burst_wr.4064610360
/workspace/coverage/default/11.hmac_datapath_stress.4293570331
/workspace/coverage/default/11.hmac_error.2047645606
/workspace/coverage/default/11.hmac_long_msg.520549619
/workspace/coverage/default/11.hmac_smoke.1313577392
/workspace/coverage/default/11.hmac_stress_all.3988318417
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/workspace/coverage/default/74.hmac_stress_all_with_rand_reset.814782297
/workspace/coverage/default/77.hmac_stress_all_with_rand_reset.1140693062
/workspace/coverage/default/78.hmac_stress_all_with_rand_reset.4123323320
/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.4039879457
/workspace/coverage/default/8.hmac_alert_test.3090807173
/workspace/coverage/default/8.hmac_back_pressure.1741137287
/workspace/coverage/default/8.hmac_burst_wr.729855820
/workspace/coverage/default/8.hmac_datapath_stress.106761734
/workspace/coverage/default/8.hmac_error.899822308
/workspace/coverage/default/8.hmac_long_msg.1947006840
/workspace/coverage/default/8.hmac_smoke.4244576287
/workspace/coverage/default/8.hmac_stress_all.1352174250
/workspace/coverage/default/8.hmac_test_hmac_vectors.1542641838
/workspace/coverage/default/8.hmac_test_sha_vectors.4131196881
/workspace/coverage/default/8.hmac_wipe_secret.3072730102
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.3743677457
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4106319666
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.69105698
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.4169291910
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3552356815
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.1273848169
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.3064401111
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2851515657
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3812219117
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.1416512413
/workspace/coverage/default/9.hmac_alert_test.797138542
/workspace/coverage/default/9.hmac_back_pressure.1211050655
/workspace/coverage/default/9.hmac_burst_wr.35268593
/workspace/coverage/default/9.hmac_datapath_stress.4262157475
/workspace/coverage/default/9.hmac_error.2896470814
/workspace/coverage/default/9.hmac_long_msg.1681521504
/workspace/coverage/default/9.hmac_smoke.2543156183
/workspace/coverage/default/9.hmac_stress_all.3592993934
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2215615590
/workspace/coverage/default/9.hmac_test_hmac_vectors.1468038974
/workspace/coverage/default/9.hmac_test_sha_vectors.55236295
/workspace/coverage/default/9.hmac_wipe_secret.1416347291
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1666235272
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.336165644
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.565840388
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.4070764852
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.1044068363
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1390929396
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1725174203



Total test records in report: 904
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T12 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1442400977 Jan 21 09:01:34 PM PST 24 Jan 21 09:01:53 PM PST 24 142132534 ps
T13 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1606496590 Jan 21 10:13:43 PM PST 24 Jan 21 10:13:50 PM PST 24 55826534 ps
T14 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1533729926 Jan 21 09:25:16 PM PST 24 Jan 21 09:25:25 PM PST 24 595474531 ps
T15 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3602150517 Jan 21 09:13:21 PM PST 24 Jan 21 09:13:26 PM PST 24 189456301 ps
T16 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4242266421 Jan 21 09:00:47 PM PST 24 Jan 21 09:01:17 PM PST 24 423378572 ps
T17 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2577016214 Jan 21 09:00:38 PM PST 24 Jan 21 09:01:06 PM PST 24 103797980 ps
T18 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2255105031 Jan 21 09:48:02 PM PST 24 Jan 21 09:48:03 PM PST 24 72764863 ps
T19 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2382150290 Jan 21 09:00:29 PM PST 24 Jan 21 09:00:57 PM PST 24 14726495 ps
T20 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1344967860 Jan 21 09:01:18 PM PST 24 Jan 21 09:01:45 PM PST 24 625043618 ps
T21 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.950150803 Jan 21 09:01:46 PM PST 24 Jan 21 09:02:07 PM PST 24 88662141 ps
T22 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1944082628 Jan 21 09:01:36 PM PST 24 Jan 21 09:01:55 PM PST 24 16718619 ps
T28 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3481764957 Jan 21 09:01:22 PM PST 24 Jan 21 09:01:46 PM PST 24 42188564 ps
T29 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3203486910 Jan 21 09:01:40 PM PST 24 Jan 21 09:01:59 PM PST 24 18511118 ps
T23 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3761565228 Jan 21 09:00:50 PM PST 24 Jan 21 09:01:19 PM PST 24 23255507 ps
T63 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.814703721 Jan 21 09:00:47 PM PST 24 Jan 21 09:01:16 PM PST 24 379042348 ps
T78 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3525141997 Jan 21 09:01:42 PM PST 24 Jan 21 09:02:02 PM PST 24 13552114 ps
T24 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.330405584 Jan 21 09:00:28 PM PST 24 Jan 21 09:00:58 PM PST 24 183247909 ps
T108 /workspace/coverage/cover_reg_top/46.hmac_intr_test.235085256 Jan 21 09:01:53 PM PST 24 Jan 21 09:02:09 PM PST 24 28841383 ps
T64 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2570691189 Jan 21 09:00:45 PM PST 24 Jan 21 09:01:14 PM PST 24 115348135 ps
T25 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1852483963 Jan 21 09:00:45 PM PST 24 Jan 21 09:01:14 PM PST 24 126976906 ps
T109 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2132329209 Jan 21 09:01:52 PM PST 24 Jan 21 09:02:09 PM PST 24 14498288 ps
T106 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1740741368 Jan 21 09:00:37 PM PST 24 Jan 21 09:01:05 PM PST 24 15447344 ps
T140 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2093415145 Jan 21 09:01:38 PM PST 24 Jan 21 09:01:56 PM PST 24 38361372 ps
T107 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2804008244 Jan 21 09:00:36 PM PST 24 Jan 21 09:01:06 PM PST 24 339587104 ps
T102 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1652003908 Jan 21 09:01:34 PM PST 24 Jan 21 09:01:54 PM PST 24 34067526 ps
T26 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.276359591 Jan 21 09:00:54 PM PST 24 Jan 21 09:01:22 PM PST 24 70038579 ps
T69 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3151750813 Jan 21 09:01:51 PM PST 24 Jan 21 09:02:08 PM PST 24 87812148 ps
T79 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.650103271 Jan 21 09:01:24 PM PST 24 Jan 21 09:01:47 PM PST 24 55800537 ps
T27 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2240681807 Jan 21 09:00:51 PM PST 24 Jan 21 09:01:19 PM PST 24 34326410 ps
T76 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3976472383 Jan 21 09:01:39 PM PST 24 Jan 21 09:01:59 PM PST 24 297369991 ps
T103 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.951181862 Jan 21 09:01:01 PM PST 24 Jan 21 09:01:28 PM PST 24 118623383 ps
T70 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3415151078 Jan 21 09:39:17 PM PST 24 Jan 21 09:39:27 PM PST 24 235623893 ps
T71 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.689930816 Jan 21 09:00:57 PM PST 24 Jan 21 09:01:26 PM PST 24 189584755 ps
T80 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.845857235 Jan 21 09:00:37 PM PST 24 Jan 21 09:01:05 PM PST 24 36678283 ps
T72 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1369932685 Jan 21 09:01:58 PM PST 24 Jan 21 09:02:15 PM PST 24 106302054 ps
T104 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.289416863 Jan 21 09:00:39 PM PST 24 Jan 21 09:01:07 PM PST 24 13815769 ps
T73 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4237952298 Jan 21 10:37:28 PM PST 24 Jan 21 10:37:41 PM PST 24 114813941 ps
T74 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4078177448 Jan 21 09:01:17 PM PST 24 Jan 21 09:01:42 PM PST 24 119873727 ps
T149 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3053115954 Jan 21 09:01:53 PM PST 24 Jan 21 09:02:10 PM PST 24 28791302 ps
T81 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4008188946 Jan 21 09:00:56 PM PST 24 Jan 21 09:01:24 PM PST 24 234746677 ps
T150 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1729571166 Jan 21 09:01:43 PM PST 24 Jan 21 09:02:03 PM PST 24 31058443 ps
T151 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.911151859 Jan 21 09:01:35 PM PST 24 Jan 21 09:01:54 PM PST 24 78926137 ps
T75 /workspace/coverage/cover_reg_top/8.hmac_intr_test.404732206 Jan 21 09:01:02 PM PST 24 Jan 21 09:01:29 PM PST 24 25124999 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4217187565 Jan 21 09:00:47 PM PST 24 Jan 21 09:01:16 PM PST 24 81363317 ps
T82 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3949363357 Jan 21 09:25:41 PM PST 24 Jan 21 09:25:47 PM PST 24 17865354 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2428306643 Jan 21 09:00:39 PM PST 24 Jan 21 09:01:07 PM PST 24 85562192 ps
T83 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3890351090 Jan 21 09:00:49 PM PST 24 Jan 21 09:01:18 PM PST 24 66757007 ps
T94 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1131324635 Jan 21 10:30:07 PM PST 24 Jan 21 10:30:10 PM PST 24 21319363 ps
T95 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1386115699 Jan 21 09:01:50 PM PST 24 Jan 21 09:02:07 PM PST 24 13145622 ps
T84 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1528724279 Jan 21 09:00:35 PM PST 24 Jan 21 09:01:04 PM PST 24 34887656 ps
T96 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.556609404 Jan 21 09:01:39 PM PST 24 Jan 21 09:01:59 PM PST 24 20180812 ps
T65 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4003429310 Jan 21 09:01:03 PM PST 24 Jan 21 09:02:17 PM PST 24 6289628318 ps
T85 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1606773890 Jan 21 09:22:13 PM PST 24 Jan 21 09:22:16 PM PST 24 80023007 ps
T66 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1209761626 Jan 21 09:00:54 PM PST 24 Jan 21 09:12:39 PM PST 24 269081117981 ps
T152 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1245151754 Jan 21 09:01:21 PM PST 24 Jan 21 09:01:45 PM PST 24 23657643 ps
T153 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4172938300 Jan 21 10:23:04 PM PST 24 Jan 21 10:23:09 PM PST 24 143842430 ps
T154 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1726011613 Jan 21 09:01:03 PM PST 24 Jan 21 09:01:30 PM PST 24 15758483 ps
T155 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.136932862 Jan 21 09:01:34 PM PST 24 Jan 21 09:01:55 PM PST 24 589788727 ps
T77 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.25873911 Jan 21 09:01:09 PM PST 24 Jan 21 09:01:38 PM PST 24 1315180948 ps
T143 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1565735486 Jan 21 09:01:18 PM PST 24 Jan 21 09:01:44 PM PST 24 660815704 ps
T156 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.178446289 Jan 21 09:01:39 PM PST 24 Jan 21 09:01:58 PM PST 24 28779119 ps
T157 /workspace/coverage/cover_reg_top/43.hmac_intr_test.406294668 Jan 21 09:01:52 PM PST 24 Jan 21 09:02:08 PM PST 24 13863584 ps
T158 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2153634327 Jan 21 09:00:36 PM PST 24 Jan 21 09:01:05 PM PST 24 76185669 ps
T159 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3114874658 Jan 21 09:01:41 PM PST 24 Jan 21 09:02:00 PM PST 24 19479795 ps
T147 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1404818821 Jan 21 09:00:47 PM PST 24 Jan 21 09:01:15 PM PST 24 191462480 ps
T160 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.634731809 Jan 21 09:00:34 PM PST 24 Jan 21 09:04:17 PM PST 24 14549806684 ps
T161 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3641310398 Jan 21 09:00:34 PM PST 24 Jan 21 09:01:03 PM PST 24 236552715 ps
T162 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4268714765 Jan 21 09:01:46 PM PST 24 Jan 21 09:02:05 PM PST 24 60378048 ps
T163 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2498634083 Jan 21 09:01:40 PM PST 24 Jan 21 09:01:59 PM PST 24 36558834 ps
T164 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1378702271 Jan 21 09:01:18 PM PST 24 Jan 21 09:01:43 PM PST 24 108519635 ps
T86 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4058509450 Jan 21 09:00:29 PM PST 24 Jan 21 09:00:59 PM PST 24 221943331 ps
T165 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3697648859 Jan 21 09:00:44 PM PST 24 Jan 21 09:01:12 PM PST 24 26342808 ps
T166 /workspace/coverage/cover_reg_top/27.hmac_intr_test.692323649 Jan 21 09:01:43 PM PST 24 Jan 21 09:02:02 PM PST 24 14561189 ps
T167 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2914541316 Jan 21 09:00:33 PM PST 24 Jan 21 09:01:05 PM PST 24 76962741 ps
T87 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.547330273 Jan 21 09:00:51 PM PST 24 Jan 21 09:01:20 PM PST 24 58269382 ps
T168 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1799597839 Jan 21 09:01:43 PM PST 24 Jan 21 09:02:03 PM PST 24 39428355 ps
T169 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.897279912 Jan 21 09:00:30 PM PST 24 Jan 21 09:01:02 PM PST 24 2661757774 ps
T144 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2030682047 Jan 21 09:01:03 PM PST 24 Jan 21 09:01:31 PM PST 24 157620181 ps
T170 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4236674467 Jan 21 09:01:44 PM PST 24 Jan 21 09:02:03 PM PST 24 49495125 ps
T171 /workspace/coverage/cover_reg_top/41.hmac_intr_test.398560255 Jan 21 09:01:50 PM PST 24 Jan 21 09:02:07 PM PST 24 14300638 ps
T145 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3691886285 Jan 21 09:00:55 PM PST 24 Jan 21 09:01:23 PM PST 24 75286745 ps
T172 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2497659937 Jan 21 09:01:55 PM PST 24 Jan 21 09:02:12 PM PST 24 19405292 ps
T173 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.742099927 Jan 21 09:01:00 PM PST 24 Jan 21 09:01:30 PM PST 24 99830362 ps
T88 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3323968706 Jan 21 09:34:32 PM PST 24 Jan 21 09:34:50 PM PST 24 20607426 ps
T148 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.560786922 Jan 21 09:00:35 PM PST 24 Jan 21 09:01:05 PM PST 24 435276429 ps
T174 /workspace/coverage/cover_reg_top/13.hmac_intr_test.21871211 Jan 21 09:01:16 PM PST 24 Jan 21 09:01:41 PM PST 24 15142849 ps
T175 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1675492049 Jan 21 09:00:56 PM PST 24 Jan 21 09:01:25 PM PST 24 22538168 ps
T89 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.380331215 Jan 21 09:00:43 PM PST 24 Jan 21 09:01:11 PM PST 24 40614260 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1348381040 Jan 21 09:00:23 PM PST 24 Jan 21 09:00:56 PM PST 24 530026802 ps
T176 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3157686602 Jan 21 09:01:42 PM PST 24 Jan 21 09:02:01 PM PST 24 15050442 ps
T177 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2981961221 Jan 21 09:17:41 PM PST 24 Jan 21 09:17:45 PM PST 24 51856350 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1133371588 Jan 21 09:00:35 PM PST 24 Jan 21 09:01:13 PM PST 24 2009160139 ps
T178 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1862168630 Jan 21 09:01:30 PM PST 24 Jan 21 09:01:51 PM PST 24 27355442 ps
T179 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3137654368 Jan 21 09:00:25 PM PST 24 Jan 21 09:00:53 PM PST 24 245962592 ps
T180 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.957750450 Jan 21 09:00:47 PM PST 24 Jan 21 09:15:35 PM PST 24 128107106341 ps
T181 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2787220722 Jan 21 09:37:04 PM PST 24 Jan 21 09:37:19 PM PST 24 16111559 ps
T182 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.553333777 Jan 21 09:00:39 PM PST 24 Jan 21 09:01:07 PM PST 24 16694021 ps
T183 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3047758365 Jan 21 09:46:42 PM PST 24 Jan 21 09:46:48 PM PST 24 477755660 ps
T184 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2859481124 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:56 PM PST 24 421574918 ps
T185 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1097226127 Jan 21 09:01:31 PM PST 24 Jan 21 09:01:51 PM PST 24 58236714 ps
T186 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1625764622 Jan 21 09:01:58 PM PST 24 Jan 21 09:02:15 PM PST 24 42495068 ps
T187 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.589840338 Jan 21 09:01:02 PM PST 24 Jan 21 09:01:30 PM PST 24 514809525 ps
T188 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.176473898 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:56 PM PST 24 113778660 ps
T189 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4098096075 Jan 21 09:00:56 PM PST 24 Jan 21 09:01:25 PM PST 24 366245511 ps
T1 /workspace/coverage/default/25.hmac_datapath_stress.3756152599 Jan 21 04:04:44 PM PST 24 Jan 21 04:05:48 PM PST 24 2538931174 ps
T2 /workspace/coverage/default/26.hmac_burst_wr.3530100246 Jan 21 04:26:56 PM PST 24 Jan 21 04:27:39 PM PST 24 905870389 ps
T3 /workspace/coverage/default/24.hmac_test_sha_vectors.473365801 Jan 21 04:04:43 PM PST 24 Jan 21 04:10:51 PM PST 24 58468331544 ps
T4 /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.403319222 Jan 21 04:08:36 PM PST 24 Jan 21 04:54:10 PM PST 24 176879594109 ps
T7 /workspace/coverage/default/14.hmac_burst_wr.2343936299 Jan 21 04:03:32 PM PST 24 Jan 21 04:03:37 PM PST 24 177302765 ps
T8 /workspace/coverage/default/19.hmac_error.4206436699 Jan 21 04:04:14 PM PST 24 Jan 21 04:04:37 PM PST 24 4731064485 ps
T9 /workspace/coverage/default/29.hmac_burst_wr.355075440 Jan 21 04:05:20 PM PST 24 Jan 21 04:06:26 PM PST 24 1298492201 ps
T5 /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.2716175398 Jan 21 04:10:21 PM PST 24 Jan 21 04:22:34 PM PST 24 56319789830 ps
T10 /workspace/coverage/default/20.hmac_wipe_secret.625996451 Jan 21 04:04:05 PM PST 24 Jan 21 04:04:19 PM PST 24 1168797086 ps
T11 /workspace/coverage/default/12.hmac_test_sha_vectors.1392010420 Jan 21 04:03:14 PM PST 24 Jan 21 04:09:40 PM PST 24 7921428085 ps
T40 /workspace/coverage/default/38.hmac_smoke.755272472 Jan 21 04:06:28 PM PST 24 Jan 21 04:06:37 PM PST 24 100021490 ps
T41 /workspace/coverage/default/22.hmac_smoke.3286484078 Jan 21 04:04:22 PM PST 24 Jan 21 04:04:27 PM PST 24 1195638731 ps
T42 /workspace/coverage/default/47.hmac_long_msg.3463129318 Jan 21 04:07:33 PM PST 24 Jan 21 04:08:46 PM PST 24 3977025169 ps
T43 /workspace/coverage/default/20.hmac_error.3581693254 Jan 21 04:35:54 PM PST 24 Jan 21 04:37:44 PM PST 24 6786800698 ps
T44 /workspace/coverage/default/49.hmac_test_sha_vectors.156095957 Jan 21 04:07:53 PM PST 24 Jan 21 04:15:30 PM PST 24 54958316271 ps
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