Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18047313

1

T1

4776

T2

13716

T3

37410

auto[1]

9119084

1

T1

6263

T2

6895

T4

59171

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9155467

1

T1

6726

T2

12813

T4

66088

auto[1]

18010930

1

T1

4313

T2

7798

T3

37410

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15695565

1

T2

10716

T3

37410

T4

31347

auto[1]

11470832

1

T1

11039

T2

9895

T4

82170

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	15443892	1			T1	3844		T2	490		T3	24343
fifo_depth[1]	1350073	1			T1	793		T2	315		T3	2518
fifo_depth[2]	1206425	1			T1	812		T2	658		T3	2292
fifo_depth[3]	1014265	1			T1	818		T2	752		T3	1960
fifo_depth[4]	992884	1			T1	817		T2	1004		T3	1498
fifo_depth[5]	837511	1			T1	772		T2	831		T3	1189
fifo_depth[6]	870850	1			T1	761		T2	1040		T3	1075
fifo_depth[7]	739356	1			T1	730		T2	918		T3	875
fifo_depth[8]	906101	1			T1	585		T2	1417		T3	672
fifo_depth[9]	520275	1			T1	452		T2	1007		T3	428
fifo_depth[10]	536584	1			T1	317		T2	1402		T3	270
fifo_depth[11]	325580	1			T1	187		T2	1193		T3	139
fifo_depth[12]	567075	1			T1	90		T2	1828		T3	86
fifo_depth[13]	251602	1			T1	42		T2	1243		T3	34
fifo_depth[14]	407422	1			T1	14		T2	1882		T3	18
fifo_depth[15]	229757	1			T1	4		T2	1337		T3	8
fifo_depth[16]	966745	1			T1	1		T2	3294		T3	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11722505

1

T1

7195

T2

20121

T3

13067

auto[1]

15443892

1

T1

3844

T2

490

T3

24343

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26199652

1

T1

11038

T2

17317

T3

37405

auto[1]

966745

1

T1

1

T2

3294

T3

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

902780

1

T2

5804

T4

773

T9

3311

auto[0]

auto[0]

auto[0]

auto[1]

923918

1

T2

1829

T4

623

T9

5477

auto[0]

auto[0]

auto[1]

auto[0]

3101163

1

T2

2037

T3

13067

T4

425

auto[0]

auto[0]

auto[1]

auto[1]

889698

1

T2

775

T4

393

T9

2868

auto[0]

auto[1]

auto[0]

auto[0]

1495093

1

T1

722

T2

3120

T4

2069

auto[0]

auto[1]

auto[0]

auto[1]

1492466

1

T1

3677

T2

1948

T4

1979

auto[0]

auto[1]

auto[1]

auto[0]

1447256

1

T1

2392

T2

2322

T4

967

auto[0]

auto[1]

auto[1]

auto[1]

1470131

1

T1

404

T2

2286

T4

1347

auto[1]

auto[0]

auto[0]

auto[0]

771500

1

T2

73

T4

7782

T8

4

auto[1]

auto[0]

auto[0]

auto[1]

778936

1

T2

25

T4

6852

T9

17

auto[1]

auto[0]

auto[1]

auto[0]

7547672

1

T2

170

T3

24343

T4

9202

auto[1]

auto[0]

auto[1]

auto[1]

779898

1

T2

3

T4

5297

T8

14

auto[1]

auto[1]

auto[0]

auto[0]

1412043

1

T1

361

T2

11

T4

22354

auto[1]

auto[1]

auto[0]

auto[1]

1378731

1

T1

1966

T2

3

T4

23656

auto[1]

auto[1]

auto[1]

auto[0]

1369806

1

T1

1301

T2

179

T4

10774

auto[1]

auto[1]

auto[1]

auto[1]

1405306

1

T1

216

T2

26

T4

19024

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1561805

1

T2

5117

T4

8555

T8

4

auto[0]

auto[0]

auto[0]

auto[1]

1577324

1

T2

1544

T4

7475

T9

4604

auto[0]

auto[0]

auto[1]

auto[0]

10530987

1

T2

2081

T3

37405

T4

9627

auto[0]

auto[0]

auto[1]

auto[1]

1549108

1

T2

720

T4

5690

T8

14

auto[0]

auto[1]

auto[0]

auto[0]

2783973

1

T1

1083

T2

2839

T4

24423

auto[0]

auto[1]

auto[0]

auto[1]

2749604

1

T1

5642

T2

1336

T4

25635

auto[0]

auto[1]

auto[1]

auto[0]

2689683

1

T1

3693

T2

1515

T4

11741

auto[0]

auto[1]

auto[1]

auto[1]

2757168

1

T1

620

T2

2165

T4

20371

auto[1]

auto[0]

auto[0]

auto[0]

112475

1

T2

760

T9

740

T6

2756

auto[1]

auto[0]

auto[0]

auto[1]

125530

1

T2

310

T9

890

T6

1260

auto[1]

auto[0]

auto[1]

auto[0]

117848

1

T2

126

T3

5

T9

742

auto[1]

auto[0]

auto[1]

auto[1]

120488

1

T2

58

T9

1404

T6

385

auto[1]

auto[1]

auto[0]

auto[0]

123163

1

T2

292

T9

953

T5

3

auto[1]

auto[1]

auto[0]

auto[1]

121593

1

T1

1

T2

615

T9

708

auto[1]

auto[1]

auto[1]

auto[0]

127379

1

T2

986

T9

3684

T6

908

auto[1]

auto[1]

auto[1]

auto[1]

118269

1

T2

147

T9

88

T6

833

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	771500	1			T2	73		T4	7782		T8	4
fifo_depth[0]	auto[0]	auto[0]	auto[1]	778936	1			T2	25		T4	6852		T9	17
fifo_depth[0]	auto[0]	auto[1]	auto[0]	7547672	1			T2	170		T3	24343		T4	9202
fifo_depth[0]	auto[0]	auto[1]	auto[1]	779898	1			T2	3		T4	5297		T8	14
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1412043	1			T1	361		T2	11		T4	22354
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1378731	1			T1	1966		T2	3		T4	23656
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1369806	1			T1	1301		T2	179		T4	10774
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1405306	1			T1	216		T2	26		T4	19024
fifo_depth[1]	auto[0]	auto[0]	auto[0]	66738	1			T2	99		T4	354		T9	35
fifo_depth[1]	auto[0]	auto[0]	auto[1]	69694	1			T2	18		T4	297		T9	23
fifo_depth[1]	auto[0]	auto[1]	auto[0]	549288	1			T2	87		T3	2518		T4	238
fifo_depth[1]	auto[0]	auto[1]	auto[1]	68506	1			T2	5		T4	206		T9	53
fifo_depth[1]	auto[1]	auto[0]	auto[0]	150464	1			T1	78		T2	10		T4	1169
fifo_depth[1]	auto[1]	auto[0]	auto[1]	148820	1			T1	397		T2	8		T4	1150
fifo_depth[1]	auto[1]	auto[1]	auto[0]	147541	1			T1	280		T2	54		T4	522
fifo_depth[1]	auto[1]	auto[1]	auto[1]	149022	1			T1	38		T2	34		T4	781
fifo_depth[2]	auto[0]	auto[0]	auto[0]	63333	1			T2	346		T4	212		T9	19
fifo_depth[2]	auto[0]	auto[0]	auto[1]	65235	1			T2	87		T4	201		T9	31
fifo_depth[2]	auto[0]	auto[1]	auto[0]	470335	1			T2	58		T3	2292		T4	113
fifo_depth[2]	auto[0]	auto[1]	auto[1]	63512	1			T2	5		T4	107		T9	61
fifo_depth[2]	auto[1]	auto[0]	auto[0]	137523	1			T1	81		T2	13		T4	567
fifo_depth[2]	auto[1]	auto[0]	auto[1]	136132	1			T1	407		T2	9		T4	542
fifo_depth[2]	auto[1]	auto[1]	auto[0]	134169	1			T1	273		T2	56		T4	294
fifo_depth[2]	auto[1]	auto[1]	auto[1]	136186	1			T1	51		T2	84		T4	348
fifo_depth[3]	auto[0]	auto[0]	auto[0]	53956	1			T2	368		T4	97		T9	33
fifo_depth[3]	auto[0]	auto[0]	auto[1]	56472	1			T2	75		T4	62		T9	17
fifo_depth[3]	auto[0]	auto[1]	auto[0]	374606	1			T2	86		T3	1960		T4	32
fifo_depth[3]	auto[0]	auto[1]	auto[1]	54431	1			T2	5		T4	31		T9	52
fifo_depth[3]	auto[1]	auto[0]	auto[0]	119792	1			T1	85		T2	31		T4	204
fifo_depth[3]	auto[1]	auto[0]	auto[1]	119044	1			T1	429		T2	9		T4	169
fifo_depth[3]	auto[1]	auto[1]	auto[0]	117366	1			T1	253		T2	58		T4	75
fifo_depth[3]	auto[1]	auto[1]	auto[1]	118598	1			T1	51		T2	120		T4	119
fifo_depth[4]	auto[0]	auto[0]	auto[0]	63979	1			T2	399		T4	70		T9	152
fifo_depth[4]	auto[0]	auto[0]	auto[1]	66103	1			T2	79		T4	47		T9	129
fifo_depth[4]	auto[0]	auto[1]	auto[0]	298507	1			T2	222		T3	1498		T4	22
fifo_depth[4]	auto[0]	auto[1]	auto[1]	65984	1			T2	5		T4	33		T9	54
fifo_depth[4]	auto[1]	auto[0]	auto[0]	125357	1			T1	79		T2	57		T4	76
fifo_depth[4]	auto[1]	auto[0]	auto[1]	127651	1			T1	418		T2	10		T4	88
fifo_depth[4]	auto[1]	auto[1]	auto[0]	121208	1			T1	272		T2	114		T4	53
fifo_depth[4]	auto[1]	auto[1]	auto[1]	124095	1			T1	48		T2	118		T4	64
fifo_depth[5]	auto[0]	auto[0]	auto[0]	51331	1			T2	422		T4	24		T9	64
fifo_depth[5]	auto[0]	auto[0]	auto[1]	52363	1			T2	70		T4	8		T9	123
fifo_depth[5]	auto[0]	auto[1]	auto[0]	244428	1			T2	85		T3	1189		T4	15
fifo_depth[5]	auto[0]	auto[1]	auto[1]	51427	1			T2	8		T4	12		T9	49
fifo_depth[5]	auto[1]	auto[0]	auto[0]	108668	1			T1	86		T2	56		T4	34
fifo_depth[5]	auto[1]	auto[0]	auto[1]	111962	1			T1	384		T2	8		T4	20
fifo_depth[5]	auto[1]	auto[1]	auto[0]	107649	1			T1	252		T2	72		T4	14
fifo_depth[5]	auto[1]	auto[1]	auto[1]	109683	1			T1	50		T2	110		T4	23
fifo_depth[6]	auto[0]	auto[0]	auto[0]	59355	1			T2	372		T4	14		T9	201
fifo_depth[6]	auto[0]	auto[0]	auto[1]	61821	1			T2	76		T4	6		T9	466
fifo_depth[6]	auto[0]	auto[1]	auto[0]	225167	1			T2	226		T3	1075		T4	4
fifo_depth[6]	auto[0]	auto[1]	auto[1]	59738	1			T2	6		T4	3		T9	64
fifo_depth[6]	auto[1]	auto[0]	auto[0]	117148	1			T1	64		T2	176		T4	14
fifo_depth[6]	auto[1]	auto[0]	auto[1]	119112	1			T1	395		T2	8		T4	9
fifo_depth[6]	auto[1]	auto[1]	auto[0]	113378	1			T1	260		T2	78		T4	5
fifo_depth[6]	auto[1]	auto[1]	auto[1]	115131	1			T1	42		T2	98		T4	9
fifo_depth[7]	auto[0]	auto[0]	auto[0]	50106	1			T2	391		T9	116		T5	20
fifo_depth[7]	auto[0]	auto[0]	auto[1]	51557	1			T2	65		T4	1		T9	470
fifo_depth[7]	auto[0]	auto[1]	auto[0]	181623	1			T2	80		T3	875		T4	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	48880	1			T2	5		T9	72		T43	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	101294	1			T1	78		T2	174		T4	4
fifo_depth[7]	auto[1]	auto[0]	auto[1]	103829	1			T1	372		T2	23		T9	313
fifo_depth[7]	auto[1]	auto[1]	auto[0]	101149	1			T1	249		T2	74		T4	3
fifo_depth[7]	auto[1]	auto[1]	auto[1]	100918	1			T1	31		T2	106		T4	3
fifo_depth[8]	auto[0]	auto[0]	auto[0]	84128	1			T2	458		T4	2		T9	407
fifo_depth[8]	auto[0]	auto[0]	auto[1]	79673	1			T2	81		T4	1		T9	424
fifo_depth[8]	auto[0]	auto[1]	auto[0]	179875	1			T2	298		T3	672		T9	126
fifo_depth[8]	auto[0]	auto[1]	auto[1]	79206	1			T2	23		T4	1		T9	161
fifo_depth[8]	auto[1]	auto[0]	auto[0]	120676	1			T1	55		T2	247		T4	1
fifo_depth[8]	auto[1]	auto[0]	auto[1]	121635	1			T1	303		T2	83		T4	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	119717	1			T1	193		T2	131		T4	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	121191	1			T1	34		T2	96		T9	149
fifo_depth[9]	auto[0]	auto[0]	auto[0]	40358	1			T2	382		T9	199		T5	13
fifo_depth[9]	auto[0]	auto[0]	auto[1]	40763	1			T2	78		T9	422		T46	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	107275	1			T2	71		T3	428		T9	89
fifo_depth[9]	auto[0]	auto[1]	auto[1]	38727	1			T2	22		T9	138		T6	515
fifo_depth[9]	auto[1]	auto[0]	auto[0]	72989	1			T1	56		T2	253		T9	175
fifo_depth[9]	auto[1]	auto[0]	auto[1]	74739	1			T1	239		T2	50		T9	265
fifo_depth[9]	auto[1]	auto[1]	auto[0]	71599	1			T1	134		T2	55		T9	221
fifo_depth[9]	auto[1]	auto[1]	auto[1]	73825	1			T1	23		T2	96		T9	6
fifo_depth[10]	auto[0]	auto[0]	auto[0]	50407	1			T2	347		T9	306		T5	9
fifo_depth[10]	auto[0]	auto[0]	auto[1]	50418	1			T2	89		T9	388		T6	1024
fifo_depth[10]	auto[0]	auto[1]	auto[0]	94096	1			T2	270		T3	270		T9	104
fifo_depth[10]	auto[0]	auto[1]	auto[1]	49218	1			T2	121		T9	136		T6	701
fifo_depth[10]	auto[1]	auto[0]	auto[0]	74125	1			T1	29		T2	218		T9	173
fifo_depth[10]	auto[1]	auto[0]	auto[1]	74598	1			T1	165		T2	214		T9	317
fifo_depth[10]	auto[1]	auto[1]	auto[0]	69945	1			T1	103		T2	42		T9	278
fifo_depth[10]	auto[1]	auto[1]	auto[1]	73777	1			T1	20		T2	101		T9	7
fifo_depth[11]	auto[0]	auto[0]	auto[0]	30258	1			T2	339		T9	177		T5	6
fifo_depth[11]	auto[0]	auto[0]	auto[1]	31672	1			T2	70		T9	383		T6	649
fifo_depth[11]	auto[0]	auto[1]	auto[0]	57452	1			T2	40		T3	139		T9	107
fifo_depth[11]	auto[0]	auto[1]	auto[1]	28775	1			T2	114		T9	156		T6	366
fifo_depth[11]	auto[1]	auto[0]	auto[0]	44614	1			T1	15		T2	252		T9	133
fifo_depth[11]	auto[1]	auto[0]	auto[1]	45781	1			T1	102		T2	203		T9	336
fifo_depth[11]	auto[1]	auto[1]	auto[0]	42783	1			T1	62		T2	63		T9	186
fifo_depth[11]	auto[1]	auto[1]	auto[1]	44245	1			T1	8		T2	112		T9	8
fifo_depth[12]	auto[0]	auto[0]	auto[0]	67422	1			T2	305		T9	331		T5	4
fifo_depth[12]	auto[0]	auto[0]	auto[1]	65901	1			T2	367		T9	661		T5	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	81782	1			T2	207		T3	86		T9	333
fifo_depth[12]	auto[0]	auto[1]	auto[1]	61533	1			T2	112		T9	123		T6	509
fifo_depth[12]	auto[1]	auto[0]	auto[0]	76136	1			T1	9		T2	259		T9	122
fifo_depth[12]	auto[1]	auto[0]	auto[1]	73275	1			T1	39		T2	196		T9	328
fifo_depth[12]	auto[1]	auto[1]	auto[0]	67042	1			T1	38		T2	128		T9	615
fifo_depth[12]	auto[1]	auto[1]	auto[1]	73984	1			T1	4		T2	254		T9	130
fifo_depth[13]	auto[0]	auto[0]	auto[0]	28962	1			T2	297		T9	163		T10	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	29696	1			T2	61		T9	283		T6	508
fifo_depth[13]	auto[0]	auto[1]	auto[0]	36353	1			T2	15		T3	34		T9	310
fifo_depth[13]	auto[0]	auto[1]	auto[1]	27380	1			T2	107		T9	123		T5	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	34685	1			T1	6		T2	262		T9	136
fifo_depth[13]	auto[1]	auto[0]	auto[1]	32045	1			T1	17		T2	186		T9	319
fifo_depth[13]	auto[1]	auto[1]	auto[0]	30181	1			T1	15		T2	58		T9	212
fifo_depth[13]	auto[1]	auto[1]	auto[1]	32300	1			T1	4		T2	257		T9	6
fifo_depth[14]	auto[0]	auto[0]	auto[0]	50758	1			T2	282		T9	243		T6	435
fifo_depth[14]	auto[0]	auto[0]	auto[1]	48972	1			T2	276		T9	511		T6	663
fifo_depth[14]	auto[0]	auto[1]	auto[0]	52824	1			T2	157		T3	18		T9	1022
fifo_depth[14]	auto[0]	auto[1]	auto[1]	45871	1			T2	105		T9	111		T6	395
fifo_depth[14]	auto[1]	auto[0]	auto[0]	56238	1			T2	411		T9	134		T5	2
fifo_depth[14]	auto[1]	auto[0]	auto[1]	53168	1			T1	8		T2	206		T9	228
fifo_depth[14]	auto[1]	auto[1]	auto[0]	47878	1			T1	6		T2	171		T9	265
fifo_depth[14]	auto[1]	auto[1]	auto[1]	51713	1			T2	274		T6	585		T30	433
fifo_depth[15]	auto[0]	auto[0]	auto[0]	29214	1			T2	237		T9	125		T6	333
fifo_depth[15]	auto[0]	auto[0]	auto[1]	28048	1			T2	27		T9	256		T6	343
fifo_depth[15]	auto[0]	auto[1]	auto[0]	29704	1			T2	9		T3	8		T9	886
fifo_depth[15]	auto[0]	auto[1]	auto[1]	26022	1			T2	74		T9	111		T6	210
fifo_depth[15]	auto[1]	auto[0]	auto[0]	32221	1			T1	1		T2	409		T9	111
fifo_depth[15]	auto[1]	auto[0]	auto[1]	29082	1			T1	1		T2	120		T9	204
fifo_depth[15]	auto[1]	auto[1]	auto[0]	28272	1			T1	2		T2	182		T9	208
fifo_depth[15]	auto[1]	auto[1]	auto[1]	27194	1			T2	279		T9	6		T6	111
fifo_depth[16]	auto[0]	auto[0]	auto[0]	112475	1			T2	760		T9	740		T6	2756
fifo_depth[16]	auto[0]	auto[0]	auto[1]	125530	1			T2	310		T9	890		T6	1260
fifo_depth[16]	auto[0]	auto[1]	auto[0]	117848	1			T2	126		T3	5		T9	742
fifo_depth[16]	auto[0]	auto[1]	auto[1]	120488	1			T2	58		T9	1404		T6	385
fifo_depth[16]	auto[1]	auto[0]	auto[0]	123163	1			T2	292		T9	953		T5	3
fifo_depth[16]	auto[1]	auto[0]	auto[1]	121593	1			T1	1		T2	615		T9	708
fifo_depth[16]	auto[1]	auto[1]	auto[0]	127379	1			T2	986		T9	3684		T6	908
fifo_depth[16]	auto[1]	auto[1]	auto[1]	118269	1			T2	147		T9	88		T6	833