Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	36220331	1			T12	10		T13	11		T15	1
all_pins[1]	36220331	1			T12	10		T13	11		T15	1
all_pins[2]	36220331	1			T12	10		T13	11		T15	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78434115	1			T12	28		T13	30		T15	3
values[0x1]	30226878	1			T12	2		T13	3		T19	3
transitions[0x0=>0x1]	26657364	1			T12	2		T13	2		T19	3
transitions[0x1=>0x0]	26657387	1			T12	2		T13	3		T19	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	36061286	1			T12	10		T13	9		T15	1
all_pins[0]	values[0x1]	159045	1			T13	2		T19	3		T28	2
all_pins[0]	transitions[0x0=>0x1]	158806	1			T13	1		T19	3		T28	2
all_pins[0]	transitions[0x1=>0x0]	13739621	1			T12	1		T28	2		T78	3
all_pins[1]	values[0x0]	19892335	1			T12	9		T13	10		T15	1
all_pins[1]	values[0x1]	16327996	1			T12	1		T13	1		T28	3
all_pins[1]	transitions[0x0=>0x1]	16203709	1			T12	1		T13	1		T28	1
all_pins[1]	transitions[0x1=>0x0]	34758	1			T13	2		T19	3		T29	2
all_pins[2]	values[0x0]	22480494	1			T12	9		T13	11		T15	1
all_pins[2]	values[0x1]	13739837	1			T12	1		T28	2		T78	3
all_pins[2]	transitions[0x0=>0x1]	10294849	1			T12	1		T78	2		T108	2
all_pins[2]	transitions[0x1=>0x0]	12883008	1			T12	1		T13	1		T28	1