Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3893 1 T12 10 T13 10 T19 4
all_values[1] 3893 1 T12 10 T13 10 T19 4
all_values[2] 3893 1 T12 10 T13 10 T19 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5545 1 T12 18 T13 15 T19 7
auto[1] 6134 1 T12 12 T13 15 T19 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4410 1 T12 18 T13 14 T19 7
auto[1] 7269 1 T12 12 T13 16 T19 5


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6686 1 T12 20 T13 17 T19 8
auto[1] 4993 1 T12 10 T13 13 T19 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 649 1 T12 7 T19 1 T29 2
all_values[0] auto[0] auto[0] auto[1] 384 1 T12 1 T29 1 T140 1
all_values[0] auto[0] auto[1] auto[0] 801 1 T12 1 T13 5 T28 5
all_values[0] auto[0] auto[1] auto[1] 364 1 T13 1 T19 1 T28 1
all_values[0] auto[1] auto[0] auto[1] 837 1 T13 2 T28 2 T29 1
all_values[0] auto[1] auto[1] auto[1] 858 1 T12 1 T13 2 T19 2
all_values[1] auto[0] auto[0] auto[0] 689 1 T12 4 T13 3 T19 2
all_values[1] auto[0] auto[0] auto[1] 397 1 T78 1 T108 1 T140 1
all_values[1] auto[0] auto[1] auto[0] 787 1 T12 1 T13 1 T19 2
all_values[1] auto[0] auto[1] auto[1] 362 1 T13 1 T28 1 T29 3
all_values[1] auto[1] auto[0] auto[1] 760 1 T12 2 T13 2 T28 1
all_values[1] auto[1] auto[1] auto[1] 898 1 T12 3 T13 3 T28 4
all_values[2] auto[0] auto[0] auto[0] 682 1 T12 2 T13 4 T19 2
all_values[2] auto[0] auto[0] auto[1] 385 1 T13 1 T29 1 T109 1
all_values[2] auto[0] auto[1] auto[0] 802 1 T12 3 T13 1 T28 5
all_values[2] auto[0] auto[1] auto[1] 384 1 T12 1 T28 1 T108 1
all_values[2] auto[1] auto[0] auto[1] 762 1 T12 2 T13 3 T19 2
all_values[2] auto[1] auto[1] auto[1] 878 1 T12 2 T13 1 T28 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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