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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.69 100.00 100.00 99.76 99.49 99.86


Total test records in report: 904
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T761 /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.854294709 Jan 21 04:06:24 PM PST 24 Jan 21 04:54:49 PM PST 24 507725161070 ps
T762 /workspace/coverage/default/32.hmac_long_msg.4092428731 Jan 21 07:10:25 PM PST 24 Jan 21 07:10:45 PM PST 24 3994543948 ps
T763 /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.2951388123 Jan 21 04:16:39 PM PST 24 Jan 21 04:31:55 PM PST 24 57214285035 ps
T764 /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.1998538360 Jan 21 04:10:32 PM PST 24 Jan 21 04:32:01 PM PST 24 25082803051 ps
T765 /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.4281383691 Jan 21 04:08:53 PM PST 24 Jan 21 05:10:15 PM PST 24 76746618001 ps
T766 /workspace/coverage/default/17.hmac_error.3020043510 Jan 21 04:03:50 PM PST 24 Jan 21 04:04:40 PM PST 24 3632976834 ps
T767 /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.822517485 Jan 21 04:09:01 PM PST 24 Jan 21 04:15:55 PM PST 24 26270319674 ps
T768 /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.2135705586 Jan 21 04:09:51 PM PST 24 Jan 21 04:19:23 PM PST 24 330722744516 ps
T769 /workspace/coverage/default/41.hmac_datapath_stress.1101877851 Jan 21 04:06:42 PM PST 24 Jan 21 04:07:47 PM PST 24 4036077387 ps
T770 /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2622612920 Jan 21 04:03:03 PM PST 24 Jan 21 04:15:17 PM PST 24 52696799885 ps
T771 /workspace/coverage/default/22.hmac_alert_test.203812994 Jan 21 04:04:34 PM PST 24 Jan 21 04:04:36 PM PST 24 30697636 ps
T772 /workspace/coverage/default/49.hmac_alert_test.1811949897 Jan 21 04:07:52 PM PST 24 Jan 21 04:07:54 PM PST 24 44416023 ps
T773 /workspace/coverage/default/11.hmac_alert_test.1275146997 Jan 21 04:03:08 PM PST 24 Jan 21 04:03:10 PM PST 24 15580132 ps
T774 /workspace/coverage/default/21.hmac_burst_wr.930295562 Jan 21 07:32:43 PM PST 24 Jan 21 07:33:23 PM PST 24 1622500652 ps
T775 /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.3845908444 Jan 21 04:09:25 PM PST 24 Jan 21 04:15:32 PM PST 24 29125122679 ps
T776 /workspace/coverage/default/11.hmac_error.2047645606 Jan 21 04:03:04 PM PST 24 Jan 21 04:05:00 PM PST 24 146762149725 ps
T54 /workspace/coverage/default/2.hmac_sec_cm.1719447164 Jan 21 04:01:42 PM PST 24 Jan 21 04:01:47 PM PST 24 132309339 ps
T777 /workspace/coverage/default/7.hmac_back_pressure.4294326631 Jan 21 04:02:31 PM PST 24 Jan 21 04:02:48 PM PST 24 1089692940 ps
T778 /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.2917998771 Jan 21 04:09:15 PM PST 24 Jan 21 05:12:02 PM PST 24 80576352468 ps
T779 /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2977948368 Jan 21 04:26:27 PM PST 24 Jan 21 04:45:59 PM PST 24 288281566499 ps
T780 /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.2974345851 Jan 21 04:09:40 PM PST 24 Jan 21 04:28:53 PM PST 24 219539439553 ps
T781 /workspace/coverage/default/34.hmac_smoke.3768750269 Jan 21 04:05:46 PM PST 24 Jan 21 04:05:49 PM PST 24 507469531 ps
T782 /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.3715662982 Jan 21 04:08:00 PM PST 24 Jan 21 04:12:15 PM PST 24 32713898429 ps
T783 /workspace/coverage/default/18.hmac_test_hmac_vectors.677456465 Jan 21 04:04:02 PM PST 24 Jan 21 04:04:06 PM PST 24 58222006 ps
T784 /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.824925206 Jan 21 04:08:02 PM PST 24 Jan 21 04:52:05 PM PST 24 60506039060 ps
T785 /workspace/coverage/default/32.hmac_smoke.1671200934 Jan 21 04:05:33 PM PST 24 Jan 21 04:05:45 PM PST 24 417528240 ps
T786 /workspace/coverage/default/44.hmac_burst_wr.3995262306 Jan 21 04:07:11 PM PST 24 Jan 21 04:07:47 PM PST 24 7383054793 ps
T787 /workspace/coverage/default/26.hmac_test_sha_vectors.1996193200 Jan 21 04:05:03 PM PST 24 Jan 21 04:12:06 PM PST 24 27432643962 ps
T788 /workspace/coverage/default/25.hmac_smoke.3583969214 Jan 21 04:04:52 PM PST 24 Jan 21 04:04:54 PM PST 24 387694543 ps
T789 /workspace/coverage/default/29.hmac_stress_all.4286096495 Jan 21 04:05:19 PM PST 24 Jan 21 04:42:10 PM PST 24 125316601013 ps
T790 /workspace/coverage/default/37.hmac_burst_wr.1664502389 Jan 21 04:06:19 PM PST 24 Jan 21 04:06:46 PM PST 24 496329821 ps
T791 /workspace/coverage/default/7.hmac_wipe_secret.4181023979 Jan 21 04:02:39 PM PST 24 Jan 21 04:03:46 PM PST 24 3665230871 ps
T792 /workspace/coverage/default/14.hmac_back_pressure.4071588593 Jan 21 04:03:31 PM PST 24 Jan 21 04:04:20 PM PST 24 8188505880 ps
T793 /workspace/coverage/default/41.hmac_test_hmac_vectors.2243235808 Jan 21 04:06:42 PM PST 24 Jan 21 04:06:57 PM PST 24 101145480 ps
T794 /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.2454633968 Jan 21 04:10:14 PM PST 24 Jan 21 04:42:49 PM PST 24 1346153281083 ps
T795 /workspace/coverage/default/17.hmac_datapath_stress.535718390 Jan 21 04:03:49 PM PST 24 Jan 21 04:05:17 PM PST 24 3484083063 ps
T796 /workspace/coverage/default/45.hmac_wipe_secret.1438706202 Jan 21 05:01:37 PM PST 24 Jan 21 05:02:52 PM PST 24 3270759202 ps
T125 /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1331312898 Jan 21 04:08:37 PM PST 24 Jan 21 04:46:39 PM PST 24 193575487897 ps
T797 /workspace/coverage/default/32.hmac_back_pressure.322740381 Jan 21 05:20:24 PM PST 24 Jan 21 05:20:41 PM PST 24 438930796 ps
T798 /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.474145680 Jan 21 04:08:39 PM PST 24 Jan 21 04:33:44 PM PST 24 69500653302 ps
T799 /workspace/coverage/default/42.hmac_burst_wr.1760453923 Jan 21 04:06:49 PM PST 24 Jan 21 04:06:59 PM PST 24 365874924 ps
T800 /workspace/coverage/default/47.hmac_datapath_stress.4036045317 Jan 21 04:07:41 PM PST 24 Jan 21 04:09:36 PM PST 24 2276765953 ps
T801 /workspace/coverage/default/46.hmac_back_pressure.3241729372 Jan 21 04:07:24 PM PST 24 Jan 21 04:08:10 PM PST 24 1390506734 ps
T802 /workspace/coverage/default/13.hmac_burst_wr.4274644967 Jan 21 04:03:14 PM PST 24 Jan 21 04:03:59 PM PST 24 900650412 ps
T803 /workspace/coverage/default/23.hmac_long_msg.983379032 Jan 21 04:04:35 PM PST 24 Jan 21 04:05:59 PM PST 24 52352996471 ps
T804 /workspace/coverage/default/46.hmac_error.3318789828 Jan 21 04:43:18 PM PST 24 Jan 21 04:43:27 PM PST 24 578871721 ps
T805 /workspace/coverage/default/32.hmac_burst_wr.2780831901 Jan 21 04:05:45 PM PST 24 Jan 21 04:05:54 PM PST 24 462823821 ps
T806 /workspace/coverage/default/16.hmac_wipe_secret.18897825 Jan 21 04:03:48 PM PST 24 Jan 21 04:04:02 PM PST 24 270659984 ps
T807 /workspace/coverage/default/43.hmac_test_sha_vectors.338222629 Jan 21 04:07:03 PM PST 24 Jan 21 04:14:27 PM PST 24 26089663847 ps
T808 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3753237844 Jan 21 04:10:12 PM PST 24 Jan 21 05:39:51 PM PST 24 106355012456 ps
T809 /workspace/coverage/default/38.hmac_datapath_stress.3107758736 Jan 21 04:06:22 PM PST 24 Jan 21 04:07:07 PM PST 24 1337843975 ps
T810 /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1771000719 Jan 21 04:05:15 PM PST 24 Jan 21 04:28:18 PM PST 24 84966368786 ps
T811 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2571714513 Jan 21 04:08:40 PM PST 24 Jan 21 04:17:45 PM PST 24 33779150593 ps
T812 /workspace/coverage/default/0.hmac_test_sha_vectors.3222547766 Jan 21 04:30:26 PM PST 24 Jan 21 04:38:01 PM PST 24 109846806489 ps
T813 /workspace/coverage/default/25.hmac_wipe_secret.1652516051 Jan 21 04:04:51 PM PST 24 Jan 21 04:06:15 PM PST 24 4786309514 ps
T814 /workspace/coverage/default/8.hmac_back_pressure.1741137287 Jan 21 04:02:38 PM PST 24 Jan 21 04:03:18 PM PST 24 16406281396 ps
T815 /workspace/coverage/default/16.hmac_stress_all.3471122179 Jan 21 04:03:48 PM PST 24 Jan 21 04:04:02 PM PST 24 6747284907 ps
T816 /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.4174428679 Jan 21 04:07:26 PM PST 24 Jan 21 04:10:33 PM PST 24 3504925439 ps
T817 /workspace/coverage/default/24.hmac_back_pressure.1681631612 Jan 21 04:04:37 PM PST 24 Jan 21 04:04:55 PM PST 24 514576246 ps
T818 /workspace/coverage/default/37.hmac_smoke.1278738781 Jan 21 04:06:16 PM PST 24 Jan 21 04:06:22 PM PST 24 745727628 ps
T819 /workspace/coverage/default/10.hmac_smoke.3963995797 Jan 21 04:42:57 PM PST 24 Jan 21 04:43:02 PM PST 24 269030718 ps
T820 /workspace/coverage/default/26.hmac_error.3101329451 Jan 21 04:26:21 PM PST 24 Jan 21 04:28:25 PM PST 24 10010631459 ps
T821 /workspace/coverage/default/23.hmac_wipe_secret.3303688272 Jan 21 04:04:40 PM PST 24 Jan 21 04:04:58 PM PST 24 328185109 ps
T822 /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.423602689 Jan 21 04:10:12 PM PST 24 Jan 21 04:31:01 PM PST 24 100787591398 ps
T823 /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.1585558080 Jan 21 04:06:55 PM PST 24 Jan 21 04:33:39 PM PST 24 132976196399 ps
T824 /workspace/coverage/default/0.hmac_burst_wr.546656207 Jan 21 04:01:15 PM PST 24 Jan 21 04:02:06 PM PST 24 13451107501 ps
T825 /workspace/coverage/default/6.hmac_test_sha_vectors.1914653819 Jan 21 04:02:15 PM PST 24 Jan 21 04:10:18 PM PST 24 158796565054 ps
T826 /workspace/coverage/default/3.hmac_test_hmac_vectors.3351694686 Jan 21 05:29:48 PM PST 24 Jan 21 05:29:50 PM PST 24 54246340 ps
T827 /workspace/coverage/default/38.hmac_test_hmac_vectors.43452576 Jan 21 04:06:35 PM PST 24 Jan 21 04:06:55 PM PST 24 190654301 ps
T828 /workspace/coverage/default/42.hmac_stress_all.2761989629 Jan 21 04:07:01 PM PST 24 Jan 21 04:33:13 PM PST 24 90091297780 ps
T829 /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.3849275949 Jan 21 04:08:03 PM PST 24 Jan 21 04:25:04 PM PST 24 71353028973 ps
T830 /workspace/coverage/default/39.hmac_error.523735969 Jan 21 04:06:31 PM PST 24 Jan 21 04:09:30 PM PST 24 22849923522 ps
T831 /workspace/coverage/default/4.hmac_alert_test.3227085798 Jan 21 04:02:04 PM PST 24 Jan 21 04:02:09 PM PST 24 111780780 ps
T832 /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.4105902453 Jan 21 04:09:21 PM PST 24 Jan 21 04:36:13 PM PST 24 63395152250 ps
T833 /workspace/coverage/default/40.hmac_long_msg.3492159538 Jan 21 04:06:36 PM PST 24 Jan 21 04:07:56 PM PST 24 11004910104 ps
T834 /workspace/coverage/default/16.hmac_back_pressure.714575074 Jan 21 04:03:44 PM PST 24 Jan 21 04:04:07 PM PST 24 667650518 ps
T835 /workspace/coverage/default/43.hmac_datapath_stress.1788304978 Jan 21 04:06:56 PM PST 24 Jan 21 04:08:44 PM PST 24 1882758483 ps
T836 /workspace/coverage/default/45.hmac_test_sha_vectors.2650730323 Jan 21 04:07:20 PM PST 24 Jan 21 04:15:29 PM PST 24 40869834034 ps
T837 /workspace/coverage/default/6.hmac_burst_wr.3659868204 Jan 21 04:02:14 PM PST 24 Jan 21 04:02:31 PM PST 24 1783673241 ps
T838 /workspace/coverage/default/21.hmac_alert_test.1398257531 Jan 21 04:04:20 PM PST 24 Jan 21 04:04:22 PM PST 24 43700239 ps
T839 /workspace/coverage/default/42.hmac_wipe_secret.3268815581 Jan 21 04:06:57 PM PST 24 Jan 21 04:08:18 PM PST 24 3912840556 ps
T840 /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.2193455753 Jan 21 04:08:03 PM PST 24 Jan 21 04:12:07 PM PST 24 30686224991 ps
T841 /workspace/coverage/default/35.hmac_long_msg.976781628 Jan 21 06:09:13 PM PST 24 Jan 21 06:09:16 PM PST 24 212630137 ps
T842 /workspace/coverage/default/21.hmac_stress_all.418859759 Jan 21 04:04:27 PM PST 24 Jan 21 04:30:45 PM PST 24 348232442672 ps
T843 /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1487223378 Jan 21 04:04:09 PM PST 24 Jan 21 04:34:06 PM PST 24 37563015461 ps
T844 /workspace/coverage/default/25.hmac_back_pressure.1984014655 Jan 21 04:04:46 PM PST 24 Jan 21 04:05:26 PM PST 24 1310494548 ps
T845 /workspace/coverage/default/49.hmac_test_hmac_vectors.2341932307 Jan 21 04:07:55 PM PST 24 Jan 21 04:07:58 PM PST 24 88313770 ps
T846 /workspace/coverage/default/4.hmac_error.3285738093 Jan 21 04:02:05 PM PST 24 Jan 21 04:02:55 PM PST 24 3655895297 ps
T847 /workspace/coverage/default/41.hmac_smoke.1174495819 Jan 21 04:06:36 PM PST 24 Jan 21 04:06:57 PM PST 24 112750524 ps
T848 /workspace/coverage/default/45.hmac_stress_all.3848610320 Jan 21 04:07:24 PM PST 24 Jan 21 04:13:15 PM PST 24 113582799311 ps
T849 /workspace/coverage/default/5.hmac_test_sha_vectors.2740903162 Jan 21 05:37:00 PM PST 24 Jan 21 05:44:55 PM PST 24 34392193752 ps
T850 /workspace/coverage/default/20.hmac_test_hmac_vectors.1627206742 Jan 21 04:55:09 PM PST 24 Jan 21 04:55:12 PM PST 24 53525540 ps
T851 /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.565840388 Jan 21 04:08:26 PM PST 24 Jan 21 04:34:13 PM PST 24 141501373819 ps
T852 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1588877403 Jan 21 09:00:35 PM PST 24 Jan 21 09:09:14 PM PST 24 1047923533913 ps
T853 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3870445537 Jan 21 09:01:53 PM PST 24 Jan 21 09:02:10 PM PST 24 42626075 ps
T854 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2132537574 Jan 21 09:00:38 PM PST 24 Jan 21 09:01:05 PM PST 24 36810476 ps
T855 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2489873330 Jan 21 09:01:53 PM PST 24 Jan 21 09:02:09 PM PST 24 18052988 ps
T856 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.26720792 Jan 21 09:35:07 PM PST 24 Jan 21 09:35:14 PM PST 24 21399738 ps
T857 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2722764271 Jan 21 09:00:45 PM PST 24 Jan 21 09:01:13 PM PST 24 26253001 ps
T858 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3461636349 Jan 21 10:09:21 PM PST 24 Jan 21 10:09:23 PM PST 24 34414899 ps
T859 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.391714026 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:54 PM PST 24 18053650 ps
T860 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.564303951 Jan 21 09:01:07 PM PST 24 Jan 21 09:01:35 PM PST 24 20804355 ps
T861 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3112939822 Jan 21 09:01:36 PM PST 24 Jan 21 09:01:55 PM PST 24 40889117 ps
T862 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3484559604 Jan 21 09:01:17 PM PST 24 Jan 21 09:01:43 PM PST 24 114808432 ps
T863 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3130371282 Jan 21 09:22:53 PM PST 24 Jan 21 09:22:55 PM PST 24 73590442 ps
T68 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4088650956 Jan 21 09:00:34 PM PST 24 Jan 21 09:01:04 PM PST 24 64508380 ps
T864 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2943135703 Jan 21 09:00:34 PM PST 24 Jan 21 09:01:03 PM PST 24 52432610 ps
T865 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2255782848 Jan 21 09:31:14 PM PST 24 Jan 21 09:31:24 PM PST 24 52598434 ps
T866 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3810222574 Jan 21 09:01:43 PM PST 24 Jan 21 09:02:03 PM PST 24 20073334 ps
T867 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.231052442 Jan 21 09:01:15 PM PST 24 Jan 21 09:01:40 PM PST 24 52831278 ps
T868 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1995077956 Jan 21 09:01:55 PM PST 24 Jan 21 09:02:13 PM PST 24 14881141 ps
T869 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1000514616 Jan 21 09:01:43 PM PST 24 Jan 21 09:02:56 PM PST 24 16442963411 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2914272597 Jan 21 09:00:34 PM PST 24 Jan 21 09:01:04 PM PST 24 1741025420 ps
T870 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.181956908 Jan 21 09:00:27 PM PST 24 Jan 21 09:00:55 PM PST 24 24539475 ps
T146 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4258863765 Jan 21 09:01:21 PM PST 24 Jan 21 09:01:47 PM PST 24 158995588 ps
T871 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3521330926 Jan 21 09:00:25 PM PST 24 Jan 21 09:00:53 PM PST 24 20846018 ps
T872 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.145378850 Jan 21 09:00:48 PM PST 24 Jan 21 09:01:15 PM PST 24 22550451 ps
T873 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4093468684 Jan 21 09:00:42 PM PST 24 Jan 21 09:01:10 PM PST 24 19163537 ps
T874 /workspace/coverage/cover_reg_top/11.hmac_intr_test.590197161 Jan 21 09:40:21 PM PST 24 Jan 21 09:40:27 PM PST 24 12820205 ps
T875 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2614563844 Jan 21 09:00:58 PM PST 24 Jan 21 09:01:26 PM PST 24 11349456 ps
T876 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.881101316 Jan 21 09:51:31 PM PST 24 Jan 21 09:51:36 PM PST 24 51832347 ps
T877 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3969649623 Jan 21 09:00:47 PM PST 24 Jan 21 09:01:15 PM PST 24 29863062 ps
T98 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1014153010 Jan 21 09:01:01 PM PST 24 Jan 21 09:01:28 PM PST 24 26464311 ps
T878 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2119200201 Jan 21 09:01:37 PM PST 24 Jan 21 09:01:56 PM PST 24 104313102 ps
T99 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.847015662 Jan 21 09:37:31 PM PST 24 Jan 21 09:37:38 PM PST 24 12930955 ps
T879 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4226626454 Jan 21 09:01:33 PM PST 24 Jan 21 09:01:55 PM PST 24 193157006 ps
T880 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2713439106 Jan 21 09:01:32 PM PST 24 Jan 21 09:01:52 PM PST 24 45452376 ps
T881 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2531622 Jan 21 09:00:49 PM PST 24 Jan 21 09:01:17 PM PST 24 26382385 ps
T882 /workspace/coverage/cover_reg_top/3.hmac_intr_test.500705069 Jan 21 09:00:32 PM PST 24 Jan 21 09:01:01 PM PST 24 11859911 ps
T883 /workspace/coverage/cover_reg_top/0.hmac_intr_test.237751104 Jan 21 09:00:28 PM PST 24 Jan 21 09:00:55 PM PST 24 23406274 ps
T884 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3698149966 Jan 21 09:00:35 PM PST 24 Jan 21 09:01:04 PM PST 24 23230152 ps
T885 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2180301874 Jan 21 09:01:39 PM PST 24 Jan 21 09:01:59 PM PST 24 244523982 ps
T886 /workspace/coverage/cover_reg_top/35.hmac_intr_test.438975393 Jan 21 09:01:53 PM PST 24 Jan 21 09:02:10 PM PST 24 16533991 ps
T67 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.7216757 Jan 21 10:35:53 PM PST 24 Jan 21 10:36:05 PM PST 24 590055542 ps
T887 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2859779312 Jan 21 09:00:45 PM PST 24 Jan 21 09:01:13 PM PST 24 144771729 ps
T888 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1900301354 Jan 21 09:00:55 PM PST 24 Jan 21 09:01:23 PM PST 24 22559228 ps
T889 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4204326613 Jan 21 09:01:35 PM PST 24 Jan 21 09:01:56 PM PST 24 148045910 ps
T890 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3550277710 Jan 21 09:01:41 PM PST 24 Jan 21 09:02:00 PM PST 24 124355903 ps
T891 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1267648617 Jan 21 09:00:33 PM PST 24 Jan 21 09:01:03 PM PST 24 61195530 ps
T892 /workspace/coverage/cover_reg_top/38.hmac_intr_test.407858825 Jan 21 09:01:55 PM PST 24 Jan 21 09:02:13 PM PST 24 28326338 ps
T893 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.169973211 Jan 21 09:01:34 PM PST 24 Jan 21 09:01:54 PM PST 24 17349149 ps
T894 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3117156162 Jan 21 09:00:35 PM PST 24 Jan 21 09:01:03 PM PST 24 15873278 ps
T895 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1744686614 Jan 21 09:01:36 PM PST 24 Jan 21 09:01:55 PM PST 24 98431217 ps
T896 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3830207933 Jan 21 09:01:46 PM PST 24 Jan 21 09:02:05 PM PST 24 33375634 ps
T897 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3646877272 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:54 PM PST 24 16150055 ps
T898 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2529952463 Jan 21 09:00:39 PM PST 24 Jan 21 09:01:07 PM PST 24 44411712 ps
T899 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4159783817 Jan 21 09:00:52 PM PST 24 Jan 21 09:01:22 PM PST 24 283031966 ps
T141 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.235934749 Jan 21 09:15:05 PM PST 24 Jan 21 09:15:09 PM PST 24 215719655 ps
T142 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3917757987 Jan 21 09:01:44 PM PST 24 Jan 21 09:02:04 PM PST 24 220602286 ps
T900 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2207936786 Jan 21 09:00:34 PM PST 24 Jan 21 09:01:04 PM PST 24 87579510 ps
T901 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.479638916 Jan 21 09:01:15 PM PST 24 Jan 21 09:01:40 PM PST 24 136861634 ps
T902 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2588112296 Jan 21 09:00:56 PM PST 24 Jan 21 09:01:24 PM PST 24 67008885 ps
T903 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1798609159 Jan 21 09:00:33 PM PST 24 Jan 21 09:01:02 PM PST 24 17011968 ps
T904 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.879609253 Jan 21 09:00:43 PM PST 24 Jan 21 09:01:11 PM PST 24 90656765 ps

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1442400977
Short name T12
Test name
Test status
Simulation time 142132534 ps
CPU time 0.62 seconds
Started Jan 21 09:01:34 PM PST 24
Finished Jan 21 09:01:53 PM PST 24
Peak memory 183636 kb
Host smart-c8e33ce6-1ec1-4dec-9071-89822de00f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442400977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1442400977
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.403319222
Short name T4
Test name
Test status
Simulation time 176879594109 ps
CPU time 2732.26 seconds
Started Jan 21 04:08:36 PM PST 24
Finished Jan 21 04:54:10 PM PST 24
Peak memory 263816 kb
Host smart-180d4676-584a-4e78-bcee-58270e7abf1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403319222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.403319222
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1533729926
Short name T14
Test name
Test status
Simulation time 595474531 ps
CPU time 2.63 seconds
Started Jan 21 09:25:16 PM PST 24
Finished Jan 21 09:25:25 PM PST 24
Peak memory 198144 kb
Host smart-dca45701-5e62-443b-b193-a0ac04c7e744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533729926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1533729926
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.318401986
Short name T6
Test name
Test status
Simulation time 1619426580449 ps
CPU time 3785.55 seconds
Started Jan 21 04:08:01 PM PST 24
Finished Jan 21 05:11:08 PM PST 24
Peak memory 258348 kb
Host smart-68f37237-f6b0-4b4b-985d-7d59e2b90664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318401986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.318401986
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4242266421
Short name T16
Test name
Test status
Simulation time 423378572 ps
CPU time 3.59 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:01:17 PM PST 24
Peak memory 198400 kb
Host smart-d4fcb23f-6dcc-4022-9243-19e3d3c49b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242266421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4242266421
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1637591551
Short name T91
Test name
Test status
Simulation time 638066340365 ps
CPU time 2596.75 seconds
Started Jan 21 04:08:41 PM PST 24
Finished Jan 21 04:52:00 PM PST 24
Peak memory 247536 kb
Host smart-3e3208ee-dcb3-4921-8d59-440c788e55e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637591551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.1637591551
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1606496590
Short name T13
Test name
Test status
Simulation time 55826534 ps
CPU time 0.61 seconds
Started Jan 21 10:13:43 PM PST 24
Finished Jan 21 10:13:50 PM PST 24
Peak memory 183620 kb
Host smart-4ae19000-dc7f-41e6-b214-42f5aaf42fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606496590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1606496590
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4003429310
Short name T65
Test name
Test status
Simulation time 6289628318 ps
CPU time 48.59 seconds
Started Jan 21 09:01:03 PM PST 24
Finished Jan 21 09:02:17 PM PST 24
Peak memory 198532 kb
Host smart-23e20b0c-b529-407a-95ad-f4630718ce1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003429310 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4003429310
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3949363357
Short name T82
Test name
Test status
Simulation time 17865354 ps
CPU time 0.76 seconds
Started Jan 21 09:25:41 PM PST 24
Finished Jan 21 09:25:47 PM PST 24
Peak memory 194920 kb
Host smart-4391e558-55cb-4e0f-b270-8b2398ac9e0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949363357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3949363357
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1891171204
Short name T50
Test name
Test status
Simulation time 220010806 ps
CPU time 0.9 seconds
Started Jan 21 04:02:07 PM PST 24
Finished Jan 21 04:02:11 PM PST 24
Peak memory 216128 kb
Host smart-fa587577-62da-44e7-a51d-54df7539dd81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891171204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1891171204
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1790314045
Short name T129
Test name
Test status
Simulation time 164939711371 ps
CPU time 1977.9 seconds
Started Jan 21 04:09:32 PM PST 24
Finished Jan 21 04:42:31 PM PST 24
Peak memory 248532 kb
Host smart-390b23af-c4b5-422a-ad47-724cf606f020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790314045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.1790314045
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.235934749
Short name T141
Test name
Test status
Simulation time 215719655 ps
CPU time 2.36 seconds
Started Jan 21 09:15:05 PM PST 24
Finished Jan 21 09:15:09 PM PST 24
Peak memory 198060 kb
Host smart-03ebf8ad-c6cf-4a08-89f1-255e37b117bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235934749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.235934749
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2490839450
Short name T124
Test name
Test status
Simulation time 17737693745 ps
CPU time 346.12 seconds
Started Jan 21 04:01:26 PM PST 24
Finished Jan 21 04:07:13 PM PST 24
Peak memory 234028 kb
Host smart-ce9865c2-7a40-44fe-8889-8984e37a0196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490839450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2490839450
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1413293960
Short name T120
Test name
Test status
Simulation time 170091767687 ps
CPU time 2063.54 seconds
Started Jan 21 04:03:40 PM PST 24
Finished Jan 21 04:38:05 PM PST 24
Peak memory 233076 kb
Host smart-c7b0e57e-3b3f-4d8e-bd82-cacde25db32f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413293960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.1413293960
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.945018630
Short name T135
Test name
Test status
Simulation time 101465295355 ps
CPU time 422.2 seconds
Started Jan 21 04:10:14 PM PST 24
Finished Jan 21 04:17:18 PM PST 24
Peak memory 243416 kb
Host smart-76ad5ed9-5ae3-4333-881e-51b79485ffe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945018630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.945018630
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.289416863
Short name T104
Test name
Test status
Simulation time 13815769 ps
CPU time 0.61 seconds
Started Jan 21 09:00:39 PM PST 24
Finished Jan 21 09:01:07 PM PST 24
Peak memory 193588 kb
Host smart-3d41ec34-3b81-4bb8-befb-6cdeb46bde51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289416863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.289416863
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/default/14.hmac_alert_test.626202675
Short name T252
Test name
Test status
Simulation time 19049271 ps
CPU time 0.6 seconds
Started Jan 21 04:03:32 PM PST 24
Finished Jan 21 04:03:34 PM PST 24
Peak memory 192504 kb
Host smart-e82c4727-8bde-4b9f-bbd2-d7c986b4c2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626202675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.626202675
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1729571166
Short name T150
Test name
Test status
Simulation time 31058443 ps
CPU time 0.65 seconds
Started Jan 21 09:01:43 PM PST 24
Finished Jan 21 09:02:03 PM PST 24
Peak memory 183600 kb
Host smart-9b244e4d-7641-45c0-81fd-a5252b343803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729571166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1729571166
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3086576789
Short name T276
Test name
Test status
Simulation time 4347804827 ps
CPU time 59.3 seconds
Started Jan 21 04:01:17 PM PST 24
Finished Jan 21 04:02:18 PM PST 24
Peak memory 199164 kb
Host smart-1cd6912a-ed4d-40a6-9427-b783b736a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086576789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3086576789
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1331312898
Short name T125
Test name
Test status
Simulation time 193575487897 ps
CPU time 2280.47 seconds
Started Jan 21 04:08:37 PM PST 24
Finished Jan 21 04:46:39 PM PST 24
Peak memory 250556 kb
Host smart-1c46e009-50cf-401d-a3be-71058308c6a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331312898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.1331312898
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.3641110773
Short name T136
Test name
Test status
Simulation time 127468799205 ps
CPU time 679.69 seconds
Started Jan 21 04:09:07 PM PST 24
Finished Jan 21 04:20:29 PM PST 24
Peak memory 215748 kb
Host smart-f84e84ff-7059-4969-886e-18e0bbf49f46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641110773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.3641110773
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_error.1776560908
Short name T138
Test name
Test status
Simulation time 2420666886 ps
CPU time 118.26 seconds
Started Jan 21 04:04:04 PM PST 24
Finished Jan 21 04:06:08 PM PST 24
Peak memory 199092 kb
Host smart-7380f182-eed6-422f-b5b7-09fcb63c418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776560908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1776560908
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1988519385
Short name T137
Test name
Test status
Simulation time 136402647094 ps
CPU time 1861.97 seconds
Started Jan 21 04:06:06 PM PST 24
Finished Jan 21 04:37:14 PM PST 24
Peak memory 248440 kb
Host smart-ea263cd2-ae3d-473d-8bca-26d1956aaa63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988519385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.1988519385
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.7216757
Short name T67
Test name
Test status
Simulation time 590055542 ps
CPU time 2.47 seconds
Started Jan 21 10:35:53 PM PST 24
Finished Jan 21 10:36:05 PM PST 24
Peak memory 198164 kb
Host smart-b91e309d-7930-4af9-b47a-bf23107da2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7216757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.7216757
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4088650956
Short name T68
Test name
Test status
Simulation time 64508380 ps
CPU time 1.28 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:01:04 PM PST 24
Peak memory 197768 kb
Host smart-cd8551b6-f810-4a80-b451-5d8d5870c147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088650956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4088650956
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4058509450
Short name T86
Test name
Test status
Simulation time 221943331 ps
CPU time 1.93 seconds
Started Jan 21 09:00:29 PM PST 24
Finished Jan 21 09:00:59 PM PST 24
Peak memory 192004 kb
Host smart-77d6fb06-6983-4952-8029-4d2c2a9a6f4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058509450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4058509450
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1348381040
Short name T90
Test name
Test status
Simulation time 530026802 ps
CPU time 5.53 seconds
Started Jan 21 09:00:23 PM PST 24
Finished Jan 21 09:00:56 PM PST 24
Peak memory 192032 kb
Host smart-06b55c5f-dc51-47f2-b060-7f54a298ace5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348381040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1348381040
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3646877272
Short name T897
Test name
Test status
Simulation time 16150055 ps
CPU time 0.61 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:54 PM PST 24
Peak memory 193768 kb
Host smart-df6249e5-7629-4b20-b091-5eee119b6717
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646877272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3646877272
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3521330926
Short name T871
Test name
Test status
Simulation time 20846018 ps
CPU time 1.13 seconds
Started Jan 21 09:00:25 PM PST 24
Finished Jan 21 09:00:53 PM PST 24
Peak memory 198220 kb
Host smart-b67dc15f-38d0-4fcf-81c6-9c8d9f9d4f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521330926 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3521330926
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.181956908
Short name T870
Test name
Test status
Simulation time 24539475 ps
CPU time 0.72 seconds
Started Jan 21 09:00:27 PM PST 24
Finished Jan 21 09:00:55 PM PST 24
Peak memory 193948 kb
Host smart-937b241a-292b-4e4f-be39-8f8e201d6c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181956908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.181956908
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.237751104
Short name T883
Test name
Test status
Simulation time 23406274 ps
CPU time 0.62 seconds
Started Jan 21 09:00:28 PM PST 24
Finished Jan 21 09:00:55 PM PST 24
Peak memory 183624 kb
Host smart-df31f7a8-19b3-4baf-a6d2-f9bd05589010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237751104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.237751104
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.391714026
Short name T859
Test name
Test status
Simulation time 18053650 ps
CPU time 0.88 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:54 PM PST 24
Peak memory 195108 kb
Host smart-09110618-046b-45c6-bb8e-5700f661ac94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391714026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.391714026
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.330405584
Short name T24
Test name
Test status
Simulation time 183247909 ps
CPU time 3.09 seconds
Started Jan 21 09:00:28 PM PST 24
Finished Jan 21 09:00:58 PM PST 24
Peak memory 198364 kb
Host smart-a02d2065-d5b6-452a-b091-190351725bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330405584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.330405584
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.176473898
Short name T188
Test name
Test status
Simulation time 113778660 ps
CPU time 2.31 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:56 PM PST 24
Peak memory 198216 kb
Host smart-c75e5d86-260e-4988-bf2c-0e8f774299e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176473898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.176473898
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2914272597
Short name T97
Test name
Test status
Simulation time 1741025420 ps
CPU time 2 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:01:04 PM PST 24
Peak memory 183792 kb
Host smart-24d8a61d-a869-4edd-bb54-56ca013b29a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914272597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2914272597
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2914541316
Short name T167
Test name
Test status
Simulation time 76962741 ps
CPU time 3.21 seconds
Started Jan 21 09:00:33 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 192020 kb
Host smart-8a036290-3d80-4778-bb4a-98e748af701c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914541316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2914541316
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1798609159
Short name T903
Test name
Test status
Simulation time 17011968 ps
CPU time 0.66 seconds
Started Jan 21 09:00:33 PM PST 24
Finished Jan 21 09:01:02 PM PST 24
Peak memory 193664 kb
Host smart-52e88fb1-8840-4ca9-b6af-e1c90628d21f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798609159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1798609159
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.634731809
Short name T160
Test name
Test status
Simulation time 14549806684 ps
CPU time 194.04 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:04:17 PM PST 24
Peak memory 206684 kb
Host smart-44502516-7e34-4dd9-b888-6e0a3ed05fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634731809 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.634731809
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2382150290
Short name T19
Test name
Test status
Simulation time 14726495 ps
CPU time 0.57 seconds
Started Jan 21 09:00:29 PM PST 24
Finished Jan 21 09:00:57 PM PST 24
Peak memory 183628 kb
Host smart-5ec20d38-6a2c-4bbb-89af-8fcd93366f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382150290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2382150290
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3641310398
Short name T161
Test name
Test status
Simulation time 236552715 ps
CPU time 1.37 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:01:03 PM PST 24
Peak memory 191956 kb
Host smart-f2cefe78-a665-488f-89fd-b5afafe72b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641310398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3641310398
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2859481124
Short name T184
Test name
Test status
Simulation time 421574918 ps
CPU time 3.01 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:56 PM PST 24
Peak memory 198404 kb
Host smart-16f0c08c-a13d-41d7-b90b-1389b0a150cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859481124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2859481124
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3137654368
Short name T179
Test name
Test status
Simulation time 245962592 ps
CPU time 1.27 seconds
Started Jan 21 09:00:25 PM PST 24
Finished Jan 21 09:00:53 PM PST 24
Peak memory 197984 kb
Host smart-fe2c1dc9-134b-442c-ab2f-493bee2e503d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137654368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3137654368
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3323968706
Short name T88
Test name
Test status
Simulation time 20607426 ps
CPU time 0.69 seconds
Started Jan 21 09:34:32 PM PST 24
Finished Jan 21 09:34:50 PM PST 24
Peak memory 194432 kb
Host smart-24a3c577-52c6-48be-9357-6a8562ac4d87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323968706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3323968706
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2614563844
Short name T875
Test name
Test status
Simulation time 11349456 ps
CPU time 0.56 seconds
Started Jan 21 09:00:58 PM PST 24
Finished Jan 21 09:01:26 PM PST 24
Peak memory 183576 kb
Host smart-18ef2a06-ae28-450c-bed1-99b8c42ec23e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614563844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2614563844
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.881101316
Short name T876
Test name
Test status
Simulation time 51832347 ps
CPU time 1.13 seconds
Started Jan 21 09:51:31 PM PST 24
Finished Jan 21 09:51:36 PM PST 24
Peak memory 191992 kb
Host smart-d18d4363-5fd1-4237-a88a-4d1c062af6e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881101316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.881101316
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.742099927
Short name T173
Test name
Test status
Simulation time 99830362 ps
CPU time 2.8 seconds
Started Jan 21 09:01:00 PM PST 24
Finished Jan 21 09:01:30 PM PST 24
Peak memory 198380 kb
Host smart-9126d87b-123d-4b62-999d-498b1f72fe7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742099927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.742099927
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.564303951
Short name T860
Test name
Test status
Simulation time 20804355 ps
CPU time 1.52 seconds
Started Jan 21 09:01:07 PM PST 24
Finished Jan 21 09:01:35 PM PST 24
Peak memory 198424 kb
Host smart-38c4e4ff-ce8c-4e82-b1c4-c0ac51d57dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564303951 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.564303951
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.590197161
Short name T874
Test name
Test status
Simulation time 12820205 ps
CPU time 0.59 seconds
Started Jan 21 09:40:21 PM PST 24
Finished Jan 21 09:40:27 PM PST 24
Peak memory 183640 kb
Host smart-9b6f1119-3230-48b1-921d-905dba317046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590197161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.590197161
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4237952298
Short name T73
Test name
Test status
Simulation time 114813941 ps
CPU time 1.16 seconds
Started Jan 21 10:37:28 PM PST 24
Finished Jan 21 10:37:41 PM PST 24
Peak memory 192048 kb
Host smart-80405d33-82a3-4602-9fa9-740d863ce80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237952298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4237952298
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3602150517
Short name T15
Test name
Test status
Simulation time 189456301 ps
CPU time 2.51 seconds
Started Jan 21 09:13:21 PM PST 24
Finished Jan 21 09:13:26 PM PST 24
Peak memory 198316 kb
Host smart-1572ed9e-a8b5-4c2c-b21f-92d3c7d7d4b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602150517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3602150517
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1378702271
Short name T164
Test name
Test status
Simulation time 108519635 ps
CPU time 1.46 seconds
Started Jan 21 09:01:18 PM PST 24
Finished Jan 21 09:01:43 PM PST 24
Peak memory 198452 kb
Host smart-1be9eebb-fd98-4aa4-9565-ce864ba9da47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378702271 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1378702271
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2255105031
Short name T18
Test name
Test status
Simulation time 72764863 ps
CPU time 0.73 seconds
Started Jan 21 09:48:02 PM PST 24
Finished Jan 21 09:48:03 PM PST 24
Peak memory 194036 kb
Host smart-2b2e124a-7194-4096-a618-2a41ab0b22d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255105031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2255105031
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3481764957
Short name T28
Test name
Test status
Simulation time 42188564 ps
CPU time 0.58 seconds
Started Jan 21 09:01:22 PM PST 24
Finished Jan 21 09:01:46 PM PST 24
Peak memory 183820 kb
Host smart-cb194d3a-e3dc-4214-9cff-b5102860814f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481764957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3481764957
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.231052442
Short name T867
Test name
Test status
Simulation time 52831278 ps
CPU time 1.06 seconds
Started Jan 21 09:01:15 PM PST 24
Finished Jan 21 09:01:40 PM PST 24
Peak memory 196448 kb
Host smart-da3aa8c3-d921-498c-aa2b-e6e9dfca574a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231052442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.231052442
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.25873911
Short name T77
Test name
Test status
Simulation time 1315180948 ps
CPU time 2.92 seconds
Started Jan 21 09:01:09 PM PST 24
Finished Jan 21 09:01:38 PM PST 24
Peak memory 198468 kb
Host smart-2a74b67d-2d04-47b8-851c-c7f2a5580750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.25873911
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1565735486
Short name T143
Test name
Test status
Simulation time 660815704 ps
CPU time 2.37 seconds
Started Jan 21 09:01:18 PM PST 24
Finished Jan 21 09:01:44 PM PST 24
Peak memory 198132 kb
Host smart-36da8326-3f4a-4532-b554-a7cdb26d5402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565735486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1565735486
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1245151754
Short name T152
Test name
Test status
Simulation time 23657643 ps
CPU time 1.32 seconds
Started Jan 21 09:01:21 PM PST 24
Finished Jan 21 09:01:45 PM PST 24
Peak memory 198424 kb
Host smart-a70cf810-2772-49b8-8129-936d1c6f2e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245151754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1245151754
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.479638916
Short name T901
Test name
Test status
Simulation time 136861634 ps
CPU time 0.7 seconds
Started Jan 21 09:01:15 PM PST 24
Finished Jan 21 09:01:40 PM PST 24
Peak memory 194012 kb
Host smart-088189f1-0d01-4280-87b5-15e434048029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479638916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.479638916
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.21871211
Short name T174
Test name
Test status
Simulation time 15142849 ps
CPU time 0.57 seconds
Started Jan 21 09:01:16 PM PST 24
Finished Jan 21 09:01:41 PM PST 24
Peak memory 183644 kb
Host smart-4c675f08-071d-4583-836d-4fd84fa8b2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21871211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.21871211
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.650103271
Short name T79
Test name
Test status
Simulation time 55800537 ps
CPU time 1.12 seconds
Started Jan 21 09:01:24 PM PST 24
Finished Jan 21 09:01:47 PM PST 24
Peak memory 192180 kb
Host smart-1e126985-a792-4d27-8d52-b2b7da4a00cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650103271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.650103271
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3484559604
Short name T862
Test name
Test status
Simulation time 114808432 ps
CPU time 2.66 seconds
Started Jan 21 09:01:17 PM PST 24
Finished Jan 21 09:01:43 PM PST 24
Peak memory 198432 kb
Host smart-51347a5c-63d2-46a2-988e-4052229fed9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484559604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3484559604
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4258863765
Short name T146
Test name
Test status
Simulation time 158995588 ps
CPU time 2.55 seconds
Started Jan 21 09:01:21 PM PST 24
Finished Jan 21 09:01:47 PM PST 24
Peak memory 198160 kb
Host smart-b8eaaf6e-7f24-47be-bb23-8fad6298e71f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258863765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4258863765
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1097226127
Short name T185
Test name
Test status
Simulation time 58236714 ps
CPU time 0.86 seconds
Started Jan 21 09:01:31 PM PST 24
Finished Jan 21 09:01:51 PM PST 24
Peak memory 198284 kb
Host smart-6b2fab3d-d111-4e83-853b-dbc5692d5cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097226127 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1097226127
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.178446289
Short name T156
Test name
Test status
Simulation time 28779119 ps
CPU time 0.64 seconds
Started Jan 21 09:01:39 PM PST 24
Finished Jan 21 09:01:58 PM PST 24
Peak memory 194128 kb
Host smart-33d8c925-dceb-4c0f-9a42-793f15734210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178446289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.178446289
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2981961221
Short name T177
Test name
Test status
Simulation time 51856350 ps
CPU time 0.56 seconds
Started Jan 21 09:17:41 PM PST 24
Finished Jan 21 09:17:45 PM PST 24
Peak memory 183652 kb
Host smart-2e5ad349-e8c5-42d9-8f09-0e03637b81aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981961221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2981961221
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1744686614
Short name T895
Test name
Test status
Simulation time 98431217 ps
CPU time 1.2 seconds
Started Jan 21 09:01:36 PM PST 24
Finished Jan 21 09:01:55 PM PST 24
Peak memory 191984 kb
Host smart-0392df25-28a4-4464-82b1-0ff2c15c6e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744686614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1744686614
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1344967860
Short name T20
Test name
Test status
Simulation time 625043618 ps
CPU time 3.39 seconds
Started Jan 21 09:01:18 PM PST 24
Finished Jan 21 09:01:45 PM PST 24
Peak memory 198360 kb
Host smart-6afd9aa1-6d42-45fa-ad98-537b97af3ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344967860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1344967860
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4078177448
Short name T74
Test name
Test status
Simulation time 119873727 ps
CPU time 1.28 seconds
Started Jan 21 09:01:17 PM PST 24
Finished Jan 21 09:01:42 PM PST 24
Peak memory 197780 kb
Host smart-bac58208-0158-47b4-a976-c5c166451be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078177448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.4078177448
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.169973211
Short name T893
Test name
Test status
Simulation time 17349149 ps
CPU time 0.89 seconds
Started Jan 21 09:01:34 PM PST 24
Finished Jan 21 09:01:54 PM PST 24
Peak memory 198296 kb
Host smart-f3ad6510-ce51-4017-a422-75921264fc9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169973211 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.169973211
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3415151078
Short name T70
Test name
Test status
Simulation time 235623893 ps
CPU time 0.63 seconds
Started Jan 21 09:39:17 PM PST 24
Finished Jan 21 09:39:27 PM PST 24
Peak memory 193732 kb
Host smart-03d56a2c-a44d-4ff0-b8d7-4782199085b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415151078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3415151078
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3112939822
Short name T861
Test name
Test status
Simulation time 40889117 ps
CPU time 0.62 seconds
Started Jan 21 09:01:36 PM PST 24
Finished Jan 21 09:01:55 PM PST 24
Peak memory 183620 kb
Host smart-022a17ce-6fe8-4c76-ba83-acfe8da86a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112939822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3112939822
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1862168630
Short name T178
Test name
Test status
Simulation time 27355442 ps
CPU time 1.15 seconds
Started Jan 21 09:01:30 PM PST 24
Finished Jan 21 09:01:51 PM PST 24
Peak memory 196808 kb
Host smart-2e8e89ec-a75f-4965-bb08-fedb37e16ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862168630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1862168630
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4226626454
Short name T879
Test name
Test status
Simulation time 193157006 ps
CPU time 3.27 seconds
Started Jan 21 09:01:33 PM PST 24
Finished Jan 21 09:01:55 PM PST 24
Peak memory 198388 kb
Host smart-acb2f7cd-d716-43d2-b45f-71e240c95cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226626454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4226626454
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1944082628
Short name T22
Test name
Test status
Simulation time 16718619 ps
CPU time 0.88 seconds
Started Jan 21 09:01:36 PM PST 24
Finished Jan 21 09:01:55 PM PST 24
Peak memory 198284 kb
Host smart-68253c5e-4cb0-4ee6-ae5e-5db91c5b5a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944082628 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1944082628
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1606773890
Short name T85
Test name
Test status
Simulation time 80023007 ps
CPU time 0.71 seconds
Started Jan 21 09:22:13 PM PST 24
Finished Jan 21 09:22:16 PM PST 24
Peak memory 194060 kb
Host smart-49499b70-3596-4f58-8f99-5569466db40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606773890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1606773890
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1652003908
Short name T102
Test name
Test status
Simulation time 34067526 ps
CPU time 0.94 seconds
Started Jan 21 09:01:34 PM PST 24
Finished Jan 21 09:01:54 PM PST 24
Peak memory 191836 kb
Host smart-9c6fb147-bc9a-42fb-87b4-fa95d1717c3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652003908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1652003908
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3976472383
Short name T76
Test name
Test status
Simulation time 297369991 ps
CPU time 1.62 seconds
Started Jan 21 09:01:39 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 198432 kb
Host smart-a3e8f431-bba2-4e78-801a-92e10e385ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976472383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3976472383
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2119200201
Short name T878
Test name
Test status
Simulation time 104313102 ps
CPU time 1.74 seconds
Started Jan 21 09:01:37 PM PST 24
Finished Jan 21 09:01:56 PM PST 24
Peak memory 197992 kb
Host smart-342147d2-cd35-4dbe-9c32-c9653657812d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119200201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2119200201
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.556609404
Short name T96
Test name
Test status
Simulation time 20180812 ps
CPU time 1.68 seconds
Started Jan 21 09:01:39 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 198420 kb
Host smart-130609c8-14de-4667-968c-747ea8baa905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556609404 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.556609404
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1131324635
Short name T94
Test name
Test status
Simulation time 21319363 ps
CPU time 0.73 seconds
Started Jan 21 10:30:07 PM PST 24
Finished Jan 21 10:30:10 PM PST 24
Peak memory 194352 kb
Host smart-a957fe0e-f657-4de6-9e25-d4c83161d5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131324635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1131324635
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2713439106
Short name T880
Test name
Test status
Simulation time 45452376 ps
CPU time 0.62 seconds
Started Jan 21 09:01:32 PM PST 24
Finished Jan 21 09:01:52 PM PST 24
Peak memory 183584 kb
Host smart-a88efba0-8ab1-423d-8da4-4ea84dff7204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713439106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2713439106
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.26720792
Short name T856
Test name
Test status
Simulation time 21399738 ps
CPU time 1 seconds
Started Jan 21 09:35:07 PM PST 24
Finished Jan 21 09:35:14 PM PST 24
Peak memory 196808 kb
Host smart-c28cf969-f783-4a79-a1aa-a06129456f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26720792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_
outstanding.26720792
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4204326613
Short name T889
Test name
Test status
Simulation time 148045910 ps
CPU time 3.17 seconds
Started Jan 21 09:01:35 PM PST 24
Finished Jan 21 09:01:56 PM PST 24
Peak memory 198336 kb
Host smart-1eba386c-338f-49a4-8575-3c597968d595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204326613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4204326613
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.136932862
Short name T155
Test name
Test status
Simulation time 589788727 ps
CPU time 1.93 seconds
Started Jan 21 09:01:34 PM PST 24
Finished Jan 21 09:01:55 PM PST 24
Peak memory 197972 kb
Host smart-52aa5e5d-4cea-475d-ab01-f5d76d047ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136932862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.136932862
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.950150803
Short name T21
Test name
Test status
Simulation time 88662141 ps
CPU time 2.34 seconds
Started Jan 21 09:01:46 PM PST 24
Finished Jan 21 09:02:07 PM PST 24
Peak memory 198636 kb
Host smart-73ebc2b9-b33c-47a2-ab33-3927c557e4ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950150803 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.950150803
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4172938300
Short name T153
Test name
Test status
Simulation time 143842430 ps
CPU time 0.73 seconds
Started Jan 21 10:23:04 PM PST 24
Finished Jan 21 10:23:09 PM PST 24
Peak memory 194024 kb
Host smart-56ec9ec7-3c19-4b9c-9300-a182037eba2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172938300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4172938300
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3047758365
Short name T183
Test name
Test status
Simulation time 477755660 ps
CPU time 1.44 seconds
Started Jan 21 09:46:42 PM PST 24
Finished Jan 21 09:46:48 PM PST 24
Peak memory 196792 kb
Host smart-28d11713-ee32-4ccd-8483-984f7057aea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047758365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3047758365
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2180301874
Short name T885
Test name
Test status
Simulation time 244523982 ps
CPU time 2.16 seconds
Started Jan 21 09:01:39 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 198360 kb
Host smart-70d495ec-c1df-4b5c-83c1-538b0e465cac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180301874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2180301874
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.911151859
Short name T151
Test name
Test status
Simulation time 78926137 ps
CPU time 1.16 seconds
Started Jan 21 09:01:35 PM PST 24
Finished Jan 21 09:01:54 PM PST 24
Peak memory 198396 kb
Host smart-cabbcc37-c32a-4cf6-89a3-6ff1808570ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911151859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.911151859
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1000514616
Short name T869
Test name
Test status
Simulation time 16442963411 ps
CPU time 54.19 seconds
Started Jan 21 09:01:43 PM PST 24
Finished Jan 21 09:02:56 PM PST 24
Peak memory 206616 kb
Host smart-82e15436-9239-429e-a839-452352d20328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000514616 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1000514616
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.847015662
Short name T99
Test name
Test status
Simulation time 12930955 ps
CPU time 0.64 seconds
Started Jan 21 09:37:31 PM PST 24
Finished Jan 21 09:37:38 PM PST 24
Peak memory 193964 kb
Host smart-298fa17f-6651-42e8-9f73-94532f845730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847015662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.847015662
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3810222574
Short name T866
Test name
Test status
Simulation time 20073334 ps
CPU time 0.6 seconds
Started Jan 21 09:01:43 PM PST 24
Finished Jan 21 09:02:03 PM PST 24
Peak memory 183540 kb
Host smart-f1ab8117-af31-4bfe-9504-6f68b697ee6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810222574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3810222574
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3130371282
Short name T863
Test name
Test status
Simulation time 73590442 ps
CPU time 1.21 seconds
Started Jan 21 09:22:53 PM PST 24
Finished Jan 21 09:22:55 PM PST 24
Peak memory 192012 kb
Host smart-93d76e54-088f-4784-a527-f46e0afcec0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130371282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3130371282
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2255782848
Short name T865
Test name
Test status
Simulation time 52598434 ps
CPU time 1.74 seconds
Started Jan 21 09:31:14 PM PST 24
Finished Jan 21 09:31:24 PM PST 24
Peak memory 198428 kb
Host smart-db1385f1-6343-4e98-a7d0-aab4ae6f626d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255782848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2255782848
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3917757987
Short name T142
Test name
Test status
Simulation time 220602286 ps
CPU time 1.24 seconds
Started Jan 21 09:01:44 PM PST 24
Finished Jan 21 09:02:04 PM PST 24
Peak memory 197816 kb
Host smart-4fa7bf87-7407-4b66-b9d0-df76b0364449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917757987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3917757987
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2577016214
Short name T17
Test name
Test status
Simulation time 103797980 ps
CPU time 1.22 seconds
Started Jan 21 09:00:38 PM PST 24
Finished Jan 21 09:01:06 PM PST 24
Peak memory 192008 kb
Host smart-0acd7ca0-490d-412e-9816-115502cd6279
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577016214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2577016214
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2804008244
Short name T107
Test name
Test status
Simulation time 339587104 ps
CPU time 3.44 seconds
Started Jan 21 09:00:36 PM PST 24
Finished Jan 21 09:01:06 PM PST 24
Peak memory 191904 kb
Host smart-367abf12-0d0c-424b-8ab6-466ee0873a0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804008244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2804008244
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1740741368
Short name T106
Test name
Test status
Simulation time 15447344 ps
CPU time 0.64 seconds
Started Jan 21 09:00:37 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 193788 kb
Host smart-09d3f13b-4b0e-449f-8ce3-dcb162ec70ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740741368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1740741368
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1588877403
Short name T852
Test name
Test status
Simulation time 1047923533913 ps
CPU time 491.29 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:09:14 PM PST 24
Peak memory 211924 kb
Host smart-cb1a0153-91d6-4bf6-8a6b-8ccb4902143b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588877403 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1588877403
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1528724279
Short name T84
Test name
Test status
Simulation time 34887656 ps
CPU time 0.68 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:01:04 PM PST 24
Peak memory 194588 kb
Host smart-fb4fb508-0761-4b92-a1e6-e293e7f62689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528724279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1528724279
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2132537574
Short name T854
Test name
Test status
Simulation time 36810476 ps
CPU time 0.57 seconds
Started Jan 21 09:00:38 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 183636 kb
Host smart-fc369a57-510f-4782-b723-a273f342ffe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132537574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2132537574
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.845857235
Short name T80
Test name
Test status
Simulation time 36678283 ps
CPU time 0.81 seconds
Started Jan 21 09:00:37 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 191868 kb
Host smart-efffcf19-6cc7-4677-9b12-f2bf0dd39fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845857235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.845857235
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.897279912
Short name T169
Test name
Test status
Simulation time 2661757774 ps
CPU time 3.59 seconds
Started Jan 21 09:00:30 PM PST 24
Finished Jan 21 09:01:02 PM PST 24
Peak memory 198492 kb
Host smart-fd5bf3e3-e9e8-4a80-9c79-3f1ca74c4fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897279912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.897279912
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.560786922
Short name T148
Test name
Test status
Simulation time 435276429 ps
CPU time 1.81 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 198308 kb
Host smart-e5c938f9-21a7-42ef-8ffa-3f19db0ce431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560786922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.560786922
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3157686602
Short name T176
Test name
Test status
Simulation time 15050442 ps
CPU time 0.61 seconds
Started Jan 21 09:01:42 PM PST 24
Finished Jan 21 09:02:01 PM PST 24
Peak memory 183648 kb
Host smart-cedca97a-2f37-4cb3-83a1-d94a9ee33ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157686602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3157686602
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3461636349
Short name T858
Test name
Test status
Simulation time 34414899 ps
CPU time 0.61 seconds
Started Jan 21 10:09:21 PM PST 24
Finished Jan 21 10:09:23 PM PST 24
Peak memory 183620 kb
Host smart-28923a19-3cfe-4d95-861c-c70f4ae023c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461636349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3461636349
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3550277710
Short name T890
Test name
Test status
Simulation time 124355903 ps
CPU time 0.58 seconds
Started Jan 21 09:01:41 PM PST 24
Finished Jan 21 09:02:00 PM PST 24
Peak memory 183604 kb
Host smart-ad643869-d796-4fa8-836e-31d08aa35c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550277710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3550277710
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3203486910
Short name T29
Test name
Test status
Simulation time 18511118 ps
CPU time 0.58 seconds
Started Jan 21 09:01:40 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 183644 kb
Host smart-bb89050b-333e-491a-91e0-04055b2eda55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203486910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3203486910
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3114874658
Short name T159
Test name
Test status
Simulation time 19479795 ps
CPU time 0.62 seconds
Started Jan 21 09:01:41 PM PST 24
Finished Jan 21 09:02:00 PM PST 24
Peak memory 183620 kb
Host smart-a863cbca-fd35-40dd-ace6-55cb8a2157e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114874658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3114874658
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2498634083
Short name T163
Test name
Test status
Simulation time 36558834 ps
CPU time 0.56 seconds
Started Jan 21 09:01:40 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 183616 kb
Host smart-2f15ddc1-37b7-4396-a5b8-47468bae0138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498634083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2498634083
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.692323649
Short name T166
Test name
Test status
Simulation time 14561189 ps
CPU time 0.6 seconds
Started Jan 21 09:01:43 PM PST 24
Finished Jan 21 09:02:02 PM PST 24
Peak memory 183640 kb
Host smart-e94f7110-25cf-4165-bc25-2fde2fb74bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692323649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.692323649
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2787220722
Short name T181
Test name
Test status
Simulation time 16111559 ps
CPU time 0.58 seconds
Started Jan 21 09:37:04 PM PST 24
Finished Jan 21 09:37:19 PM PST 24
Peak memory 183580 kb
Host smart-9951f541-d4c8-4078-8c09-4c222d0b25f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787220722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2787220722
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1799597839
Short name T168
Test name
Test status
Simulation time 39428355 ps
CPU time 0.55 seconds
Started Jan 21 09:01:43 PM PST 24
Finished Jan 21 09:02:03 PM PST 24
Peak memory 183536 kb
Host smart-5551ad5d-8048-4a79-a7ac-f80104afc2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799597839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1799597839
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2943135703
Short name T864
Test name
Test status
Simulation time 52432610 ps
CPU time 1.19 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:01:03 PM PST 24
Peak memory 194980 kb
Host smart-751d66d6-c0cc-423d-a213-b3865b5dedaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943135703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2943135703
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1133371588
Short name T92
Test name
Test status
Simulation time 2009160139 ps
CPU time 9.63 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:01:13 PM PST 24
Peak memory 192012 kb
Host smart-a88feec7-1cac-40c5-a9e5-eb9f9205a32d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133371588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1133371588
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3117156162
Short name T894
Test name
Test status
Simulation time 15873278 ps
CPU time 0.63 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:01:03 PM PST 24
Peak memory 193684 kb
Host smart-4c2d2e66-74ad-409f-8e58-d3ca1fc73d8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117156162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3117156162
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.553333777
Short name T182
Test name
Test status
Simulation time 16694021 ps
CPU time 1.37 seconds
Started Jan 21 09:00:39 PM PST 24
Finished Jan 21 09:01:07 PM PST 24
Peak memory 198384 kb
Host smart-1b245e19-b10a-4eaf-8059-90aafac0364d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553333777 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.553333777
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3698149966
Short name T884
Test name
Test status
Simulation time 23230152 ps
CPU time 0.61 seconds
Started Jan 21 09:00:35 PM PST 24
Finished Jan 21 09:01:04 PM PST 24
Peak memory 193448 kb
Host smart-fc483114-e51b-4449-bc11-584a604cff17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698149966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3698149966
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.500705069
Short name T882
Test name
Test status
Simulation time 11859911 ps
CPU time 0.58 seconds
Started Jan 21 09:00:32 PM PST 24
Finished Jan 21 09:01:01 PM PST 24
Peak memory 183580 kb
Host smart-b5eb6d01-ed22-478a-a1ae-8a751c30e2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500705069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.500705069
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2153634327
Short name T158
Test name
Test status
Simulation time 76185669 ps
CPU time 1 seconds
Started Jan 21 09:00:36 PM PST 24
Finished Jan 21 09:01:05 PM PST 24
Peak memory 192004 kb
Host smart-3146b04b-9135-41f6-aed5-7d8c590422c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153634327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2153634327
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1267648617
Short name T891
Test name
Test status
Simulation time 61195530 ps
CPU time 1.5 seconds
Started Jan 21 09:00:33 PM PST 24
Finished Jan 21 09:01:03 PM PST 24
Peak memory 198376 kb
Host smart-c509d2f1-91e4-459a-8e22-c0f5c47c5f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267648617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1267648617
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3525141997
Short name T78
Test name
Test status
Simulation time 13552114 ps
CPU time 0.6 seconds
Started Jan 21 09:01:42 PM PST 24
Finished Jan 21 09:02:02 PM PST 24
Peak memory 183648 kb
Host smart-024ecbfb-0a52-4f16-a413-1bfe78181ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525141997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3525141997
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2093415145
Short name T140
Test name
Test status
Simulation time 38361372 ps
CPU time 0.54 seconds
Started Jan 21 09:01:38 PM PST 24
Finished Jan 21 09:01:56 PM PST 24
Peak memory 183648 kb
Host smart-a342cdd9-f420-4246-876b-b62b587bede3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093415145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2093415145
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4236674467
Short name T170
Test name
Test status
Simulation time 49495125 ps
CPU time 0.58 seconds
Started Jan 21 09:01:44 PM PST 24
Finished Jan 21 09:02:03 PM PST 24
Peak memory 183540 kb
Host smart-c0579a02-5d5f-4d8d-91e7-052deed6043f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236674467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4236674467
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3830207933
Short name T896
Test name
Test status
Simulation time 33375634 ps
CPU time 0.61 seconds
Started Jan 21 09:01:46 PM PST 24
Finished Jan 21 09:02:05 PM PST 24
Peak memory 183824 kb
Host smart-694bae13-733a-4889-b5fb-5637d27d4761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830207933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3830207933
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4268714765
Short name T162
Test name
Test status
Simulation time 60378048 ps
CPU time 0.6 seconds
Started Jan 21 09:01:46 PM PST 24
Finished Jan 21 09:02:05 PM PST 24
Peak memory 183824 kb
Host smart-c2fb820e-eba3-41e5-99a4-40f2a8fe7137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268714765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4268714765
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.438975393
Short name T886
Test name
Test status
Simulation time 16533991 ps
CPU time 0.64 seconds
Started Jan 21 09:01:53 PM PST 24
Finished Jan 21 09:02:10 PM PST 24
Peak memory 183624 kb
Host smart-c0335cd8-b811-4899-bba4-d66ae2655ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438975393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.438975393
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2489873330
Short name T855
Test name
Test status
Simulation time 18052988 ps
CPU time 0.58 seconds
Started Jan 21 09:01:53 PM PST 24
Finished Jan 21 09:02:09 PM PST 24
Peak memory 183644 kb
Host smart-ea202d50-c63d-4dce-a998-e7944435e339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489873330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2489873330
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3053115954
Short name T149
Test name
Test status
Simulation time 28791302 ps
CPU time 0.59 seconds
Started Jan 21 09:01:53 PM PST 24
Finished Jan 21 09:02:10 PM PST 24
Peak memory 183648 kb
Host smart-e4323e86-4a80-43e6-899e-f6f0d8a157e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053115954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3053115954
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.407858825
Short name T892
Test name
Test status
Simulation time 28326338 ps
CPU time 0.62 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:02:13 PM PST 24
Peak memory 183628 kb
Host smart-baaf195d-ede9-45c7-b854-8c12d1fd725e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407858825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.407858825
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3870445537
Short name T853
Test name
Test status
Simulation time 42626075 ps
CPU time 0.59 seconds
Started Jan 21 09:01:53 PM PST 24
Finished Jan 21 09:02:10 PM PST 24
Peak memory 183652 kb
Host smart-84f59a3a-7db4-441c-9924-13cb4049b30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870445537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3870445537
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.547330273
Short name T87
Test name
Test status
Simulation time 58269382 ps
CPU time 1.19 seconds
Started Jan 21 09:00:51 PM PST 24
Finished Jan 21 09:01:20 PM PST 24
Peak memory 183808 kb
Host smart-edab4424-d610-4dee-a739-2136c730cd78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547330273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.547330273
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4159783817
Short name T899
Test name
Test status
Simulation time 283031966 ps
CPU time 3.11 seconds
Started Jan 21 09:00:52 PM PST 24
Finished Jan 21 09:01:22 PM PST 24
Peak memory 191980 kb
Host smart-de8a9270-88e3-4292-985d-cc6c6a6ff5bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159783817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4159783817
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3697648859
Short name T165
Test name
Test status
Simulation time 26342808 ps
CPU time 0.71 seconds
Started Jan 21 09:00:44 PM PST 24
Finished Jan 21 09:01:12 PM PST 24
Peak memory 194084 kb
Host smart-be0da9ac-9f83-46bb-b6d9-b0c249a29480
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697648859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3697648859
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.957750450
Short name T180
Test name
Test status
Simulation time 128107106341 ps
CPU time 861.65 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:15:35 PM PST 24
Peak memory 210716 kb
Host smart-3df4420a-86d2-46a3-9221-5c09e0c2e7a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957750450 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.957750450
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.380331215
Short name T89
Test name
Test status
Simulation time 40614260 ps
CPU time 0.75 seconds
Started Jan 21 09:00:43 PM PST 24
Finished Jan 21 09:01:11 PM PST 24
Peak memory 194228 kb
Host smart-b1ec784c-8174-4fa6-9d30-ece86466c15e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380331215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.380331215
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2529952463
Short name T898
Test name
Test status
Simulation time 44411712 ps
CPU time 0.56 seconds
Started Jan 21 09:00:39 PM PST 24
Finished Jan 21 09:01:07 PM PST 24
Peak memory 183632 kb
Host smart-c8b4779a-9142-487a-8225-29daf5f47dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529952463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2529952463
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4217187565
Short name T105
Test name
Test status
Simulation time 81363317 ps
CPU time 1.01 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:01:16 PM PST 24
Peak memory 191944 kb
Host smart-a4b0e42f-a282-4bd7-86ba-68434423aa40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217187565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4217187565
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2207936786
Short name T900
Test name
Test status
Simulation time 87579510 ps
CPU time 1.52 seconds
Started Jan 21 09:00:34 PM PST 24
Finished Jan 21 09:01:04 PM PST 24
Peak memory 198648 kb
Host smart-cc371993-874e-4dc6-b595-c4ec93b4fe75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207936786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2207936786
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2428306643
Short name T93
Test name
Test status
Simulation time 85562192 ps
CPU time 1.2 seconds
Started Jan 21 09:00:39 PM PST 24
Finished Jan 21 09:01:07 PM PST 24
Peak memory 197356 kb
Host smart-58f01610-530a-4924-9bd1-ed0ae7b0663a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428306643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2428306643
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2132329209
Short name T109
Test name
Test status
Simulation time 14498288 ps
CPU time 0.58 seconds
Started Jan 21 09:01:52 PM PST 24
Finished Jan 21 09:02:09 PM PST 24
Peak memory 183648 kb
Host smart-6c878fac-16ed-42a3-924b-0067979a1946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132329209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2132329209
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.398560255
Short name T171
Test name
Test status
Simulation time 14300638 ps
CPU time 0.58 seconds
Started Jan 21 09:01:50 PM PST 24
Finished Jan 21 09:02:07 PM PST 24
Peak memory 183644 kb
Host smart-db980be7-5e97-4376-a528-ae79be2f6aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398560255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.398560255
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1386115699
Short name T95
Test name
Test status
Simulation time 13145622 ps
CPU time 0.59 seconds
Started Jan 21 09:01:50 PM PST 24
Finished Jan 21 09:02:07 PM PST 24
Peak memory 183640 kb
Host smart-e2ac3b6c-a4a0-47eb-815f-ccdb2ec2d2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386115699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1386115699
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.406294668
Short name T157
Test name
Test status
Simulation time 13863584 ps
CPU time 0.63 seconds
Started Jan 21 09:01:52 PM PST 24
Finished Jan 21 09:02:08 PM PST 24
Peak memory 183528 kb
Host smart-221a2a1e-59e7-4ff8-ac8d-ec63701da82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406294668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.406294668
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1995077956
Short name T868
Test name
Test status
Simulation time 14881141 ps
CPU time 0.6 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:02:13 PM PST 24
Peak memory 183636 kb
Host smart-dc5c7ad4-0219-4245-9e92-88ef13f28d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995077956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1995077956
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3151750813
Short name T69
Test name
Test status
Simulation time 87812148 ps
CPU time 0.6 seconds
Started Jan 21 09:01:51 PM PST 24
Finished Jan 21 09:02:08 PM PST 24
Peak memory 183624 kb
Host smart-a24e6f64-827b-478b-9864-88d5015e49c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151750813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3151750813
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.235085256
Short name T108
Test name
Test status
Simulation time 28841383 ps
CPU time 0.55 seconds
Started Jan 21 09:01:53 PM PST 24
Finished Jan 21 09:02:09 PM PST 24
Peak memory 183640 kb
Host smart-756a700e-4581-4452-89ee-6cbade20519c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235085256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.235085256
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2497659937
Short name T172
Test name
Test status
Simulation time 19405292 ps
CPU time 0.59 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:02:12 PM PST 24
Peak memory 183620 kb
Host smart-b082b6fe-9437-4814-82b7-61c43c3a9019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497659937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2497659937
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1625764622
Short name T186
Test name
Test status
Simulation time 42495068 ps
CPU time 0.6 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:02:15 PM PST 24
Peak memory 183604 kb
Host smart-f705602c-ca4b-47f2-9a2b-e2c625ffd5fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625764622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1625764622
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1369932685
Short name T72
Test name
Test status
Simulation time 106302054 ps
CPU time 0.6 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:02:15 PM PST 24
Peak memory 183604 kb
Host smart-775f1d0e-dc57-4d52-92bf-50fa0e0d726b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369932685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1369932685
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2240681807
Short name T27
Test name
Test status
Simulation time 34326410 ps
CPU time 1.21 seconds
Started Jan 21 09:00:51 PM PST 24
Finished Jan 21 09:01:19 PM PST 24
Peak memory 198456 kb
Host smart-57d876b1-c3b4-48da-821d-bb7db5a7ed1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240681807 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2240681807
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.145378850
Short name T872
Test name
Test status
Simulation time 22550451 ps
CPU time 0.7 seconds
Started Jan 21 09:00:48 PM PST 24
Finished Jan 21 09:01:15 PM PST 24
Peak memory 193944 kb
Host smart-f4bab822-ef88-4813-a8c4-a946c247ec15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145378850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.145378850
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2722764271
Short name T857
Test name
Test status
Simulation time 26253001 ps
CPU time 0.58 seconds
Started Jan 21 09:00:45 PM PST 24
Finished Jan 21 09:01:13 PM PST 24
Peak memory 183648 kb
Host smart-ea0b1b71-80c0-4e98-b28f-439a02385bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722764271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2722764271
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3890351090
Short name T83
Test name
Test status
Simulation time 66757007 ps
CPU time 1.45 seconds
Started Jan 21 09:00:49 PM PST 24
Finished Jan 21 09:01:18 PM PST 24
Peak memory 192008 kb
Host smart-fa4e6709-4c69-4b0e-99bf-f2c447ecbebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890351090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3890351090
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.879609253
Short name T904
Test name
Test status
Simulation time 90656765 ps
CPU time 1.52 seconds
Started Jan 21 09:00:43 PM PST 24
Finished Jan 21 09:01:11 PM PST 24
Peak memory 198420 kb
Host smart-f744d6dc-ce10-4f9a-9557-9ef0de67c6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879609253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.879609253
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1404818821
Short name T147
Test name
Test status
Simulation time 191462480 ps
CPU time 1.24 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:01:15 PM PST 24
Peak memory 197944 kb
Host smart-c2dcd677-bceb-4199-a974-c3e998ce62a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404818821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1404818821
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3761565228
Short name T23
Test name
Test status
Simulation time 23255507 ps
CPU time 1.8 seconds
Started Jan 21 09:00:50 PM PST 24
Finished Jan 21 09:01:19 PM PST 24
Peak memory 198440 kb
Host smart-caa6d2a7-591f-4327-b39a-e2df956178a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761565228 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3761565228
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2531622
Short name T881
Test name
Test status
Simulation time 26382385 ps
CPU time 0.63 seconds
Started Jan 21 09:00:49 PM PST 24
Finished Jan 21 09:01:17 PM PST 24
Peak memory 194008 kb
Host smart-f181f60d-1adf-4f9b-bbd7-60925cc90245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2531622
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3969649623
Short name T877
Test name
Test status
Simulation time 29863062 ps
CPU time 0.6 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:01:15 PM PST 24
Peak memory 183652 kb
Host smart-6150807d-db9a-4eb0-8ea7-644632e5e30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969649623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3969649623
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2859779312
Short name T887
Test name
Test status
Simulation time 144771729 ps
CPU time 1.33 seconds
Started Jan 21 09:00:45 PM PST 24
Finished Jan 21 09:01:13 PM PST 24
Peak memory 192048 kb
Host smart-77bf3303-17fa-4233-afd9-47b5681e3d54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859779312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2859779312
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1852483963
Short name T25
Test name
Test status
Simulation time 126976906 ps
CPU time 1.85 seconds
Started Jan 21 09:00:45 PM PST 24
Finished Jan 21 09:01:14 PM PST 24
Peak memory 198472 kb
Host smart-ad62803c-2dde-404c-aec8-364fb663432c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852483963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1852483963
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2570691189
Short name T64
Test name
Test status
Simulation time 115348135 ps
CPU time 1.78 seconds
Started Jan 21 09:00:45 PM PST 24
Finished Jan 21 09:01:14 PM PST 24
Peak memory 198160 kb
Host smart-46413657-3e07-4bce-ac10-fba72a7e4fda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570691189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2570691189
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1726011613
Short name T154
Test name
Test status
Simulation time 15758483 ps
CPU time 0.84 seconds
Started Jan 21 09:01:03 PM PST 24
Finished Jan 21 09:01:30 PM PST 24
Peak memory 198332 kb
Host smart-8ad1105e-9cfe-4062-8930-8f5276b114fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726011613 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1726011613
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2588112296
Short name T902
Test name
Test status
Simulation time 67008885 ps
CPU time 0.68 seconds
Started Jan 21 09:00:56 PM PST 24
Finished Jan 21 09:01:24 PM PST 24
Peak memory 194560 kb
Host smart-d83e5640-0bae-4487-9b95-e89825524282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588112296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2588112296
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4093468684
Short name T873
Test name
Test status
Simulation time 19163537 ps
CPU time 0.53 seconds
Started Jan 21 09:00:42 PM PST 24
Finished Jan 21 09:01:10 PM PST 24
Peak memory 183576 kb
Host smart-4c5d0d82-8870-4703-b8ff-2fb6705fa14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093468684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4093468684
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.951181862
Short name T103
Test name
Test status
Simulation time 118623383 ps
CPU time 1.34 seconds
Started Jan 21 09:01:01 PM PST 24
Finished Jan 21 09:01:28 PM PST 24
Peak memory 192000 kb
Host smart-b05eecab-1e96-4394-8935-da128537629f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951181862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.951181862
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.814703721
Short name T63
Test name
Test status
Simulation time 379042348 ps
CPU time 1.88 seconds
Started Jan 21 09:00:47 PM PST 24
Finished Jan 21 09:01:16 PM PST 24
Peak memory 198152 kb
Host smart-0c57b1ff-f348-4c1a-b3e5-6f342546e7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814703721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.814703721
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.689930816
Short name T71
Test name
Test status
Simulation time 189584755 ps
CPU time 1.66 seconds
Started Jan 21 09:00:57 PM PST 24
Finished Jan 21 09:01:26 PM PST 24
Peak memory 198376 kb
Host smart-d3da4b83-a3cd-4b30-bb8a-92213f8be3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689930816 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.689930816
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1900301354
Short name T888
Test name
Test status
Simulation time 22559228 ps
CPU time 0.74 seconds
Started Jan 21 09:00:55 PM PST 24
Finished Jan 21 09:01:23 PM PST 24
Peak memory 193924 kb
Host smart-379647c2-877b-4a87-8fc8-8146e10acd36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900301354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1900301354
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.404732206
Short name T75
Test name
Test status
Simulation time 25124999 ps
CPU time 0.58 seconds
Started Jan 21 09:01:02 PM PST 24
Finished Jan 21 09:01:29 PM PST 24
Peak memory 183576 kb
Host smart-3c598569-d1e7-4ea7-9618-fc9dc6d8bf5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404732206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.404732206
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4008188946
Short name T81
Test name
Test status
Simulation time 234746677 ps
CPU time 1.04 seconds
Started Jan 21 09:00:56 PM PST 24
Finished Jan 21 09:01:24 PM PST 24
Peak memory 191984 kb
Host smart-f0d4fc5f-d1a6-48eb-b0ae-d468b8c11f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008188946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4008188946
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.276359591
Short name T26
Test name
Test status
Simulation time 70038579 ps
CPU time 1.19 seconds
Started Jan 21 09:00:54 PM PST 24
Finished Jan 21 09:01:22 PM PST 24
Peak memory 198472 kb
Host smart-c91d954d-b834-4f95-8ad6-a03c05d0693b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276359591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.276359591
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3691886285
Short name T145
Test name
Test status
Simulation time 75286745 ps
CPU time 1.24 seconds
Started Jan 21 09:00:55 PM PST 24
Finished Jan 21 09:01:23 PM PST 24
Peak memory 197732 kb
Host smart-af6248c9-0956-4c86-8ed7-f5179d42defb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691886285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3691886285
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1209761626
Short name T66
Test name
Test status
Simulation time 269081117981 ps
CPU time 677.66 seconds
Started Jan 21 09:00:54 PM PST 24
Finished Jan 21 09:12:39 PM PST 24
Peak memory 206640 kb
Host smart-75869efa-b23d-48e0-aea2-40be7ab8ab52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209761626 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1209761626
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1014153010
Short name T98
Test name
Test status
Simulation time 26464311 ps
CPU time 0.63 seconds
Started Jan 21 09:01:01 PM PST 24
Finished Jan 21 09:01:28 PM PST 24
Peak memory 193720 kb
Host smart-8578351d-7157-4ab4-a5da-66cad15523f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014153010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1014153010
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1675492049
Short name T175
Test name
Test status
Simulation time 22538168 ps
CPU time 0.58 seconds
Started Jan 21 09:00:56 PM PST 24
Finished Jan 21 09:01:25 PM PST 24
Peak memory 183620 kb
Host smart-3bbc45c0-d329-4f10-a840-eaadacad17c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675492049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1675492049
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4098096075
Short name T189
Test name
Test status
Simulation time 366245511 ps
CPU time 1.45 seconds
Started Jan 21 09:00:56 PM PST 24
Finished Jan 21 09:01:25 PM PST 24
Peak memory 192028 kb
Host smart-40f11e99-91aa-44e8-a6c5-ed7fc50f416f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098096075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4098096075
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.589840338
Short name T187
Test name
Test status
Simulation time 514809525 ps
CPU time 2.28 seconds
Started Jan 21 09:01:02 PM PST 24
Finished Jan 21 09:01:30 PM PST 24
Peak memory 198380 kb
Host smart-cc28166a-c390-455f-aad9-4f44e3b9025f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589840338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.589840338
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2030682047
Short name T144
Test name
Test status
Simulation time 157620181 ps
CPU time 2.46 seconds
Started Jan 21 09:01:03 PM PST 24
Finished Jan 21 09:01:31 PM PST 24
Peak memory 198188 kb
Host smart-c3c5bb86-c1ee-46c4-a97d-41cd2a76ff16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030682047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2030682047
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1012740116
Short name T574
Test name
Test status
Simulation time 17398115 ps
CPU time 0.54 seconds
Started Jan 21 04:01:25 PM PST 24
Finished Jan 21 04:01:26 PM PST 24
Peak memory 192576 kb
Host smart-38e06499-29a5-4536-b249-349026f47575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012740116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1012740116
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1479950846
Short name T740
Test name
Test status
Simulation time 3952311313 ps
CPU time 13.41 seconds
Started Jan 21 04:01:16 PM PST 24
Finished Jan 21 04:01:32 PM PST 24
Peak memory 199168 kb
Host smart-857999de-ea7d-4f2c-bedb-9b4a4852c8d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479950846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1479950846
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.546656207
Short name T824
Test name
Test status
Simulation time 13451107501 ps
CPU time 48.67 seconds
Started Jan 21 04:01:15 PM PST 24
Finished Jan 21 04:02:06 PM PST 24
Peak memory 199136 kb
Host smart-012bd0a4-ba98-42ff-98f7-b744b09258fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546656207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.546656207
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3342065187
Short name T465
Test name
Test status
Simulation time 9567208717 ps
CPU time 113.51 seconds
Started Jan 21 04:01:16 PM PST 24
Finished Jan 21 04:03:11 PM PST 24
Peak memory 199196 kb
Host smart-568d32ea-24ca-4f98-abdf-85bc0ef28240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342065187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3342065187
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2344787134
Short name T511
Test name
Test status
Simulation time 10737889725 ps
CPU time 119.08 seconds
Started Jan 21 04:01:17 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 199216 kb
Host smart-41be21f2-8175-48e3-8ca0-ba018e9e6a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344787134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2344787134
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3570648450
Short name T281
Test name
Test status
Simulation time 8558767047 ps
CPU time 37.45 seconds
Started Jan 21 04:01:08 PM PST 24
Finished Jan 21 04:01:48 PM PST 24
Peak memory 199176 kb
Host smart-245cbb72-bc64-4602-9b2a-5b419f262c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570648450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3570648450
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2582417949
Short name T52
Test name
Test status
Simulation time 88401161 ps
CPU time 0.88 seconds
Started Jan 21 04:01:22 PM PST 24
Finished Jan 21 04:01:24 PM PST 24
Peak memory 216128 kb
Host smart-dde61ea4-c06b-4e65-8405-5668b88a9c48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582417949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2582417949
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2941705377
Short name T305
Test name
Test status
Simulation time 314118700 ps
CPU time 3.5 seconds
Started Jan 21 04:01:07 PM PST 24
Finished Jan 21 04:01:13 PM PST 24
Peak memory 198924 kb
Host smart-a30ab3de-8120-4de9-8c59-556774e2367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941705377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2941705377
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3810242247
Short name T583
Test name
Test status
Simulation time 95240806588 ps
CPU time 1905.16 seconds
Started Jan 21 04:01:23 PM PST 24
Finished Jan 21 04:33:09 PM PST 24
Peak memory 256644 kb
Host smart-f7557ff4-a6f0-498b-a228-05114a41ff7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810242247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3810242247
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2015069224
Short name T537
Test name
Test status
Simulation time 122492827 ps
CPU time 0.94 seconds
Started Jan 21 04:01:15 PM PST 24
Finished Jan 21 04:01:19 PM PST 24
Peak memory 196264 kb
Host smart-90658afb-ed53-47a3-ac49-80b968d328dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015069224 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2015069224
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3222547766
Short name T812
Test name
Test status
Simulation time 109846806489 ps
CPU time 454.09 seconds
Started Jan 21 04:30:26 PM PST 24
Finished Jan 21 04:38:01 PM PST 24
Peak memory 199076 kb
Host smart-b7b2a872-2e01-4578-b9af-0f8327f43c9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222547766 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.3222547766
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2699125347
Short name T487
Test name
Test status
Simulation time 13084507 ps
CPU time 0.58 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:01:47 PM PST 24
Peak memory 193328 kb
Host smart-b95c8e47-baa7-4c87-933a-98a897e45526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699125347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2699125347
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3881213945
Short name T519
Test name
Test status
Simulation time 1315872116 ps
CPU time 38.17 seconds
Started Jan 21 04:01:24 PM PST 24
Finished Jan 21 04:02:03 PM PST 24
Peak memory 207376 kb
Host smart-2ffc0e75-6712-452b-9e6e-bf015a1ab1f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881213945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3881213945
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1994458366
Short name T353
Test name
Test status
Simulation time 6398021341 ps
CPU time 50.7 seconds
Started Jan 21 05:13:53 PM PST 24
Finished Jan 21 05:15:38 PM PST 24
Peak memory 199168 kb
Host smart-8935a1a3-4d52-4538-b926-9f218e10b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994458366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1994458366
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2304136193
Short name T228
Test name
Test status
Simulation time 1110339906 ps
CPU time 30.18 seconds
Started Jan 21 06:18:20 PM PST 24
Finished Jan 21 06:18:57 PM PST 24
Peak memory 199028 kb
Host smart-d8c9ff60-ed29-405e-9cdc-1b8b6ad0f45a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304136193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2304136193
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.684898341
Short name T401
Test name
Test status
Simulation time 1779595660 ps
CPU time 82.2 seconds
Started Jan 21 04:01:28 PM PST 24
Finished Jan 21 04:02:53 PM PST 24
Peak memory 199080 kb
Host smart-9d640590-0fb5-41ff-8ff6-a0c693b3734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684898341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.684898341
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3540648259
Short name T590
Test name
Test status
Simulation time 16228069100 ps
CPU time 54.84 seconds
Started Jan 21 04:01:26 PM PST 24
Finished Jan 21 04:02:22 PM PST 24
Peak memory 199072 kb
Host smart-6fcb018a-eca1-40ed-b1df-9f11b1cb75f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540648259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3540648259
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1394586793
Short name T51
Test name
Test status
Simulation time 93180532 ps
CPU time 1.02 seconds
Started Jan 21 04:52:20 PM PST 24
Finished Jan 21 04:52:21 PM PST 24
Peak memory 217168 kb
Host smart-addcdb82-d599-4008-ad9f-3492d82897c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394586793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1394586793
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.542573832
Short name T617
Test name
Test status
Simulation time 326623383 ps
CPU time 2.15 seconds
Started Jan 21 04:24:50 PM PST 24
Finished Jan 21 04:24:53 PM PST 24
Peak memory 198872 kb
Host smart-a6c26eef-6cfb-4ed8-844d-e58f65c10c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542573832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.542573832
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4110102397
Short name T659
Test name
Test status
Simulation time 18402412670 ps
CPU time 958.62 seconds
Started Jan 21 05:35:41 PM PST 24
Finished Jan 21 05:51:48 PM PST 24
Peak memory 240180 kb
Host smart-b7662954-af8c-4de3-ad30-f0af466bf504
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110102397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4110102397
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2739070275
Short name T557
Test name
Test status
Simulation time 53517933462 ps
CPU time 1203.3 seconds
Started Jan 21 04:34:37 PM PST 24
Finished Jan 21 04:54:46 PM PST 24
Peak memory 256696 kb
Host smart-1de30101-eae9-4e20-acf5-58b2f72b7a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739070275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2739070275
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.984477206
Short name T591
Test name
Test status
Simulation time 598361618 ps
CPU time 1.24 seconds
Started Jan 21 04:54:34 PM PST 24
Finished Jan 21 04:54:36 PM PST 24
Peak memory 197420 kb
Host smart-67c067a2-cbb7-42b5-a18d-d37d46a2fba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984477206 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.984477206
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1394465695
Short name T755
Test name
Test status
Simulation time 17507826445 ps
CPU time 469.44 seconds
Started Jan 21 05:50:26 PM PST 24
Finished Jan 21 05:58:16 PM PST 24
Peak memory 199112 kb
Host smart-ee32d78b-edd6-48fd-83be-136c2de0e06e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394465695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.1394465695
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1206773569
Short name T422
Test name
Test status
Simulation time 78320251 ps
CPU time 3.76 seconds
Started Jan 21 04:01:34 PM PST 24
Finished Jan 21 04:01:46 PM PST 24
Peak memory 199036 kb
Host smart-e2e57167-af6e-4821-aba8-35d789da6f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206773569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1206773569
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1238277063
Short name T340
Test name
Test status
Simulation time 12737196 ps
CPU time 0.59 seconds
Started Jan 21 04:03:09 PM PST 24
Finished Jan 21 04:03:11 PM PST 24
Peak memory 193780 kb
Host smart-5ccad4a2-3a3f-43f2-a35b-20002ad473b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238277063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1238277063
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3478496552
Short name T438
Test name
Test status
Simulation time 845848427 ps
CPU time 12.81 seconds
Started Jan 21 04:37:33 PM PST 24
Finished Jan 21 04:37:46 PM PST 24
Peak memory 207296 kb
Host smart-2bddfdd5-29ab-486f-a321-830657e927df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478496552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3478496552
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.604737029
Short name T115
Test name
Test status
Simulation time 10987679105 ps
CPU time 42.41 seconds
Started Jan 21 04:02:51 PM PST 24
Finished Jan 21 04:03:35 PM PST 24
Peak memory 199128 kb
Host smart-6292d880-5c66-4e1b-bfd9-30290dfbfb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604737029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.604737029
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1095952690
Short name T626
Test name
Test status
Simulation time 1097346958 ps
CPU time 11.78 seconds
Started Jan 21 04:02:50 PM PST 24
Finished Jan 21 04:03:04 PM PST 24
Peak memory 199068 kb
Host smart-9f881579-4f20-413a-870b-7659c2bfcba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095952690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1095952690
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1886490387
Short name T711
Test name
Test status
Simulation time 969384032 ps
CPU time 8.95 seconds
Started Jan 21 04:02:51 PM PST 24
Finished Jan 21 04:03:02 PM PST 24
Peak memory 199000 kb
Host smart-d023c983-e809-4f5f-8ab9-9384092ad0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886490387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1886490387
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.317964774
Short name T348
Test name
Test status
Simulation time 20608214148 ps
CPU time 87.6 seconds
Started Jan 21 04:02:53 PM PST 24
Finished Jan 21 04:04:24 PM PST 24
Peak memory 199148 kb
Host smart-638b8afb-0115-4ab3-a12a-1b70bd46d0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317964774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.317964774
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3963995797
Short name T819
Test name
Test status
Simulation time 269030718 ps
CPU time 4.15 seconds
Started Jan 21 04:42:57 PM PST 24
Finished Jan 21 04:43:02 PM PST 24
Peak memory 198868 kb
Host smart-dbf339af-c979-465f-b2c3-d4cc2f74d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963995797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3963995797
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2801085472
Short name T122
Test name
Test status
Simulation time 337704044237 ps
CPU time 1856.13 seconds
Started Jan 21 04:03:08 PM PST 24
Finished Jan 21 04:34:07 PM PST 24
Peak memory 199128 kb
Host smart-c440d227-d7f0-46f9-a19a-7d129432ec86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801085472 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2801085472
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2622612920
Short name T770
Test name
Test status
Simulation time 52696799885 ps
CPU time 731.48 seconds
Started Jan 21 04:03:03 PM PST 24
Finished Jan 21 04:15:17 PM PST 24
Peak memory 238960 kb
Host smart-c60be0e6-91ba-492a-b4c9-4543921ea0ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622612920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.2622612920
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3630482747
Short name T622
Test name
Test status
Simulation time 92811160 ps
CPU time 1.09 seconds
Started Jan 21 04:03:02 PM PST 24
Finished Jan 21 04:03:05 PM PST 24
Peak memory 197228 kb
Host smart-18f3f8d6-f7bc-469a-9f94-85698c2a1bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630482747 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3630482747
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.952357759
Short name T342
Test name
Test status
Simulation time 28246458207 ps
CPU time 437.44 seconds
Started Jan 21 04:03:02 PM PST 24
Finished Jan 21 04:10:22 PM PST 24
Peak memory 199140 kb
Host smart-136bb658-7a83-4557-850a-565136b3146c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952357759 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_test_sha_vectors.952357759
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.985579701
Short name T698
Test name
Test status
Simulation time 3594475732 ps
CPU time 38.3 seconds
Started Jan 21 04:03:14 PM PST 24
Finished Jan 21 04:03:56 PM PST 24
Peak memory 199180 kb
Host smart-7011064e-d7e3-4a2b-9e56-386122bffe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985579701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.985579701
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3732832246
Short name T372
Test name
Test status
Simulation time 135630461506 ps
CPU time 1170.98 seconds
Started Jan 21 04:38:03 PM PST 24
Finished Jan 21 04:57:34 PM PST 24
Peak memory 229720 kb
Host smart-8f8dc65e-bac7-4ac7-83c6-8746ed0a87da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732832246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.3732832246
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2545144552
Short name T112
Test name
Test status
Simulation time 74538132707 ps
CPU time 299.99 seconds
Started Jan 21 04:08:34 PM PST 24
Finished Jan 21 04:13:35 PM PST 24
Peak memory 207592 kb
Host smart-ac495db9-6332-4b09-bcf6-ab37bfaceb95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545144552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.2545144552
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.1561928706
Short name T486
Test name
Test status
Simulation time 808801493245 ps
CPU time 1074.07 seconds
Started Jan 21 04:08:41 PM PST 24
Finished Jan 21 04:26:37 PM PST 24
Peak memory 213576 kb
Host smart-45921348-7f33-4b82-be52-0fdd3d52060f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561928706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.1561928706
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.310220122
Short name T594
Test name
Test status
Simulation time 404433775286 ps
CPU time 1988.55 seconds
Started Jan 21 04:08:39 PM PST 24
Finished Jan 21 04:41:49 PM PST 24
Peak memory 252540 kb
Host smart-54a7aec9-f733-4e3b-bf31-89a7a61f592e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310220122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.310220122
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2571714513
Short name T811
Test name
Test status
Simulation time 33779150593 ps
CPU time 544.22 seconds
Started Jan 21 04:08:40 PM PST 24
Finished Jan 21 04:17:45 PM PST 24
Peak memory 215688 kb
Host smart-4d7b49bd-238b-4e27-b484-b825b8b79c1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571714513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.2571714513
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3704659424
Short name T639
Test name
Test status
Simulation time 89423039156 ps
CPU time 1386.11 seconds
Started Jan 21 04:08:41 PM PST 24
Finished Jan 21 04:31:49 PM PST 24
Peak memory 248456 kb
Host smart-5330afc6-9f05-4b46-b583-07f3ad817023
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704659424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3704659424
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.474145680
Short name T798
Test name
Test status
Simulation time 69500653302 ps
CPU time 1502.82 seconds
Started Jan 21 04:08:39 PM PST 24
Finished Jan 21 04:33:44 PM PST 24
Peak memory 248160 kb
Host smart-14f7d236-7867-45b3-80e7-67f486838d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474145680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.474145680
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.1927276991
Short name T310
Test name
Test status
Simulation time 238408224260 ps
CPU time 3470.05 seconds
Started Jan 21 04:08:44 PM PST 24
Finished Jan 21 05:06:35 PM PST 24
Peak memory 232104 kb
Host smart-5ee5d813-ba7a-41b6-90f3-a3505d0ec762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927276991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.1927276991
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1275146997
Short name T773
Test name
Test status
Simulation time 15580132 ps
CPU time 0.55 seconds
Started Jan 21 04:03:08 PM PST 24
Finished Jan 21 04:03:10 PM PST 24
Peak memory 193500 kb
Host smart-1c4aef20-81b8-42b3-a8eb-ae5c0dd733aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275146997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1275146997
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2791585433
Short name T282
Test name
Test status
Simulation time 1425262470 ps
CPU time 51.21 seconds
Started Jan 21 04:03:15 PM PST 24
Finished Jan 21 04:04:09 PM PST 24
Peak memory 223256 kb
Host smart-b5f88f36-6b5d-4bcf-89a8-b0ef21e3ee4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791585433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2791585433
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4064610360
Short name T380
Test name
Test status
Simulation time 6593922418 ps
CPU time 66.04 seconds
Started Jan 21 04:03:03 PM PST 24
Finished Jan 21 04:04:11 PM PST 24
Peak memory 199112 kb
Host smart-79507dff-aa94-45bd-8e81-053a0adf8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064610360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4064610360
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4293570331
Short name T246
Test name
Test status
Simulation time 7034231620 ps
CPU time 92.13 seconds
Started Jan 21 04:03:14 PM PST 24
Finished Jan 21 04:04:50 PM PST 24
Peak memory 199176 kb
Host smart-35fb1145-2fae-4b47-a7e1-0d12c3748152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293570331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4293570331
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2047645606
Short name T776
Test name
Test status
Simulation time 146762149725 ps
CPU time 114.38 seconds
Started Jan 21 04:03:04 PM PST 24
Finished Jan 21 04:05:00 PM PST 24
Peak memory 199144 kb
Host smart-af247462-9fd7-438b-b12a-e688594e948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047645606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2047645606
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.520549619
Short name T292
Test name
Test status
Simulation time 550489071 ps
CPU time 8.61 seconds
Started Jan 21 04:57:01 PM PST 24
Finished Jan 21 04:57:10 PM PST 24
Peak memory 198948 kb
Host smart-4db79d86-6026-4a83-864b-b674f5b88ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520549619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.520549619
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1313577392
Short name T547
Test name
Test status
Simulation time 126438834 ps
CPU time 1.05 seconds
Started Jan 21 04:03:06 PM PST 24
Finished Jan 21 04:03:08 PM PST 24
Peak memory 197548 kb
Host smart-f3a848cc-bf8d-4220-b34a-070e956cb77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313577392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1313577392
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3988318417
Short name T483
Test name
Test status
Simulation time 341895360097 ps
CPU time 1670.94 seconds
Started Jan 21 05:38:49 PM PST 24
Finished Jan 21 06:06:48 PM PST 24
Peak memory 235980 kb
Host smart-d70d77ca-dcfa-46e1-b345-862c214fb8d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988318417 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3988318417
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.3024249421
Short name T757
Test name
Test status
Simulation time 520599463037 ps
CPU time 2229.35 seconds
Started Jan 21 05:20:17 PM PST 24
Finished Jan 21 05:57:29 PM PST 24
Peak memory 257712 kb
Host smart-e9026887-1be6-4e95-8754-620daf94bc21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024249421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.3024249421
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2343007359
Short name T201
Test name
Test status
Simulation time 73882148 ps
CPU time 1.15 seconds
Started Jan 21 04:03:08 PM PST 24
Finished Jan 21 04:03:11 PM PST 24
Peak memory 197224 kb
Host smart-abf72f03-c5d1-4d13-8410-f05e7946ebb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343007359 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2343007359
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2468314068
Short name T410
Test name
Test status
Simulation time 51252809474 ps
CPU time 398.21 seconds
Started Jan 21 04:03:28 PM PST 24
Finished Jan 21 04:10:08 PM PST 24
Peak memory 199132 kb
Host smart-3b31b86f-fcfd-4281-84f0-1afa13a05078
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468314068 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2468314068
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2750226041
Short name T202
Test name
Test status
Simulation time 2009917652 ps
CPU time 16.89 seconds
Started Jan 21 04:03:06 PM PST 24
Finished Jan 21 04:03:24 PM PST 24
Peak memory 199076 kb
Host smart-f368ed80-eec8-4394-a443-995a8a0a67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750226041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2750226041
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.822517485
Short name T767
Test name
Test status
Simulation time 26270319674 ps
CPU time 413.09 seconds
Started Jan 21 04:09:01 PM PST 24
Finished Jan 21 04:15:55 PM PST 24
Peak memory 213704 kb
Host smart-3e5682d2-8d08-47ac-a152-26cf216cba49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822517485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.822517485
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.1510762837
Short name T425
Test name
Test status
Simulation time 61191381187 ps
CPU time 2719.89 seconds
Started Jan 21 04:08:54 PM PST 24
Finished Jan 21 04:54:15 PM PST 24
Peak memory 248044 kb
Host smart-227fbff0-fed7-460b-84fc-7376f1d250af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510762837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.1510762837
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1031776273
Short name T289
Test name
Test status
Simulation time 62445811114 ps
CPU time 2961.04 seconds
Started Jan 21 04:08:54 PM PST 24
Finished Jan 21 04:58:16 PM PST 24
Peak memory 256672 kb
Host smart-3315c92a-6172-4b21-b7a6-de2d633b09b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031776273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1031776273
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.256395234
Short name T119
Test name
Test status
Simulation time 164767984148 ps
CPU time 2313.63 seconds
Started Jan 21 04:08:55 PM PST 24
Finished Jan 21 04:47:30 PM PST 24
Peak memory 224088 kb
Host smart-bf0ad3be-5d64-4ded-8ebe-9abd109c9f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256395234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.256395234
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.4281383691
Short name T765
Test name
Test status
Simulation time 76746618001 ps
CPU time 3680.64 seconds
Started Jan 21 04:08:53 PM PST 24
Finished Jan 21 05:10:15 PM PST 24
Peak memory 255712 kb
Host smart-ca70dbc4-5624-4bf6-879c-0a855bcf6d37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4281383691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.4281383691
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.3482268618
Short name T748
Test name
Test status
Simulation time 64486595354 ps
CPU time 1070.07 seconds
Started Jan 21 04:08:55 PM PST 24
Finished Jan 21 04:26:46 PM PST 24
Peak memory 232352 kb
Host smart-af828efc-388f-4061-a1bb-731ff9427f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482268618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.3482268618
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.3668251218
Short name T130
Test name
Test status
Simulation time 709230442475 ps
CPU time 1750.63 seconds
Started Jan 21 04:08:58 PM PST 24
Finished Jan 21 04:38:10 PM PST 24
Peak memory 246024 kb
Host smart-de5ff873-197b-49e1-8e94-2b68f0d2edbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668251218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.3668251218
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.3473772161
Short name T114
Test name
Test status
Simulation time 51119315158 ps
CPU time 370.85 seconds
Started Jan 21 04:08:59 PM PST 24
Finished Jan 21 04:15:11 PM PST 24
Peak memory 216008 kb
Host smart-6911a05a-2fe1-43db-a5ae-bc31ab56bfdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473772161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.3473772161
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2781862373
Short name T525
Test name
Test status
Simulation time 17590523 ps
CPU time 0.58 seconds
Started Jan 21 04:03:13 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 193344 kb
Host smart-896e4887-1c3d-4747-ae2d-50aa1b177936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781862373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2781862373
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.994129005
Short name T269
Test name
Test status
Simulation time 2170885228 ps
CPU time 34.07 seconds
Started Jan 21 04:03:08 PM PST 24
Finished Jan 21 04:03:44 PM PST 24
Peak memory 214940 kb
Host smart-4458dafe-eccb-4db8-8293-40a6f6caa442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994129005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.994129005
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2839139476
Short name T266
Test name
Test status
Simulation time 66791493 ps
CPU time 1.75 seconds
Started Jan 21 04:19:47 PM PST 24
Finished Jan 21 04:20:02 PM PST 24
Peak memory 198048 kb
Host smart-3387da87-181a-4192-b710-c156542cf528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839139476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2839139476
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2324662622
Short name T193
Test name
Test status
Simulation time 1175905456 ps
CPU time 61.93 seconds
Started Jan 21 04:03:26 PM PST 24
Finished Jan 21 04:04:30 PM PST 24
Peak memory 199124 kb
Host smart-de7d2944-fdd6-4b09-bb81-49df1c8a2471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324662622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2324662622
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2715717126
Short name T693
Test name
Test status
Simulation time 9641420029 ps
CPU time 167.38 seconds
Started Jan 21 04:22:36 PM PST 24
Finished Jan 21 04:25:32 PM PST 24
Peak memory 199192 kb
Host smart-833826cc-b57e-4639-b2d6-5e70e8e227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715717126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2715717126
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4005268602
Short name T535
Test name
Test status
Simulation time 20096400515 ps
CPU time 64.15 seconds
Started Jan 21 04:03:09 PM PST 24
Finished Jan 21 04:04:15 PM PST 24
Peak memory 199380 kb
Host smart-c52d1268-09d2-4caa-983a-3fbd7e57474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005268602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4005268602
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2656476384
Short name T312
Test name
Test status
Simulation time 1189147283 ps
CPU time 2.24 seconds
Started Jan 21 04:03:09 PM PST 24
Finished Jan 21 04:03:13 PM PST 24
Peak memory 199076 kb
Host smart-65c3a737-e99f-41c4-bfaf-957c59bdf30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656476384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2656476384
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1459989980
Short name T258
Test name
Test status
Simulation time 100167441323 ps
CPU time 1762.82 seconds
Started Jan 21 04:03:12 PM PST 24
Finished Jan 21 04:32:38 PM PST 24
Peak memory 229840 kb
Host smart-15e0cd2c-9c0c-47b9-8914-60960a789c59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459989980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1459989980
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.3782291140
Short name T586
Test name
Test status
Simulation time 119573479168 ps
CPU time 1484.15 seconds
Started Jan 21 04:03:37 PM PST 24
Finished Jan 21 04:28:24 PM PST 24
Peak memory 255668 kb
Host smart-0a49a90f-a4a7-42aa-8f26-97be9071c5b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782291140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.3782291140
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2155272337
Short name T670
Test name
Test status
Simulation time 27768820 ps
CPU time 0.88 seconds
Started Jan 21 04:03:14 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 196188 kb
Host smart-fb533f08-f6d8-40ba-9ce4-9580c4fd291f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155272337 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2155272337
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1392010420
Short name T11
Test name
Test status
Simulation time 7921428085 ps
CPU time 382.89 seconds
Started Jan 21 04:03:14 PM PST 24
Finished Jan 21 04:09:40 PM PST 24
Peak memory 199100 kb
Host smart-892f1b12-3495-458d-ac5f-8b92cd30b24e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392010420 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.1392010420
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2785663430
Short name T341
Test name
Test status
Simulation time 1382112505 ps
CPU time 8.95 seconds
Started Jan 21 04:03:06 PM PST 24
Finished Jan 21 04:03:16 PM PST 24
Peak memory 199112 kb
Host smart-687b740d-8050-4676-9887-8310aaa2d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785663430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2785663430
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.1777823398
Short name T559
Test name
Test status
Simulation time 60094845854 ps
CPU time 946.98 seconds
Started Jan 21 04:08:59 PM PST 24
Finished Jan 21 04:24:48 PM PST 24
Peak memory 230688 kb
Host smart-8eecd33d-140e-4003-961a-195cba966efe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777823398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.1777823398
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.4274090424
Short name T661
Test name
Test status
Simulation time 71668757317 ps
CPU time 3640.26 seconds
Started Jan 21 04:09:02 PM PST 24
Finished Jan 21 05:09:45 PM PST 24
Peak memory 256688 kb
Host smart-681d0e71-a771-4597-b49f-05f7554551af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274090424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.4274090424
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.3866522500
Short name T337
Test name
Test status
Simulation time 31886645197 ps
CPU time 811.57 seconds
Started Jan 21 04:09:03 PM PST 24
Finished Jan 21 04:22:36 PM PST 24
Peak memory 246444 kb
Host smart-dd71831b-358f-46f0-a159-56d1a57e5b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866522500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.3866522500
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.1687351352
Short name T377
Test name
Test status
Simulation time 70389427628 ps
CPU time 1048.28 seconds
Started Jan 21 04:09:04 PM PST 24
Finished Jan 21 04:26:34 PM PST 24
Peak memory 223976 kb
Host smart-afc2274f-2998-4f53-8b83-79d93ff87c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687351352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.1687351352
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.2749479567
Short name T679
Test name
Test status
Simulation time 66873669274 ps
CPU time 3115.76 seconds
Started Jan 21 04:09:04 PM PST 24
Finished Jan 21 05:01:02 PM PST 24
Peak memory 243368 kb
Host smart-5582b33a-e94d-4ac2-8127-15bc480be5ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749479567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.2749479567
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.111474074
Short name T273
Test name
Test status
Simulation time 309134589897 ps
CPU time 1248.11 seconds
Started Jan 21 04:09:02 PM PST 24
Finished Jan 21 04:29:53 PM PST 24
Peak memory 229380 kb
Host smart-f7c54a64-276e-4f9e-a1b2-26e8467482ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111474074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.111474074
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.1761910717
Short name T123
Test name
Test status
Simulation time 75321019330 ps
CPU time 1640.27 seconds
Started Jan 21 04:09:02 PM PST 24
Finished Jan 21 04:36:25 PM PST 24
Peak memory 229344 kb
Host smart-d741621a-d61d-4ebd-a654-1d2c40711054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761910717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.1761910717
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.1607085975
Short name T357
Test name
Test status
Simulation time 166558999174 ps
CPU time 717.66 seconds
Started Jan 21 04:09:01 PM PST 24
Finished Jan 21 04:21:00 PM PST 24
Peak memory 248212 kb
Host smart-925d8595-6fea-46c7-b52b-d48b5714f25c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607085975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.1607085975
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.4174738872
Short name T423
Test name
Test status
Simulation time 427222646274 ps
CPU time 1621.68 seconds
Started Jan 21 04:54:56 PM PST 24
Finished Jan 21 05:21:59 PM PST 24
Peak memory 232144 kb
Host smart-f3542148-b7e6-4a7b-8e48-4d9cbfd7c391
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174738872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.4174738872
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2156875901
Short name T579
Test name
Test status
Simulation time 41948850 ps
CPU time 0.57 seconds
Started Jan 21 04:03:21 PM PST 24
Finished Jan 21 04:03:22 PM PST 24
Peak memory 192552 kb
Host smart-4eb41ff6-e67b-49e3-a2b8-cbe1fe7e3838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156875901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2156875901
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3541286141
Short name T702
Test name
Test status
Simulation time 3185566546 ps
CPU time 24.97 seconds
Started Jan 21 04:03:18 PM PST 24
Finished Jan 21 04:03:46 PM PST 24
Peak memory 207264 kb
Host smart-4cf5458c-34f9-4c69-bcb4-6462431a8a8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541286141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3541286141
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4274644967
Short name T802
Test name
Test status
Simulation time 900650412 ps
CPU time 41.07 seconds
Started Jan 21 04:03:14 PM PST 24
Finished Jan 21 04:03:59 PM PST 24
Peak memory 199108 kb
Host smart-d593fe09-7adb-4969-b575-3d57053a72a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274644967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4274644967
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3128761158
Short name T211
Test name
Test status
Simulation time 2243796929 ps
CPU time 115.77 seconds
Started Jan 21 04:03:13 PM PST 24
Finished Jan 21 04:05:13 PM PST 24
Peak memory 199180 kb
Host smart-65b8fd35-434e-4ed0-91f2-aa86dd482f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128761158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3128761158
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3733904380
Short name T713
Test name
Test status
Simulation time 26791981084 ps
CPU time 24.12 seconds
Started Jan 21 04:03:23 PM PST 24
Finished Jan 21 04:03:50 PM PST 24
Peak memory 199188 kb
Host smart-4098a8a9-c21e-4440-b975-e8a4fd53468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733904380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3733904380
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1599808078
Short name T504
Test name
Test status
Simulation time 1388770495 ps
CPU time 13.77 seconds
Started Jan 21 04:15:20 PM PST 24
Finished Jan 21 04:15:36 PM PST 24
Peak memory 199048 kb
Host smart-5c6bc2d6-5bae-4487-a180-47cfee5a26f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599808078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1599808078
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2192190587
Short name T288
Test name
Test status
Simulation time 288314049 ps
CPU time 3.69 seconds
Started Jan 21 06:25:14 PM PST 24
Finished Jan 21 06:25:19 PM PST 24
Peak memory 198820 kb
Host smart-c10a85e6-d834-4482-baa2-fe816de8f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192190587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2192190587
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3017884301
Short name T690
Test name
Test status
Simulation time 30734916407 ps
CPU time 1176.49 seconds
Started Jan 21 04:03:25 PM PST 24
Finished Jan 21 04:23:04 PM PST 24
Peak memory 240200 kb
Host smart-7678c505-2cc2-46c4-a509-a31568c7c039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017884301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3017884301
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2773824420
Short name T100
Test name
Test status
Simulation time 49258763005 ps
CPU time 663.97 seconds
Started Jan 21 04:03:27 PM PST 24
Finished Jan 21 04:14:33 PM PST 24
Peak memory 247808 kb
Host smart-cf7e4513-e153-4027-8efc-22af757dad09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773824420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2773824420
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.252955821
Short name T471
Test name
Test status
Simulation time 379454364 ps
CPU time 0.87 seconds
Started Jan 21 04:03:23 PM PST 24
Finished Jan 21 04:03:26 PM PST 24
Peak memory 196696 kb
Host smart-62752d2f-9da1-4c3f-88b9-9854bff78c80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252955821 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.252955821
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.533985034
Short name T629
Test name
Test status
Simulation time 82715135130 ps
CPU time 475.24 seconds
Started Jan 21 04:03:23 PM PST 24
Finished Jan 21 04:11:21 PM PST 24
Peak memory 199036 kb
Host smart-90111171-9e9e-4329-8af6-c92541504a0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533985034 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_test_sha_vectors.533985034
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3034970174
Short name T235
Test name
Test status
Simulation time 11000337665 ps
CPU time 67.71 seconds
Started Jan 21 04:03:24 PM PST 24
Finished Jan 21 04:04:34 PM PST 24
Peak memory 199088 kb
Host smart-016d5ccf-32ad-42c8-bf66-9db0401b3ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034970174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3034970174
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1207728421
Short name T300
Test name
Test status
Simulation time 140987523644 ps
CPU time 4267.06 seconds
Started Jan 21 04:09:08 PM PST 24
Finished Jan 21 05:20:18 PM PST 24
Peak memory 273100 kb
Host smart-a2ece7b5-ee5d-476a-be8f-367db59410d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207728421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1207728421
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.2781633277
Short name T314
Test name
Test status
Simulation time 228034190780 ps
CPU time 2919.45 seconds
Started Jan 21 04:34:37 PM PST 24
Finished Jan 21 05:23:22 PM PST 24
Peak memory 248292 kb
Host smart-fcbbef55-1004-4657-b78c-357ef37fbda0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781633277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.2781633277
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.663139171
Short name T283
Test name
Test status
Simulation time 7403591877 ps
CPU time 387.24 seconds
Started Jan 21 04:09:04 PM PST 24
Finished Jan 21 04:15:33 PM PST 24
Peak memory 245392 kb
Host smart-3eb4d321-4ffb-4833-aa1f-5a4e66743a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663139171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.663139171
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.4074163440
Short name T406
Test name
Test status
Simulation time 36375714613 ps
CPU time 1849.36 seconds
Started Jan 21 04:09:08 PM PST 24
Finished Jan 21 04:40:00 PM PST 24
Peak memory 244640 kb
Host smart-8ec08790-6d43-4b83-bf0d-892f2dba0fc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074163440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.4074163440
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1967727287
Short name T364
Test name
Test status
Simulation time 41587782869 ps
CPU time 700.46 seconds
Started Jan 21 04:09:17 PM PST 24
Finished Jan 21 04:21:02 PM PST 24
Peak memory 256612 kb
Host smart-7861f23a-45ab-4947-a656-f86471898968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967727287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.1967727287
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1265468694
Short name T222
Test name
Test status
Simulation time 41875304880 ps
CPU time 333.83 seconds
Started Jan 21 04:09:09 PM PST 24
Finished Jan 21 04:14:45 PM PST 24
Peak memory 215732 kb
Host smart-d7a410ff-5509-4e6f-a740-5c44d84c704c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265468694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1265468694
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.3133715293
Short name T515
Test name
Test status
Simulation time 235861891746 ps
CPU time 2327.95 seconds
Started Jan 21 04:09:17 PM PST 24
Finished Jan 21 04:48:10 PM PST 24
Peak memory 256728 kb
Host smart-a48818a8-ed87-4c3f-a9c4-349629b206fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133715293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.3133715293
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3262536936
Short name T668
Test name
Test status
Simulation time 14168930758 ps
CPU time 223 seconds
Started Jan 21 04:09:15 PM PST 24
Finished Jan 21 04:13:05 PM PST 24
Peak memory 222648 kb
Host smart-c0b1c35b-d693-4ea7-a785-204d7fb64838
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262536936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3262536936
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.246470529
Short name T512
Test name
Test status
Simulation time 172598743223 ps
CPU time 1302.06 seconds
Started Jan 21 04:09:16 PM PST 24
Finished Jan 21 04:31:04 PM PST 24
Peak memory 264448 kb
Host smart-89af780d-c3b0-4b0d-ae79-b567b8b643a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246470529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.246470529
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.3476183740
Short name T744
Test name
Test status
Simulation time 31879613813 ps
CPU time 115.8 seconds
Started Jan 21 04:09:16 PM PST 24
Finished Jan 21 04:11:17 PM PST 24
Peak memory 215128 kb
Host smart-50f1d931-d714-4b62-a1be-da9af8ac8084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476183740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.3476183740
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4071588593
Short name T792
Test name
Test status
Simulation time 8188505880 ps
CPU time 48.01 seconds
Started Jan 21 04:03:31 PM PST 24
Finished Jan 21 04:04:20 PM PST 24
Peak memory 215572 kb
Host smart-92601b1a-2b91-44fa-856b-5ef0cb63a02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071588593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4071588593
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2343936299
Short name T7
Test name
Test status
Simulation time 177302765 ps
CPU time 3 seconds
Started Jan 21 04:03:32 PM PST 24
Finished Jan 21 04:03:37 PM PST 24
Peak memory 199324 kb
Host smart-1df16e4d-784e-401e-a5fb-fff7043f7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343936299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2343936299
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3298445294
Short name T237
Test name
Test status
Simulation time 1862305723 ps
CPU time 24.95 seconds
Started Jan 21 04:17:23 PM PST 24
Finished Jan 21 04:17:49 PM PST 24
Peak memory 199144 kb
Host smart-c1ab1b5a-5a48-473f-962c-c591a726d88c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298445294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3298445294
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1273806079
Short name T564
Test name
Test status
Simulation time 15210524129 ps
CPU time 158.44 seconds
Started Jan 21 04:03:33 PM PST 24
Finished Jan 21 04:06:13 PM PST 24
Peak memory 199196 kb
Host smart-e25fd1cf-d1ad-456f-a7b0-424928f9df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273806079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1273806079
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3606562436
Short name T508
Test name
Test status
Simulation time 1120546740 ps
CPU time 53.18 seconds
Started Jan 21 04:03:22 PM PST 24
Finished Jan 21 04:04:17 PM PST 24
Peak memory 199184 kb
Host smart-ae88698c-cdaa-423a-971d-3c4a2008ff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606562436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3606562436
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.626718374
Short name T561
Test name
Test status
Simulation time 351408213 ps
CPU time 4.07 seconds
Started Jan 21 04:03:23 PM PST 24
Finished Jan 21 04:03:30 PM PST 24
Peak memory 198412 kb
Host smart-972db48c-8dfe-4f2b-982c-513df3af70f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626718374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.626718374
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2157265652
Short name T127
Test name
Test status
Simulation time 85197017253 ps
CPU time 1070.27 seconds
Started Jan 21 04:03:31 PM PST 24
Finished Jan 21 04:21:23 PM PST 24
Peak memory 235944 kb
Host smart-5a0d40c1-7f20-405c-965b-0140acaeefe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157265652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2157265652
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2150609075
Short name T634
Test name
Test status
Simulation time 15981606283 ps
CPU time 113.78 seconds
Started Jan 21 04:03:31 PM PST 24
Finished Jan 21 04:05:26 PM PST 24
Peak memory 199520 kb
Host smart-9a923576-a07a-409e-ba00-dc5ae38b479d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150609075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2150609075
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.869374137
Short name T233
Test name
Test status
Simulation time 53403488 ps
CPU time 1.1 seconds
Started Jan 21 04:03:32 PM PST 24
Finished Jan 21 04:03:35 PM PST 24
Peak memory 197820 kb
Host smart-c97179a0-363f-48da-a354-3573c09d95ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869374137 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.869374137
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3283386175
Short name T614
Test name
Test status
Simulation time 42821845793 ps
CPU time 468.84 seconds
Started Jan 21 04:03:32 PM PST 24
Finished Jan 21 04:11:23 PM PST 24
Peak memory 199036 kb
Host smart-65c340a5-2689-4078-96ca-98d8b2cf195b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283386175 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.3283386175
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2354880687
Short name T446
Test name
Test status
Simulation time 1657119816 ps
CPU time 18.54 seconds
Started Jan 21 04:03:31 PM PST 24
Finished Jan 21 04:03:51 PM PST 24
Peak memory 199076 kb
Host smart-d0e75024-18fa-4273-b704-d32fbbcd6b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354880687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2354880687
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.463318148
Short name T640
Test name
Test status
Simulation time 58984192543 ps
CPU time 1121.12 seconds
Started Jan 21 04:09:16 PM PST 24
Finished Jan 21 04:28:03 PM PST 24
Peak memory 259756 kb
Host smart-2c33c470-728b-41f2-b6ce-e56d9df20a84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463318148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.463318148
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.2917998771
Short name T778
Test name
Test status
Simulation time 80576352468 ps
CPU time 3759.5 seconds
Started Jan 21 04:09:15 PM PST 24
Finished Jan 21 05:12:02 PM PST 24
Peak memory 258928 kb
Host smart-2f810cb9-2823-480b-8861-c70b4240d9a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917998771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.2917998771
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.998949207
Short name T643
Test name
Test status
Simulation time 221465384289 ps
CPU time 1680.02 seconds
Started Jan 21 04:09:15 PM PST 24
Finished Jan 21 04:37:22 PM PST 24
Peak memory 215656 kb
Host smart-334d76e4-7aef-43f0-a1f6-6c7588656f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998949207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.998949207
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.4105902453
Short name T832
Test name
Test status
Simulation time 63395152250 ps
CPU time 1607.13 seconds
Started Jan 21 04:09:21 PM PST 24
Finished Jan 21 04:36:13 PM PST 24
Peak memory 210280 kb
Host smart-d6644a69-6d96-4d89-91ce-06b53d313293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105902453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.4105902453
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.927407578
Short name T462
Test name
Test status
Simulation time 137941191228 ps
CPU time 1326.8 seconds
Started Jan 21 04:09:22 PM PST 24
Finished Jan 21 04:31:33 PM PST 24
Peak memory 223844 kb
Host smart-81e8e2dc-0ac7-4abc-9be6-bf077e5e3e87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927407578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.927407578
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.3080345274
Short name T735
Test name
Test status
Simulation time 242892824717 ps
CPU time 1055.11 seconds
Started Jan 21 04:09:23 PM PST 24
Finished Jan 21 04:27:02 PM PST 24
Peak memory 256624 kb
Host smart-7e2d29a9-3efc-45d2-b80f-675116b33c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080345274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.3080345274
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.447705670
Short name T567
Test name
Test status
Simulation time 124626482209 ps
CPU time 1523.82 seconds
Started Jan 21 04:33:16 PM PST 24
Finished Jan 21 04:58:42 PM PST 24
Peak memory 232084 kb
Host smart-c7498d4a-8006-4089-8677-480765976f16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447705670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.447705670
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.1189815956
Short name T456
Test name
Test status
Simulation time 251363234505 ps
CPU time 2988.66 seconds
Started Jan 21 04:09:24 PM PST 24
Finished Jan 21 04:59:15 PM PST 24
Peak memory 244164 kb
Host smart-4a5442ca-5d24-4458-a99a-ec6be101dc91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189815956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.1189815956
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1089456950
Short name T226
Test name
Test status
Simulation time 75896228643 ps
CPU time 850.33 seconds
Started Jan 21 04:09:30 PM PST 24
Finished Jan 21 04:23:42 PM PST 24
Peak memory 227488 kb
Host smart-af049d02-ed33-45ae-8fff-bae28bec7909
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089456950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1089456950
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3880190014
Short name T299
Test name
Test status
Simulation time 14462472 ps
CPU time 0.57 seconds
Started Jan 21 04:03:35 PM PST 24
Finished Jan 21 04:03:37 PM PST 24
Peak memory 193472 kb
Host smart-2c69d3b2-baac-4e85-8c11-c41e15a00a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880190014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3880190014
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3576863440
Short name T529
Test name
Test status
Simulation time 501515936 ps
CPU time 2.78 seconds
Started Jan 21 04:03:29 PM PST 24
Finished Jan 21 04:03:32 PM PST 24
Peak memory 207296 kb
Host smart-b411c032-f46b-4101-9bd6-a72fd049273c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576863440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3576863440
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3663502165
Short name T490
Test name
Test status
Simulation time 1831560041 ps
CPU time 19.29 seconds
Started Jan 21 04:03:44 PM PST 24
Finished Jan 21 04:04:07 PM PST 24
Peak memory 199144 kb
Host smart-7621ee4f-f908-498a-99d3-da505cb46c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663502165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3663502165
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3402486442
Short name T599
Test name
Test status
Simulation time 1754182185 ps
CPU time 58.96 seconds
Started Jan 21 04:03:29 PM PST 24
Finished Jan 21 04:04:29 PM PST 24
Peak memory 199052 kb
Host smart-2da0228d-dc63-4552-ab57-98441a457ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402486442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3402486442
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.660827383
Short name T589
Test name
Test status
Simulation time 135260259 ps
CPU time 6.28 seconds
Started Jan 21 04:03:40 PM PST 24
Finished Jan 21 04:03:47 PM PST 24
Peak memory 198972 kb
Host smart-5cf3c84f-cf8a-4ef1-a18e-a7a7c75acd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660827383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.660827383
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2390532703
Short name T358
Test name
Test status
Simulation time 5712962238 ps
CPU time 70.53 seconds
Started Jan 21 04:03:30 PM PST 24
Finished Jan 21 04:04:41 PM PST 24
Peak memory 199176 kb
Host smart-d1610ce3-5cbe-4163-8fdb-6a342b54a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390532703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2390532703
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1642879006
Short name T373
Test name
Test status
Simulation time 163120596 ps
CPU time 3.88 seconds
Started Jan 21 04:03:29 PM PST 24
Finished Jan 21 04:03:34 PM PST 24
Peak memory 199032 kb
Host smart-fdde00b4-d6af-4489-a24b-db58cf0daeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642879006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1642879006
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1816358314
Short name T409
Test name
Test status
Simulation time 26008029969 ps
CPU time 1254.5 seconds
Started Jan 21 04:03:45 PM PST 24
Finished Jan 21 04:24:42 PM PST 24
Peak memory 240140 kb
Host smart-cb36cf27-1da6-4243-9552-8e281db9b3e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816358314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1816358314
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2721656074
Short name T635
Test name
Test status
Simulation time 192473497 ps
CPU time 0.91 seconds
Started Jan 21 04:03:45 PM PST 24
Finished Jan 21 04:03:49 PM PST 24
Peak memory 196684 kb
Host smart-2df91a2d-8ad0-40bc-9dbc-6fe26a0fe516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721656074 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2721656074
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2726600287
Short name T494
Test name
Test status
Simulation time 46669072980 ps
CPU time 328.79 seconds
Started Jan 21 04:03:37 PM PST 24
Finished Jan 21 04:09:08 PM PST 24
Peak memory 199052 kb
Host smart-69974165-f710-4d02-8f8b-4b420f40b500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726600287 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.2726600287
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3032369148
Short name T274
Test name
Test status
Simulation time 9739220524 ps
CPU time 76.59 seconds
Started Jan 21 04:03:45 PM PST 24
Finished Jan 21 04:05:05 PM PST 24
Peak memory 199196 kb
Host smart-b036e6e0-4777-4799-96c1-db7f88b56af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032369148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3032369148
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.508544118
Short name T678
Test name
Test status
Simulation time 60275527746 ps
CPU time 603.89 seconds
Started Jan 21 04:09:26 PM PST 24
Finished Jan 21 04:19:31 PM PST 24
Peak memory 214976 kb
Host smart-59751b49-7a2e-4f8b-8cae-b35ee3b1e687
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508544118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.508544118
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.3845908444
Short name T775
Test name
Test status
Simulation time 29125122679 ps
CPU time 365.25 seconds
Started Jan 21 04:09:25 PM PST 24
Finished Jan 21 04:15:32 PM PST 24
Peak memory 233096 kb
Host smart-23e54234-6425-45a7-a52c-df9cda4ff624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845908444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.3845908444
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.1384135540
Short name T625
Test name
Test status
Simulation time 10271602144 ps
CPU time 502.67 seconds
Started Jan 21 04:09:26 PM PST 24
Finished Jan 21 04:17:50 PM PST 24
Peak memory 227960 kb
Host smart-46979b42-39f5-4624-b598-2bde61a9fe84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384135540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.1384135540
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.3446135817
Short name T660
Test name
Test status
Simulation time 313094218730 ps
CPU time 4099.3 seconds
Started Jan 21 04:09:29 PM PST 24
Finished Jan 21 05:17:50 PM PST 24
Peak memory 223876 kb
Host smart-e775acab-382b-49d0-b669-67a0c0a9f822
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446135817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.3446135817
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2630931300
Short name T460
Test name
Test status
Simulation time 392600554037 ps
CPU time 1017.68 seconds
Started Jan 21 04:09:29 PM PST 24
Finished Jan 21 04:26:28 PM PST 24
Peak memory 213996 kb
Host smart-cb022d17-0698-4871-9026-5369e2c2ce4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630931300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.2630931300
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.2339604676
Short name T449
Test name
Test status
Simulation time 60809984065 ps
CPU time 3070.6 seconds
Started Jan 21 04:09:30 PM PST 24
Finished Jan 21 05:00:43 PM PST 24
Peak memory 249520 kb
Host smart-09a08827-bc0b-46f9-b52f-0a951e2473e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339604676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.2339604676
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.1957062373
Short name T503
Test name
Test status
Simulation time 109957119059 ps
CPU time 261.94 seconds
Started Jan 21 04:09:31 PM PST 24
Finished Jan 21 04:13:54 PM PST 24
Peak memory 215748 kb
Host smart-db77dbfd-f218-43bb-b8fc-06ea49c9b076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957062373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.1957062373
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1932873941
Short name T209
Test name
Test status
Simulation time 54799910126 ps
CPU time 420.36 seconds
Started Jan 21 04:09:27 PM PST 24
Finished Jan 21 04:16:29 PM PST 24
Peak memory 235892 kb
Host smart-4b1f19d8-9b02-4643-b847-24dcac997207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932873941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1932873941
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.2742025901
Short name T387
Test name
Test status
Simulation time 36041741973 ps
CPU time 527.56 seconds
Started Jan 21 04:29:44 PM PST 24
Finished Jan 21 04:38:33 PM PST 24
Peak memory 215700 kb
Host smart-3d34a103-35c2-4555-b4fe-2c1ba92d6d37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742025901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.2742025901
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3800541209
Short name T657
Test name
Test status
Simulation time 15423178 ps
CPU time 0.55 seconds
Started Jan 21 04:03:46 PM PST 24
Finished Jan 21 04:03:49 PM PST 24
Peak memory 192484 kb
Host smart-436434b7-c45a-4f85-84a6-39b7216db8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800541209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3800541209
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.714575074
Short name T834
Test name
Test status
Simulation time 667650518 ps
CPU time 18.97 seconds
Started Jan 21 04:03:44 PM PST 24
Finished Jan 21 04:04:07 PM PST 24
Peak memory 207316 kb
Host smart-6babfa9b-a1c8-4b02-b1ed-6023e4f8ae23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714575074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.714575074
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4294744878
Short name T550
Test name
Test status
Simulation time 2582672178 ps
CPU time 32.23 seconds
Started Jan 21 04:03:38 PM PST 24
Finished Jan 21 04:04:12 PM PST 24
Peak memory 199136 kb
Host smart-aa33700a-cc2c-40b5-9ddb-6cdf12226dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294744878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4294744878
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.734564993
Short name T577
Test name
Test status
Simulation time 110193451 ps
CPU time 4.61 seconds
Started Jan 21 04:03:38 PM PST 24
Finished Jan 21 04:03:44 PM PST 24
Peak memory 199112 kb
Host smart-98f5e8f2-9fa7-4a4a-a451-d079ffabbcf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734564993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.734564993
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2112497806
Short name T510
Test name
Test status
Simulation time 7153888159 ps
CPU time 84.4 seconds
Started Jan 21 04:03:51 PM PST 24
Finished Jan 21 04:05:19 PM PST 24
Peak memory 199200 kb
Host smart-0ad74fb1-a750-4219-be40-354e32126134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112497806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2112497806
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2178899855
Short name T307
Test name
Test status
Simulation time 7369847826 ps
CPU time 64.42 seconds
Started Jan 21 04:03:35 PM PST 24
Finished Jan 21 04:04:40 PM PST 24
Peak memory 199136 kb
Host smart-ee5c0dd3-f2dd-4591-ab13-6787881f31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178899855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2178899855
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3291698111
Short name T602
Test name
Test status
Simulation time 61876182 ps
CPU time 0.62 seconds
Started Jan 21 04:03:42 PM PST 24
Finished Jan 21 04:03:47 PM PST 24
Peak memory 194224 kb
Host smart-168be279-7960-4fb2-98de-886f7097d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291698111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3291698111
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3471122179
Short name T815
Test name
Test status
Simulation time 6747284907 ps
CPU time 12.37 seconds
Started Jan 21 04:03:48 PM PST 24
Finished Jan 21 04:04:02 PM PST 24
Peak memory 223792 kb
Host smart-45d16dff-0f3f-4caa-bfd7-b752f3008701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471122179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3471122179
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.2424955724
Short name T116
Test name
Test status
Simulation time 222820134186 ps
CPU time 1999.41 seconds
Started Jan 21 04:03:47 PM PST 24
Finished Jan 21 04:37:08 PM PST 24
Peak memory 248488 kb
Host smart-520d0560-7c1f-4fc2-bb01-be4f9a392a91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424955724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.2424955724
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3988265475
Short name T432
Test name
Test status
Simulation time 178737301 ps
CPU time 0.9 seconds
Started Jan 21 04:03:48 PM PST 24
Finished Jan 21 04:03:51 PM PST 24
Peak memory 196320 kb
Host smart-5760d8fa-1ed7-476a-b40d-8ab5f9a8f263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988265475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3988265475
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.139781899
Short name T197
Test name
Test status
Simulation time 118222997732 ps
CPU time 414.59 seconds
Started Jan 21 04:03:45 PM PST 24
Finished Jan 21 04:10:43 PM PST 24
Peak memory 199172 kb
Host smart-1ca5aa3b-329e-4ed9-b4fa-ade7f96251dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139781899 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_sha_vectors.139781899
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.18897825
Short name T806
Test name
Test status
Simulation time 270659984 ps
CPU time 13.05 seconds
Started Jan 21 04:03:48 PM PST 24
Finished Jan 21 04:04:02 PM PST 24
Peak memory 199096 kb
Host smart-b79806c3-a67f-4dea-8f8d-8a5845da06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18897825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.18897825
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.3653594136
Short name T587
Test name
Test status
Simulation time 84447572632 ps
CPU time 305.88 seconds
Started Jan 21 04:09:34 PM PST 24
Finished Jan 21 04:14:41 PM PST 24
Peak memory 215712 kb
Host smart-66dc5c36-ebd1-4114-9c6b-92e9124c939d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653594136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.3653594136
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.3585794031
Short name T623
Test name
Test status
Simulation time 71131013985 ps
CPU time 842.89 seconds
Started Jan 21 04:09:35 PM PST 24
Finished Jan 21 04:23:39 PM PST 24
Peak memory 241772 kb
Host smart-cd2e7d0e-11d2-4db2-9045-d9760613f2fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585794031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.3585794031
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.1450984956
Short name T207
Test name
Test status
Simulation time 321145407888 ps
CPU time 2056.43 seconds
Started Jan 21 04:09:34 PM PST 24
Finished Jan 21 04:43:52 PM PST 24
Peak memory 245444 kb
Host smart-917e8940-e8b8-462a-acdf-8f56c133b307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450984956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.1450984956
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.1204474372
Short name T521
Test name
Test status
Simulation time 73833377450 ps
CPU time 2877.74 seconds
Started Jan 21 04:09:41 PM PST 24
Finished Jan 21 04:57:41 PM PST 24
Peak memory 257184 kb
Host smart-b49b5581-720e-44eb-b806-c0be87610d1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204474372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.1204474372
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.1020318570
Short name T532
Test name
Test status
Simulation time 82936940275 ps
CPU time 1287.02 seconds
Started Jan 21 04:09:41 PM PST 24
Finished Jan 21 04:31:10 PM PST 24
Peak memory 226648 kb
Host smart-60270d50-6774-4a3b-bbae-6d1a3e7b7033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020318570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.1020318570
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.2974345851
Short name T780
Test name
Test status
Simulation time 219539439553 ps
CPU time 1151.16 seconds
Started Jan 21 04:09:40 PM PST 24
Finished Jan 21 04:28:53 PM PST 24
Peak memory 256668 kb
Host smart-4a36416e-7cc6-4b9d-b98d-a659a8c21b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974345851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.2974345851
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.4273004927
Short name T644
Test name
Test status
Simulation time 211818314233 ps
CPU time 990.07 seconds
Started Jan 21 04:09:43 PM PST 24
Finished Jan 21 04:26:18 PM PST 24
Peak memory 214860 kb
Host smart-51c1a5f0-3392-4aae-8cfa-859aa429b977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273004927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.4273004927
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.1891408810
Short name T758
Test name
Test status
Simulation time 68656467459 ps
CPU time 558.95 seconds
Started Jan 21 04:09:47 PM PST 24
Finished Jan 21 04:19:09 PM PST 24
Peak memory 207552 kb
Host smart-e26ce44a-cfe4-4bcb-92a5-a632b0057a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891408810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.1891408810
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1417236171
Short name T552
Test name
Test status
Simulation time 52006030531 ps
CPU time 2435.35 seconds
Started Jan 21 04:09:48 PM PST 24
Finished Jan 21 04:50:26 PM PST 24
Peak memory 246480 kb
Host smart-6ea8a8a9-99af-4d6a-a02d-d270e461930e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417236171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1417236171
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.3000103780
Short name T540
Test name
Test status
Simulation time 6679783282 ps
CPU time 82.03 seconds
Started Jan 21 04:09:47 PM PST 24
Finished Jan 21 04:11:12 PM PST 24
Peak memory 199300 kb
Host smart-2fd64111-35ae-41b6-904d-a32f61d8ceba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000103780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.3000103780
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2284351721
Short name T603
Test name
Test status
Simulation time 13092598 ps
CPU time 0.55 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:03:58 PM PST 24
Peak memory 192464 kb
Host smart-76a64e1a-14b1-4dcc-83eb-629725ca368b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284351721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2284351721
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1291551472
Short name T404
Test name
Test status
Simulation time 4198425794 ps
CPU time 33.75 seconds
Started Jan 21 04:03:50 PM PST 24
Finished Jan 21 04:04:26 PM PST 24
Peak memory 225712 kb
Host smart-5a9db45c-c141-42a5-83d1-5423692992ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291551472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1291551472
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3920508034
Short name T667
Test name
Test status
Simulation time 5417114828 ps
CPU time 42.77 seconds
Started Jan 21 04:03:51 PM PST 24
Finished Jan 21 04:04:37 PM PST 24
Peak memory 199192 kb
Host smart-6fd5bb18-72c0-4701-b11d-10e96d4bb6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920508034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3920508034
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.535718390
Short name T795
Test name
Test status
Simulation time 3484083063 ps
CPU time 86.16 seconds
Started Jan 21 04:03:49 PM PST 24
Finished Jan 21 04:05:17 PM PST 24
Peak memory 199176 kb
Host smart-8a6f6b90-7dd5-4d61-815a-94fb449b481e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535718390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.535718390
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3020043510
Short name T766
Test name
Test status
Simulation time 3632976834 ps
CPU time 47.94 seconds
Started Jan 21 04:03:50 PM PST 24
Finished Jan 21 04:04:40 PM PST 24
Peak memory 199188 kb
Host smart-31f8d5b4-4303-4080-bdb1-08749cc1e07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020043510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3020043510
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3673304149
Short name T685
Test name
Test status
Simulation time 5402404555 ps
CPU time 67.04 seconds
Started Jan 21 04:03:50 PM PST 24
Finished Jan 21 04:05:00 PM PST 24
Peak memory 199148 kb
Host smart-915e0fab-aa5e-4fc9-9aa2-e35455f1ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673304149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3673304149
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.4228229648
Short name T441
Test name
Test status
Simulation time 248579956 ps
CPU time 1.69 seconds
Started Jan 21 04:03:45 PM PST 24
Finished Jan 21 04:03:49 PM PST 24
Peak memory 198856 kb
Host smart-f399f760-da69-4f76-99d9-45e77b8b53e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228229648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4228229648
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1320303521
Short name T296
Test name
Test status
Simulation time 21270619078 ps
CPU time 224.88 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:07:43 PM PST 24
Peak memory 221044 kb
Host smart-8b12be94-57be-436d-b87e-d7c7955e4968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320303521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1320303521
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.2072525592
Short name T417
Test name
Test status
Simulation time 192101791954 ps
CPU time 878.77 seconds
Started Jan 21 04:03:53 PM PST 24
Finished Jan 21 04:18:34 PM PST 24
Peak memory 223872 kb
Host smart-2e502912-99eb-4e71-bcd1-92e6a7c7d023
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072525592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.2072525592
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3586440184
Short name T262
Test name
Test status
Simulation time 81330090 ps
CPU time 1.01 seconds
Started Jan 21 04:03:51 PM PST 24
Finished Jan 21 04:03:55 PM PST 24
Peak memory 197000 kb
Host smart-656c74d5-7f38-44a3-b577-30567b4f4959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586440184 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3586440184
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3579062321
Short name T415
Test name
Test status
Simulation time 7546718997 ps
CPU time 356.92 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:09:55 PM PST 24
Peak memory 199060 kb
Host smart-18d92407-ec1a-445f-8d00-3327db9622da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579062321 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.3579062321
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4050530705
Short name T624
Test name
Test status
Simulation time 3991331238 ps
CPU time 50.49 seconds
Started Jan 21 04:03:52 PM PST 24
Finished Jan 21 04:04:45 PM PST 24
Peak memory 199104 kb
Host smart-6c629c9a-6d5a-42ba-bf6f-9f32486773ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050530705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4050530705
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1645672279
Short name T444
Test name
Test status
Simulation time 410168624277 ps
CPU time 1649.11 seconds
Started Jan 21 04:09:53 PM PST 24
Finished Jan 21 04:37:24 PM PST 24
Peak memory 256744 kb
Host smart-c3ffcd15-1d85-4ec7-9246-1c7135404875
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645672279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.1645672279
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.2270545911
Short name T319
Test name
Test status
Simulation time 151923787454 ps
CPU time 1796.33 seconds
Started Jan 21 04:09:53 PM PST 24
Finished Jan 21 04:39:51 PM PST 24
Peak memory 226604 kb
Host smart-f5d34527-8bae-49dc-b62e-1e54df2b9149
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270545911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.2270545911
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.2951388123
Short name T763
Test name
Test status
Simulation time 57214285035 ps
CPU time 913.95 seconds
Started Jan 21 04:16:39 PM PST 24
Finished Jan 21 04:31:55 PM PST 24
Peak memory 215752 kb
Host smart-8517fdae-9637-4715-a384-50bff21fed17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951388123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.2951388123
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.1044919114
Short name T430
Test name
Test status
Simulation time 88537869280 ps
CPU time 1528.66 seconds
Started Jan 21 04:09:52 PM PST 24
Finished Jan 21 04:35:22 PM PST 24
Peak memory 242052 kb
Host smart-e5bdbc74-6e18-46bf-a570-566965252dcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044919114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.1044919114
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.2135705586
Short name T768
Test name
Test status
Simulation time 330722744516 ps
CPU time 569.93 seconds
Started Jan 21 04:09:51 PM PST 24
Finished Jan 21 04:19:23 PM PST 24
Peak memory 223932 kb
Host smart-5d29da83-e739-4c85-8a14-f817ff353d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135705586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.2135705586
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.1327287709
Short name T742
Test name
Test status
Simulation time 257830024597 ps
CPU time 442.42 seconds
Started Jan 21 04:09:54 PM PST 24
Finished Jan 21 04:17:17 PM PST 24
Peak memory 249488 kb
Host smart-170122b9-43db-4e3e-9b64-98c60b615b72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327287709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.1327287709
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.4088544565
Short name T38
Test name
Test status
Simulation time 623818477485 ps
CPU time 2452.45 seconds
Started Jan 21 04:10:00 PM PST 24
Finished Jan 21 04:50:54 PM PST 24
Peak memory 256584 kb
Host smart-7135568f-6c41-4915-a56f-278b119450f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088544565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.4088544565
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.3925488968
Short name T581
Test name
Test status
Simulation time 49119363229 ps
CPU time 178.13 seconds
Started Jan 21 04:09:58 PM PST 24
Finished Jan 21 04:12:57 PM PST 24
Peak memory 215536 kb
Host smart-2fbc6e6c-ea2e-4d0a-b57d-5a120cc23ab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925488968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.3925488968
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1271104932
Short name T466
Test name
Test status
Simulation time 12819784 ps
CPU time 0.56 seconds
Started Jan 21 04:04:02 PM PST 24
Finished Jan 21 04:04:06 PM PST 24
Peak memory 193548 kb
Host smart-ef1f7337-0254-4dc8-abc5-b1465ae6bc82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271104932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1271104932
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2357601223
Short name T498
Test name
Test status
Simulation time 1555952953 ps
CPU time 52.87 seconds
Started Jan 21 04:03:53 PM PST 24
Finished Jan 21 04:04:48 PM PST 24
Peak memory 223876 kb
Host smart-a2fc888e-04a6-49bc-9a7a-9fbee0e42723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357601223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2357601223
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3020773517
Short name T451
Test name
Test status
Simulation time 76920720 ps
CPU time 1.36 seconds
Started Jan 21 04:04:01 PM PST 24
Finished Jan 21 04:04:04 PM PST 24
Peak memory 198992 kb
Host smart-daa026db-d4c3-4b24-92e2-95c40aa6ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020773517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3020773517
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2914800993
Short name T745
Test name
Test status
Simulation time 1658034639 ps
CPU time 84.34 seconds
Started Jan 21 04:04:07 PM PST 24
Finished Jan 21 04:05:37 PM PST 24
Peak memory 199104 kb
Host smart-1292f9d2-454b-4475-b9f4-5d6f25fc5af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914800993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2914800993
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1490136702
Short name T390
Test name
Test status
Simulation time 28450891229 ps
CPU time 110.32 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:05:48 PM PST 24
Peak memory 199204 kb
Host smart-e0142fe8-6efa-4389-8e0b-bd0c46edb46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490136702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1490136702
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.866488450
Short name T662
Test name
Test status
Simulation time 1195065307 ps
CPU time 3.13 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:04:01 PM PST 24
Peak memory 199076 kb
Host smart-fdb9747b-b611-43ad-b8e4-4b54ba08cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866488450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.866488450
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3199531728
Short name T699
Test name
Test status
Simulation time 1764025989 ps
CPU time 41.79 seconds
Started Jan 21 04:04:02 PM PST 24
Finished Jan 21 04:04:45 PM PST 24
Peak memory 223660 kb
Host smart-71ba1249-da19-44fd-a859-ab1db2c88752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199531728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3199531728
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.902644046
Short name T627
Test name
Test status
Simulation time 106696223094 ps
CPU time 1583.78 seconds
Started Jan 21 04:03:58 PM PST 24
Finished Jan 21 04:30:23 PM PST 24
Peak memory 256008 kb
Host smart-bca83f31-8af7-4849-b5b3-3778785eec82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902644046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.902644046
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.677456465
Short name T783
Test name
Test status
Simulation time 58222006 ps
CPU time 0.95 seconds
Started Jan 21 04:04:02 PM PST 24
Finished Jan 21 04:04:06 PM PST 24
Peak memory 196792 kb
Host smart-7f3540aa-11f6-44cd-97f6-016e8ca724f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677456465 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.677456465
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1706083160
Short name T463
Test name
Test status
Simulation time 27782537420 ps
CPU time 359.97 seconds
Started Jan 21 04:04:05 PM PST 24
Finished Jan 21 04:10:10 PM PST 24
Peak memory 199324 kb
Host smart-db853f1d-fb74-40d5-a9a2-760fd8be7ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706083160 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1706083160
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.762911800
Short name T558
Test name
Test status
Simulation time 450151056 ps
CPU time 13.96 seconds
Started Jan 21 04:03:59 PM PST 24
Finished Jan 21 04:04:13 PM PST 24
Peak memory 199088 kb
Host smart-7fdfedff-9d57-4305-978e-0a64a8bf066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762911800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.762911800
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.1167269731
Short name T101
Test name
Test status
Simulation time 255982387652 ps
CPU time 3084.98 seconds
Started Jan 21 04:56:06 PM PST 24
Finished Jan 21 05:47:32 PM PST 24
Peak memory 259776 kb
Host smart-df45889d-609a-4797-9929-670b6db9b60d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167269731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.1167269731
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3560063695
Short name T630
Test name
Test status
Simulation time 11741853660 ps
CPU time 233.63 seconds
Started Jan 21 04:10:00 PM PST 24
Finished Jan 21 04:13:55 PM PST 24
Peak memory 215688 kb
Host smart-9bca0cc8-2ad0-40a7-bd81-6142f7e2b525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560063695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.3560063695
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.1410886727
Short name T370
Test name
Test status
Simulation time 81373359602 ps
CPU time 3693.66 seconds
Started Jan 21 04:10:00 PM PST 24
Finished Jan 21 05:11:36 PM PST 24
Peak memory 256852 kb
Host smart-de6c2c8d-bd30-48ed-8944-f2cb2706f895
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410886727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.1410886727
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.1065939016
Short name T610
Test name
Test status
Simulation time 233345283983 ps
CPU time 297.73 seconds
Started Jan 21 04:10:04 PM PST 24
Finished Jan 21 04:15:03 PM PST 24
Peak memory 243072 kb
Host smart-a26b98d1-fc70-4d7f-b092-1f67b866b0d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065939016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.1065939016
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3753237844
Short name T808
Test name
Test status
Simulation time 106355012456 ps
CPU time 5377.58 seconds
Started Jan 21 04:10:12 PM PST 24
Finished Jan 21 05:39:51 PM PST 24
Peak memory 274080 kb
Host smart-cc68324f-77b5-464a-9502-58d57f4a450c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753237844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.3753237844
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2727114379
Short name T420
Test name
Test status
Simulation time 11028467380 ps
CPU time 220.3 seconds
Started Jan 21 04:35:24 PM PST 24
Finished Jan 21 04:39:06 PM PST 24
Peak memory 215700 kb
Host smart-7b44b372-0fef-4f46-9cf9-fe63eeeb8c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727114379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.2727114379
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.1902897296
Short name T601
Test name
Test status
Simulation time 120251622207 ps
CPU time 1001.88 seconds
Started Jan 21 04:55:43 PM PST 24
Finished Jan 21 05:12:26 PM PST 24
Peak memory 244344 kb
Host smart-22a7592b-0bf6-49f5-9c09-2f0269046350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902897296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.1902897296
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.423602689
Short name T822
Test name
Test status
Simulation time 100787591398 ps
CPU time 1247.6 seconds
Started Jan 21 04:10:12 PM PST 24
Finished Jan 21 04:31:01 PM PST 24
Peak memory 257628 kb
Host smart-c071dfaa-7686-483f-9bd0-a3f7de9edf25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423602689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.423602689
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.162669556
Short name T134
Test name
Test status
Simulation time 112882964582 ps
CPU time 1529.64 seconds
Started Jan 21 04:32:33 PM PST 24
Finished Jan 21 04:58:04 PM PST 24
Peak memory 244432 kb
Host smart-d8b9b499-7a45-42f6-8cc0-a55e5470fe7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162669556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.162669556
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.3930591014
Short name T349
Test name
Test status
Simulation time 101311951645 ps
CPU time 914.59 seconds
Started Jan 21 04:10:15 PM PST 24
Finished Jan 21 04:25:30 PM PST 24
Peak memory 199368 kb
Host smart-db458afe-8e88-4c3a-920f-136d9d52efdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930591014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.3930591014
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2238052369
Short name T223
Test name
Test status
Simulation time 44854829 ps
CPU time 0.56 seconds
Started Jan 21 04:04:04 PM PST 24
Finished Jan 21 04:04:10 PM PST 24
Peak memory 193284 kb
Host smart-39ab8c14-aa52-46a6-878e-975e40f0f9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238052369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2238052369
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3839448237
Short name T295
Test name
Test status
Simulation time 3958361534 ps
CPU time 28.05 seconds
Started Jan 21 04:04:03 PM PST 24
Finished Jan 21 04:04:37 PM PST 24
Peak memory 207344 kb
Host smart-d5734855-987b-4338-bd95-e5ad1834d168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839448237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3839448237
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3553117291
Short name T566
Test name
Test status
Simulation time 7752156559 ps
CPU time 18.55 seconds
Started Jan 21 04:04:07 PM PST 24
Finished Jan 21 04:04:32 PM PST 24
Peak memory 199168 kb
Host smart-8fc2e3eb-128f-4e84-b2e4-29a7d663c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553117291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3553117291
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1240779947
Short name T513
Test name
Test status
Simulation time 6208108411 ps
CPU time 84.21 seconds
Started Jan 21 04:04:03 PM PST 24
Finished Jan 21 04:05:30 PM PST 24
Peak memory 199176 kb
Host smart-c07ad4e3-49e2-48b3-8af8-931b2da743cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240779947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1240779947
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4206436699
Short name T8
Test name
Test status
Simulation time 4731064485 ps
CPU time 20.56 seconds
Started Jan 21 04:04:14 PM PST 24
Finished Jan 21 04:04:37 PM PST 24
Peak memory 199120 kb
Host smart-451348e3-e598-428e-8388-e29cae98ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206436699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4206436699
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2392653991
Short name T477
Test name
Test status
Simulation time 1080711650 ps
CPU time 55.21 seconds
Started Jan 21 04:04:00 PM PST 24
Finished Jan 21 04:04:56 PM PST 24
Peak memory 199064 kb
Host smart-b6eb3975-1184-4910-928b-d7653a1225f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392653991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2392653991
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2996699850
Short name T580
Test name
Test status
Simulation time 1418591040 ps
CPU time 3.83 seconds
Started Jan 21 04:04:00 PM PST 24
Finished Jan 21 04:04:05 PM PST 24
Peak memory 199096 kb
Host smart-4595d6e8-e9b5-47a7-b8d3-ebdea65bb4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996699850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2996699850
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2551323586
Short name T650
Test name
Test status
Simulation time 45791056699 ps
CPU time 1200.7 seconds
Started Jan 21 04:04:07 PM PST 24
Finished Jan 21 04:24:14 PM PST 24
Peak memory 223844 kb
Host smart-e6f80c53-24ce-46ed-ad3c-e87e0e8362e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551323586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2551323586
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1487223378
Short name T843
Test name
Test status
Simulation time 37563015461 ps
CPU time 1792.04 seconds
Started Jan 21 04:04:09 PM PST 24
Finished Jan 21 04:34:06 PM PST 24
Peak memory 254736 kb
Host smart-4e98a745-15a3-4925-8086-858b73bbb962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487223378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1487223378
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2967401353
Short name T592
Test name
Test status
Simulation time 69614004 ps
CPU time 1.28 seconds
Started Jan 21 05:56:34 PM PST 24
Finished Jan 21 05:56:36 PM PST 24
Peak memory 198508 kb
Host smart-7734bc74-fb7d-44c7-8d82-82155ec92fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967401353 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2967401353
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.798622398
Short name T313
Test name
Test status
Simulation time 46845984839 ps
CPU time 559.98 seconds
Started Jan 21 04:29:26 PM PST 24
Finished Jan 21 04:38:47 PM PST 24
Peak memory 199164 kb
Host smart-84f56545-721d-4cde-9ab4-7fe4c97dcd86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798622398 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_sha_vectors.798622398
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1575076261
Short name T230
Test name
Test status
Simulation time 2237914555 ps
CPU time 44.13 seconds
Started Jan 21 04:04:14 PM PST 24
Finished Jan 21 04:05:01 PM PST 24
Peak memory 199124 kb
Host smart-1200bfce-1117-4555-b12d-2c3b7d591546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575076261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1575076261
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.4171179415
Short name T746
Test name
Test status
Simulation time 20715549204 ps
CPU time 375.37 seconds
Started Jan 21 04:10:15 PM PST 24
Finished Jan 21 04:16:31 PM PST 24
Peak memory 207556 kb
Host smart-e3606ac8-4fae-435a-b8dd-db156c199ae0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171179415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.4171179415
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.1471309181
Short name T391
Test name
Test status
Simulation time 36581796236 ps
CPU time 1582.67 seconds
Started Jan 21 04:10:14 PM PST 24
Finished Jan 21 04:36:38 PM PST 24
Peak memory 224336 kb
Host smart-bf4145bf-e7ed-42d3-a6e4-266dabcf9223
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471309181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.1471309181
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.2454633968
Short name T794
Test name
Test status
Simulation time 1346153281083 ps
CPU time 1953.01 seconds
Started Jan 21 04:10:14 PM PST 24
Finished Jan 21 04:42:49 PM PST 24
Peak memory 248624 kb
Host smart-0bedbc78-4b87-4964-b92e-36b5ff211a6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454633968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.2454633968
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.741156336
Short name T111
Test name
Test status
Simulation time 429066387028 ps
CPU time 5012.08 seconds
Started Jan 21 04:10:20 PM PST 24
Finished Jan 21 05:33:59 PM PST 24
Peak memory 246232 kb
Host smart-150fed5a-0769-467d-abe6-65db2b1da215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741156336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.741156336
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.2716175398
Short name T5
Test name
Test status
Simulation time 56319789830 ps
CPU time 727.79 seconds
Started Jan 21 04:10:21 PM PST 24
Finished Jan 21 04:22:34 PM PST 24
Peak memory 223876 kb
Host smart-acba2363-af7c-421c-885c-5c07d440d8c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716175398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.2716175398
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.1543332130
Short name T582
Test name
Test status
Simulation time 26525395479 ps
CPU time 361.06 seconds
Started Jan 21 04:10:19 PM PST 24
Finished Jan 21 04:16:27 PM PST 24
Peak memory 240292 kb
Host smart-6bae50c8-f602-49e0-86ad-69c342beb76d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543332130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.1543332130
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3438735426
Short name T362
Test name
Test status
Simulation time 450937713049 ps
CPU time 1530.97 seconds
Started Jan 21 04:10:19 PM PST 24
Finished Jan 21 04:35:57 PM PST 24
Peak memory 258672 kb
Host smart-cd0e05a7-1b72-4de6-af51-2e3d3f74b129
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438735426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.3438735426
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.1998538360
Short name T764
Test name
Test status
Simulation time 25082803051 ps
CPU time 1287.7 seconds
Started Jan 21 04:10:32 PM PST 24
Finished Jan 21 04:32:01 PM PST 24
Peak memory 245440 kb
Host smart-23f631cd-1679-4c25-ae96-96e3ef7e2a65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998538360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.1998538360
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.1499551402
Short name T412
Test name
Test status
Simulation time 269350399517 ps
CPU time 3066.58 seconds
Started Jan 21 04:10:29 PM PST 24
Finished Jan 21 05:01:38 PM PST 24
Peak memory 258304 kb
Host smart-6e0950a0-7310-4573-93c0-e629b64d36b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499551402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.1499551402
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1509448086
Short name T393
Test name
Test status
Simulation time 42560579 ps
CPU time 0.59 seconds
Started Jan 21 04:20:01 PM PST 24
Finished Jan 21 04:20:09 PM PST 24
Peak memory 192600 kb
Host smart-f77cf29b-33b9-40b3-a3e4-346002262666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509448086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1509448086
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.325728763
Short name T479
Test name
Test status
Simulation time 248580416 ps
CPU time 11.04 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:01:58 PM PST 24
Peak memory 221672 kb
Host smart-6c774b9d-1864-4889-a747-c34a355e201a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325728763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.325728763
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2815571591
Short name T59
Test name
Test status
Simulation time 158862393 ps
CPU time 7.17 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:01:54 PM PST 24
Peak memory 199060 kb
Host smart-0ee9f7c6-e019-41ea-b6dc-660b1b251e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815571591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2815571591
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1394303965
Short name T421
Test name
Test status
Simulation time 3410871016 ps
CPU time 83.09 seconds
Started Jan 21 04:01:39 PM PST 24
Finished Jan 21 04:03:09 PM PST 24
Peak memory 199132 kb
Host smart-e1d032a8-21f3-4725-9309-afc1daa6c072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394303965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1394303965
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3861632345
Short name T329
Test name
Test status
Simulation time 802214980 ps
CPU time 18.28 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:02:05 PM PST 24
Peak memory 199088 kb
Host smart-3daa5a50-2a77-4796-a6c6-d7e182bce3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861632345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3861632345
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.56922893
Short name T247
Test name
Test status
Simulation time 8381357706 ps
CPU time 36.95 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:02:24 PM PST 24
Peak memory 199088 kb
Host smart-db9f24dd-5d10-406c-957c-3b56315a643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56922893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.56922893
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1719447164
Short name T54
Test name
Test status
Simulation time 132309339 ps
CPU time 0.79 seconds
Started Jan 21 04:01:42 PM PST 24
Finished Jan 21 04:01:47 PM PST 24
Peak memory 215908 kb
Host smart-3ba43cb6-9e65-4e0f-a80d-b6975fae1deb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719447164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1719447164
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.83533693
Short name T728
Test name
Test status
Simulation time 1360651119 ps
CPU time 3.75 seconds
Started Jan 21 04:01:43 PM PST 24
Finished Jan 21 04:01:51 PM PST 24
Peak memory 199160 kb
Host smart-a5965fd3-a160-46c5-b617-a77dde951168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83533693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.83533693
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4237312282
Short name T309
Test name
Test status
Simulation time 141927092525 ps
CPU time 504.49 seconds
Started Jan 21 04:01:45 PM PST 24
Finished Jan 21 04:10:12 PM PST 24
Peak memory 199168 kb
Host smart-594cef40-3a76-4783-8d29-78251f905907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237312282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4237312282
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.40065596
Short name T676
Test name
Test status
Simulation time 35003496237 ps
CPU time 1589.4 seconds
Started Jan 21 04:01:42 PM PST 24
Finished Jan 21 04:28:16 PM PST 24
Peak memory 249392 kb
Host smart-a906698e-e564-425e-ac1e-0c3c30eeb26f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40065596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.40065596
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3948070583
Short name T478
Test name
Test status
Simulation time 44589009 ps
CPU time 0.86 seconds
Started Jan 21 04:01:39 PM PST 24
Finished Jan 21 04:01:47 PM PST 24
Peak memory 196112 kb
Host smart-fbd76f1a-5850-43ee-82a0-b0f8ea807726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948070583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3948070583
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3595479979
Short name T700
Test name
Test status
Simulation time 55877628777 ps
CPU time 456.54 seconds
Started Jan 21 04:01:41 PM PST 24
Finished Jan 21 04:09:23 PM PST 24
Peak memory 199168 kb
Host smart-95632136-eb62-4446-8880-f05ebdd7bf66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595479979 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.3595479979
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3977789921
Short name T527
Test name
Test status
Simulation time 618692455 ps
CPU time 3.86 seconds
Started Jan 21 04:01:38 PM PST 24
Finished Jan 21 04:01:49 PM PST 24
Peak memory 199012 kb
Host smart-01df0bf7-1dd7-4482-a1e2-6e6f7c83df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977789921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3977789921
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1345247448
Short name T523
Test name
Test status
Simulation time 18639294 ps
CPU time 0.55 seconds
Started Jan 21 05:40:59 PM PST 24
Finished Jan 21 05:41:01 PM PST 24
Peak memory 193540 kb
Host smart-43f8ec8d-4392-4a51-b417-509177ff4986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345247448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1345247448
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2176451792
Short name T325
Test name
Test status
Simulation time 1332519022 ps
CPU time 25.75 seconds
Started Jan 21 04:04:05 PM PST 24
Finished Jan 21 04:04:36 PM PST 24
Peak memory 240056 kb
Host smart-64756039-ac11-421e-80e4-d35e26253229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176451792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2176451792
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3420245754
Short name T369
Test name
Test status
Simulation time 511280250 ps
CPU time 10.87 seconds
Started Jan 21 04:04:06 PM PST 24
Finished Jan 21 04:04:23 PM PST 24
Peak memory 198952 kb
Host smart-9ffb7e87-bb0c-4094-9f40-96b09b492a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420245754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3420245754
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3520743303
Short name T203
Test name
Test status
Simulation time 3253300703 ps
CPU time 101.29 seconds
Started Jan 21 04:36:57 PM PST 24
Finished Jan 21 04:38:39 PM PST 24
Peak memory 199136 kb
Host smart-b777f564-d583-4b6c-931e-99721327a9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520743303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3520743303
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3581693254
Short name T43
Test name
Test status
Simulation time 6786800698 ps
CPU time 108.59 seconds
Started Jan 21 04:35:54 PM PST 24
Finished Jan 21 04:37:44 PM PST 24
Peak memory 199188 kb
Host smart-4d14fb9e-056f-4e3f-92ea-6ddfafa1a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581693254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3581693254
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1081914825
Short name T371
Test name
Test status
Simulation time 955459716 ps
CPU time 23.22 seconds
Started Jan 21 04:04:06 PM PST 24
Finished Jan 21 04:04:36 PM PST 24
Peak memory 199120 kb
Host smart-2cd14ca8-143d-4403-bcd5-5a1aade1888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081914825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1081914825
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2109730275
Short name T272
Test name
Test status
Simulation time 680239612 ps
CPU time 4.38 seconds
Started Jan 21 04:04:06 PM PST 24
Finished Jan 21 04:04:16 PM PST 24
Peak memory 199084 kb
Host smart-8be169c7-58c6-453e-a9de-ddfea21096a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109730275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2109730275
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3989965829
Short name T133
Test name
Test status
Simulation time 96557466887 ps
CPU time 1155.46 seconds
Started Jan 21 04:04:16 PM PST 24
Finished Jan 21 04:23:33 PM PST 24
Peak memory 207452 kb
Host smart-3f8866bf-f9d0-4777-9d8f-ce3808c3021d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989965829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3989965829
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1627206742
Short name T850
Test name
Test status
Simulation time 53525540 ps
CPU time 1.25 seconds
Started Jan 21 04:55:09 PM PST 24
Finished Jan 21 04:55:12 PM PST 24
Peak memory 197280 kb
Host smart-4a7cf807-74ca-4c0c-8151-f8f3fad20b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627206742 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1627206742
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3529729425
Short name T327
Test name
Test status
Simulation time 35067847612 ps
CPU time 397.34 seconds
Started Jan 21 04:04:14 PM PST 24
Finished Jan 21 04:10:54 PM PST 24
Peak memory 199076 kb
Host smart-a6d40ec8-db41-4f84-90dc-aabce66ce55e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529729425 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3529729425
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.625996451
Short name T10
Test name
Test status
Simulation time 1168797086 ps
CPU time 8.91 seconds
Started Jan 21 04:04:05 PM PST 24
Finished Jan 21 04:04:19 PM PST 24
Peak memory 199092 kb
Host smart-9b46af0e-1c7e-493f-8881-3d511f1ba0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625996451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.625996451
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1398257531
Short name T838
Test name
Test status
Simulation time 43700239 ps
CPU time 0.62 seconds
Started Jan 21 04:04:20 PM PST 24
Finished Jan 21 04:04:22 PM PST 24
Peak memory 193268 kb
Host smart-99f1e17f-ae9c-4c24-8a76-a25dfea213fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398257531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1398257531
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3930221585
Short name T736
Test name
Test status
Simulation time 2444839447 ps
CPU time 15.29 seconds
Started Jan 21 04:04:15 PM PST 24
Finished Jan 21 04:04:33 PM PST 24
Peak memory 223800 kb
Host smart-75cc87d9-04bb-4ad7-b04d-82f9eb1358b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930221585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3930221585
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.930295562
Short name T774
Test name
Test status
Simulation time 1622500652 ps
CPU time 29.45 seconds
Started Jan 21 07:32:43 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 199112 kb
Host smart-b976598a-f016-4f44-8d78-20d25c7f151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930295562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.930295562
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1591530716
Short name T215
Test name
Test status
Simulation time 1551852326 ps
CPU time 20.01 seconds
Started Jan 21 04:04:16 PM PST 24
Finished Jan 21 04:04:38 PM PST 24
Peak memory 199064 kb
Host smart-9d12a306-0bf4-4d02-902c-932979c116b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591530716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1591530716
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3641185408
Short name T363
Test name
Test status
Simulation time 44951622900 ps
CPU time 170.44 seconds
Started Jan 21 06:06:20 PM PST 24
Finished Jan 21 06:09:14 PM PST 24
Peak memory 199184 kb
Host smart-9f2cac04-cb0b-4ad2-8c48-ce86e66ebcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641185408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3641185408
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2850647989
Short name T332
Test name
Test status
Simulation time 638164475 ps
CPU time 8.07 seconds
Started Jan 21 04:04:19 PM PST 24
Finished Jan 21 04:04:28 PM PST 24
Peak memory 199096 kb
Host smart-6d140107-8321-46cc-9d8b-200a4a50a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850647989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2850647989
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2144718259
Short name T279
Test name
Test status
Simulation time 275753371 ps
CPU time 3.61 seconds
Started Jan 21 04:04:15 PM PST 24
Finished Jan 21 04:04:21 PM PST 24
Peak memory 199000 kb
Host smart-7b2ad51a-b685-42b2-a2f3-5050136bc4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144718259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2144718259
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.418859759
Short name T842
Test name
Test status
Simulation time 348232442672 ps
CPU time 1576.87 seconds
Started Jan 21 04:04:27 PM PST 24
Finished Jan 21 04:30:45 PM PST 24
Peak memory 226904 kb
Host smart-761c4893-2128-4af2-b3d6-ae7322264194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418859759 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.418859759
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.2571817354
Short name T418
Test name
Test status
Simulation time 69859038911 ps
CPU time 129.06 seconds
Started Jan 21 04:04:24 PM PST 24
Finished Jan 21 04:06:35 PM PST 24
Peak memory 215740 kb
Host smart-ba5ee152-d4cf-4010-a5bc-79e10ef63d8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571817354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.2571817354
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.85184450
Short name T60
Test name
Test status
Simulation time 106926890 ps
CPU time 1.05 seconds
Started Jan 21 04:04:23 PM PST 24
Finished Jan 21 04:04:25 PM PST 24
Peak memory 196496 kb
Host smart-04d0a972-0db9-40d2-9769-27dd3fb5a5d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85184450 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_test_hmac_vectors.85184450
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.4074208077
Short name T375
Test name
Test status
Simulation time 7802495277 ps
CPU time 403.61 seconds
Started Jan 21 04:32:45 PM PST 24
Finished Jan 21 04:39:37 PM PST 24
Peak memory 199076 kb
Host smart-fd80671e-ab07-4f29-afff-de07366c8d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074208077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.4074208077
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3923641088
Short name T343
Test name
Test status
Simulation time 6167185310 ps
CPU time 26.81 seconds
Started Jan 21 04:04:15 PM PST 24
Finished Jan 21 04:04:44 PM PST 24
Peak memory 199160 kb
Host smart-14570476-67ac-4dc3-a42f-d0a395e4beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923641088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3923641088
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.203812994
Short name T771
Test name
Test status
Simulation time 30697636 ps
CPU time 0.54 seconds
Started Jan 21 04:04:34 PM PST 24
Finished Jan 21 04:04:36 PM PST 24
Peak memory 192560 kb
Host smart-0d942f74-6f42-4fbe-bef6-9e8a6df26a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203812994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.203812994
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2981058510
Short name T344
Test name
Test status
Simulation time 2186346073 ps
CPU time 39.87 seconds
Started Jan 21 04:04:18 PM PST 24
Finished Jan 21 04:04:59 PM PST 24
Peak memory 225260 kb
Host smart-5a2980b3-29ae-4989-947e-2adb472af45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981058510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2981058510
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1086491070
Short name T649
Test name
Test status
Simulation time 7317897605 ps
CPU time 32.44 seconds
Started Jan 21 04:04:21 PM PST 24
Finished Jan 21 04:04:54 PM PST 24
Peak memory 199096 kb
Host smart-297fc168-e0a9-4148-bceb-ab01cb77740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086491070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1086491070
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2156998755
Short name T520
Test name
Test status
Simulation time 1265107077 ps
CPU time 59.78 seconds
Started Jan 21 04:04:20 PM PST 24
Finished Jan 21 04:05:21 PM PST 24
Peak memory 199068 kb
Host smart-0f171a51-3157-4c28-b78d-95fabf4f1f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156998755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2156998755
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2980915824
Short name T467
Test name
Test status
Simulation time 13031879951 ps
CPU time 84.79 seconds
Started Jan 21 04:04:23 PM PST 24
Finished Jan 21 04:05:49 PM PST 24
Peak memory 199168 kb
Host smart-8668ef91-b23f-49a4-a2fd-20808c409bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980915824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2980915824
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1817326587
Short name T433
Test name
Test status
Simulation time 704098864 ps
CPU time 36.96 seconds
Started Jan 21 04:04:22 PM PST 24
Finished Jan 21 04:04:59 PM PST 24
Peak memory 198932 kb
Host smart-58915fa3-4d51-49f3-8790-38cec72b057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817326587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1817326587
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3286484078
Short name T41
Test name
Test status
Simulation time 1195638731 ps
CPU time 4.2 seconds
Started Jan 21 04:04:22 PM PST 24
Finished Jan 21 04:04:27 PM PST 24
Peak memory 198364 kb
Host smart-3cdcd649-ea4d-4055-ac59-150f7ef54876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286484078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3286484078
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1256097428
Short name T435
Test name
Test status
Simulation time 484000634295 ps
CPU time 2130.59 seconds
Started Jan 21 04:04:22 PM PST 24
Finished Jan 21 04:39:53 PM PST 24
Peak memory 207448 kb
Host smart-afc2931e-e701-4159-a3cf-4ca2f7b034e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256097428 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1256097428
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.1507733720
Short name T398
Test name
Test status
Simulation time 77709355277 ps
CPU time 1966.83 seconds
Started Jan 21 04:04:19 PM PST 24
Finished Jan 21 04:37:07 PM PST 24
Peak memory 249508 kb
Host smart-93a34c1b-7dbc-43cd-8fdf-75271836db05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507733720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.1507733720
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1036243090
Short name T427
Test name
Test status
Simulation time 108105103 ps
CPU time 0.92 seconds
Started Jan 21 04:04:22 PM PST 24
Finished Jan 21 04:04:24 PM PST 24
Peak memory 196096 kb
Host smart-e2b69c90-b8f7-4d3f-be4a-c71e8677d645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036243090 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1036243090
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2879057034
Short name T37
Test name
Test status
Simulation time 6566422472 ps
CPU time 326.53 seconds
Started Jan 21 04:04:24 PM PST 24
Finished Jan 21 04:09:52 PM PST 24
Peak memory 199036 kb
Host smart-e6792e21-6ca1-496a-ae70-47f7892cb2a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879057034 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.2879057034
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1159257705
Short name T210
Test name
Test status
Simulation time 4181137579 ps
CPU time 36.66 seconds
Started Jan 21 04:04:25 PM PST 24
Finished Jan 21 04:05:03 PM PST 24
Peak memory 199384 kb
Host smart-65d2370c-ec72-4d44-bb97-4fd9c2c7cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159257705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1159257705
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.382421742
Short name T49
Test name
Test status
Simulation time 12721782 ps
CPU time 0.61 seconds
Started Jan 21 04:32:40 PM PST 24
Finished Jan 21 04:32:51 PM PST 24
Peak memory 193464 kb
Host smart-78ae4ee2-e9bd-4152-85e4-f8bc49d0ee04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382421742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.382421742
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3222574853
Short name T36
Test name
Test status
Simulation time 1804714840 ps
CPU time 15.41 seconds
Started Jan 21 04:04:35 PM PST 24
Finished Jan 21 04:04:52 PM PST 24
Peak memory 214960 kb
Host smart-a1d6641e-1fc5-43ec-9206-9a4dc661b946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222574853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3222574853
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.95834962
Short name T331
Test name
Test status
Simulation time 2423688967 ps
CPU time 20.74 seconds
Started Jan 21 04:04:35 PM PST 24
Finished Jan 21 04:04:57 PM PST 24
Peak memory 199104 kb
Host smart-9187bcdd-34e0-4d6d-a489-b8d103c28366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95834962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.95834962
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3851940409
Short name T588
Test name
Test status
Simulation time 351457916 ps
CPU time 9.13 seconds
Started Jan 21 04:04:39 PM PST 24
Finished Jan 21 04:04:51 PM PST 24
Peak memory 199140 kb
Host smart-fcc50f20-5a2f-41ee-ba09-439d619fb6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851940409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3851940409
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.790727940
Short name T256
Test name
Test status
Simulation time 2177304249 ps
CPU time 84.18 seconds
Started Jan 21 04:04:40 PM PST 24
Finished Jan 21 04:06:06 PM PST 24
Peak memory 199212 kb
Host smart-0b1906ac-ad4e-4385-b58f-e46e2becc643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790727940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.790727940
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.983379032
Short name T803
Test name
Test status
Simulation time 52352996471 ps
CPU time 83.43 seconds
Started Jan 21 04:04:35 PM PST 24
Finished Jan 21 04:05:59 PM PST 24
Peak memory 199168 kb
Host smart-28245e55-b1df-4fd7-8234-d4bcc4613ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983379032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.983379032
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3013744487
Short name T311
Test name
Test status
Simulation time 373443515 ps
CPU time 2.32 seconds
Started Jan 21 04:04:32 PM PST 24
Finished Jan 21 04:04:35 PM PST 24
Peak memory 199092 kb
Host smart-92699aa1-f6c0-453d-b1e3-1115043ce3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013744487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3013744487
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1121688502
Short name T555
Test name
Test status
Simulation time 78201263451 ps
CPU time 989 seconds
Started Jan 21 04:04:36 PM PST 24
Finished Jan 21 04:21:07 PM PST 24
Peak memory 199192 kb
Host smart-9a780e02-6747-42d2-9f5c-adff940d4483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121688502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1121688502
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.2050865673
Short name T121
Test name
Test status
Simulation time 99071779391 ps
CPU time 3994.2 seconds
Started Jan 21 05:38:32 PM PST 24
Finished Jan 21 06:45:07 PM PST 24
Peak memory 254016 kb
Host smart-94f0575e-1edb-4d52-b3b6-403f49d04ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050865673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.2050865673
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.426541523
Short name T397
Test name
Test status
Simulation time 32457937 ps
CPU time 1.03 seconds
Started Jan 21 04:04:41 PM PST 24
Finished Jan 21 04:04:43 PM PST 24
Peak memory 197084 kb
Host smart-07c3d7c0-ef90-4bbc-b0f8-dcd4c1d71ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426541523 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.426541523
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1144770041
Short name T34
Test name
Test status
Simulation time 7508260357 ps
CPU time 360.69 seconds
Started Jan 21 04:04:40 PM PST 24
Finished Jan 21 04:10:43 PM PST 24
Peak memory 199068 kb
Host smart-8bc4ea74-9341-4453-b101-c264ae69913f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144770041 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.1144770041
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3303688272
Short name T821
Test name
Test status
Simulation time 328185109 ps
CPU time 15.71 seconds
Started Jan 21 04:04:40 PM PST 24
Finished Jan 21 04:04:58 PM PST 24
Peak memory 199104 kb
Host smart-b3bb45b9-7cd2-4f01-b063-5ed6499dedfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303688272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3303688272
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2192967942
Short name T717
Test name
Test status
Simulation time 39601873 ps
CPU time 0.55 seconds
Started Jan 21 04:04:46 PM PST 24
Finished Jan 21 04:04:48 PM PST 24
Peak memory 192572 kb
Host smart-ca1ca45d-2991-4a0e-af0d-d10fb018eda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192967942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2192967942
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1681631612
Short name T817
Test name
Test status
Simulation time 514576246 ps
CPU time 16 seconds
Started Jan 21 04:04:37 PM PST 24
Finished Jan 21 04:04:55 PM PST 24
Peak memory 201136 kb
Host smart-2957cefc-95b4-4115-a558-5e74839c2209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681631612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1681631612
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3250367352
Short name T294
Test name
Test status
Simulation time 4844614256 ps
CPU time 16.12 seconds
Started Jan 21 04:04:40 PM PST 24
Finished Jan 21 04:04:58 PM PST 24
Peak memory 199088 kb
Host smart-b1a8592f-a066-4279-bc5c-255afa2ab54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250367352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3250367352
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1018532794
Short name T303
Test name
Test status
Simulation time 13409299771 ps
CPU time 141.27 seconds
Started Jan 21 04:04:43 PM PST 24
Finished Jan 21 04:07:06 PM PST 24
Peak memory 199200 kb
Host smart-221a4718-0079-4ac0-ad24-e7725a5b6ecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018532794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1018532794
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2457118662
Short name T367
Test name
Test status
Simulation time 2534084245 ps
CPU time 119.05 seconds
Started Jan 21 04:04:38 PM PST 24
Finished Jan 21 04:06:38 PM PST 24
Peak memory 199140 kb
Host smart-427b4fed-5343-4ba8-95bb-47c753905459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457118662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2457118662
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3412784580
Short name T315
Test name
Test status
Simulation time 10788288997 ps
CPU time 72.15 seconds
Started Jan 21 04:04:38 PM PST 24
Finished Jan 21 04:05:52 PM PST 24
Peak memory 199152 kb
Host smart-df966ea0-872c-464b-9ada-f03f0339b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412784580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3412784580
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.345058153
Short name T677
Test name
Test status
Simulation time 409504783 ps
CPU time 2.97 seconds
Started Jan 21 05:16:50 PM PST 24
Finished Jan 21 05:16:54 PM PST 24
Peak memory 199080 kb
Host smart-0e82de16-a660-4d3c-8304-8cb557beea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345058153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.345058153
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1040994246
Short name T336
Test name
Test status
Simulation time 93008042440 ps
CPU time 899.36 seconds
Started Jan 21 04:04:39 PM PST 24
Finished Jan 21 04:19:41 PM PST 24
Peak memory 227892 kb
Host smart-0fb0a826-b879-49dd-b951-d88477a93012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040994246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1040994246
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.1348043878
Short name T301
Test name
Test status
Simulation time 752967739990 ps
CPU time 934.22 seconds
Started Jan 21 04:04:45 PM PST 24
Finished Jan 21 04:20:20 PM PST 24
Peak memory 248484 kb
Host smart-83c0659a-756b-489c-9dc3-818a978060af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348043878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.1348043878
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2671876404
Short name T190
Test name
Test status
Simulation time 295855083 ps
CPU time 0.87 seconds
Started Jan 21 04:04:41 PM PST 24
Finished Jan 21 04:04:43 PM PST 24
Peak memory 196388 kb
Host smart-fff756d7-1a65-4afb-b7e9-fd60bea05f08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671876404 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2671876404
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.473365801
Short name T3
Test name
Test status
Simulation time 58468331544 ps
CPU time 367.45 seconds
Started Jan 21 04:04:43 PM PST 24
Finished Jan 21 04:10:51 PM PST 24
Peak memory 199124 kb
Host smart-6b9e7bb4-2d23-441f-9b97-5280aa94d0b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473365801 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.hmac_test_sha_vectors.473365801
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.833814668
Short name T613
Test name
Test status
Simulation time 2956309582 ps
CPU time 34.61 seconds
Started Jan 21 04:04:37 PM PST 24
Finished Jan 21 04:05:13 PM PST 24
Peak memory 199100 kb
Host smart-82b86040-e4a3-4f94-a34a-deeeadceb708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833814668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.833814668
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4124653206
Short name T565
Test name
Test status
Simulation time 42364714 ps
CPU time 0.6 seconds
Started Jan 21 04:04:55 PM PST 24
Finished Jan 21 04:04:57 PM PST 24
Peak memory 192508 kb
Host smart-50fcefe1-add5-4a9f-9037-1f5eadbfc683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124653206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4124653206
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1984014655
Short name T844
Test name
Test status
Simulation time 1310494548 ps
CPU time 39.59 seconds
Started Jan 21 04:04:46 PM PST 24
Finished Jan 21 04:05:26 PM PST 24
Peak memory 207344 kb
Host smart-9d540640-241a-48d0-b094-a3af6d136b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984014655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1984014655
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.171001788
Short name T753
Test name
Test status
Simulation time 3623432275 ps
CPU time 34.04 seconds
Started Jan 21 04:04:47 PM PST 24
Finished Jan 21 04:05:21 PM PST 24
Peak memory 199384 kb
Host smart-27236ec4-1c07-40d0-9ef0-9e03dda2e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171001788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.171001788
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3756152599
Short name T1
Test name
Test status
Simulation time 2538931174 ps
CPU time 62.87 seconds
Started Jan 21 04:04:44 PM PST 24
Finished Jan 21 04:05:48 PM PST 24
Peak memory 199200 kb
Host smart-aeea685a-1ee5-4ea5-ae9d-652781176b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756152599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3756152599
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2438022938
Short name T455
Test name
Test status
Simulation time 3845784024 ps
CPU time 60.07 seconds
Started Jan 21 04:04:50 PM PST 24
Finished Jan 21 04:05:52 PM PST 24
Peak memory 199044 kb
Host smart-a5910dbb-ef1f-4521-ba95-f93a95e90deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438022938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2438022938
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1223174706
Short name T389
Test name
Test status
Simulation time 9461613479 ps
CPU time 40.37 seconds
Started Jan 21 04:04:44 PM PST 24
Finished Jan 21 04:05:26 PM PST 24
Peak memory 199180 kb
Host smart-6c58e185-2d27-4b66-b5cf-d8d5b52e00bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223174706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1223174706
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3583969214
Short name T788
Test name
Test status
Simulation time 387694543 ps
CPU time 1.45 seconds
Started Jan 21 04:04:52 PM PST 24
Finished Jan 21 04:04:54 PM PST 24
Peak memory 198600 kb
Host smart-7bd7c361-ee8c-4929-8615-cad307a8e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583969214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3583969214
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2049241551
Short name T749
Test name
Test status
Simulation time 52030952030 ps
CPU time 935.96 seconds
Started Jan 21 04:04:54 PM PST 24
Finished Jan 21 04:20:31 PM PST 24
Peak memory 214564 kb
Host smart-762bf7fc-0b8c-43b5-bebe-e03646fb9684
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049241551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2049241551
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2961236540
Short name T287
Test name
Test status
Simulation time 193132218559 ps
CPU time 2037.3 seconds
Started Jan 21 04:04:52 PM PST 24
Finished Jan 21 04:38:51 PM PST 24
Peak memory 226068 kb
Host smart-f8863f01-6300-41b4-a0d0-5f3febbbf4e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961236540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.2961236540
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1055370521
Short name T381
Test name
Test status
Simulation time 70863944 ps
CPU time 1.23 seconds
Started Jan 21 04:04:46 PM PST 24
Finished Jan 21 04:04:48 PM PST 24
Peak memory 197968 kb
Host smart-073e732e-2ca4-49c7-8179-98a9951d8b0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055370521 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1055370521
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3183746660
Short name T318
Test name
Test status
Simulation time 26890071243 ps
CPU time 439.33 seconds
Started Jan 21 04:04:46 PM PST 24
Finished Jan 21 04:12:06 PM PST 24
Peak memory 199136 kb
Host smart-49d9dcbe-863f-421a-ab93-f3f12e9af413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183746660 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3183746660
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1652516051
Short name T813
Test name
Test status
Simulation time 4786309514 ps
CPU time 82.43 seconds
Started Jan 21 04:04:51 PM PST 24
Finished Jan 21 04:06:15 PM PST 24
Peak memory 199148 kb
Host smart-8a555004-a728-491a-ac12-4241733899ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652516051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1652516051
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.558798571
Short name T317
Test name
Test status
Simulation time 52061334 ps
CPU time 0.62 seconds
Started Jan 21 04:05:00 PM PST 24
Finished Jan 21 04:05:01 PM PST 24
Peak memory 194572 kb
Host smart-e97c12f9-6bff-41b2-83f5-afbf700ab547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558798571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.558798571
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4094216601
Short name T631
Test name
Test status
Simulation time 3259222673 ps
CPU time 51.71 seconds
Started Jan 21 04:54:30 PM PST 24
Finished Jan 21 04:55:23 PM PST 24
Peak memory 223772 kb
Host smart-c53fda0d-05b8-4fdd-9490-876180672b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094216601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4094216601
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3530100246
Short name T2
Test name
Test status
Simulation time 905870389 ps
CPU time 41.78 seconds
Started Jan 21 04:26:56 PM PST 24
Finished Jan 21 04:27:39 PM PST 24
Peak memory 199116 kb
Host smart-030fd1ee-d33d-410f-a0e0-d252bc579bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530100246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3530100246
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.660410369
Short name T615
Test name
Test status
Simulation time 2228969698 ps
CPU time 115.5 seconds
Started Jan 21 04:04:52 PM PST 24
Finished Jan 21 04:06:49 PM PST 24
Peak memory 199112 kb
Host smart-6c9be160-9f1b-43a0-87c0-e136e8e741f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660410369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.660410369
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3101329451
Short name T820
Test name
Test status
Simulation time 10010631459 ps
CPU time 120.89 seconds
Started Jan 21 04:26:21 PM PST 24
Finished Jan 21 04:28:25 PM PST 24
Peak memory 199164 kb
Host smart-0e2116e1-eb89-4ded-999c-70832d8cb7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101329451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3101329451
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2235816459
Short name T562
Test name
Test status
Simulation time 996330954 ps
CPU time 51.94 seconds
Started Jan 21 04:04:52 PM PST 24
Finished Jan 21 04:05:45 PM PST 24
Peak memory 199128 kb
Host smart-118352c0-3c89-401c-858e-efc7a1f68c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235816459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2235816459
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.538320374
Short name T491
Test name
Test status
Simulation time 707699478 ps
CPU time 1.5 seconds
Started Jan 21 04:32:14 PM PST 24
Finished Jan 21 04:32:21 PM PST 24
Peak memory 197668 kb
Host smart-5a0759e4-2b91-4727-8b4e-9f473697ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538320374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.538320374
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2072655941
Short name T593
Test name
Test status
Simulation time 79811637091 ps
CPU time 968.25 seconds
Started Jan 21 04:05:01 PM PST 24
Finished Jan 21 04:21:10 PM PST 24
Peak memory 199208 kb
Host smart-4b7bc65e-1bfd-4e19-8452-1027d4f6ca05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072655941 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2072655941
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.1296050767
Short name T442
Test name
Test status
Simulation time 50729777027 ps
CPU time 838.19 seconds
Started Jan 21 04:05:01 PM PST 24
Finished Jan 21 04:19:00 PM PST 24
Peak memory 248496 kb
Host smart-18608b27-6f65-42c0-aa5a-a0f0a14e9cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296050767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.1296050767
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.4006226675
Short name T447
Test name
Test status
Simulation time 32488747 ps
CPU time 1.22 seconds
Started Jan 21 04:05:06 PM PST 24
Finished Jan 21 04:05:10 PM PST 24
Peak memory 198428 kb
Host smart-efd1a227-be76-455b-9473-fa48b44fd034
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006226675 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.4006226675
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1996193200
Short name T787
Test name
Test status
Simulation time 27432643962 ps
CPU time 420.28 seconds
Started Jan 21 04:05:03 PM PST 24
Finished Jan 21 04:12:06 PM PST 24
Peak memory 199196 kb
Host smart-3063c043-1284-4b29-b89d-362d8c100c6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996193200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.1996193200
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1115556638
Short name T470
Test name
Test status
Simulation time 3455570307 ps
CPU time 61.88 seconds
Started Jan 21 04:35:33 PM PST 24
Finished Jan 21 04:36:36 PM PST 24
Peak memory 199396 kb
Host smart-c86eea18-b03c-4900-ae9d-120ac223f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115556638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1115556638
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.35427639
Short name T706
Test name
Test status
Simulation time 39386168 ps
CPU time 0.57 seconds
Started Jan 21 04:05:16 PM PST 24
Finished Jan 21 04:05:27 PM PST 24
Peak memory 192528 kb
Host smart-92ad0cb2-816e-47ba-8e6d-777e07824af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.35427639
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2174188208
Short name T654
Test name
Test status
Simulation time 244112289 ps
CPU time 7.14 seconds
Started Jan 21 04:05:00 PM PST 24
Finished Jan 21 04:05:08 PM PST 24
Peak memory 207304 kb
Host smart-0d3a9b36-49b9-4eb5-8260-1c692ca2e46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174188208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2174188208
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.149823651
Short name T243
Test name
Test status
Simulation time 3450282365 ps
CPU time 16.7 seconds
Started Jan 21 04:05:01 PM PST 24
Finished Jan 21 04:05:18 PM PST 24
Peak memory 199152 kb
Host smart-fc6d3c47-d0ca-44f2-b4d4-55741709f7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149823651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.149823651
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3142116503
Short name T563
Test name
Test status
Simulation time 910012477 ps
CPU time 11.86 seconds
Started Jan 21 04:05:07 PM PST 24
Finished Jan 21 04:05:21 PM PST 24
Peak memory 199288 kb
Host smart-f8a22303-adb4-4228-87dd-0cd5f2de67b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142116503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3142116503
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.324023326
Short name T257
Test name
Test status
Simulation time 3675167371 ps
CPU time 179.12 seconds
Started Jan 21 04:05:03 PM PST 24
Finished Jan 21 04:08:05 PM PST 24
Peak memory 199212 kb
Host smart-dabb66a1-e2ae-4571-88c9-ab042962f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324023326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.324023326
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.40398425
Short name T328
Test name
Test status
Simulation time 8841468289 ps
CPU time 41.44 seconds
Started Jan 21 04:05:02 PM PST 24
Finished Jan 21 04:05:46 PM PST 24
Peak memory 199144 kb
Host smart-7bb0b664-8119-4438-b8a8-ef292740433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40398425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.40398425
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2369252388
Short name T707
Test name
Test status
Simulation time 46230974 ps
CPU time 1.37 seconds
Started Jan 21 04:05:07 PM PST 24
Finished Jan 21 04:05:10 PM PST 24
Peak memory 198928 kb
Host smart-91f5b595-6e96-4742-8f4b-ea9cce6b7108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369252388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2369252388
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.838316113
Short name T575
Test name
Test status
Simulation time 108946739651 ps
CPU time 669.44 seconds
Started Jan 21 04:05:13 PM PST 24
Finished Jan 21 04:16:25 PM PST 24
Peak memory 199212 kb
Host smart-65906dde-56da-41ac-a4eb-db427257e890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838316113 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.838316113
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.510182079
Short name T648
Test name
Test status
Simulation time 174121364905 ps
CPU time 2185.98 seconds
Started Jan 21 04:05:14 PM PST 24
Finished Jan 21 04:41:47 PM PST 24
Peak memory 236256 kb
Host smart-28e06c07-007f-49b4-bb48-3ac09fac5b7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510182079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.510182079
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.904940771
Short name T213
Test name
Test status
Simulation time 127574854 ps
CPU time 1.16 seconds
Started Jan 21 04:05:14 PM PST 24
Finished Jan 21 04:05:18 PM PST 24
Peak memory 196588 kb
Host smart-b07262b5-7e96-41ac-8925-73cd2398eca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904940771 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.904940771
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.132880690
Short name T302
Test name
Test status
Simulation time 77943100410 ps
CPU time 498.53 seconds
Started Jan 21 04:05:16 PM PST 24
Finished Jan 21 04:13:43 PM PST 24
Peak memory 199132 kb
Host smart-f1520aaf-5d54-483e-b0e8-d3bb81fb26d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132880690 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.hmac_test_sha_vectors.132880690
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1615010162
Short name T570
Test name
Test status
Simulation time 5088208831 ps
CPU time 85.02 seconds
Started Jan 21 04:05:07 PM PST 24
Finished Jan 21 04:06:34 PM PST 24
Peak memory 199200 kb
Host smart-e4b12538-5a84-44d3-9278-88c0bfa9a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615010162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1615010162
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.614537846
Short name T229
Test name
Test status
Simulation time 13423744 ps
CPU time 0.56 seconds
Started Jan 21 04:05:17 PM PST 24
Finished Jan 21 04:05:28 PM PST 24
Peak memory 192548 kb
Host smart-47a181d7-1e2b-4efb-b04e-bd2f35c26c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614537846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.614537846
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1759613456
Short name T378
Test name
Test status
Simulation time 3806217101 ps
CPU time 30.01 seconds
Started Jan 21 04:05:18 PM PST 24
Finished Jan 21 04:05:58 PM PST 24
Peak memory 211488 kb
Host smart-b9ce8eac-a5e7-494e-b05f-3b0120508489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759613456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1759613456
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1705421880
Short name T265
Test name
Test status
Simulation time 1753027685 ps
CPU time 24.64 seconds
Started Jan 21 04:05:16 PM PST 24
Finished Jan 21 04:05:51 PM PST 24
Peak memory 199108 kb
Host smart-66cf373b-09c0-4c16-8246-55fe6c3e2881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705421880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1705421880
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3485512686
Short name T756
Test name
Test status
Simulation time 1619212382 ps
CPU time 79.76 seconds
Started Jan 21 04:05:17 PM PST 24
Finished Jan 21 04:06:47 PM PST 24
Peak memory 199012 kb
Host smart-f8fa186c-8a09-4c91-a45a-b371df10d466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485512686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3485512686
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.51248927
Short name T405
Test name
Test status
Simulation time 56185313531 ps
CPU time 83.66 seconds
Started Jan 21 04:05:12 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 199188 kb
Host smart-6c0ea922-29a3-4ccc-9f4b-21a4e6dc52d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51248927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.51248927
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1299637278
Short name T126
Test name
Test status
Simulation time 1599208711 ps
CPU time 79.59 seconds
Started Jan 21 04:05:15 PM PST 24
Finished Jan 21 04:06:43 PM PST 24
Peak memory 199052 kb
Host smart-0eeae676-c14b-4246-9e34-8e9448f04544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299637278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1299637278
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1084317050
Short name T458
Test name
Test status
Simulation time 446636433 ps
CPU time 4.29 seconds
Started Jan 21 04:05:13 PM PST 24
Finished Jan 21 04:05:19 PM PST 24
Peak memory 198880 kb
Host smart-0a9ee4f3-eacd-45ca-b66e-7b278215def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084317050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1084317050
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1078676727
Short name T268
Test name
Test status
Simulation time 3198331076 ps
CPU time 151.02 seconds
Started Jan 21 04:05:15 PM PST 24
Finished Jan 21 04:07:55 PM PST 24
Peak memory 199140 kb
Host smart-c9aa976c-109b-41c8-8fb2-b49813a94632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078676727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1078676727
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1771000719
Short name T810
Test name
Test status
Simulation time 84966368786 ps
CPU time 1374.57 seconds
Started Jan 21 04:05:15 PM PST 24
Finished Jan 21 04:28:18 PM PST 24
Peak memory 240852 kb
Host smart-d5186d2c-dde8-46b8-8f99-df1bce482a98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771000719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.1771000719
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4094732318
Short name T723
Test name
Test status
Simulation time 206255801 ps
CPU time 1.17 seconds
Started Jan 21 04:05:14 PM PST 24
Finished Jan 21 04:05:22 PM PST 24
Peak memory 198200 kb
Host smart-a50ef83b-ddcd-421b-9bd8-8e5fcf5b921c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094732318 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4094732318
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.384091517
Short name T33
Test name
Test status
Simulation time 9213506258 ps
CPU time 378.25 seconds
Started Jan 21 04:05:16 PM PST 24
Finished Jan 21 04:11:42 PM PST 24
Peak memory 199084 kb
Host smart-64cf0fdd-5636-405e-a4b5-fcc43aa9ebb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384091517 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.384091517
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3247218895
Short name T578
Test name
Test status
Simulation time 546644650 ps
CPU time 6.86 seconds
Started Jan 21 04:05:16 PM PST 24
Finished Jan 21 04:05:30 PM PST 24
Peak memory 199076 kb
Host smart-5e6d3836-65e5-44f6-ba3c-feea23cf74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247218895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3247218895
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3811682676
Short name T725
Test name
Test status
Simulation time 23143759 ps
CPU time 0.55 seconds
Started Jan 21 04:05:27 PM PST 24
Finished Jan 21 04:05:37 PM PST 24
Peak memory 192752 kb
Host smart-7098dc3b-c7bc-4137-b223-e1c8ec419c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811682676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3811682676
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.37937421
Short name T264
Test name
Test status
Simulation time 753962532 ps
CPU time 22.58 seconds
Started Jan 21 04:05:21 PM PST 24
Finished Jan 21 04:05:50 PM PST 24
Peak memory 207332 kb
Host smart-4646bddc-e48e-4093-b3fc-e9f998ca5c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37937421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.37937421
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.355075440
Short name T9
Test name
Test status
Simulation time 1298492201 ps
CPU time 58.17 seconds
Started Jan 21 04:05:20 PM PST 24
Finished Jan 21 04:06:26 PM PST 24
Peak memory 199064 kb
Host smart-03bcc180-811c-4af1-ba15-0a08276fb7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355075440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.355075440
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.311528403
Short name T368
Test name
Test status
Simulation time 594153659 ps
CPU time 28.6 seconds
Started Jan 21 04:05:20 PM PST 24
Finished Jan 21 04:05:57 PM PST 24
Peak memory 199080 kb
Host smart-50dd535b-7137-477b-a704-e544ca264126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311528403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.311528403
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1544367631
Short name T636
Test name
Test status
Simulation time 19843171790 ps
CPU time 152.26 seconds
Started Jan 21 04:05:21 PM PST 24
Finished Jan 21 04:08:00 PM PST 24
Peak memory 199216 kb
Host smart-d8296706-8849-407b-a5a0-dbca0493d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544367631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1544367631
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.182180493
Short name T509
Test name
Test status
Simulation time 2507363148 ps
CPU time 44.99 seconds
Started Jan 21 04:05:24 PM PST 24
Finished Jan 21 04:06:15 PM PST 24
Peak memory 199116 kb
Host smart-ba93e41c-53d7-4d2b-ba43-a29554fb4f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182180493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.182180493
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.579817188
Short name T285
Test name
Test status
Simulation time 493564296 ps
CPU time 1.69 seconds
Started Jan 21 04:05:23 PM PST 24
Finished Jan 21 04:05:30 PM PST 24
Peak memory 198780 kb
Host smart-12786314-9bdb-457d-8447-e0f129e9fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579817188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.579817188
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4286096495
Short name T789
Test name
Test status
Simulation time 125316601013 ps
CPU time 2202.06 seconds
Started Jan 21 04:05:19 PM PST 24
Finished Jan 21 04:42:10 PM PST 24
Peak memory 241052 kb
Host smart-acd5e1bc-b152-4409-b079-e8f065481c53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286096495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4286096495
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.2426143510
Short name T551
Test name
Test status
Simulation time 44329805286 ps
CPU time 808.82 seconds
Started Jan 21 04:05:21 PM PST 24
Finished Jan 21 04:18:57 PM PST 24
Peak memory 230644 kb
Host smart-7ac8e419-3466-4d8d-8920-7be52e2b0cbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426143510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.2426143510
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.861860741
Short name T609
Test name
Test status
Simulation time 267322445 ps
CPU time 0.95 seconds
Started Jan 21 04:05:20 PM PST 24
Finished Jan 21 04:05:29 PM PST 24
Peak memory 196756 kb
Host smart-826b8844-b17f-464b-a71d-fde77c51ae0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861860741 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.861860741
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.4284992908
Short name T647
Test name
Test status
Simulation time 74160183929 ps
CPU time 530.39 seconds
Started Jan 21 04:26:20 PM PST 24
Finished Jan 21 04:35:13 PM PST 24
Peak memory 199132 kb
Host smart-94ab25bb-5b51-4682-8f0f-d492f30d3e18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284992908 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.4284992908
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2231505178
Short name T242
Test name
Test status
Simulation time 2766094662 ps
CPU time 18.63 seconds
Started Jan 21 04:05:20 PM PST 24
Finished Jan 21 04:05:47 PM PST 24
Peak memory 199052 kb
Host smart-5d68af15-760b-48c7-b9ed-3b9994dfd50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231505178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2231505178
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2955645118
Short name T605
Test name
Test status
Simulation time 12458759 ps
CPU time 0.58 seconds
Started Jan 21 04:02:04 PM PST 24
Finished Jan 21 04:02:09 PM PST 24
Peak memory 192512 kb
Host smart-beb0961c-c252-405a-ba48-bac9e7f22286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955645118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2955645118
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4210528813
Short name T448
Test name
Test status
Simulation time 2413823729 ps
CPU time 20.23 seconds
Started Jan 21 04:01:44 PM PST 24
Finished Jan 21 04:02:08 PM PST 24
Peak memory 217636 kb
Host smart-b4d0b72f-de8d-46a8-ab93-cb65176a6c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210528813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4210528813
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1971913821
Short name T721
Test name
Test status
Simulation time 294129330 ps
CPU time 6.4 seconds
Started Jan 21 04:01:52 PM PST 24
Finished Jan 21 04:02:00 PM PST 24
Peak memory 199108 kb
Host smart-a44c4f5b-2d0a-43bb-a412-5c8788bdc4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971913821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1971913821
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2064705732
Short name T680
Test name
Test status
Simulation time 3935812372 ps
CPU time 125.32 seconds
Started Jan 21 05:10:47 PM PST 24
Finished Jan 21 05:12:54 PM PST 24
Peak memory 199180 kb
Host smart-45088845-b5a0-4f96-800a-d2274ff96dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064705732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2064705732
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1302061463
Short name T249
Test name
Test status
Simulation time 2540313525 ps
CPU time 22.78 seconds
Started Jan 21 07:32:11 PM PST 24
Finished Jan 21 07:32:36 PM PST 24
Peak memory 199184 kb
Host smart-c60e4b63-2ada-4c81-a8ad-2e7beb5d51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302061463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1302061463
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2703175048
Short name T531
Test name
Test status
Simulation time 1393030732 ps
CPU time 81.35 seconds
Started Jan 21 04:54:58 PM PST 24
Finished Jan 21 04:56:20 PM PST 24
Peak memory 199164 kb
Host smart-a333b377-bcb5-4c69-becb-8e2401299cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703175048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2703175048
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3506002548
Short name T53
Test name
Test status
Simulation time 73652719 ps
CPU time 0.88 seconds
Started Jan 21 04:01:57 PM PST 24
Finished Jan 21 04:02:03 PM PST 24
Peak memory 215876 kb
Host smart-425ff960-e5fb-4a6b-9dae-d0510eff2eb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506002548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3506002548
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2901392258
Short name T55
Test name
Test status
Simulation time 285050581 ps
CPU time 3.2 seconds
Started Jan 21 04:01:46 PM PST 24
Finished Jan 21 04:01:51 PM PST 24
Peak memory 198820 kb
Host smart-7db79720-9018-424a-a752-6ef51c5aefc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901392258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2901392258
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1823210691
Short name T549
Test name
Test status
Simulation time 62340456249 ps
CPU time 1074.06 seconds
Started Jan 21 04:01:56 PM PST 24
Finished Jan 21 04:19:56 PM PST 24
Peak memory 240152 kb
Host smart-a0ff18c9-aeb6-4246-a789-62a8731ae970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823210691 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1823210691
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3111188711
Short name T497
Test name
Test status
Simulation time 293878696216 ps
CPU time 1565.69 seconds
Started Jan 21 04:02:00 PM PST 24
Finished Jan 21 04:28:10 PM PST 24
Peak memory 232144 kb
Host smart-ddce1b32-5c2b-41f0-8e41-0960932adf0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111188711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3111188711
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3351694686
Short name T826
Test name
Test status
Simulation time 54246340 ps
CPU time 1 seconds
Started Jan 21 05:29:48 PM PST 24
Finished Jan 21 05:29:50 PM PST 24
Peak memory 197476 kb
Host smart-7ccea59f-9f6a-4eb8-bd5d-6995deafb3af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351694686 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3351694686
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1465275079
Short name T664
Test name
Test status
Simulation time 7313759611 ps
CPU time 67.26 seconds
Started Jan 21 04:01:49 PM PST 24
Finished Jan 21 04:02:59 PM PST 24
Peak memory 199208 kb
Host smart-ed7aad13-c9ca-42f3-af4d-a623eee074f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465275079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1465275079
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.996230205
Short name T48
Test name
Test status
Simulation time 67051153 ps
CPU time 0.55 seconds
Started Jan 21 04:05:25 PM PST 24
Finished Jan 21 04:05:33 PM PST 24
Peak memory 192620 kb
Host smart-04133683-394f-43b7-82d8-64a8c0ec3e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996230205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.996230205
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3633070110
Short name T528
Test name
Test status
Simulation time 1227731254 ps
CPU time 33.12 seconds
Started Jan 21 04:05:28 PM PST 24
Finished Jan 21 04:06:12 PM PST 24
Peak memory 199060 kb
Host smart-b0ed6914-07fc-43e6-bb6e-8cba2e020d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633070110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3633070110
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1462088499
Short name T251
Test name
Test status
Simulation time 1170019247 ps
CPU time 12.57 seconds
Started Jan 21 04:05:27 PM PST 24
Finished Jan 21 04:05:48 PM PST 24
Peak memory 199084 kb
Host smart-a74997b3-83d9-402f-a420-def6666f54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462088499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1462088499
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1410379148
Short name T722
Test name
Test status
Simulation time 1954422909 ps
CPU time 96.88 seconds
Started Jan 21 04:05:29 PM PST 24
Finished Jan 21 04:07:16 PM PST 24
Peak memory 199084 kb
Host smart-a4565355-928d-4b5b-9ff5-bf8da33189d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410379148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1410379148
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2834057559
Short name T715
Test name
Test status
Simulation time 55879627440 ps
CPU time 163.07 seconds
Started Jan 21 04:05:26 PM PST 24
Finished Jan 21 04:08:16 PM PST 24
Peak memory 199252 kb
Host smart-e96e9b7a-08bf-4f67-9c4e-5b50d2546000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834057559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2834057559
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3693345885
Short name T548
Test name
Test status
Simulation time 162954841 ps
CPU time 8.34 seconds
Started Jan 21 04:05:25 PM PST 24
Finished Jan 21 04:05:41 PM PST 24
Peak memory 199112 kb
Host smart-b2782936-3e78-4f28-97f2-5a5ef94f1ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693345885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3693345885
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3241509770
Short name T225
Test name
Test status
Simulation time 373370874 ps
CPU time 1.48 seconds
Started Jan 21 04:05:25 PM PST 24
Finished Jan 21 04:05:34 PM PST 24
Peak memory 198860 kb
Host smart-ebd6ceca-3cdc-48ff-bb6c-0d4539e4af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241509770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3241509770
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.4126798615
Short name T118
Test name
Test status
Simulation time 29647551047 ps
CPU time 1504.85 seconds
Started Jan 21 04:05:24 PM PST 24
Finished Jan 21 04:30:35 PM PST 24
Peak memory 207372 kb
Host smart-e2738c2c-94a7-44ac-b7d5-18305a86ecf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126798615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.4126798615
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.864461780
Short name T255
Test name
Test status
Simulation time 26038592588 ps
CPU time 1332.51 seconds
Started Jan 21 04:05:24 PM PST 24
Finished Jan 21 04:27:44 PM PST 24
Peak memory 232060 kb
Host smart-bbbcfcfc-c7ab-45f4-8bde-aeaf2c4b4a29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864461780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.864461780
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.646012192
Short name T729
Test name
Test status
Simulation time 60039321 ps
CPU time 0.96 seconds
Started Jan 21 04:05:26 PM PST 24
Finished Jan 21 04:05:34 PM PST 24
Peak memory 196900 kb
Host smart-39223502-5644-4c3e-b5c8-7f592428b98b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646012192 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.646012192
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2306529188
Short name T607
Test name
Test status
Simulation time 177743085479 ps
CPU time 508.22 seconds
Started Jan 21 04:05:27 PM PST 24
Finished Jan 21 04:14:03 PM PST 24
Peak memory 199100 kb
Host smart-f817f960-9d9b-46c8-8eff-0053a77d1cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306529188 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.2306529188
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.520561755
Short name T212
Test name
Test status
Simulation time 4797874687 ps
CPU time 48.07 seconds
Started Jan 21 04:05:26 PM PST 24
Finished Jan 21 04:06:22 PM PST 24
Peak memory 199168 kb
Host smart-8a088c28-4688-48ad-a59b-014c56c66981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520561755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.520561755
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4132647433
Short name T452
Test name
Test status
Simulation time 76439880 ps
CPU time 2.45 seconds
Started Jan 21 04:05:27 PM PST 24
Finished Jan 21 04:05:39 PM PST 24
Peak memory 198964 kb
Host smart-27ce16bd-af59-4d48-a6c2-0a1be223cc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132647433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4132647433
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2022748490
Short name T524
Test name
Test status
Simulation time 563523154 ps
CPU time 10.53 seconds
Started Jan 21 04:05:27 PM PST 24
Finished Jan 21 04:05:47 PM PST 24
Peak memory 199080 kb
Host smart-71478e94-7a31-4e1c-b414-cba7cbfa33e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022748490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2022748490
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.822420783
Short name T261
Test name
Test status
Simulation time 4221029241 ps
CPU time 104.75 seconds
Started Jan 21 04:05:29 PM PST 24
Finished Jan 21 04:07:24 PM PST 24
Peak memory 199144 kb
Host smart-536a9b42-a583-40db-bfcb-6fc2de65bb81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822420783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.822420783
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3678912989
Short name T671
Test name
Test status
Simulation time 7601462136 ps
CPU time 105.26 seconds
Started Jan 21 04:05:30 PM PST 24
Finished Jan 21 04:07:25 PM PST 24
Peak memory 199168 kb
Host smart-6a8963cd-f131-40bf-87a0-a2ecf74b21f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678912989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3678912989
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2061595968
Short name T208
Test name
Test status
Simulation time 17558341805 ps
CPU time 45.64 seconds
Started Jan 21 04:05:29 PM PST 24
Finished Jan 21 04:06:24 PM PST 24
Peak memory 199144 kb
Host smart-0f4377a5-7c59-4822-8172-93fb1d2fda91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061595968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2061595968
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2560999887
Short name T385
Test name
Test status
Simulation time 440018973 ps
CPU time 2.01 seconds
Started Jan 21 04:05:26 PM PST 24
Finished Jan 21 04:05:35 PM PST 24
Peak memory 198884 kb
Host smart-eda506f3-5534-4e94-bf1b-27df4961f64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560999887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2560999887
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.474506825
Short name T232
Test name
Test status
Simulation time 17845352320 ps
CPU time 335.68 seconds
Started Jan 21 04:36:19 PM PST 24
Finished Jan 21 04:41:56 PM PST 24
Peak memory 199264 kb
Host smart-5c14cd44-7e0f-40c2-b66e-9db2105478c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474506825 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.474506825
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.729222264
Short name T701
Test name
Test status
Simulation time 15014180387 ps
CPU time 300.18 seconds
Started Jan 21 04:05:30 PM PST 24
Finished Jan 21 04:10:40 PM PST 24
Peak memory 242284 kb
Host smart-844149d0-d44e-4a2e-8986-24da59369620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729222264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.729222264
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2434380203
Short name T481
Test name
Test status
Simulation time 52233992 ps
CPU time 1.06 seconds
Started Jan 21 05:31:46 PM PST 24
Finished Jan 21 05:31:48 PM PST 24
Peak memory 196884 kb
Host smart-2d266882-39b2-4e2f-a228-473d9a701f7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434380203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2434380203
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2608024983
Short name T688
Test name
Test status
Simulation time 68701398495 ps
CPU time 406.33 seconds
Started Jan 21 04:05:30 PM PST 24
Finished Jan 21 04:12:26 PM PST 24
Peak memory 199100 kb
Host smart-4f48588a-4908-42df-ac7e-2c6385b989ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608024983 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.2608024983
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2638875763
Short name T658
Test name
Test status
Simulation time 379284987 ps
CPU time 16.5 seconds
Started Jan 21 04:05:31 PM PST 24
Finished Jan 21 04:05:56 PM PST 24
Peak memory 199108 kb
Host smart-5af96b41-ffae-4a9a-85dd-92a1610b8b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638875763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2638875763
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1121880448
Short name T227
Test name
Test status
Simulation time 71102102 ps
CPU time 0.55 seconds
Started Jan 21 04:05:41 PM PST 24
Finished Jan 21 04:05:44 PM PST 24
Peak memory 193548 kb
Host smart-5374d3e5-87d4-44c8-9231-caac3e5b19c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121880448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1121880448
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.322740381
Short name T797
Test name
Test status
Simulation time 438930796 ps
CPU time 16.6 seconds
Started Jan 21 05:20:24 PM PST 24
Finished Jan 21 05:20:41 PM PST 24
Peak memory 207312 kb
Host smart-f9c15e69-92a2-4766-abc8-a5330dc308e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322740381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.322740381
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2780831901
Short name T805
Test name
Test status
Simulation time 462823821 ps
CPU time 9.07 seconds
Started Jan 21 04:05:45 PM PST 24
Finished Jan 21 04:05:54 PM PST 24
Peak memory 198912 kb
Host smart-0826eada-095f-442d-a967-df1071eca5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780831901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2780831901
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2729318113
Short name T379
Test name
Test status
Simulation time 72951708 ps
CPU time 4.16 seconds
Started Jan 21 04:51:58 PM PST 24
Finished Jan 21 04:52:03 PM PST 24
Peak memory 199036 kb
Host smart-87e6d6a2-dfb9-4427-9373-aca38fe4ca50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729318113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2729318113
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1930393830
Short name T672
Test name
Test status
Simulation time 78166966279 ps
CPU time 231.44 seconds
Started Jan 21 04:33:41 PM PST 24
Finished Jan 21 04:37:34 PM PST 24
Peak memory 199156 kb
Host smart-3fb01d87-0379-495c-8a6c-192a647eb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930393830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1930393830
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4092428731
Short name T762
Test name
Test status
Simulation time 3994543948 ps
CPU time 19.22 seconds
Started Jan 21 07:10:25 PM PST 24
Finished Jan 21 07:10:45 PM PST 24
Peak memory 199164 kb
Host smart-db1328c3-4896-4042-affd-6774cbad28dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092428731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4092428731
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1671200934
Short name T785
Test name
Test status
Simulation time 417528240 ps
CPU time 4.48 seconds
Started Jan 21 04:05:33 PM PST 24
Finished Jan 21 04:05:45 PM PST 24
Peak memory 199080 kb
Host smart-a252f276-f49c-4599-b538-87b12c3baaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671200934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1671200934
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1385530015
Short name T440
Test name
Test status
Simulation time 302167820796 ps
CPU time 1327.26 seconds
Started Jan 21 04:26:17 PM PST 24
Finished Jan 21 04:48:26 PM PST 24
Peak memory 199184 kb
Host smart-28718fdf-6a75-416d-a009-5bae42e4583d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385530015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1385530015
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.811678200
Short name T400
Test name
Test status
Simulation time 55825750604 ps
CPU time 2592.41 seconds
Started Jan 21 04:05:41 PM PST 24
Finished Jan 21 04:48:56 PM PST 24
Peak memory 248472 kb
Host smart-6dda5796-14b2-4574-ba88-df69c18ed3c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811678200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.811678200
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3748669035
Short name T403
Test name
Test status
Simulation time 71855703 ps
CPU time 1.21 seconds
Started Jan 21 04:05:45 PM PST 24
Finished Jan 21 04:05:47 PM PST 24
Peak memory 196540 kb
Host smart-7d430468-585e-478e-990a-acd3249b5143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748669035 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3748669035
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2001103152
Short name T675
Test name
Test status
Simulation time 34653363946 ps
CPU time 412.04 seconds
Started Jan 21 04:05:37 PM PST 24
Finished Jan 21 04:12:35 PM PST 24
Peak memory 199060 kb
Host smart-81103686-676f-408f-a6c6-93ef89b26ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001103152 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.2001103152
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3684904083
Short name T750
Test name
Test status
Simulation time 1577177318 ps
CPU time 74.11 seconds
Started Jan 21 04:05:40 PM PST 24
Finished Jan 21 04:06:57 PM PST 24
Peak memory 199132 kb
Host smart-b5ef52c0-b56d-48ef-9e46-1e15063455ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684904083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3684904083
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3124155694
Short name T553
Test name
Test status
Simulation time 10495645 ps
CPU time 0.55 seconds
Started Jan 21 04:05:47 PM PST 24
Finished Jan 21 04:05:51 PM PST 24
Peak memory 192568 kb
Host smart-dc456c23-7577-457e-9c86-1e78da896621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124155694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3124155694
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2818496198
Short name T231
Test name
Test status
Simulation time 15036443180 ps
CPU time 37.15 seconds
Started Jan 21 04:23:01 PM PST 24
Finished Jan 21 04:23:43 PM PST 24
Peak memory 211040 kb
Host smart-4d8916cf-7177-4dc9-90b3-cab14e514da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818496198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2818496198
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.350167162
Short name T384
Test name
Test status
Simulation time 21552324902 ps
CPU time 44.45 seconds
Started Jan 21 04:05:36 PM PST 24
Finished Jan 21 04:06:26 PM PST 24
Peak memory 199104 kb
Host smart-1deda462-3fce-408f-bab8-c5ce8c5d8693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350167162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.350167162
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1859212488
Short name T195
Test name
Test status
Simulation time 2422893544 ps
CPU time 34.99 seconds
Started Jan 21 06:02:26 PM PST 24
Finished Jan 21 06:03:02 PM PST 24
Peak memory 199240 kb
Host smart-e6de4407-44fb-41b2-8d27-302a2d56c06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859212488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1859212488
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1657820217
Short name T461
Test name
Test status
Simulation time 106316171256 ps
CPU time 119.04 seconds
Started Jan 21 04:05:49 PM PST 24
Finished Jan 21 04:07:51 PM PST 24
Peak memory 199112 kb
Host smart-ee8cf9b1-261c-4666-bb9a-255ae9482736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657820217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1657820217
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2704495591
Short name T330
Test name
Test status
Simulation time 1645501876 ps
CPU time 26.73 seconds
Started Jan 21 04:05:37 PM PST 24
Finished Jan 21 04:06:09 PM PST 24
Peak memory 199096 kb
Host smart-2bf7bdb7-4baa-427c-9677-92498d0ed4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704495591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2704495591
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4061675400
Short name T394
Test name
Test status
Simulation time 152383417 ps
CPU time 2.05 seconds
Started Jan 21 04:05:41 PM PST 24
Finished Jan 21 04:05:46 PM PST 24
Peak memory 198924 kb
Host smart-d9b7b804-145b-4d47-8aab-2a3612382f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061675400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4061675400
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2578840317
Short name T454
Test name
Test status
Simulation time 120044883624 ps
CPU time 1059.13 seconds
Started Jan 21 04:05:45 PM PST 24
Finished Jan 21 04:23:25 PM PST 24
Peak memory 199156 kb
Host smart-7f5262b0-ed82-41c8-a03e-4efcdcf937d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578840317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2578840317
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1016740021
Short name T689
Test name
Test status
Simulation time 62752258384 ps
CPU time 469.75 seconds
Started Jan 21 04:05:45 PM PST 24
Finished Jan 21 04:13:36 PM PST 24
Peak memory 224924 kb
Host smart-4931197d-1534-4014-8ba9-58e69e1b7c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016740021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1016740021
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.20333491
Short name T254
Test name
Test status
Simulation time 236248649 ps
CPU time 1.13 seconds
Started Jan 21 04:05:47 PM PST 24
Finished Jan 21 04:05:51 PM PST 24
Peak memory 196664 kb
Host smart-619c6637-090f-4a77-b3b8-c313a1050fe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20333491 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.hmac_test_hmac_vectors.20333491
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3920460031
Short name T306
Test name
Test status
Simulation time 108196511471 ps
CPU time 428.98 seconds
Started Jan 21 04:05:46 PM PST 24
Finished Jan 21 04:12:56 PM PST 24
Peak memory 199128 kb
Host smart-034eb09e-e190-460b-b0a7-93b18736ffce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920460031 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3920460031
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4011733632
Short name T655
Test name
Test status
Simulation time 33237441852 ps
CPU time 70.81 seconds
Started Jan 21 04:05:47 PM PST 24
Finished Jan 21 04:07:02 PM PST 24
Peak memory 199132 kb
Host smart-9647bc65-2530-4ce5-8844-874be32dcdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011733632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4011733632
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3029058078
Short name T47
Test name
Test status
Simulation time 15519879 ps
CPU time 0.6 seconds
Started Jan 21 04:05:56 PM PST 24
Finished Jan 21 04:06:01 PM PST 24
Peak memory 193804 kb
Host smart-b0121a37-3cff-4b4f-be72-ca6e7c71f3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029058078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3029058078
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3649943002
Short name T240
Test name
Test status
Simulation time 2109051458 ps
CPU time 32.88 seconds
Started Jan 21 04:05:46 PM PST 24
Finished Jan 21 04:06:23 PM PST 24
Peak memory 207304 kb
Host smart-141a5d5b-fa83-4538-b03a-c4858c18fc76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649943002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3649943002
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2369860703
Short name T656
Test name
Test status
Simulation time 2690822423 ps
CPU time 28.48 seconds
Started Jan 21 04:05:45 PM PST 24
Finished Jan 21 04:06:14 PM PST 24
Peak memory 199100 kb
Host smart-1a162384-78a2-46de-ae71-0a3b032dec2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369860703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2369860703
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.571004362
Short name T673
Test name
Test status
Simulation time 452683630 ps
CPU time 18.85 seconds
Started Jan 21 04:05:49 PM PST 24
Finished Jan 21 04:06:11 PM PST 24
Peak memory 199072 kb
Host smart-36759855-88c9-484c-b5e2-d46045a5748c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571004362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.571004362
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.883187135
Short name T198
Test name
Test status
Simulation time 1283713367 ps
CPU time 13.46 seconds
Started Jan 21 04:05:50 PM PST 24
Finished Jan 21 04:06:06 PM PST 24
Peak memory 198992 kb
Host smart-070f5dc7-6b5d-4153-b916-e90f643346d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883187135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.883187135
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4278662285
Short name T604
Test name
Test status
Simulation time 904581614 ps
CPU time 44.54 seconds
Started Jan 21 04:05:50 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 199240 kb
Host smart-3c76a0de-e3ee-4414-86ac-9f534a1090eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278662285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4278662285
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3768750269
Short name T781
Test name
Test status
Simulation time 507469531 ps
CPU time 1.6 seconds
Started Jan 21 04:05:46 PM PST 24
Finished Jan 21 04:05:49 PM PST 24
Peak memory 198864 kb
Host smart-0905129c-5cd4-4950-9d24-e7531a164bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768750269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3768750269
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1329084834
Short name T752
Test name
Test status
Simulation time 14246005199 ps
CPU time 48.45 seconds
Started Jan 21 04:30:41 PM PST 24
Finished Jan 21 04:31:30 PM PST 24
Peak memory 199228 kb
Host smart-61366777-2844-4061-a910-757c8ca1dc32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329084834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1329084834
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.956680863
Short name T239
Test name
Test status
Simulation time 281032678665 ps
CPU time 3147.88 seconds
Started Jan 21 04:05:54 PM PST 24
Finished Jan 21 04:58:25 PM PST 24
Peak memory 260132 kb
Host smart-3a904f26-c0fe-4ac2-b2f8-815ac6554397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956680863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.956680863
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.716176033
Short name T606
Test name
Test status
Simulation time 189615617 ps
CPU time 1.18 seconds
Started Jan 21 04:05:57 PM PST 24
Finished Jan 21 04:06:05 PM PST 24
Peak memory 197180 kb
Host smart-e8370ea5-a442-449f-a150-220ce8fcaa18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716176033 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.716176033
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.853143666
Short name T399
Test name
Test status
Simulation time 89643704248 ps
CPU time 578 seconds
Started Jan 21 04:28:49 PM PST 24
Finished Jan 21 04:38:28 PM PST 24
Peak memory 199164 kb
Host smart-af8f290e-d6aa-4d11-9768-77d65b774906
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853143666 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.853143666
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.135761533
Short name T621
Test name
Test status
Simulation time 4603316569 ps
CPU time 50.22 seconds
Started Jan 21 04:05:53 PM PST 24
Finished Jan 21 04:06:44 PM PST 24
Peak memory 199188 kb
Host smart-4ec8d63e-8536-4804-885f-37b4231d07d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135761533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.135761533
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1119384977
Short name T469
Test name
Test status
Simulation time 45230655 ps
CPU time 0.59 seconds
Started Jan 21 04:06:06 PM PST 24
Finished Jan 21 04:06:12 PM PST 24
Peak memory 192596 kb
Host smart-46a3aadc-e5ef-4f4b-baf8-a27536b4719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119384977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1119384977
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1404151349
Short name T484
Test name
Test status
Simulation time 2373408388 ps
CPU time 6.93 seconds
Started Jan 21 04:05:57 PM PST 24
Finished Jan 21 04:06:08 PM PST 24
Peak memory 207348 kb
Host smart-e3eb92bd-7200-4212-88da-9205277f916e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404151349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1404151349
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3648308722
Short name T646
Test name
Test status
Simulation time 1571302961 ps
CPU time 18.47 seconds
Started Jan 21 04:06:04 PM PST 24
Finished Jan 21 04:06:27 PM PST 24
Peak memory 199020 kb
Host smart-f0046fc5-10ca-4ea0-8447-d67ea54fedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648308722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3648308722
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2840761061
Short name T645
Test name
Test status
Simulation time 7053602512 ps
CPU time 90.21 seconds
Started Jan 21 04:06:02 PM PST 24
Finished Jan 21 04:07:38 PM PST 24
Peak memory 199168 kb
Host smart-6f797f69-df20-4685-870b-2d6af9a55fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840761061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2840761061
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.906866888
Short name T224
Test name
Test status
Simulation time 3415513405 ps
CPU time 44.48 seconds
Started Jan 21 04:06:02 PM PST 24
Finished Jan 21 04:06:53 PM PST 24
Peak memory 199172 kb
Host smart-ddda584e-3225-43c5-bbb4-dc650f353d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906866888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.906866888
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.976781628
Short name T841
Test name
Test status
Simulation time 212630137 ps
CPU time 1.95 seconds
Started Jan 21 06:09:13 PM PST 24
Finished Jan 21 06:09:16 PM PST 24
Peak memory 198996 kb
Host smart-4194cdcf-45f1-417f-8a53-491761efc784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976781628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.976781628
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.147129774
Short name T308
Test name
Test status
Simulation time 265584298 ps
CPU time 3.86 seconds
Started Jan 21 04:05:55 PM PST 24
Finished Jan 21 04:06:02 PM PST 24
Peak memory 199064 kb
Host smart-3a68e75a-5636-44e6-b524-774618aa1a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147129774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.147129774
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3989576290
Short name T533
Test name
Test status
Simulation time 206195186250 ps
CPU time 662.92 seconds
Started Jan 21 04:06:11 PM PST 24
Finished Jan 21 04:17:20 PM PST 24
Peak memory 199192 kb
Host smart-030e7bb8-ddd5-46b4-b8be-bb60275966fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989576290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3989576290
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3108291903
Short name T271
Test name
Test status
Simulation time 31899771 ps
CPU time 1.1 seconds
Started Jan 21 04:06:03 PM PST 24
Finished Jan 21 04:06:09 PM PST 24
Peak memory 197596 kb
Host smart-c2c9295f-27e4-4d58-9f6e-2379ef93a6db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108291903 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3108291903
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1336854339
Short name T751
Test name
Test status
Simulation time 26594206561 ps
CPU time 437.51 seconds
Started Jan 21 04:06:03 PM PST 24
Finished Jan 21 04:13:26 PM PST 24
Peak memory 199120 kb
Host smart-2a25f44a-9cac-4851-8278-2ea1cebee64f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336854339 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.1336854339
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1815784020
Short name T443
Test name
Test status
Simulation time 3972063539 ps
CPU time 54.66 seconds
Started Jan 21 04:22:23 PM PST 24
Finished Jan 21 04:23:19 PM PST 24
Peak memory 199160 kb
Host smart-d8c0c246-1ac6-4bcb-80db-e8a1c2ba6f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815784020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1815784020
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1818235516
Short name T526
Test name
Test status
Simulation time 38117031 ps
CPU time 0.56 seconds
Started Jan 21 04:06:18 PM PST 24
Finished Jan 21 04:06:24 PM PST 24
Peak memory 192664 kb
Host smart-05c8e58b-1f2c-49a5-bebd-ccbd6c649bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818235516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1818235516
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1404075945
Short name T297
Test name
Test status
Simulation time 6378085932 ps
CPU time 21.95 seconds
Started Jan 21 04:06:07 PM PST 24
Finished Jan 21 04:06:34 PM PST 24
Peak memory 199176 kb
Host smart-6d849eef-0377-4840-8a88-827666798d7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404075945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1404075945
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1333424428
Short name T595
Test name
Test status
Simulation time 1370003254 ps
CPU time 19.38 seconds
Started Jan 21 04:06:12 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 199224 kb
Host smart-f4e84b40-3cda-4e3d-8cf4-975cc08ac54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333424428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1333424428
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.637844457
Short name T253
Test name
Test status
Simulation time 896154173 ps
CPU time 22.59 seconds
Started Jan 21 04:06:11 PM PST 24
Finished Jan 21 04:06:39 PM PST 24
Peak memory 199144 kb
Host smart-1dbbb75d-8fe8-4f92-956c-7bda5325c575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637844457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.637844457
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2945143508
Short name T236
Test name
Test status
Simulation time 50309791532 ps
CPU time 172.88 seconds
Started Jan 21 04:06:12 PM PST 24
Finished Jan 21 04:09:10 PM PST 24
Peak memory 199388 kb
Host smart-8eae7883-d2b2-4d82-8b82-7f9464c408b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945143508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2945143508
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1753014318
Short name T747
Test name
Test status
Simulation time 2304407091 ps
CPU time 57.57 seconds
Started Jan 21 04:06:06 PM PST 24
Finished Jan 21 04:07:09 PM PST 24
Peak memory 199136 kb
Host smart-0a14e7e1-9ecb-4ed3-9483-b72c7ec56b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753014318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1753014318
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2857641715
Short name T501
Test name
Test status
Simulation time 369477898 ps
CPU time 2.25 seconds
Started Jan 21 04:29:25 PM PST 24
Finished Jan 21 04:29:28 PM PST 24
Peak memory 199128 kb
Host smart-822be1a7-6b71-41db-9170-0438ac201aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857641715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2857641715
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4109782001
Short name T539
Test name
Test status
Simulation time 257476944398 ps
CPU time 819.19 seconds
Started Jan 21 05:36:17 PM PST 24
Finished Jan 21 05:49:59 PM PST 24
Peak memory 199196 kb
Host smart-8bd9d8dc-cef7-4bb2-9ac5-fa7dad989fcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109782001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4109782001
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.3417235000
Short name T687
Test name
Test status
Simulation time 16699879365 ps
CPU time 899.98 seconds
Started Jan 21 04:06:13 PM PST 24
Finished Jan 21 04:21:19 PM PST 24
Peak memory 247908 kb
Host smart-124be424-a8c8-476e-b2d1-b5770c31a03e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417235000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.3417235000
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2755481305
Short name T200
Test name
Test status
Simulation time 97327565 ps
CPU time 0.9 seconds
Started Jan 21 04:06:15 PM PST 24
Finished Jan 21 04:06:21 PM PST 24
Peak memory 196332 kb
Host smart-4ec136ed-b010-4f73-b27b-ff9e2344bc39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755481305 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2755481305
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.4067387013
Short name T355
Test name
Test status
Simulation time 7313973442 ps
CPU time 357.02 seconds
Started Jan 21 04:06:13 PM PST 24
Finished Jan 21 04:12:16 PM PST 24
Peak memory 199124 kb
Host smart-1b72f59e-19fa-47c4-a128-0cd5aa3ed1eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067387013 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.4067387013
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2615919129
Short name T277
Test name
Test status
Simulation time 1781109184 ps
CPU time 31.13 seconds
Started Jan 21 04:06:08 PM PST 24
Finished Jan 21 04:06:44 PM PST 24
Peak memory 199096 kb
Host smart-f23d2d8d-d8e0-4189-8d81-73ba7f345535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615919129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2615919129
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.633682738
Short name T704
Test name
Test status
Simulation time 213642660 ps
CPU time 0.59 seconds
Started Jan 21 04:06:23 PM PST 24
Finished Jan 21 04:06:31 PM PST 24
Peak memory 193312 kb
Host smart-0d712831-7aeb-4917-9f61-88cee45c8277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633682738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.633682738
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1360098876
Short name T267
Test name
Test status
Simulation time 502534297 ps
CPU time 6.68 seconds
Started Jan 21 04:25:55 PM PST 24
Finished Jan 21 04:26:07 PM PST 24
Peak memory 222948 kb
Host smart-fa2a5ba0-02a2-4b5f-acd1-607c79539cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360098876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1360098876
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1664502389
Short name T790
Test name
Test status
Simulation time 496329821 ps
CPU time 22.29 seconds
Started Jan 21 04:06:19 PM PST 24
Finished Jan 21 04:06:46 PM PST 24
Peak memory 199072 kb
Host smart-3d01098d-6fd0-4b28-8cde-040173170cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664502389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1664502389
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.743204766
Short name T238
Test name
Test status
Simulation time 1634360575 ps
CPU time 93.69 seconds
Started Jan 21 05:18:58 PM PST 24
Finished Jan 21 05:20:33 PM PST 24
Peak memory 199076 kb
Host smart-40ba818b-e869-4fdf-9de1-7f8a3940d46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743204766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.743204766
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.348275965
Short name T347
Test name
Test status
Simulation time 10664069725 ps
CPU time 133.07 seconds
Started Jan 21 04:06:19 PM PST 24
Finished Jan 21 04:08:36 PM PST 24
Peak memory 199220 kb
Host smart-8e189f19-2a02-41ed-93b2-dadb81691287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348275965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.348275965
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.901979132
Short name T739
Test name
Test status
Simulation time 1504539917 ps
CPU time 80.75 seconds
Started Jan 21 06:55:30 PM PST 24
Finished Jan 21 06:56:57 PM PST 24
Peak memory 199124 kb
Host smart-310e8229-2189-4ddc-a243-28847cbcdef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901979132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.901979132
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1278738781
Short name T818
Test name
Test status
Simulation time 745727628 ps
CPU time 2.02 seconds
Started Jan 21 04:06:16 PM PST 24
Finished Jan 21 04:06:22 PM PST 24
Peak memory 199020 kb
Host smart-2e9dd2ae-db3b-4d89-af32-b6e2088db88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278738781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1278738781
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3633277654
Short name T298
Test name
Test status
Simulation time 85156899332 ps
CPU time 2104.64 seconds
Started Jan 21 04:06:22 PM PST 24
Finished Jan 21 04:41:35 PM PST 24
Peak memory 240188 kb
Host smart-dafc8e75-7f0e-49d9-a70c-4c4a83ee3c55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633277654 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3633277654
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.854294709
Short name T761
Test name
Test status
Simulation time 507725161070 ps
CPU time 2897.26 seconds
Started Jan 21 04:06:24 PM PST 24
Finished Jan 21 04:54:49 PM PST 24
Peak memory 250504 kb
Host smart-ab773b10-848a-44bc-8f4f-8626cae26f1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854294709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.854294709
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1031833196
Short name T556
Test name
Test status
Simulation time 268652498 ps
CPU time 1.12 seconds
Started Jan 21 04:06:29 PM PST 24
Finished Jan 21 04:06:36 PM PST 24
Peak memory 198116 kb
Host smart-a0a59657-121c-497d-a19c-6ca7ce6a0041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031833196 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1031833196
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1272585807
Short name T244
Test name
Test status
Simulation time 38261653895 ps
CPU time 448.18 seconds
Started Jan 21 04:06:28 PM PST 24
Finished Jan 21 04:14:03 PM PST 24
Peak memory 199064 kb
Host smart-614b1311-da34-4fa5-8dc8-8f768e675efe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272585807 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.1272585807
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1757162937
Short name T692
Test name
Test status
Simulation time 10993740918 ps
CPU time 48.04 seconds
Started Jan 21 04:33:17 PM PST 24
Finished Jan 21 04:34:06 PM PST 24
Peak memory 199112 kb
Host smart-d3ffe8f0-e802-4b33-9055-b32cc0d6832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757162937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1757162937
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.969833874
Short name T416
Test name
Test status
Simulation time 100217997 ps
CPU time 0.57 seconds
Started Jan 21 04:06:31 PM PST 24
Finished Jan 21 04:06:39 PM PST 24
Peak memory 194560 kb
Host smart-0f93c251-486f-42ee-b297-f49808a3a762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969833874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.969833874
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2324284402
Short name T217
Test name
Test status
Simulation time 291531448 ps
CPU time 7.8 seconds
Started Jan 21 04:06:22 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 199124 kb
Host smart-34e7f503-cc88-48a6-8f29-8cfe64cd657f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324284402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2324284402
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3725727293
Short name T320
Test name
Test status
Simulation time 4949395001 ps
CPU time 57.53 seconds
Started Jan 21 04:06:29 PM PST 24
Finished Jan 21 04:07:33 PM PST 24
Peak memory 199160 kb
Host smart-d7e288ff-e54e-42de-8c19-a36238bdff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725727293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3725727293
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3107758736
Short name T809
Test name
Test status
Simulation time 1337843975 ps
CPU time 37.13 seconds
Started Jan 21 04:06:22 PM PST 24
Finished Jan 21 04:07:07 PM PST 24
Peak memory 199076 kb
Host smart-9cb34627-2884-4a28-82e5-e98bfdccc426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107758736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3107758736
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.138523619
Short name T738
Test name
Test status
Simulation time 33141383878 ps
CPU time 92.21 seconds
Started Jan 21 04:06:28 PM PST 24
Finished Jan 21 04:08:07 PM PST 24
Peak memory 199140 kb
Host smart-016b2e07-e659-4046-b219-084dec1fe868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138523619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.138523619
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3448786663
Short name T214
Test name
Test status
Simulation time 2789276776 ps
CPU time 12.6 seconds
Started Jan 21 04:17:20 PM PST 24
Finished Jan 21 04:17:35 PM PST 24
Peak memory 199140 kb
Host smart-4800689a-1f9c-4c2a-a944-135070f20fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448786663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3448786663
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.755272472
Short name T40
Test name
Test status
Simulation time 100021490 ps
CPU time 2.37 seconds
Started Jan 21 04:06:28 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 198940 kb
Host smart-d7338725-d46e-441f-91e5-dd3e2f0c39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755272472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.755272472
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2411022207
Short name T585
Test name
Test status
Simulation time 158800933838 ps
CPU time 827.7 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:20:41 PM PST 24
Peak memory 231976 kb
Host smart-892d320a-fada-4fa7-80d9-9ce8bce55ac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411022207 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2411022207
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.3030696170
Short name T596
Test name
Test status
Simulation time 46987966115 ps
CPU time 676.75 seconds
Started Jan 21 04:06:32 PM PST 24
Finished Jan 21 04:18:05 PM PST 24
Peak memory 215676 kb
Host smart-d4c5fd27-85bc-46e8-842c-e4d42ce65592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030696170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.3030696170
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.43452576
Short name T827
Test name
Test status
Simulation time 190654301 ps
CPU time 1.09 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:06:55 PM PST 24
Peak memory 197472 kb
Host smart-f8ce0681-c18b-4c4f-8260-074242f0e0cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43452576 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_hmac_vectors.43452576
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2130730392
Short name T683
Test name
Test status
Simulation time 67853678218 ps
CPU time 358.51 seconds
Started Jan 21 04:06:21 PM PST 24
Finished Jan 21 04:12:28 PM PST 24
Peak memory 199104 kb
Host smart-1c1aae95-a803-497a-a99b-482e199c60dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130730392 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2130730392
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3713628298
Short name T352
Test name
Test status
Simulation time 4046588344 ps
CPU time 70.68 seconds
Started Jan 21 04:06:23 PM PST 24
Finished Jan 21 04:07:42 PM PST 24
Peak memory 199160 kb
Host smart-ceca6767-533f-4556-b7f6-975cb02337f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713628298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3713628298
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.77333270
Short name T351
Test name
Test status
Simulation time 35245913 ps
CPU time 0.57 seconds
Started Jan 21 04:06:36 PM PST 24
Finished Jan 21 04:06:54 PM PST 24
Peak memory 193484 kb
Host smart-db5222fd-abc5-46fc-acb3-fae654aaa174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77333270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.77333270
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3522157121
Short name T505
Test name
Test status
Simulation time 664145855 ps
CPU time 21.13 seconds
Started Jan 21 04:06:29 PM PST 24
Finished Jan 21 04:06:56 PM PST 24
Peak memory 215020 kb
Host smart-84a66b07-ca42-46b8-bb50-6388a8015616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522157121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3522157121
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1394073842
Short name T334
Test name
Test status
Simulation time 2950982047 ps
CPU time 16.18 seconds
Started Jan 21 04:06:28 PM PST 24
Finished Jan 21 04:06:51 PM PST 24
Peak memory 199184 kb
Host smart-747d9002-13b2-4208-9fba-102dd838e369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394073842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1394073842
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.326518848
Short name T338
Test name
Test status
Simulation time 2949863460 ps
CPU time 158.06 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:09:29 PM PST 24
Peak memory 199084 kb
Host smart-5fa39282-123e-422f-80c5-616ab0df6553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326518848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.326518848
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.523735969
Short name T830
Test name
Test status
Simulation time 22849923522 ps
CPU time 171.83 seconds
Started Jan 21 04:06:31 PM PST 24
Finished Jan 21 04:09:30 PM PST 24
Peak memory 199140 kb
Host smart-965eec2b-c786-4169-b9b9-b13a8c031856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523735969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.523735969
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.645074221
Short name T290
Test name
Test status
Simulation time 3195634131 ps
CPU time 86.32 seconds
Started Jan 21 04:06:32 PM PST 24
Finished Jan 21 04:08:12 PM PST 24
Peak memory 199360 kb
Host smart-e50ccee1-6342-49c4-87bf-789cf4516ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645074221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.645074221
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2414871239
Short name T291
Test name
Test status
Simulation time 725631216 ps
CPU time 2.14 seconds
Started Jan 21 04:06:31 PM PST 24
Finished Jan 21 04:06:40 PM PST 24
Peak memory 198996 kb
Host smart-eaac1e49-5f96-4a42-8000-c021be37e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414871239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2414871239
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1641129958
Short name T674
Test name
Test status
Simulation time 9490763580 ps
CPU time 96.2 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:08:28 PM PST 24
Peak memory 223768 kb
Host smart-77d2e2a7-3267-41e0-acb2-eb4cdb4905f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641129958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1641129958
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.866716878
Short name T608
Test name
Test status
Simulation time 72556815455 ps
CPU time 868.01 seconds
Started Jan 21 04:06:40 PM PST 24
Finished Jan 21 04:21:24 PM PST 24
Peak memory 244708 kb
Host smart-572c1f03-4a21-4a20-8e84-3c63ba98ddc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866716878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.866716878
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4081745274
Short name T346
Test name
Test status
Simulation time 51502984 ps
CPU time 0.95 seconds
Started Jan 21 04:06:31 PM PST 24
Finished Jan 21 04:06:39 PM PST 24
Peak memory 197432 kb
Host smart-1ea83536-6078-4dba-b344-1f88ac5719cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081745274 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.4081745274
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.512269010
Short name T507
Test name
Test status
Simulation time 7503148803 ps
CPU time 371.49 seconds
Started Jan 21 04:06:32 PM PST 24
Finished Jan 21 04:13:00 PM PST 24
Peak memory 199104 kb
Host smart-5e6a51f5-83fb-41ec-9a6b-197fa6f182a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512269010 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_sha_vectors.512269010
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1503433818
Short name T642
Test name
Test status
Simulation time 9991184227 ps
CPU time 70.09 seconds
Started Jan 21 04:06:32 PM PST 24
Finished Jan 21 04:07:59 PM PST 24
Peak memory 199164 kb
Host smart-623a978b-1150-4e73-b949-7cbcf02cf589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503433818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1503433818
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3227085798
Short name T831
Test name
Test status
Simulation time 111780780 ps
CPU time 0.56 seconds
Started Jan 21 04:02:04 PM PST 24
Finished Jan 21 04:02:09 PM PST 24
Peak memory 192516 kb
Host smart-c0221b8f-d435-4a6e-bf2e-44e22b7e9a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227085798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3227085798
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2778061508
Short name T733
Test name
Test status
Simulation time 1163663482 ps
CPU time 40.92 seconds
Started Jan 21 04:01:56 PM PST 24
Finished Jan 21 04:02:42 PM PST 24
Peak memory 244044 kb
Host smart-902a11e7-721f-4146-b8ee-65db7ec44bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778061508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2778061508
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1031316622
Short name T360
Test name
Test status
Simulation time 14057213543 ps
CPU time 54.63 seconds
Started Jan 21 04:50:35 PM PST 24
Finished Jan 21 04:51:35 PM PST 24
Peak memory 199224 kb
Host smart-4961e75e-79aa-4bd0-8d7a-b81ad15735ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031316622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1031316622
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1050823905
Short name T383
Test name
Test status
Simulation time 13017073705 ps
CPU time 32.37 seconds
Started Jan 21 04:01:59 PM PST 24
Finished Jan 21 04:02:35 PM PST 24
Peak memory 199224 kb
Host smart-33305675-baa4-4673-a9fb-a6dbb02075c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050823905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1050823905
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3285738093
Short name T846
Test name
Test status
Simulation time 3655895297 ps
CPU time 45.67 seconds
Started Jan 21 04:02:05 PM PST 24
Finished Jan 21 04:02:55 PM PST 24
Peak memory 199156 kb
Host smart-817943c1-df02-4f04-bd73-bc300e5f724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285738093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3285738093
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3206026575
Short name T323
Test name
Test status
Simulation time 587578252 ps
CPU time 5.83 seconds
Started Jan 21 04:01:57 PM PST 24
Finished Jan 21 04:02:07 PM PST 24
Peak memory 198876 kb
Host smart-1983bc77-a411-4c3c-8c0c-99b6499f74ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206026575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3206026575
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2176701640
Short name T759
Test name
Test status
Simulation time 401103418 ps
CPU time 1.67 seconds
Started Jan 21 04:01:58 PM PST 24
Finished Jan 21 04:02:04 PM PST 24
Peak memory 198892 kb
Host smart-a8c3fdd0-c506-4fa6-b477-62957982f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176701640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2176701640
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1754724459
Short name T131
Test name
Test status
Simulation time 47362149232 ps
CPU time 1098.46 seconds
Started Jan 21 04:02:09 PM PST 24
Finished Jan 21 04:20:29 PM PST 24
Peak memory 235456 kb
Host smart-e5aa5356-0038-48ff-9f69-6f254e091754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754724459 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1754724459
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3078600759
Short name T737
Test name
Test status
Simulation time 178184735 ps
CPU time 0.9 seconds
Started Jan 21 04:02:06 PM PST 24
Finished Jan 21 04:02:10 PM PST 24
Peak memory 196808 kb
Host smart-7218d85f-8fc8-4140-81bb-cf605f57de88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078600759 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3078600759
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1695087356
Short name T365
Test name
Test status
Simulation time 55992675325 ps
CPU time 444.43 seconds
Started Jan 21 04:02:07 PM PST 24
Finished Jan 21 04:09:34 PM PST 24
Peak memory 199136 kb
Host smart-8c0a6d23-8d1e-4c49-8ef0-678dd19b9051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695087356 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.1695087356
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3090227169
Short name T695
Test name
Test status
Simulation time 7267684141 ps
CPU time 70.91 seconds
Started Jan 21 05:03:44 PM PST 24
Finished Jan 21 05:04:56 PM PST 24
Peak memory 199168 kb
Host smart-1628c3c9-2adf-4af1-9d3b-589eebdc86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090227169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3090227169
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2205561847
Short name T612
Test name
Test status
Simulation time 18078577 ps
CPU time 0.56 seconds
Started Jan 21 04:06:36 PM PST 24
Finished Jan 21 04:06:54 PM PST 24
Peak memory 192500 kb
Host smart-bc14fa82-e7d5-4c30-89c7-1648dba47210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205561847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2205561847
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.601196166
Short name T56
Test name
Test status
Simulation time 4759032142 ps
CPU time 17.41 seconds
Started Jan 21 04:06:34 PM PST 24
Finished Jan 21 04:07:07 PM PST 24
Peak memory 199172 kb
Host smart-16ae60a1-3b35-4f1c-859d-84e5a960931a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601196166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.601196166
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2763990655
Short name T221
Test name
Test status
Simulation time 927724043 ps
CPU time 6.64 seconds
Started Jan 21 04:06:37 PM PST 24
Finished Jan 21 04:07:01 PM PST 24
Peak memory 199044 kb
Host smart-04cf3e4e-bb99-4dde-a4a4-3840511a3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763990655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2763990655
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1673332723
Short name T199
Test name
Test status
Simulation time 187957633 ps
CPU time 9.51 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:07:02 PM PST 24
Peak memory 198864 kb
Host smart-901bac76-f5b7-4500-b0f5-1bad76d1bf96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673332723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1673332723
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4091290837
Short name T245
Test name
Test status
Simulation time 4783011923 ps
CPU time 61.06 seconds
Started Jan 21 04:06:39 PM PST 24
Finished Jan 21 04:07:57 PM PST 24
Peak memory 199160 kb
Host smart-43dc20e2-3a7d-4773-9679-e005c7498e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091290837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4091290837
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3492159538
Short name T833
Test name
Test status
Simulation time 11004910104 ps
CPU time 62.16 seconds
Started Jan 21 04:06:36 PM PST 24
Finished Jan 21 04:07:56 PM PST 24
Peak memory 199176 kb
Host smart-a8caf5c0-4330-4423-9339-a080e2b9e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492159538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3492159538
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.4251548820
Short name T250
Test name
Test status
Simulation time 70348076 ps
CPU time 1.77 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:06:53 PM PST 24
Peak memory 199096 kb
Host smart-ac71aeb3-ba29-4830-893e-30a5fbe68c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251548820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4251548820
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.831563028
Short name T694
Test name
Test status
Simulation time 78927277003 ps
CPU time 1891.35 seconds
Started Jan 21 04:06:39 PM PST 24
Finished Jan 21 04:38:27 PM PST 24
Peak memory 231924 kb
Host smart-be8f76d8-acc7-4f02-a292-ea0e6730fba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831563028 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.831563028
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.4131810539
Short name T206
Test name
Test status
Simulation time 127481452546 ps
CPU time 1116.39 seconds
Started Jan 21 04:06:39 PM PST 24
Finished Jan 21 04:25:32 PM PST 24
Peak memory 215736 kb
Host smart-bbd1636e-7453-4aca-a63a-bcad019d1936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131810539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.4131810539
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3364881183
Short name T628
Test name
Test status
Simulation time 78437073 ps
CPU time 1.03 seconds
Started Jan 21 04:06:35 PM PST 24
Finished Jan 21 04:06:52 PM PST 24
Peak memory 197628 kb
Host smart-d36b3d58-2352-41d7-b13d-fef0fa9f55d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364881183 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3364881183
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1572424967
Short name T652
Test name
Test status
Simulation time 6860438699 ps
CPU time 332.46 seconds
Started Jan 21 04:06:38 PM PST 24
Finished Jan 21 04:12:27 PM PST 24
Peak memory 199144 kb
Host smart-2379b37d-bbfe-4737-981f-a36b969d903a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572424967 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.1572424967
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3072445425
Short name T411
Test name
Test status
Simulation time 10969151031 ps
CPU time 50.02 seconds
Started Jan 21 04:06:40 PM PST 24
Finished Jan 21 04:07:46 PM PST 24
Peak memory 199164 kb
Host smart-b852f8a1-4e2b-4540-adb5-fbf720940f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072445425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3072445425
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2210008930
Short name T616
Test name
Test status
Simulation time 35402251 ps
CPU time 0.6 seconds
Started Jan 21 05:01:11 PM PST 24
Finished Jan 21 05:01:13 PM PST 24
Peak memory 184348 kb
Host smart-6ab71e1e-f6f3-4f06-9da3-d02cd4a7ca51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210008930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2210008930
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4071559713
Short name T260
Test name
Test status
Simulation time 1571278445 ps
CPU time 13.37 seconds
Started Jan 21 04:06:45 PM PST 24
Finished Jan 21 04:07:10 PM PST 24
Peak memory 201676 kb
Host smart-d9615b78-6702-47bd-8802-a4e3204a7785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071559713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4071559713
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3186608497
Short name T719
Test name
Test status
Simulation time 10244982859 ps
CPU time 33.11 seconds
Started Jan 21 04:06:49 PM PST 24
Finished Jan 21 04:07:31 PM PST 24
Peak memory 199168 kb
Host smart-a654ee39-39e4-470a-924b-26765b8a63d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186608497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3186608497
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1101877851
Short name T769
Test name
Test status
Simulation time 4036077387 ps
CPU time 50.82 seconds
Started Jan 21 04:06:42 PM PST 24
Finished Jan 21 04:07:47 PM PST 24
Peak memory 199148 kb
Host smart-7c8b352a-2309-47d4-9ca3-696eb5fd41f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101877851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1101877851
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3071986612
Short name T536
Test name
Test status
Simulation time 2952154088 ps
CPU time 71.75 seconds
Started Jan 21 04:06:43 PM PST 24
Finished Jan 21 04:08:08 PM PST 24
Peak memory 199164 kb
Host smart-cf66a9ee-97fa-472b-ba57-e1c25521d976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071986612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3071986612
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2377669379
Short name T703
Test name
Test status
Simulation time 7068951737 ps
CPU time 91.73 seconds
Started Jan 21 04:06:37 PM PST 24
Finished Jan 21 04:08:26 PM PST 24
Peak memory 199084 kb
Host smart-89e2a616-2a82-418e-bccf-ab3336fdbe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377669379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2377669379
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1174495819
Short name T847
Test name
Test status
Simulation time 112750524 ps
CPU time 2.92 seconds
Started Jan 21 04:06:36 PM PST 24
Finished Jan 21 04:06:57 PM PST 24
Peak memory 198944 kb
Host smart-57ae436f-e177-43ae-908a-f44e7c698092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174495819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1174495819
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2839422596
Short name T476
Test name
Test status
Simulation time 82249941935 ps
CPU time 141.27 seconds
Started Jan 21 04:06:49 PM PST 24
Finished Jan 21 04:09:19 PM PST 24
Peak memory 199196 kb
Host smart-a0559d1b-2406-4bef-9059-ffb5549c1d0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839422596 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2839422596
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1911034524
Short name T495
Test name
Test status
Simulation time 15009106147 ps
CPU time 218.11 seconds
Started Jan 21 04:06:42 PM PST 24
Finished Jan 21 04:10:34 PM PST 24
Peak memory 207636 kb
Host smart-a8535b18-b440-44ba-bc95-0d4baccac2e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911034524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1911034524
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2243235808
Short name T793
Test name
Test status
Simulation time 101145480 ps
CPU time 1.16 seconds
Started Jan 21 04:06:42 PM PST 24
Finished Jan 21 04:06:57 PM PST 24
Peak memory 197116 kb
Host smart-10ace7d4-e7a7-4228-b6d7-90e71118e95e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243235808 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2243235808
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1014562599
Short name T192
Test name
Test status
Simulation time 5653542605 ps
CPU time 69.6 seconds
Started Jan 21 04:06:49 PM PST 24
Finished Jan 21 04:08:07 PM PST 24
Peak memory 199156 kb
Host smart-8c31f470-85c6-44fa-8b8b-bca4d34a7cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014562599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1014562599
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3481458241
Short name T45
Test name
Test status
Simulation time 58958689 ps
CPU time 0.59 seconds
Started Jan 21 04:06:58 PM PST 24
Finished Jan 21 04:07:13 PM PST 24
Peak memory 184292 kb
Host smart-97e5b3f1-d323-4c75-a12e-5f958ffc7ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481458241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3481458241
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1125462033
Short name T270
Test name
Test status
Simulation time 3359224496 ps
CPU time 24.95 seconds
Started Jan 21 04:35:30 PM PST 24
Finished Jan 21 04:35:55 PM PST 24
Peak memory 207392 kb
Host smart-945d9261-a39a-4b3d-b1b0-0749d924cebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125462033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1125462033
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1760453923
Short name T799
Test name
Test status
Simulation time 365874924 ps
CPU time 1.65 seconds
Started Jan 21 04:06:49 PM PST 24
Finished Jan 21 04:06:59 PM PST 24
Peak memory 199180 kb
Host smart-a6005947-3582-47eb-867c-d96f696a7f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760453923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1760453923
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4070355052
Short name T732
Test name
Test status
Simulation time 96142981 ps
CPU time 2.28 seconds
Started Jan 21 04:06:50 PM PST 24
Finished Jan 21 04:07:01 PM PST 24
Peak memory 199100 kb
Host smart-67f5e670-8d4a-431e-b326-cc247163064c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070355052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4070355052
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.237123778
Short name T611
Test name
Test status
Simulation time 2392953892 ps
CPU time 14.23 seconds
Started Jan 21 04:06:51 PM PST 24
Finished Jan 21 04:07:15 PM PST 24
Peak memory 198164 kb
Host smart-f2a765ff-7519-4165-9ba2-da0fbf1d3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237123778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.237123778
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3970573899
Short name T600
Test name
Test status
Simulation time 1676713247 ps
CPU time 89.43 seconds
Started Jan 21 04:06:50 PM PST 24
Finished Jan 21 04:08:29 PM PST 24
Peak memory 199344 kb
Host smart-8160904c-7195-4595-9ac7-9cc60cb50c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970573899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3970573899
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1820239808
Short name T280
Test name
Test status
Simulation time 23107216 ps
CPU time 0.81 seconds
Started Jan 21 04:06:54 PM PST 24
Finished Jan 21 04:07:09 PM PST 24
Peak memory 196792 kb
Host smart-4bf3e499-b33a-4994-9655-c9b6ef8503f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820239808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1820239808
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2761989629
Short name T828
Test name
Test status
Simulation time 90091297780 ps
CPU time 1560.22 seconds
Started Jan 21 04:07:01 PM PST 24
Finished Jan 21 04:33:13 PM PST 24
Peak memory 228952 kb
Host smart-aa596960-5783-4b15-a515-7db685b5decd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761989629 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2761989629
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.1585558080
Short name T823
Test name
Test status
Simulation time 132976196399 ps
CPU time 1588.42 seconds
Started Jan 21 04:06:55 PM PST 24
Finished Jan 21 04:33:39 PM PST 24
Peak memory 257672 kb
Host smart-3278136e-1c33-4785-adff-333a0ddcf07b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585558080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.1585558080
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2249965541
Short name T419
Test name
Test status
Simulation time 64667150 ps
CPU time 1.15 seconds
Started Jan 21 04:06:59 PM PST 24
Finished Jan 21 04:07:13 PM PST 24
Peak memory 197524 kb
Host smart-dc81bbc3-5037-4e06-b2bd-03c7f0e784c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249965541 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2249965541
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2498920697
Short name T724
Test name
Test status
Simulation time 86561497014 ps
CPU time 435.25 seconds
Started Jan 21 04:07:02 PM PST 24
Finished Jan 21 04:14:28 PM PST 24
Peak memory 198960 kb
Host smart-a28902fc-ffa3-42d7-ab9d-eb1acd788a6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498920697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2498920697
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3268815581
Short name T839
Test name
Test status
Simulation time 3912840556 ps
CPU time 66.22 seconds
Started Jan 21 04:06:57 PM PST 24
Finished Jan 21 04:08:18 PM PST 24
Peak memory 199212 kb
Host smart-6061c936-33bf-45c3-a1bc-845b060c9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268815581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3268815581
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1044918246
Short name T439
Test name
Test status
Simulation time 12859383 ps
CPU time 0.59 seconds
Started Jan 21 05:01:33 PM PST 24
Finished Jan 21 05:01:35 PM PST 24
Peak memory 192600 kb
Host smart-b10ba772-c6c5-4c92-820e-493e94a18593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044918246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1044918246
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3750657441
Short name T514
Test name
Test status
Simulation time 3930568735 ps
CPU time 31.9 seconds
Started Jan 21 04:06:57 PM PST 24
Finished Jan 21 04:07:44 PM PST 24
Peak memory 223776 kb
Host smart-324a503b-6cb1-45eb-85b1-16f0664ab535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750657441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3750657441
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.910700403
Short name T716
Test name
Test status
Simulation time 5047725649 ps
CPU time 55.01 seconds
Started Jan 21 04:06:55 PM PST 24
Finished Jan 21 04:08:05 PM PST 24
Peak memory 199184 kb
Host smart-c2305cc2-886d-4e31-aa0d-03b170f56378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910700403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.910700403
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1788304978
Short name T835
Test name
Test status
Simulation time 1882758483 ps
CPU time 94.36 seconds
Started Jan 21 04:06:56 PM PST 24
Finished Jan 21 04:08:44 PM PST 24
Peak memory 199112 kb
Host smart-8546f108-afd3-4a6f-b043-9d9bdc5ac2e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788304978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1788304978
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2379452037
Short name T263
Test name
Test status
Simulation time 4922871812 ps
CPU time 38.89 seconds
Started Jan 21 04:07:02 PM PST 24
Finished Jan 21 04:07:52 PM PST 24
Peak memory 198788 kb
Host smart-197e2c7a-4dec-4e6f-adcd-4ba1b5cc88ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379452037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2379452037
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3509536214
Short name T731
Test name
Test status
Simulation time 13046627533 ps
CPU time 60.47 seconds
Started Jan 21 06:10:52 PM PST 24
Finished Jan 21 06:11:53 PM PST 24
Peak memory 199168 kb
Host smart-04e9cc01-c874-4ac1-be50-b071002e07eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509536214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3509536214
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.221967019
Short name T651
Test name
Test status
Simulation time 643569693 ps
CPU time 3.73 seconds
Started Jan 21 04:06:58 PM PST 24
Finished Jan 21 04:07:16 PM PST 24
Peak memory 198904 kb
Host smart-ac1104c5-050d-45eb-aeaa-d451be0d71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221967019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.221967019
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4267929208
Short name T335
Test name
Test status
Simulation time 31466405223 ps
CPU time 369.09 seconds
Started Jan 21 04:07:05 PM PST 24
Finished Jan 21 04:13:22 PM PST 24
Peak memory 207396 kb
Host smart-d45af592-67bc-415f-9bb7-664e18f04e3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267929208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4267929208
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.933655490
Short name T730
Test name
Test status
Simulation time 161706653150 ps
CPU time 485.77 seconds
Started Jan 21 04:07:05 PM PST 24
Finished Jan 21 04:15:19 PM PST 24
Peak memory 207480 kb
Host smart-f86b214d-f988-44fa-8b45-f1de83ba97a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933655490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.933655490
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1872473904
Short name T284
Test name
Test status
Simulation time 31778184 ps
CPU time 1.07 seconds
Started Jan 21 04:07:04 PM PST 24
Finished Jan 21 04:07:14 PM PST 24
Peak memory 196812 kb
Host smart-ad83f345-4e3b-45b0-99be-3e0e9546f624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872473904 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1872473904
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.338222629
Short name T807
Test name
Test status
Simulation time 26089663847 ps
CPU time 433.43 seconds
Started Jan 21 04:07:03 PM PST 24
Finished Jan 21 04:14:27 PM PST 24
Peak memory 199036 kb
Host smart-de3b8b01-67bf-4d1a-844b-1ddac2209050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338222629 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_sha_vectors.338222629
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.637954724
Short name T450
Test name
Test status
Simulation time 7122784199 ps
CPU time 59.48 seconds
Started Jan 21 04:07:06 PM PST 24
Finished Jan 21 04:08:12 PM PST 24
Peak memory 199128 kb
Host smart-495e325d-1584-4b0f-92e3-b43a9626b437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637954724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.637954724
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.329037250
Short name T396
Test name
Test status
Simulation time 38669085 ps
CPU time 0.57 seconds
Started Jan 21 04:07:14 PM PST 24
Finished Jan 21 04:07:19 PM PST 24
Peak memory 192420 kb
Host smart-38cc46a5-167e-49e4-9ad9-2823d9da87eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329037250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.329037250
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2052949562
Short name T663
Test name
Test status
Simulation time 2275268122 ps
CPU time 8.31 seconds
Started Jan 21 04:07:14 PM PST 24
Finished Jan 21 04:07:26 PM PST 24
Peak memory 214484 kb
Host smart-110722dd-472e-41e3-9d34-0ca8c51a351c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052949562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2052949562
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3995262306
Short name T786
Test name
Test status
Simulation time 7383054793 ps
CPU time 32.09 seconds
Started Jan 21 04:07:11 PM PST 24
Finished Jan 21 04:07:47 PM PST 24
Peak memory 199088 kb
Host smart-741b0239-66c7-4638-bbb0-ed595fa9e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995262306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3995262306
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4158449529
Short name T57
Test name
Test status
Simulation time 6135270236 ps
CPU time 82.05 seconds
Started Jan 21 04:07:12 PM PST 24
Finished Jan 21 04:08:38 PM PST 24
Peak memory 199100 kb
Host smart-ad0e2444-322b-4636-adac-f7e43f0c0204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158449529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4158449529
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1954485767
Short name T388
Test name
Test status
Simulation time 4748572369 ps
CPU time 118.12 seconds
Started Jan 21 04:07:14 PM PST 24
Finished Jan 21 04:09:16 PM PST 24
Peak memory 199184 kb
Host smart-a31f768f-1bb8-4863-beab-6dd851ddba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954485767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1954485767
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3454358198
Short name T620
Test name
Test status
Simulation time 1643068080 ps
CPU time 81.63 seconds
Started Jan 21 04:07:10 PM PST 24
Finished Jan 21 04:08:37 PM PST 24
Peak memory 199084 kb
Host smart-2e0b7f92-6a55-412b-b895-b5d7568a9019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454358198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3454358198
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2412272444
Short name T196
Test name
Test status
Simulation time 233167178 ps
CPU time 1.82 seconds
Started Jan 21 04:07:13 PM PST 24
Finished Jan 21 04:07:18 PM PST 24
Peak memory 199080 kb
Host smart-2edb89d4-a537-480f-999e-09135ebd5636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412272444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2412272444
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2363544431
Short name T205
Test name
Test status
Simulation time 8006181314 ps
CPU time 136.81 seconds
Started Jan 21 04:07:12 PM PST 24
Finished Jan 21 04:09:32 PM PST 24
Peak memory 214960 kb
Host smart-8810c188-55a6-4951-8d74-0ba84caa4bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363544431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2363544431
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.853777920
Short name T530
Test name
Test status
Simulation time 138458404765 ps
CPU time 1948.67 seconds
Started Jan 21 04:07:13 PM PST 24
Finished Jan 21 04:39:45 PM PST 24
Peak memory 232148 kb
Host smart-672bbb06-53c7-4087-8a89-17238a6f4df1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853777920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.853777920
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.778468108
Short name T522
Test name
Test status
Simulation time 114203889 ps
CPU time 0.95 seconds
Started Jan 21 04:07:12 PM PST 24
Finished Jan 21 04:07:17 PM PST 24
Peak memory 196056 kb
Host smart-858b7b95-763c-47d1-a6f9-f70709e915ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778468108 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.778468108
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1891773745
Short name T402
Test name
Test status
Simulation time 71301943418 ps
CPU time 430.19 seconds
Started Jan 21 04:07:12 PM PST 24
Finished Jan 21 04:14:26 PM PST 24
Peak memory 199064 kb
Host smart-f253085d-93b0-43ce-bf1f-19fa39da4604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891773745 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.1891773745
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2148875042
Short name T382
Test name
Test status
Simulation time 6836792110 ps
CPU time 21.04 seconds
Started Jan 21 04:07:11 PM PST 24
Finished Jan 21 04:07:36 PM PST 24
Peak memory 199188 kb
Host smart-18809b8f-f38f-4435-9b45-d94ab631e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148875042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2148875042
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3590607161
Short name T304
Test name
Test status
Simulation time 22202503 ps
CPU time 0.54 seconds
Started Jan 21 04:07:26 PM PST 24
Finished Jan 21 04:07:28 PM PST 24
Peak memory 192512 kb
Host smart-9866a9c7-a81e-4a11-85d4-9f423915df5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590607161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3590607161
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4172867169
Short name T275
Test name
Test status
Simulation time 28765764 ps
CPU time 1.15 seconds
Started Jan 21 05:16:35 PM PST 24
Finished Jan 21 05:16:37 PM PST 24
Peak memory 198960 kb
Host smart-76e90594-5ad8-4a47-8739-e396e1249f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172867169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4172867169
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4045063163
Short name T569
Test name
Test status
Simulation time 2399313716 ps
CPU time 26.98 seconds
Started Jan 21 04:07:20 PM PST 24
Finished Jan 21 04:07:50 PM PST 24
Peak memory 199204 kb
Host smart-c4fb2452-1f74-400b-9d88-9d0c8b16337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045063163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4045063163
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3222955558
Short name T395
Test name
Test status
Simulation time 691488633 ps
CPU time 8.98 seconds
Started Jan 21 04:32:37 PM PST 24
Finished Jan 21 04:32:47 PM PST 24
Peak memory 199160 kb
Host smart-d1cdabc6-c688-4707-9467-8014774fdcde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222955558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3222955558
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3373054524
Short name T727
Test name
Test status
Simulation time 39561543676 ps
CPU time 108.56 seconds
Started Jan 21 04:07:19 PM PST 24
Finished Jan 21 04:09:11 PM PST 24
Peak memory 199176 kb
Host smart-b28415b8-3086-4693-8c5d-1dce341c67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373054524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3373054524
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2677160309
Short name T453
Test name
Test status
Simulation time 1125506654 ps
CPU time 55.52 seconds
Started Jan 21 04:07:12 PM PST 24
Finished Jan 21 04:08:12 PM PST 24
Peak memory 199052 kb
Host smart-ab6c47ad-a58e-4c58-b0c8-10db73be6c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677160309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2677160309
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2874513031
Short name T542
Test name
Test status
Simulation time 119080375 ps
CPU time 1.67 seconds
Started Jan 21 04:07:11 PM PST 24
Finished Jan 21 04:07:17 PM PST 24
Peak memory 198796 kb
Host smart-9e198167-f8d9-4af6-bf55-8937df3342e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874513031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2874513031
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3848610320
Short name T848
Test name
Test status
Simulation time 113582799311 ps
CPU time 349.17 seconds
Started Jan 21 04:07:24 PM PST 24
Finished Jan 21 04:13:15 PM PST 24
Peak memory 199204 kb
Host smart-f8437865-20d2-4b45-b930-66c35c91ac05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848610320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3848610320
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.4174428679
Short name T816
Test name
Test status
Simulation time 3504925439 ps
CPU time 185.41 seconds
Started Jan 21 04:07:26 PM PST 24
Finished Jan 21 04:10:33 PM PST 24
Peak memory 199536 kb
Host smart-39bc1421-6bae-4a29-ba11-086ae8c1b0ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174428679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.4174428679
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3392499209
Short name T760
Test name
Test status
Simulation time 111521369 ps
CPU time 0.87 seconds
Started Jan 21 04:07:26 PM PST 24
Finished Jan 21 04:07:28 PM PST 24
Peak memory 196252 kb
Host smart-10be61f6-f2fa-44db-820c-3c64dd6b2e7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392499209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3392499209
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2650730323
Short name T836
Test name
Test status
Simulation time 40869834034 ps
CPU time 486.63 seconds
Started Jan 21 04:07:20 PM PST 24
Finished Jan 21 04:15:29 PM PST 24
Peak memory 199152 kb
Host smart-ecf57027-f618-43bb-9f24-f85fc54f2895
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650730323 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.2650730323
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1438706202
Short name T796
Test name
Test status
Simulation time 3270759202 ps
CPU time 46.54 seconds
Started Jan 21 05:01:37 PM PST 24
Finished Jan 21 05:02:52 PM PST 24
Peak memory 199196 kb
Host smart-10642dbb-12b4-4a23-b0da-1382d2081a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438706202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1438706202
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.176887503
Short name T653
Test name
Test status
Simulation time 20587011 ps
CPU time 0.56 seconds
Started Jan 21 04:07:30 PM PST 24
Finished Jan 21 04:07:32 PM PST 24
Peak memory 192560 kb
Host smart-96047296-0ef4-4e75-a1f1-af57ebec9187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176887503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.176887503
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3241729372
Short name T801
Test name
Test status
Simulation time 1390506734 ps
CPU time 45.1 seconds
Started Jan 21 04:07:24 PM PST 24
Finished Jan 21 04:08:10 PM PST 24
Peak memory 221244 kb
Host smart-3741e811-3ee0-4189-a8c7-28ce8c46ff1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241729372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3241729372
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4274463555
Short name T472
Test name
Test status
Simulation time 8414441312 ps
CPU time 31.38 seconds
Started Jan 21 04:53:08 PM PST 24
Finished Jan 21 04:53:40 PM PST 24
Peak memory 199160 kb
Host smart-e5af9ec9-4db7-4015-b683-0c663ef1b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274463555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4274463555
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.857948811
Short name T726
Test name
Test status
Simulation time 257615638 ps
CPU time 13.91 seconds
Started Jan 21 04:07:24 PM PST 24
Finished Jan 21 04:07:39 PM PST 24
Peak memory 199092 kb
Host smart-cdac2b0a-1b42-48ae-8276-c021b5a0f3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857948811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.857948811
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3318789828
Short name T804
Test name
Test status
Simulation time 578871721 ps
CPU time 7.62 seconds
Started Jan 21 04:43:18 PM PST 24
Finished Jan 21 04:43:27 PM PST 24
Peak memory 198796 kb
Host smart-b6cfeb69-becf-460b-855d-bba5b1e03474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318789828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3318789828
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.524206834
Short name T568
Test name
Test status
Simulation time 1784430971 ps
CPU time 50.95 seconds
Started Jan 21 04:07:27 PM PST 24
Finished Jan 21 04:08:19 PM PST 24
Peak memory 199036 kb
Host smart-a2bdfa33-14a0-4a18-a232-b6baab3cd752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524206834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.524206834
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2758844684
Short name T546
Test name
Test status
Simulation time 97283186 ps
CPU time 1.46 seconds
Started Jan 21 05:09:48 PM PST 24
Finished Jan 21 05:09:50 PM PST 24
Peak memory 198868 kb
Host smart-e6873845-3616-4717-96f9-d2026c5b94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758844684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2758844684
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1748060130
Short name T428
Test name
Test status
Simulation time 17752021880 ps
CPU time 206.83 seconds
Started Jan 21 04:07:33 PM PST 24
Finished Jan 21 04:11:02 PM PST 24
Peak memory 207440 kb
Host smart-d38739d3-7d22-4554-a6cb-4b11e8d154fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748060130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1748060130
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.1893966537
Short name T139
Test name
Test status
Simulation time 57973718765 ps
CPU time 1012.18 seconds
Started Jan 21 04:14:45 PM PST 24
Finished Jan 21 04:31:38 PM PST 24
Peak memory 246632 kb
Host smart-3c4905c2-f1f1-40dc-82d0-6e20e60515e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893966537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.1893966537
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3798684799
Short name T413
Test name
Test status
Simulation time 56551786 ps
CPU time 0.91 seconds
Started Jan 21 04:07:35 PM PST 24
Finished Jan 21 04:07:38 PM PST 24
Peak memory 196116 kb
Host smart-49354288-4da9-4f58-a095-c23508ba617b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798684799 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3798684799
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.629492415
Short name T681
Test name
Test status
Simulation time 161638215230 ps
CPU time 403.44 seconds
Started Jan 21 04:07:32 PM PST 24
Finished Jan 21 04:14:16 PM PST 24
Peak memory 199124 kb
Host smart-541af4f3-320f-47ce-b1f5-54c41af000c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629492415 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.hmac_test_sha_vectors.629492415
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.356211825
Short name T500
Test name
Test status
Simulation time 990186203 ps
CPU time 12.66 seconds
Started Jan 21 04:07:33 PM PST 24
Finished Jan 21 04:07:47 PM PST 24
Peak memory 199088 kb
Host smart-4c2de052-622a-472e-ab9f-b17b1e9deade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356211825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.356211825
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2146400711
Short name T58
Test name
Test status
Simulation time 15584501 ps
CPU time 0.57 seconds
Started Jan 21 04:07:40 PM PST 24
Finished Jan 21 04:07:42 PM PST 24
Peak memory 193532 kb
Host smart-44580b07-e889-4412-ab7b-2bf00b1044d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146400711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2146400711
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2708530680
Short name T437
Test name
Test status
Simulation time 5020788538 ps
CPU time 16.78 seconds
Started Jan 21 04:07:32 PM PST 24
Finished Jan 21 04:07:50 PM PST 24
Peak memory 215536 kb
Host smart-f9114f73-4ad4-4d95-b3cc-7cb285e6ea33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708530680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2708530680
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2009148520
Short name T128
Test name
Test status
Simulation time 4082043525 ps
CPU time 37.91 seconds
Started Jan 21 04:07:41 PM PST 24
Finished Jan 21 04:08:20 PM PST 24
Peak memory 199216 kb
Host smart-1c54759b-7b97-47f7-bdc2-544e5900f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009148520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2009148520
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4036045317
Short name T800
Test name
Test status
Simulation time 2276765953 ps
CPU time 113.97 seconds
Started Jan 21 04:07:41 PM PST 24
Finished Jan 21 04:09:36 PM PST 24
Peak memory 199148 kb
Host smart-3175ddb9-1ac4-48bd-af84-8543878f276e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036045317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4036045317
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3844396800
Short name T293
Test name
Test status
Simulation time 30837771071 ps
CPU time 57.36 seconds
Started Jan 21 04:07:36 PM PST 24
Finished Jan 21 04:08:35 PM PST 24
Peak memory 199124 kb
Host smart-3978d29c-edcb-49fe-a635-a670e331e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844396800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3844396800
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3463129318
Short name T42
Test name
Test status
Simulation time 3977025169 ps
CPU time 71.18 seconds
Started Jan 21 04:07:33 PM PST 24
Finished Jan 21 04:08:46 PM PST 24
Peak memory 199116 kb
Host smart-dfece268-51d8-4055-8d26-c84ee0e0caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463129318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3463129318
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2753112487
Short name T517
Test name
Test status
Simulation time 651205966 ps
CPU time 2.76 seconds
Started Jan 21 04:07:34 PM PST 24
Finished Jan 21 04:07:38 PM PST 24
Peak memory 199088 kb
Host smart-c11179bf-bcba-4797-bae3-11169543d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753112487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2753112487
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3606922229
Short name T220
Test name
Test status
Simulation time 4724280580 ps
CPU time 47.36 seconds
Started Jan 21 04:07:37 PM PST 24
Finished Jan 21 04:08:25 PM PST 24
Peak memory 207424 kb
Host smart-f92a2843-a259-4f70-90d6-f66abe4fd5e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606922229 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3606922229
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.3402663177
Short name T506
Test name
Test status
Simulation time 46189855862 ps
CPU time 760.07 seconds
Started Jan 21 04:07:36 PM PST 24
Finished Jan 21 04:20:18 PM PST 24
Peak memory 244856 kb
Host smart-689c741c-8083-4fde-b85c-2de11ff30621
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402663177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.3402663177
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1466655411
Short name T598
Test name
Test status
Simulation time 52642516 ps
CPU time 1.15 seconds
Started Jan 21 04:07:39 PM PST 24
Finished Jan 21 04:07:42 PM PST 24
Peak memory 197624 kb
Host smart-d98b6506-a5a8-458d-b2a9-aeea49864fe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466655411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1466655411
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.674434531
Short name T392
Test name
Test status
Simulation time 24714672522 ps
CPU time 400.66 seconds
Started Jan 21 04:07:37 PM PST 24
Finished Jan 21 04:14:19 PM PST 24
Peak memory 199040 kb
Host smart-db4f056a-3989-407d-b2d8-4be5056fe240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674434531 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.hmac_test_sha_vectors.674434531
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.723423503
Short name T686
Test name
Test status
Simulation time 3385226081 ps
CPU time 60.28 seconds
Started Jan 21 04:07:39 PM PST 24
Finished Jan 21 04:08:41 PM PST 24
Peak memory 199092 kb
Host smart-6ed06074-5eb6-48a2-ac5b-d143a81ca98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723423503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.723423503
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4158375900
Short name T356
Test name
Test status
Simulation time 23739877 ps
CPU time 0.63 seconds
Started Jan 21 04:32:38 PM PST 24
Finished Jan 21 04:32:40 PM PST 24
Peak memory 193660 kb
Host smart-29060ee5-41ce-41e6-8573-d15b9d1b32c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158375900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4158375900
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4092881084
Short name T464
Test name
Test status
Simulation time 5792553616 ps
CPU time 42.37 seconds
Started Jan 21 04:07:44 PM PST 24
Finished Jan 21 04:08:28 PM PST 24
Peak memory 220964 kb
Host smart-e9e16c2e-496a-4012-9f3d-6ec03d83ccc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092881084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4092881084
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3049278377
Short name T219
Test name
Test status
Simulation time 1533436052 ps
CPU time 31.99 seconds
Started Jan 21 04:07:43 PM PST 24
Finished Jan 21 04:08:16 PM PST 24
Peak memory 199184 kb
Host smart-8e52fabc-78fd-4bf8-b7a4-3166fadddbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049278377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3049278377
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2549496601
Short name T286
Test name
Test status
Simulation time 3536159595 ps
CPU time 46.48 seconds
Started Jan 21 04:07:45 PM PST 24
Finished Jan 21 04:08:32 PM PST 24
Peak memory 199104 kb
Host smart-03e70998-49b0-4143-9ae5-d4b0d0998169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549496601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2549496601
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.626626735
Short name T734
Test name
Test status
Simulation time 65064428424 ps
CPU time 81.86 seconds
Started Jan 21 04:07:47 PM PST 24
Finished Jan 21 04:09:12 PM PST 24
Peak memory 199148 kb
Host smart-0b934909-49b7-4669-89e8-9dedf3c38f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626626735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.626626735
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2902769716
Short name T480
Test name
Test status
Simulation time 4906859476 ps
CPU time 63.16 seconds
Started Jan 21 04:07:40 PM PST 24
Finished Jan 21 04:08:44 PM PST 24
Peak memory 199172 kb
Host smart-5e416214-713a-4238-8c5e-49e9431db37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902769716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2902769716
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3446655999
Short name T194
Test name
Test status
Simulation time 64434981 ps
CPU time 0.67 seconds
Started Jan 21 04:07:40 PM PST 24
Finished Jan 21 04:07:42 PM PST 24
Peak memory 194780 kb
Host smart-aeff5f5f-11e2-4bcd-a9eb-999a99c8edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446655999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3446655999
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4139630206
Short name T696
Test name
Test status
Simulation time 84948528690 ps
CPU time 1061.8 seconds
Started Jan 21 04:07:54 PM PST 24
Finished Jan 21 04:25:37 PM PST 24
Peak memory 207340 kb
Host smart-50e2aea0-0512-4af3-9ec7-7bc99d6ce6df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139630206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4139630206
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.725954105
Short name T573
Test name
Test status
Simulation time 712600602285 ps
CPU time 1091.55 seconds
Started Jan 21 04:07:53 PM PST 24
Finished Jan 21 04:26:06 PM PST 24
Peak memory 260736 kb
Host smart-cb8fcd9c-7cf3-453b-a46c-d41221cb3227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725954105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.725954105
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.11368966
Short name T720
Test name
Test status
Simulation time 220779557 ps
CPU time 1.18 seconds
Started Jan 21 04:07:44 PM PST 24
Finished Jan 21 04:07:46 PM PST 24
Peak memory 196888 kb
Host smart-04452039-22ee-43dc-9cc6-f608da4a927f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368966 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_hmac_vectors.11368966
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.931825988
Short name T632
Test name
Test status
Simulation time 125872280432 ps
CPU time 481.83 seconds
Started Jan 21 04:07:48 PM PST 24
Finished Jan 21 04:15:53 PM PST 24
Peak memory 199308 kb
Host smart-8218ca37-88c5-40b5-aede-39f00056298e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931825988 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_sha_vectors.931825988
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2829599125
Short name T638
Test name
Test status
Simulation time 41721111519 ps
CPU time 67.44 seconds
Started Jan 21 04:07:44 PM PST 24
Finished Jan 21 04:08:52 PM PST 24
Peak memory 199116 kb
Host smart-9e1c5ac0-82f6-456d-80f6-1f6fcce6380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829599125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2829599125
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1811949897
Short name T772
Test name
Test status
Simulation time 44416023 ps
CPU time 0.55 seconds
Started Jan 21 04:07:52 PM PST 24
Finished Jan 21 04:07:54 PM PST 24
Peak memory 192504 kb
Host smart-9282fc78-d2f9-4187-b2c7-6ab48a3fa2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811949897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1811949897
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3660905096
Short name T584
Test name
Test status
Simulation time 506872020 ps
CPU time 7.24 seconds
Started Jan 21 04:07:56 PM PST 24
Finished Jan 21 04:08:05 PM PST 24
Peak memory 199020 kb
Host smart-42f66ee4-bffe-49e1-9b3a-74dc4d4b52da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660905096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3660905096
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2780592088
Short name T322
Test name
Test status
Simulation time 25538596272 ps
CPU time 38.44 seconds
Started Jan 21 04:07:55 PM PST 24
Finished Jan 21 04:08:36 PM PST 24
Peak memory 199204 kb
Host smart-59588918-50fa-4aef-8703-c14f78788c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780592088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2780592088
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1872628101
Short name T754
Test name
Test status
Simulation time 867944650 ps
CPU time 43.89 seconds
Started Jan 21 04:07:54 PM PST 24
Finished Jan 21 04:08:39 PM PST 24
Peak memory 199064 kb
Host smart-f7464c45-c5cb-4e6b-95ba-76489b62d19e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872628101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1872628101
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3830652438
Short name T468
Test name
Test status
Simulation time 4672052950 ps
CPU time 16 seconds
Started Jan 21 04:07:52 PM PST 24
Finished Jan 21 04:08:09 PM PST 24
Peak memory 199136 kb
Host smart-b39ffc88-8d46-4740-ac73-b3355207b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830652438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3830652438
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1302568040
Short name T489
Test name
Test status
Simulation time 10909204758 ps
CPU time 47.28 seconds
Started Jan 21 04:07:56 PM PST 24
Finished Jan 21 04:08:45 PM PST 24
Peak memory 199084 kb
Host smart-f4dfdd08-e567-4165-8573-63e6f02d54e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302568040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1302568040
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.173489656
Short name T408
Test name
Test status
Simulation time 253929078 ps
CPU time 3.42 seconds
Started Jan 21 04:07:53 PM PST 24
Finished Jan 21 04:07:57 PM PST 24
Peak memory 198972 kb
Host smart-dbb13f7b-7652-47cc-a267-f65d82bd41cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173489656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.173489656
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.245780892
Short name T31
Test name
Test status
Simulation time 4835490197 ps
CPU time 197.08 seconds
Started Jan 21 04:07:55 PM PST 24
Finished Jan 21 04:11:14 PM PST 24
Peak memory 223784 kb
Host smart-15971f8b-aa32-4117-ad53-17b4c2f725e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245780892 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.245780892
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2977948368
Short name T779
Test name
Test status
Simulation time 288281566499 ps
CPU time 1165.33 seconds
Started Jan 21 04:26:27 PM PST 24
Finished Jan 21 04:45:59 PM PST 24
Peak memory 227404 kb
Host smart-9da0b3aa-9750-47b4-9f00-e020a959c255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977948368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.2977948368
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2341932307
Short name T845
Test name
Test status
Simulation time 88313770 ps
CPU time 1.16 seconds
Started Jan 21 04:07:55 PM PST 24
Finished Jan 21 04:07:58 PM PST 24
Peak memory 197380 kb
Host smart-4cf866e4-5f2f-428c-b1d0-43e7d54c392f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341932307 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2341932307
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.156095957
Short name T44
Test name
Test status
Simulation time 54958316271 ps
CPU time 455.34 seconds
Started Jan 21 04:07:53 PM PST 24
Finished Jan 21 04:15:30 PM PST 24
Peak memory 199088 kb
Host smart-0495e828-3835-4d53-98e9-906e196537b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156095957 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_test_sha_vectors.156095957
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.389392087
Short name T571
Test name
Test status
Simulation time 9522042294 ps
CPU time 53.84 seconds
Started Jan 21 04:07:57 PM PST 24
Finished Jan 21 04:08:52 PM PST 24
Peak memory 199096 kb
Host smart-f855421d-d1e0-4865-908b-f2ea86df9d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389392087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.389392087
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1311636376
Short name T709
Test name
Test status
Simulation time 37161429 ps
CPU time 0.58 seconds
Started Jan 21 06:06:41 PM PST 24
Finished Jan 21 06:06:44 PM PST 24
Peak memory 193564 kb
Host smart-f0828341-dfd9-4a74-b726-f78d11938bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311636376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1311636376
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2886902755
Short name T741
Test name
Test status
Simulation time 1645798781 ps
CPU time 10.26 seconds
Started Jan 21 04:02:10 PM PST 24
Finished Jan 21 04:02:22 PM PST 24
Peak memory 207296 kb
Host smart-c78403de-15f7-4874-bfe7-f6639a14b227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886902755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2886902755
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3525355533
Short name T499
Test name
Test status
Simulation time 320098080 ps
CPU time 3.19 seconds
Started Jan 21 04:02:08 PM PST 24
Finished Jan 21 04:02:14 PM PST 24
Peak memory 199128 kb
Host smart-8e78d771-c49e-41f6-8f79-360eadce7325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525355533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3525355533
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3731422667
Short name T641
Test name
Test status
Simulation time 7121086146 ps
CPU time 87.45 seconds
Started Jan 21 04:02:06 PM PST 24
Finished Jan 21 04:03:37 PM PST 24
Peak memory 199160 kb
Host smart-ffc6c0cf-08cf-4b4f-90d2-fc242e0c6ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731422667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3731422667
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2257613960
Short name T218
Test name
Test status
Simulation time 3887071320 ps
CPU time 104.22 seconds
Started Jan 21 04:14:38 PM PST 24
Finished Jan 21 04:16:23 PM PST 24
Peak memory 199124 kb
Host smart-af7be725-31b6-4b3c-9ae0-2c9604e64895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257613960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2257613960
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2257046031
Short name T474
Test name
Test status
Simulation time 49868963 ps
CPU time 0.69 seconds
Started Jan 21 04:25:35 PM PST 24
Finished Jan 21 04:25:36 PM PST 24
Peak memory 194612 kb
Host smart-9e42c9ba-37b1-43d5-88ff-8500238a2fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257046031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2257046031
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1924064506
Short name T718
Test name
Test status
Simulation time 795250374 ps
CPU time 2.88 seconds
Started Jan 21 04:02:10 PM PST 24
Finished Jan 21 04:02:14 PM PST 24
Peak memory 198836 kb
Host smart-36d56a93-062f-430d-a895-14c59a508504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924064506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1924064506
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2572132665
Short name T110
Test name
Test status
Simulation time 7921596227 ps
CPU time 130.77 seconds
Started Jan 21 04:02:13 PM PST 24
Finished Jan 21 04:04:25 PM PST 24
Peak memory 199200 kb
Host smart-56b43900-864e-41d8-b4f6-47bf803fd596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572132665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2572132665
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1570630445
Short name T407
Test name
Test status
Simulation time 166697886933 ps
CPU time 1533.3 seconds
Started Jan 21 04:02:20 PM PST 24
Finished Jan 21 04:27:58 PM PST 24
Peak memory 255804 kb
Host smart-04d8a556-fe98-4a6e-a57a-4fd2e0a6a585
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570630445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1570630445
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4275305951
Short name T354
Test name
Test status
Simulation time 39202739 ps
CPU time 0.89 seconds
Started Jan 21 04:02:15 PM PST 24
Finished Jan 21 04:02:16 PM PST 24
Peak memory 196292 kb
Host smart-652c6e39-27bb-4b6a-aac7-167f7d28c605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275305951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.4275305951
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2740903162
Short name T849
Test name
Test status
Simulation time 34392193752 ps
CPU time 470.97 seconds
Started Jan 21 05:37:00 PM PST 24
Finished Jan 21 05:44:55 PM PST 24
Peak memory 199128 kb
Host smart-57ee677e-2a95-4d05-811c-ef344c0060b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740903162 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2740903162
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1343108884
Short name T572
Test name
Test status
Simulation time 4428957135 ps
CPU time 15.81 seconds
Started Jan 21 04:02:14 PM PST 24
Finished Jan 21 04:02:31 PM PST 24
Peak memory 199176 kb
Host smart-7bfc4014-bf07-4e6f-95f8-20cbbf62faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343108884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1343108884
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.3715662982
Short name T782
Test name
Test status
Simulation time 32713898429 ps
CPU time 253.81 seconds
Started Jan 21 04:08:00 PM PST 24
Finished Jan 21 04:12:15 PM PST 24
Peak memory 215728 kb
Host smart-4c87b5a6-9da4-4a0c-8a1a-18fffdd3ec5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715662982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.3715662982
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.1605613766
Short name T691
Test name
Test status
Simulation time 128140251795 ps
CPU time 1186.61 seconds
Started Jan 21 04:07:59 PM PST 24
Finished Jan 21 04:27:47 PM PST 24
Peak memory 248400 kb
Host smart-2bcf200d-8ed6-4ac3-8850-a83c2bef7d13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605613766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.1605613766
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.2180495746
Short name T361
Test name
Test status
Simulation time 16362649617 ps
CPU time 305.26 seconds
Started Jan 21 04:08:05 PM PST 24
Finished Jan 21 04:13:14 PM PST 24
Peak memory 215712 kb
Host smart-6e19acc6-60a8-4851-b158-fbed4f282507
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180495746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.2180495746
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2330385979
Short name T376
Test name
Test status
Simulation time 44762292695 ps
CPU time 820.35 seconds
Started Jan 21 04:08:03 PM PST 24
Finished Jan 21 04:21:47 PM PST 24
Peak memory 240320 kb
Host smart-c2b8c88a-a12c-4a37-be79-b803a75febaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330385979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2330385979
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3055829564
Short name T637
Test name
Test status
Simulation time 334973299501 ps
CPU time 1684.81 seconds
Started Jan 21 04:08:01 PM PST 24
Finished Jan 21 04:36:08 PM PST 24
Peak memory 235144 kb
Host smart-c73438bb-3887-4329-b9aa-491a677dc565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055829564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.3055829564
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.824925206
Short name T784
Test name
Test status
Simulation time 60506039060 ps
CPU time 2642.33 seconds
Started Jan 21 04:08:02 PM PST 24
Finished Jan 21 04:52:05 PM PST 24
Peak memory 256732 kb
Host smart-f0bfc13c-1649-4709-ba51-8c2702a78c5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824925206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.824925206
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.3577315102
Short name T62
Test name
Test status
Simulation time 65468090867 ps
CPU time 1853.6 seconds
Started Jan 21 04:07:59 PM PST 24
Finished Jan 21 04:38:54 PM PST 24
Peak memory 223884 kb
Host smart-4ec06a3f-29c4-4369-9dd5-91aa06e4340e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577315102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.3577315102
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.2325654619
Short name T666
Test name
Test status
Simulation time 172782501361 ps
CPU time 840.41 seconds
Started Jan 21 05:58:37 PM PST 24
Finished Jan 21 06:12:39 PM PST 24
Peak memory 223984 kb
Host smart-53e4537d-7932-4cba-b042-9b58d2188b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325654619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.2325654619
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.1191788139
Short name T39
Test name
Test status
Simulation time 215694812038 ps
CPU time 1978.73 seconds
Started Jan 21 04:08:03 PM PST 24
Finished Jan 21 04:41:04 PM PST 24
Peak memory 262312 kb
Host smart-44abe550-df64-4212-959c-2aff09a66d1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191788139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.1191788139
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.2193455753
Short name T840
Test name
Test status
Simulation time 30686224991 ps
CPU time 241.22 seconds
Started Jan 21 04:08:03 PM PST 24
Finished Jan 21 04:12:07 PM PST 24
Peak memory 207532 kb
Host smart-5c3100cd-5bc5-4555-ad2c-14d8937344a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193455753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.2193455753
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2444290364
Short name T502
Test name
Test status
Simulation time 31388740 ps
CPU time 0.55 seconds
Started Jan 21 04:02:27 PM PST 24
Finished Jan 21 04:02:37 PM PST 24
Peak memory 192500 kb
Host smart-06ad136f-eca3-42fb-9ae5-542e37d19e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444290364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2444290364
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.390378264
Short name T682
Test name
Test status
Simulation time 4418120631 ps
CPU time 30.5 seconds
Started Jan 21 04:02:13 PM PST 24
Finished Jan 21 04:02:45 PM PST 24
Peak memory 207360 kb
Host smart-b4bf3927-903e-46da-aae7-780f56bc32d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390378264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.390378264
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3659868204
Short name T837
Test name
Test status
Simulation time 1783673241 ps
CPU time 16.1 seconds
Started Jan 21 04:02:14 PM PST 24
Finished Jan 21 04:02:31 PM PST 24
Peak memory 199064 kb
Host smart-d7c9d1ac-5c31-4876-85fa-f5709daefa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659868204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3659868204
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1655068349
Short name T554
Test name
Test status
Simulation time 733600764 ps
CPU time 17.04 seconds
Started Jan 21 04:02:17 PM PST 24
Finished Jan 21 04:02:40 PM PST 24
Peak memory 199048 kb
Host smart-2ea04fbd-bbb9-4c04-b87f-f1f59ad9b1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655068349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1655068349
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.447920542
Short name T665
Test name
Test status
Simulation time 2051950135 ps
CPU time 32.17 seconds
Started Jan 21 04:02:15 PM PST 24
Finished Jan 21 04:02:48 PM PST 24
Peak memory 199160 kb
Host smart-020d091a-9bbb-499e-b973-ef6492374874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447920542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.447920542
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3497871114
Short name T321
Test name
Test status
Simulation time 799301391 ps
CPU time 34.94 seconds
Started Jan 21 04:02:18 PM PST 24
Finished Jan 21 04:02:58 PM PST 24
Peak memory 199064 kb
Host smart-be97dde8-362b-4b47-86cd-c9f3a3746d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497871114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3497871114
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1835162953
Short name T538
Test name
Test status
Simulation time 124251956 ps
CPU time 1.84 seconds
Started Jan 21 04:02:12 PM PST 24
Finished Jan 21 04:02:16 PM PST 24
Peak memory 199124 kb
Host smart-4790e29d-e1c7-4cfe-a76a-70148417762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835162953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1835162953
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.35266770
Short name T132
Test name
Test status
Simulation time 45483939604 ps
CPU time 796.15 seconds
Started Jan 21 04:02:30 PM PST 24
Finished Jan 21 04:15:54 PM PST 24
Peak memory 240216 kb
Host smart-3d8fb43b-493c-4945-a325-9ee604696090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35266770 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.35266770
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3567457054
Short name T259
Test name
Test status
Simulation time 91633359481 ps
CPU time 340.15 seconds
Started Jan 21 04:02:25 PM PST 24
Finished Jan 21 04:08:12 PM PST 24
Peak memory 243244 kb
Host smart-0c6f15fb-2dc2-4dd3-bfbb-102a52dcc6ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3567457054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3567457054
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.904530373
Short name T216
Test name
Test status
Simulation time 59543381 ps
CPU time 1.07 seconds
Started Jan 21 04:02:18 PM PST 24
Finished Jan 21 04:02:24 PM PST 24
Peak memory 196460 kb
Host smart-2a2541df-5dea-41f4-9571-ece02730788d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904530373 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.904530373
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1914653819
Short name T825
Test name
Test status
Simulation time 158796565054 ps
CPU time 482.56 seconds
Started Jan 21 04:02:15 PM PST 24
Finished Jan 21 04:10:18 PM PST 24
Peak memory 199084 kb
Host smart-3b01714a-647d-4c82-8387-a04cf41559bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914653819 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.1914653819
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2005722084
Short name T488
Test name
Test status
Simulation time 9271316112 ps
CPU time 90.32 seconds
Started Jan 21 05:13:30 PM PST 24
Finished Jan 21 05:16:04 PM PST 24
Peak memory 199224 kb
Host smart-e36c2726-a365-4ba5-8a58-6f5d280a7c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005722084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2005722084
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.3849275949
Short name T829
Test name
Test status
Simulation time 71353028973 ps
CPU time 1016.87 seconds
Started Jan 21 04:08:03 PM PST 24
Finished Jan 21 04:25:04 PM PST 24
Peak memory 207572 kb
Host smart-13fa115d-80cb-4c8a-9bbe-1c6a2110d4e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849275949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.3849275949
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.2504300202
Short name T117
Test name
Test status
Simulation time 83491547779 ps
CPU time 1367.29 seconds
Started Jan 21 04:08:01 PM PST 24
Finished Jan 21 04:30:50 PM PST 24
Peak memory 248468 kb
Host smart-932dd012-9d3d-4cf6-b070-cab967732eec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504300202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.2504300202
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.222019900
Short name T633
Test name
Test status
Simulation time 116994239530 ps
CPU time 2054.16 seconds
Started Jan 21 04:08:07 PM PST 24
Finished Jan 21 04:42:25 PM PST 24
Peak memory 247464 kb
Host smart-6de3f552-5268-4f81-9500-94f363cc818d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222019900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.222019900
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.581398108
Short name T714
Test name
Test status
Simulation time 34341477239 ps
CPU time 331.74 seconds
Started Jan 21 04:50:47 PM PST 24
Finished Jan 21 04:56:23 PM PST 24
Peak memory 207584 kb
Host smart-92d00855-0004-4535-bf42-ae67c67b5fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581398108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.581398108
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.2223625910
Short name T234
Test name
Test status
Simulation time 178415087813 ps
CPU time 678.15 seconds
Started Jan 21 04:08:05 PM PST 24
Finished Jan 21 04:19:27 PM PST 24
Peak memory 240336 kb
Host smart-482828d4-b0e7-4c0d-897f-9bf51ce66f44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223625910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.2223625910
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3415908552
Short name T710
Test name
Test status
Simulation time 345964960088 ps
CPU time 1846.85 seconds
Started Jan 21 04:56:53 PM PST 24
Finished Jan 21 05:27:40 PM PST 24
Peak memory 244604 kb
Host smart-0eccc079-76c4-4f32-8d77-52ed208a343c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415908552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3415908552
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1871439125
Short name T541
Test name
Test status
Simulation time 680678063869 ps
CPU time 2138.04 seconds
Started Jan 21 04:08:05 PM PST 24
Finished Jan 21 04:43:47 PM PST 24
Peak memory 228300 kb
Host smart-13ece5d0-23f8-43d2-9812-ca4c19993208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871439125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.1871439125
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.3463567953
Short name T560
Test name
Test status
Simulation time 161183514496 ps
CPU time 2235.55 seconds
Started Jan 21 04:49:26 PM PST 24
Finished Jan 21 05:26:43 PM PST 24
Peak memory 257136 kb
Host smart-7730a82a-bfa2-4ddd-9d0f-98218cb1142a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463567953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.3463567953
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.911119838
Short name T545
Test name
Test status
Simulation time 22457323622 ps
CPU time 449.91 seconds
Started Jan 21 04:30:43 PM PST 24
Finished Jan 21 04:38:13 PM PST 24
Peak memory 207736 kb
Host smart-850d35f5-b6ec-44d6-84ef-a3f213be3ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911119838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.911119838
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1408475386
Short name T414
Test name
Test status
Simulation time 19563144 ps
CPU time 0.56 seconds
Started Jan 21 04:02:37 PM PST 24
Finished Jan 21 04:02:45 PM PST 24
Peak memory 193464 kb
Host smart-06d57c87-1d46-4aa3-832f-1eed244f8151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408475386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1408475386
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4294326631
Short name T777
Test name
Test status
Simulation time 1089692940 ps
CPU time 10.05 seconds
Started Jan 21 04:02:31 PM PST 24
Finished Jan 21 04:02:48 PM PST 24
Peak memory 209280 kb
Host smart-bf255dfe-73ec-437a-8450-f365e970ec0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294326631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4294326631
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4127154721
Short name T459
Test name
Test status
Simulation time 2756562743 ps
CPU time 49.83 seconds
Started Jan 21 04:02:37 PM PST 24
Finished Jan 21 04:03:34 PM PST 24
Peak memory 199080 kb
Host smart-8221f47b-54e4-4873-8d55-e343e20c6b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127154721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4127154721
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3305776201
Short name T35
Test name
Test status
Simulation time 1722190330 ps
CPU time 76.44 seconds
Started Jan 21 04:55:27 PM PST 24
Finished Jan 21 04:56:45 PM PST 24
Peak memory 199156 kb
Host smart-8131bb98-8642-4b4f-b41e-3a9abb886da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305776201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3305776201
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2658152395
Short name T712
Test name
Test status
Simulation time 15299507431 ps
CPU time 187.66 seconds
Started Jan 21 04:02:37 PM PST 24
Finished Jan 21 04:05:52 PM PST 24
Peak memory 199112 kb
Host smart-3cdaefdc-2fd6-430c-a37c-614141e450a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658152395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2658152395
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4037160673
Short name T326
Test name
Test status
Simulation time 4011272712 ps
CPU time 54.64 seconds
Started Jan 21 04:02:37 PM PST 24
Finished Jan 21 04:03:39 PM PST 24
Peak memory 199116 kb
Host smart-070e39c6-2db5-4adc-b855-c8d48d7e41b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037160673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4037160673
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1298495674
Short name T576
Test name
Test status
Simulation time 443588712 ps
CPU time 1.77 seconds
Started Jan 21 06:09:49 PM PST 24
Finished Jan 21 06:09:57 PM PST 24
Peak memory 198828 kb
Host smart-7eb45993-a8b3-4de0-ab23-b4a07eac12e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298495674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1298495674
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3232366336
Short name T61
Test name
Test status
Simulation time 333996972852 ps
CPU time 973.96 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:19:00 PM PST 24
Peak memory 199208 kb
Host smart-1e6686e9-e6d5-43fe-8770-94c4c5773a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232366336 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3232366336
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.4121571619
Short name T543
Test name
Test status
Simulation time 50382890743 ps
CPU time 477.46 seconds
Started Jan 21 05:41:36 PM PST 24
Finished Jan 21 05:49:40 PM PST 24
Peak memory 223968 kb
Host smart-fa6434f9-045d-41ff-a956-44f58031828b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121571619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4121571619
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1656097742
Short name T248
Test name
Test status
Simulation time 69905023 ps
CPU time 1.32 seconds
Started Jan 21 04:53:50 PM PST 24
Finished Jan 21 04:53:52 PM PST 24
Peak memory 198292 kb
Host smart-bd647f48-027b-417c-a3b6-ea5e8fd780ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656097742 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1656097742
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1273774589
Short name T619
Test name
Test status
Simulation time 8179716403 ps
CPU time 409.68 seconds
Started Jan 21 04:02:31 PM PST 24
Finished Jan 21 04:09:28 PM PST 24
Peak memory 199124 kb
Host smart-1ed99bf0-06bb-4d64-ae69-3a900249d1ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273774589 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.1273774589
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4181023979
Short name T791
Test name
Test status
Simulation time 3665230871 ps
CPU time 60.42 seconds
Started Jan 21 04:02:39 PM PST 24
Finished Jan 21 04:03:46 PM PST 24
Peak memory 199168 kb
Host smart-111572f4-e5be-4f19-8204-1085c72a4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181023979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4181023979
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2311844622
Short name T473
Test name
Test status
Simulation time 253102306126 ps
CPU time 3304.56 seconds
Started Jan 21 04:08:13 PM PST 24
Finished Jan 21 05:03:19 PM PST 24
Peak memory 248480 kb
Host smart-e26fcdb9-b2d7-4ebb-abe7-deb76fe26255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311844622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2311844622
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.2799931761
Short name T278
Test name
Test status
Simulation time 30970696377 ps
CPU time 636.02 seconds
Started Jan 21 05:26:30 PM PST 24
Finished Jan 21 05:37:08 PM PST 24
Peak memory 228512 kb
Host smart-156689e4-1a99-49ff-8845-937fb2e7cecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799931761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.2799931761
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2183629255
Short name T684
Test name
Test status
Simulation time 82063590184 ps
CPU time 3099.17 seconds
Started Jan 21 04:08:14 PM PST 24
Finished Jan 21 04:59:55 PM PST 24
Peak memory 256708 kb
Host smart-65dc2739-4000-41ca-89b3-5d16fac02ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183629255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2183629255
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.814782297
Short name T544
Test name
Test status
Simulation time 85344370896 ps
CPU time 1430 seconds
Started Jan 21 04:32:28 PM PST 24
Finished Jan 21 04:56:19 PM PST 24
Peak memory 256684 kb
Host smart-17708fd5-852d-47f0-99fa-ec9fe9c41c1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814782297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.814782297
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.1140693062
Short name T316
Test name
Test status
Simulation time 54443286590 ps
CPU time 2599.14 seconds
Started Jan 21 04:08:22 PM PST 24
Finished Jan 21 04:51:44 PM PST 24
Peak memory 248428 kb
Host smart-05aa140f-39c9-43ee-9350-62bf53b1a920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140693062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.1140693062
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.4123323320
Short name T697
Test name
Test status
Simulation time 60701323927 ps
CPU time 1822.01 seconds
Started Jan 21 04:42:38 PM PST 24
Finished Jan 21 05:13:01 PM PST 24
Peak memory 223960 kb
Host smart-b329e2c7-d42f-4a5f-b829-5ba57a3dc1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123323320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.4123323320
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.4039879457
Short name T705
Test name
Test status
Simulation time 61443017413 ps
CPU time 927.44 seconds
Started Jan 21 04:08:22 PM PST 24
Finished Jan 21 04:23:52 PM PST 24
Peak memory 243388 kb
Host smart-c711ed47-a8d6-476e-8ab0-b27cd2b91bb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039879457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.4039879457
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3090807173
Short name T424
Test name
Test status
Simulation time 25059926 ps
CPU time 0.55 seconds
Started Jan 21 04:02:51 PM PST 24
Finished Jan 21 04:02:53 PM PST 24
Peak memory 192644 kb
Host smart-59b98944-65a7-489b-bc54-f41f081fab67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090807173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3090807173
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1741137287
Short name T814
Test name
Test status
Simulation time 16406281396 ps
CPU time 32.45 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 231960 kb
Host smart-2e85e697-6f33-49d5-afaf-5ed5e7d39c82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741137287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1741137287
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.729855820
Short name T241
Test name
Test status
Simulation time 12702163154 ps
CPU time 12.33 seconds
Started Jan 21 04:02:45 PM PST 24
Finished Jan 21 04:02:59 PM PST 24
Peak memory 199184 kb
Host smart-2494032a-e4b3-43d3-b40e-635b914ae2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729855820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.729855820
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.106761734
Short name T436
Test name
Test status
Simulation time 14692551943 ps
CPU time 101.15 seconds
Started Jan 21 04:26:58 PM PST 24
Finished Jan 21 04:28:44 PM PST 24
Peak memory 199104 kb
Host smart-7bd590de-5adf-41d3-a712-7eface83bfe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106761734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.106761734
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.899822308
Short name T191
Test name
Test status
Simulation time 3638877662 ps
CPU time 174.35 seconds
Started Jan 21 04:02:41 PM PST 24
Finished Jan 21 04:05:40 PM PST 24
Peak memory 199188 kb
Host smart-26478bdd-e4dc-49bf-8388-7ae01f16a809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899822308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.899822308
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1947006840
Short name T339
Test name
Test status
Simulation time 944123396 ps
CPU time 3.53 seconds
Started Jan 21 04:02:48 PM PST 24
Finished Jan 21 04:02:52 PM PST 24
Peak memory 199076 kb
Host smart-5bbf0089-ee7d-46e1-abf3-79a9669ae978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947006840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1947006840
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4244576287
Short name T534
Test name
Test status
Simulation time 165247501 ps
CPU time 0.95 seconds
Started Jan 21 04:02:33 PM PST 24
Finished Jan 21 04:02:42 PM PST 24
Peak memory 197488 kb
Host smart-d179a117-6d8b-4b14-b47a-cd9b240f676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244576287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4244576287
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1352174250
Short name T431
Test name
Test status
Simulation time 62156462813 ps
CPU time 690.81 seconds
Started Jan 21 04:02:48 PM PST 24
Finished Jan 21 04:14:20 PM PST 24
Peak memory 223808 kb
Host smart-8043e721-d81f-4fe8-818c-bc3bd44a431e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352174250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1352174250
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1542641838
Short name T434
Test name
Test status
Simulation time 633823898 ps
CPU time 1.43 seconds
Started Jan 21 05:16:55 PM PST 24
Finished Jan 21 05:16:57 PM PST 24
Peak memory 197236 kb
Host smart-62c116f4-6711-4808-a05f-19013fda8a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542641838 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1542641838
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.4131196881
Short name T516
Test name
Test status
Simulation time 45136101438 ps
CPU time 564.55 seconds
Started Jan 21 04:30:26 PM PST 24
Finished Jan 21 04:39:52 PM PST 24
Peak memory 199140 kb
Host smart-87e59f71-761b-4d08-a7f6-a6897dab4c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131196881 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.4131196881
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3072730102
Short name T597
Test name
Test status
Simulation time 995665245 ps
CPU time 15.12 seconds
Started Jan 21 04:02:47 PM PST 24
Finished Jan 21 04:03:03 PM PST 24
Peak memory 199120 kb
Host smart-53e23bc2-b6ec-43d0-9749-038b62e9b1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072730102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3072730102
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.3743677457
Short name T113
Test name
Test status
Simulation time 215377373422 ps
CPU time 1194.03 seconds
Started Jan 21 04:51:22 PM PST 24
Finished Jan 21 05:11:17 PM PST 24
Peak memory 246016 kb
Host smart-f8b181a5-0b7d-4376-9d99-afc97bdebb6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743677457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.3743677457
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4106319666
Short name T475
Test name
Test status
Simulation time 99361536664 ps
CPU time 618.26 seconds
Started Jan 21 05:11:22 PM PST 24
Finished Jan 21 05:21:42 PM PST 24
Peak memory 215936 kb
Host smart-0d1f544d-04ce-4c40-a64e-8d202515b9d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106319666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.4106319666
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.69105698
Short name T445
Test name
Test status
Simulation time 92544216923 ps
CPU time 2837.52 seconds
Started Jan 21 04:08:23 PM PST 24
Finished Jan 21 04:55:42 PM PST 24
Peak memory 256812 kb
Host smart-1a3fa768-8336-4bda-aeeb-bb4c42b9e8ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69105698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.69105698
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.4169291910
Short name T30
Test name
Test status
Simulation time 34589605579 ps
CPU time 1919.41 seconds
Started Jan 21 04:08:31 PM PST 24
Finished Jan 21 04:40:33 PM PST 24
Peak memory 240320 kb
Host smart-b429379d-7ab1-40a8-9664-7044f5c3f92a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169291910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.4169291910
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3552356815
Short name T32
Test name
Test status
Simulation time 126090950315 ps
CPU time 1689 seconds
Started Jan 21 04:08:27 PM PST 24
Finished Jan 21 04:36:36 PM PST 24
Peak memory 260784 kb
Host smart-813ff7e3-befa-495b-9135-d5cf8f2b3e49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552356815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.3552356815
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.1273848169
Short name T482
Test name
Test status
Simulation time 69874760148 ps
CPU time 249.02 seconds
Started Jan 21 04:08:32 PM PST 24
Finished Jan 21 04:12:43 PM PST 24
Peak memory 207696 kb
Host smart-0a2149c2-3e97-4c7d-a3f9-9dd5c6862369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273848169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.1273848169
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.3064401111
Short name T518
Test name
Test status
Simulation time 103152770649 ps
CPU time 444.09 seconds
Started Jan 21 04:45:21 PM PST 24
Finished Jan 21 04:52:52 PM PST 24
Peak memory 244632 kb
Host smart-813969be-b4d0-4501-83a4-bf1cc92ab42a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064401111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.3064401111
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2851515657
Short name T457
Test name
Test status
Simulation time 1300372480633 ps
CPU time 2578.83 seconds
Started Jan 21 04:08:32 PM PST 24
Finished Jan 21 04:51:33 PM PST 24
Peak memory 254716 kb
Host smart-46b3df0a-07fb-47f4-b8c5-215d9b58c200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851515657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.2851515657
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3812219117
Short name T426
Test name
Test status
Simulation time 110933274624 ps
CPU time 688.16 seconds
Started Jan 21 04:08:26 PM PST 24
Finished Jan 21 04:19:54 PM PST 24
Peak memory 245896 kb
Host smart-ff7acb2e-cd29-4042-a1c0-c11ce6b00219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812219117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.3812219117
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.1416512413
Short name T374
Test name
Test status
Simulation time 53902064105 ps
CPU time 1089.15 seconds
Started Jan 21 04:08:30 PM PST 24
Finished Jan 21 04:26:42 PM PST 24
Peak memory 256716 kb
Host smart-42e74d24-ad4c-475c-a165-2c7c8b80468f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416512413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.1416512413
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.797138542
Short name T708
Test name
Test status
Simulation time 13470505 ps
CPU time 0.58 seconds
Started Jan 21 05:13:33 PM PST 24
Finished Jan 21 05:14:35 PM PST 24
Peak memory 193572 kb
Host smart-60308104-c874-4835-b18c-2b89e657724d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797138542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.797138542
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1211050655
Short name T618
Test name
Test status
Simulation time 394520015 ps
CPU time 11.31 seconds
Started Jan 21 04:02:49 PM PST 24
Finished Jan 21 04:03:03 PM PST 24
Peak memory 199076 kb
Host smart-0af1f7a5-c850-40d7-98ba-69d1a05e5195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211050655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1211050655
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.35268593
Short name T46
Test name
Test status
Simulation time 4049990413 ps
CPU time 16.98 seconds
Started Jan 21 04:02:50 PM PST 24
Finished Jan 21 04:03:09 PM PST 24
Peak memory 199152 kb
Host smart-f213ea68-f44a-4bf4-8dae-f293d9f1d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35268593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.35268593
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4262157475
Short name T386
Test name
Test status
Simulation time 989882361 ps
CPU time 29.64 seconds
Started Jan 21 04:02:51 PM PST 24
Finished Jan 21 04:03:22 PM PST 24
Peak memory 199284 kb
Host smart-48a91f6c-091c-4e84-b5b4-0bab3823f258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262157475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4262157475
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2896470814
Short name T743
Test name
Test status
Simulation time 20919733384 ps
CPU time 65.23 seconds
Started Jan 21 04:02:53 PM PST 24
Finished Jan 21 04:04:01 PM PST 24
Peak memory 199180 kb
Host smart-78760cc3-013d-4514-a20a-809cd064f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896470814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2896470814
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1681521504
Short name T359
Test name
Test status
Simulation time 32085684430 ps
CPU time 96.63 seconds
Started Jan 21 04:02:52 PM PST 24
Finished Jan 21 04:04:32 PM PST 24
Peak memory 199156 kb
Host smart-e52168e0-1131-4924-ba8b-1484c0625c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681521504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1681521504
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2543156183
Short name T345
Test name
Test status
Simulation time 203317264 ps
CPU time 4.09 seconds
Started Jan 21 04:36:46 PM PST 24
Finished Jan 21 04:36:51 PM PST 24
Peak memory 198808 kb
Host smart-29f21e26-4aa4-473d-b690-1625193c3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543156183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2543156183
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3592993934
Short name T324
Test name
Test status
Simulation time 147241205523 ps
CPU time 947.28 seconds
Started Jan 21 05:20:08 PM PST 24
Finished Jan 21 05:35:56 PM PST 24
Peak memory 223852 kb
Host smart-21136ada-f1b9-4bce-9e9b-3e983ac034df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592993934 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3592993934
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2215615590
Short name T204
Test name
Test status
Simulation time 66157468978 ps
CPU time 336.35 seconds
Started Jan 21 04:54:11 PM PST 24
Finished Jan 21 04:59:48 PM PST 24
Peak memory 226912 kb
Host smart-a5003d6c-94e1-4d65-bdd2-61b62d0ce76f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215615590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2215615590
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1468038974
Short name T429
Test name
Test status
Simulation time 103398138 ps
CPU time 1.17 seconds
Started Jan 21 04:31:58 PM PST 24
Finished Jan 21 04:32:00 PM PST 24
Peak memory 197576 kb
Host smart-e96c62a5-871f-430b-a05f-105828b788ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468038974 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1468038974
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.55236295
Short name T669
Test name
Test status
Simulation time 113091207256 ps
CPU time 377.39 seconds
Started Jan 21 04:02:53 PM PST 24
Finished Jan 21 04:09:14 PM PST 24
Peak memory 199156 kb
Host smart-076cb269-e341-4aad-a330-0ab16c8b3d7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55236295 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.hmac_test_sha_vectors.55236295
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1416347291
Short name T493
Test name
Test status
Simulation time 1333834213 ps
CPU time 63.39 seconds
Started Jan 21 04:02:52 PM PST 24
Finished Jan 21 04:03:58 PM PST 24
Peak memory 199104 kb
Host smart-d095ee32-b527-4fa0-a774-039b68ac87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416347291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1416347291
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1666235272
Short name T492
Test name
Test status
Simulation time 29960142082 ps
CPU time 175.2 seconds
Started Jan 21 04:14:58 PM PST 24
Finished Jan 21 04:17:55 PM PST 24
Peak memory 229120 kb
Host smart-3c661720-ee25-4700-b249-aafa91d2f7da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666235272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.1666235272
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.336165644
Short name T485
Test name
Test status
Simulation time 33577126121 ps
CPU time 593.47 seconds
Started Jan 21 04:08:28 PM PST 24
Finished Jan 21 04:18:23 PM PST 24
Peak memory 215728 kb
Host smart-bbce739a-eeb4-486f-a8a9-20cd350055c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336165644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.336165644
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.565840388
Short name T851
Test name
Test status
Simulation time 141501373819 ps
CPU time 1546.5 seconds
Started Jan 21 04:08:26 PM PST 24
Finished Jan 21 04:34:13 PM PST 24
Peak memory 247008 kb
Host smart-1189398c-0583-4197-811f-c19d5bf0c6bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565840388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.565840388
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.4070764852
Short name T350
Test name
Test status
Simulation time 72266263752 ps
CPU time 1103.45 seconds
Started Jan 21 04:08:35 PM PST 24
Finished Jan 21 04:27:00 PM PST 24
Peak memory 229540 kb
Host smart-d26e1244-224f-4efe-9eef-4740cb4feb0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070764852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.4070764852
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.1044068363
Short name T366
Test name
Test status
Simulation time 14467670927 ps
CPU time 164.53 seconds
Started Jan 21 04:08:34 PM PST 24
Finished Jan 21 04:11:20 PM PST 24
Peak memory 215648 kb
Host smart-761edf4f-b730-4764-a690-e22a20afa1af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044068363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.1044068363
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1390929396
Short name T496
Test name
Test status
Simulation time 23591597460 ps
CPU time 1104.84 seconds
Started Jan 21 04:08:35 PM PST 24
Finished Jan 21 04:27:02 PM PST 24
Peak memory 213104 kb
Host smart-2d6f3f44-fa20-41e4-9a61-44c40bf3e8f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390929396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1390929396
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1725174203
Short name T333
Test name
Test status
Simulation time 647465719425 ps
CPU time 1173.85 seconds
Started Jan 21 04:08:35 PM PST 24
Finished Jan 21 04:28:10 PM PST 24
Peak memory 247548 kb
Host smart-a04d1fd6-e8aa-4525-813c-0dddbdbb2f5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725174203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.1725174203
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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