Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	36207371	1			T14	8		T20	11		T21	4
all_values[1]	36207371	1			T14	8		T20	11		T21	4
all_values[2]	36207371	1			T14	8		T20	11		T21	4

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134083

1

T14

14

T20

22

T21

5

auto[1]

108488030

1

T14

10

T20

11

T21

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78349443

1

T14

17

T20

14

T21

8

auto[1]

30272670

1

T14

7

T20

19

T21

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38050	1			T14	1		T20	3		T21	2
all_values[0]	auto[0]	auto[1]	1291	1			T14	1		T20	4		T21	1
all_values[0]	auto[1]	auto[0]	36010830	1			T14	4		T20	2		T23	1
all_values[0]	auto[1]	auto[1]	157200	1			T14	2		T20	2		T21	1
all_values[1]	auto[0]	auto[0]	27638	1			T14	3		T20	4		T23	3
all_values[1]	auto[0]	auto[1]	17030	1			T14	2		T20	4		T21	1
all_values[1]	auto[1]	auto[0]	19971373	1			T14	3		T20	2		T21	2
all_values[1]	auto[1]	auto[1]	16191330	1			T20	1		T21	1		T59	1
all_values[2]	auto[0]	auto[0]	40345	1			T14	5		T20	1		T21	1
all_values[2]	auto[0]	auto[1]	9729	1			T14	2		T20	6		T23	2
all_values[2]	auto[1]	auto[0]	22261207	1			T14	1		T20	2		T21	3
all_values[2]	auto[1]	auto[1]	13896090	1			T20	2		T59	1		T73	2