Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18348576

1

T1

6020

T2

6134

T3

1585

auto[1]

8758593

1

T1

5942

T2

6390

T3

2445

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8607632

1

T1

6613

T2

5663

T3

3834

auto[1]

18499537

1

T1

5349

T2

6861

T3

196

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16189301

1

T1

7279

T2

8265

T3

404

auto[1]

10917868

1

T1

4683

T2

4259

T3

3626

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	15269378	1			T1	11084		T2	11919		T3	3509
fifo_depth[1]	1324465	1			T1	541		T2	345		T3	226
fifo_depth[2]	1189011	1			T1	245		T2	172		T3	167
fifo_depth[3]	1008079	1			T1	66		T2	61		T3	87
fifo_depth[4]	985144	1			T1	21		T2	21		T3	32
fifo_depth[5]	839075	1			T1	4		T2	6		T3	7
fifo_depth[6]	872914	1			T1	1		T3	1		T6	1128
fifo_depth[7]	743937	1			T6	1011		T7	1463		T8	791
fifo_depth[8]	916447	1			T3	1		T6	822		T7	1216
fifo_depth[9]	524049	1			T6	678		T7	935		T8	511
fifo_depth[10]	547925	1			T6	424		T7	579		T8	375
fifo_depth[11]	331925	1			T6	242		T7	352		T8	200
fifo_depth[12]	580898	1			T6	135		T7	189		T8	101
fifo_depth[13]	253556	1			T6	56		T7	86		T8	37
fifo_depth[14]	421277	1			T6	24		T7	43		T8	19
fifo_depth[15]	235759	1			T6	8		T7	11		T8	12
fifo_depth[16]	1063330	1			T6	5		T7	4		T8	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11837791

1

T1

878

T2

605

T3

521

auto[1]

15269378

1

T1

11084

T2

11919

T3

3509

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26043839

1

T1

11962

T2

12524

T3

4030

auto[1]

1063330

1

T6

5

T7

4

T8

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

849638

1

T1

252

T2

41

T4

2646

auto[0]

auto[0]

auto[0]

auto[1]

929593

1

T1

32

T2

203

T3

24

auto[0]

auto[0]

auto[1]

auto[0]

3226244

1

T1

45

T2

60

T9

2548

auto[0]

auto[0]

auto[1]

auto[1]

961775

1

T1

213

T2

45

T3

28

auto[0]

auto[1]

auto[0]

auto[0]

1456311

1

T1

101

T2

58

T3

192

auto[0]

auto[1]

auto[0]

auto[1]

1445571

1

T1

94

T2

59

T3

277

auto[0]

auto[1]

auto[1]

auto[0]

1513324

1

T1

35

T2

24

T6

4012

auto[0]

auto[1]

auto[1]

auto[1]

1455335

1

T1

106

T2

115

T6

2014

auto[1]

auto[0]

auto[0]

auto[0]

717073

1

T1

3133

T2

913

T4

1391

auto[1]

auto[0]

auto[0]

auto[1]

703003

1

T1

451

T2

2368

T3

184

auto[1]

auto[0]

auto[1]

auto[0]

8045410

1

T1

606

T2

3663

T3

1

auto[1]

auto[0]

auto[1]

auto[1]

756565

1

T1

2547

T2

972

T3

167

auto[1]

auto[1]

auto[0]

auto[0]

1276528

1

T1

1327

T2

604

T3

1392

auto[1]

auto[1]

auto[0]

auto[1]

1229915

1

T1

1223

T2

1417

T3

1765

auto[1]

auto[1]

auto[1]

auto[0]

1264048

1

T1

521

T2

771

T6

2180

auto[1]

auto[1]

auto[1]

auto[1]

1276836

1

T1

1276

T2

1211

T6

1052

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1454957

1

T1

3385

T2

954

T4

3701

auto[0]

auto[0]

auto[0]

auto[1]

1510493

1

T1

483

T2

2571

T3

208

auto[0]

auto[0]

auto[1]

auto[0]

11125515

1

T1

651

T2

3723

T3

1

auto[0]

auto[0]

auto[1]

auto[1]

1591600

1

T1

2760

T2

1017

T3

195

auto[0]

auto[1]

auto[0]

auto[0]

2608466

1

T1

1428

T2

662

T3

1584

auto[0]

auto[1]

auto[0]

auto[1]

2532485

1

T1

1317

T2

1476

T3

2042

auto[0]

auto[1]

auto[1]

auto[0]

2634378

1

T1

556

T2

795

T6

6190

auto[0]

auto[1]

auto[1]

auto[1]

2585945

1

T1

1382

T2

1326

T6

3064

auto[1]

auto[0]

auto[0]

auto[0]

111754

1

T4

336

T5

4

T39

592

auto[1]

auto[0]

auto[0]

auto[1]

122103

1

T4

510

T5

1

T33

1

auto[1]

auto[0]

auto[1]

auto[0]

146139

1

T4

544

T5

5

T39

1399

auto[1]

auto[0]

auto[1]

auto[1]

126740

1

T4

1001

T5

4

T39

764

auto[1]

auto[1]

auto[0]

auto[0]

124373

1

T6

1

T4

704

T5

4

auto[1]

auto[1]

auto[0]

auto[1]

143001

1

T7

2

T10

1

T4

394

auto[1]

auto[1]

auto[1]

auto[0]

142994

1

T6

2

T7

2

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

146226

1

T6

2

T4

2569

T5

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	717073	1			T1	3133		T2	913		T4	1391
fifo_depth[0]	auto[0]	auto[0]	auto[1]	703003	1			T1	451		T2	2368		T3	184
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8045410	1			T1	606		T2	3663		T3	1
fifo_depth[0]	auto[0]	auto[1]	auto[1]	756565	1			T1	2547		T2	972		T3	167
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1276528	1			T1	1327		T2	604		T3	1392
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1229915	1			T1	1223		T2	1417		T3	1765
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1264048	1			T1	521		T2	771		T6	2180
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1276836	1			T1	1276		T2	1211		T6	1052
fifo_depth[1]	auto[0]	auto[0]	auto[0]	64727	1			T1	158		T2	30		T4	133
fifo_depth[1]	auto[0]	auto[0]	auto[1]	67642	1			T1	24		T2	108		T3	15
fifo_depth[1]	auto[0]	auto[1]	auto[0]	570353	1			T1	24		T2	39		T9	1490
fifo_depth[1]	auto[0]	auto[1]	auto[1]	68381	1			T1	130		T2	24		T3	10
fifo_depth[1]	auto[1]	auto[0]	auto[0]	140632	1			T1	55		T2	34		T3	79
fifo_depth[1]	auto[1]	auto[0]	auto[1]	134242	1			T1	65		T2	28		T3	122
fifo_depth[1]	auto[1]	auto[1]	auto[0]	140911	1			T1	26		T2	15		T6	434
fifo_depth[1]	auto[1]	auto[1]	auto[1]	137577	1			T1	59		T2	67		T6	226
fifo_depth[2]	auto[0]	auto[0]	auto[0]	60041	1			T1	71		T2	6		T4	113
fifo_depth[2]	auto[0]	auto[0]	auto[1]	63543	1			T1	7		T2	56		T3	5
fifo_depth[2]	auto[0]	auto[1]	auto[0]	488215	1			T1	13		T2	17		T9	646
fifo_depth[2]	auto[0]	auto[1]	auto[1]	65788	1			T1	61		T2	15		T3	11
fifo_depth[2]	auto[1]	auto[0]	auto[0]	129701	1			T1	32		T2	18		T3	58
fifo_depth[2]	auto[1]	auto[0]	auto[1]	124115	1			T1	19		T2	21		T3	93
fifo_depth[2]	auto[1]	auto[1]	auto[0]	131505	1			T1	8		T2	8		T6	465
fifo_depth[2]	auto[1]	auto[1]	auto[1]	126103	1			T1	34		T2	31		T6	216
fifo_depth[3]	auto[0]	auto[0]	auto[0]	53034	1			T1	17		T2	3		T4	138
fifo_depth[3]	auto[0]	auto[0]	auto[1]	56053	1			T1	1		T2	31		T3	3
fifo_depth[3]	auto[0]	auto[1]	auto[0]	389759	1			T1	6		T2	4		T9	289
fifo_depth[3]	auto[0]	auto[1]	auto[1]	56237	1			T1	14		T2	5		T3	4
fifo_depth[3]	auto[1]	auto[0]	auto[0]	115495	1			T1	9		T2	4		T3	35
fifo_depth[3]	auto[1]	auto[0]	auto[1]	109457	1			T1	7		T2	3		T3	45
fifo_depth[3]	auto[1]	auto[1]	auto[0]	116411	1			T1	1		T2	1		T6	436
fifo_depth[3]	auto[1]	auto[1]	auto[1]	111633	1			T1	11		T2	10		T6	220
fifo_depth[4]	auto[0]	auto[0]	auto[0]	61633	1			T1	5		T2	2		T4	136
fifo_depth[4]	auto[0]	auto[0]	auto[1]	67098	1			T2	7		T4	149		T5	986
fifo_depth[4]	auto[0]	auto[1]	auto[0]	308410	1			T1	2		T9	92		T4	3077
fifo_depth[4]	auto[0]	auto[1]	auto[1]	67595	1			T1	6		T2	1		T3	3
fifo_depth[4]	auto[1]	auto[0]	auto[0]	121528	1			T1	4		T2	2		T3	15
fifo_depth[4]	auto[1]	auto[0]	auto[1]	115728	1			T1	3		T2	4		T3	14
fifo_depth[4]	auto[1]	auto[1]	auto[0]	125999	1			T6	476		T7	571		T8	386
fifo_depth[4]	auto[1]	auto[1]	auto[1]	117153	1			T1	1		T2	5		T6	224
fifo_depth[5]	auto[0]	auto[0]	auto[0]	50922	1			T1	1		T4	94		T5	539
fifo_depth[5]	auto[0]	auto[0]	auto[1]	55369	1			T2	1		T3	1		T4	182
fifo_depth[5]	auto[0]	auto[1]	auto[0]	253310	1			T9	26		T4	2622		T5	3045
fifo_depth[5]	auto[0]	auto[1]	auto[1]	54767	1			T1	1		T4	205		T5	515
fifo_depth[5]	auto[1]	auto[0]	auto[0]	108417	1			T1	1		T3	4		T6	279
fifo_depth[5]	auto[1]	auto[0]	auto[1]	103146	1			T2	3		T3	2		T6	225
fifo_depth[5]	auto[1]	auto[1]	auto[0]	109417	1			T6	463		T7	566		T8	426
fifo_depth[5]	auto[1]	auto[1]	auto[1]	103727	1			T1	1		T2	2		T6	223
fifo_depth[6]	auto[0]	auto[0]	auto[0]	58895	1			T4	106		T5	507		T139	112
fifo_depth[6]	auto[0]	auto[0]	auto[1]	65644	1			T4	338		T5	949		T37	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	232116	1			T9	5		T4	2339		T5	2553
fifo_depth[6]	auto[0]	auto[1]	auto[1]	63711	1			T1	1		T4	241		T5	481
fifo_depth[6]	auto[1]	auto[0]	auto[0]	114043	1			T6	243		T7	159		T8	85
fifo_depth[6]	auto[1]	auto[0]	auto[1]	110116	1			T3	1		T6	220		T7	280
fifo_depth[6]	auto[1]	auto[1]	auto[0]	117415	1			T6	461		T7	573		T8	350
fifo_depth[6]	auto[1]	auto[1]	auto[1]	110974	1			T6	204		T7	530		T8	172
fifo_depth[7]	auto[0]	auto[0]	auto[0]	50142	1			T4	115		T5	467		T139	100
fifo_depth[7]	auto[0]	auto[0]	auto[1]	54980	1			T4	329		T5	827		T139	25
fifo_depth[7]	auto[0]	auto[1]	auto[0]	185933	1			T4	2084		T5	2044		T139	98
fifo_depth[7]	auto[0]	auto[1]	auto[1]	53331	1			T4	192		T5	415		T139	105
fifo_depth[7]	auto[1]	auto[0]	auto[0]	101835	1			T6	227		T7	145		T8	74
fifo_depth[7]	auto[1]	auto[0]	auto[1]	97731	1			T6	201		T7	270		T8	216
fifo_depth[7]	auto[1]	auto[1]	auto[0]	102127	1			T6	382		T7	546		T8	332
fifo_depth[7]	auto[1]	auto[1]	auto[1]	97858	1			T6	201		T7	502		T8	169
fifo_depth[8]	auto[0]	auto[0]	auto[0]	74855	1			T4	111		T5	369		T139	95
fifo_depth[8]	auto[0]	auto[0]	auto[1]	80104	1			T4	282		T5	667		T139	16
fifo_depth[8]	auto[0]	auto[1]	auto[0]	181139	1			T4	1782		T5	1451		T139	69
fifo_depth[8]	auto[0]	auto[1]	auto[1]	84173	1			T4	208		T5	386		T139	84
fifo_depth[8]	auto[1]	auto[0]	auto[0]	122262	1			T3	1		T6	184		T7	134
fifo_depth[8]	auto[1]	auto[0]	auto[1]	118093	1			T6	159		T7	233		T8	221
fifo_depth[8]	auto[1]	auto[1]	auto[0]	129529	1			T6	315		T7	447		T8	305
fifo_depth[8]	auto[1]	auto[1]	auto[1]	126292	1			T6	164		T7	402		T8	123
fifo_depth[9]	auto[0]	auto[0]	auto[0]	38680	1			T4	91		T5	280		T139	60
fifo_depth[9]	auto[0]	auto[0]	auto[1]	42531	1			T4	256		T5	547		T139	19
fifo_depth[9]	auto[0]	auto[1]	auto[0]	107471	1			T4	1170		T5	1014		T139	50
fifo_depth[9]	auto[0]	auto[1]	auto[1]	42672	1			T4	124		T5	259		T139	69
fifo_depth[9]	auto[1]	auto[0]	auto[0]	74527	1			T6	148		T7	105		T8	41
fifo_depth[9]	auto[1]	auto[0]	auto[1]	72428	1			T6	134		T7	176		T8	152
fifo_depth[9]	auto[1]	auto[1]	auto[0]	73805	1			T6	257		T7	347		T8	219
fifo_depth[9]	auto[1]	auto[1]	auto[1]	71935	1			T6	139		T7	307		T8	99
fifo_depth[10]	auto[0]	auto[0]	auto[0]	45490	1			T4	52		T5	173		T139	43
fifo_depth[10]	auto[0]	auto[0]	auto[1]	52140	1			T4	214		T5	346		T139	10
fifo_depth[10]	auto[0]	auto[1]	auto[0]	97295	1			T4	891		T5	623		T139	32
fifo_depth[10]	auto[0]	auto[1]	auto[1]	56313	1			T4	174		T5	172		T139	45
fifo_depth[10]	auto[1]	auto[0]	auto[0]	73576	1			T6	91		T7	61		T8	34
fifo_depth[10]	auto[1]	auto[0]	auto[1]	71725	1			T6	84		T7	111		T8	114
fifo_depth[10]	auto[1]	auto[1]	auto[0]	78023	1			T6	159		T7	214		T8	156
fifo_depth[10]	auto[1]	auto[1]	auto[1]	73363	1			T6	90		T7	193		T8	71
fifo_depth[11]	auto[0]	auto[0]	auto[0]	28259	1			T4	49		T5	90		T139	23
fifo_depth[11]	auto[0]	auto[0]	auto[1]	31284	1			T4	196		T5	204		T139	5
fifo_depth[11]	auto[0]	auto[1]	auto[0]	58485	1			T4	487		T5	355		T139	19
fifo_depth[11]	auto[0]	auto[1]	auto[1]	33693	1			T4	87		T5	103		T139	22
fifo_depth[11]	auto[1]	auto[0]	auto[0]	44587	1			T6	52		T7	35		T8	18
fifo_depth[11]	auto[1]	auto[0]	auto[1]	46063	1			T6	50		T7	58		T8	50
fifo_depth[11]	auto[1]	auto[1]	auto[0]	45434	1			T6	88		T7	136		T8	87
fifo_depth[11]	auto[1]	auto[1]	auto[1]	44120	1			T6	52		T7	123		T8	45
fifo_depth[12]	auto[0]	auto[0]	auto[0]	57567	1			T4	86		T5	46		T139	12
fifo_depth[12]	auto[0]	auto[0]	auto[1]	66365	1			T4	165		T5	117		T139	2
fifo_depth[12]	auto[0]	auto[1]	auto[0]	81627	1			T4	433		T5	179		T139	10
fifo_depth[12]	auto[0]	auto[1]	auto[1]	73945	1			T4	338		T5	49		T139	9
fifo_depth[12]	auto[1]	auto[0]	auto[0]	70104	1			T6	32		T7	23		T8	4
fifo_depth[12]	auto[1]	auto[0]	auto[1]	74976	1			T6	27		T7	34		T8	35
fifo_depth[12]	auto[1]	auto[1]	auto[0]	79987	1			T6	49		T7	61		T8	45
fifo_depth[12]	auto[1]	auto[1]	auto[1]	76327	1			T6	27		T7	71		T8	17
fifo_depth[13]	auto[0]	auto[0]	auto[0]	25140	1			T4	87		T5	14		T139	5
fifo_depth[13]	auto[0]	auto[0]	auto[1]	27956	1			T4	137		T5	48		T139	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	37907	1			T4	214		T5	85		T139	3
fifo_depth[13]	auto[0]	auto[1]	auto[1]	30201	1			T4	95		T5	27		T139	6
fifo_depth[13]	auto[1]	auto[0]	auto[0]	32282	1			T6	14		T7	14		T8	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	35583	1			T6	9		T7	11		T8	13
fifo_depth[13]	auto[1]	auto[1]	auto[0]	32189	1			T6	17		T7	37		T8	14
fifo_depth[13]	auto[1]	auto[1]	auto[1]	32298	1			T6	16		T7	24		T8	7
fifo_depth[14]	auto[0]	auto[0]	auto[0]	43301	1			T4	522		T5	9		T139	3
fifo_depth[14]	auto[0]	auto[0]	auto[1]	50364	1			T4	138		T5	17		T39	80
fifo_depth[14]	auto[0]	auto[1]	auto[0]	56094	1			T4	910		T5	34		T139	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	56502	1			T4	378		T5	16		T139	4
fifo_depth[14]	auto[1]	auto[0]	auto[0]	51918	1			T6	7		T7	6		T8	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	55266	1			T6	4		T7	6		T8	5
fifo_depth[14]	auto[1]	auto[1]	auto[0]	57002	1			T6	8		T7	18		T8	9
fifo_depth[14]	auto[1]	auto[1]	auto[1]	50830	1			T6	5		T7	13		T8	4
fifo_depth[15]	auto[0]	auto[0]	auto[0]	25198	1			T4	477		T5	3		T139	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	26417	1			T4	112		T5	11		T39	24
fifo_depth[15]	auto[0]	auto[1]	auto[0]	31991	1			T4	712		T5	20		T139	3
fifo_depth[15]	auto[0]	auto[1]	auto[1]	27726	1			T4	183		T5	6		T39	283
fifo_depth[15]	auto[1]	auto[0]	auto[0]	31031	1			T6	3		T10	2		T4	36
fifo_depth[15]	auto[1]	auto[0]	auto[1]	33901	1			T7	3		T8	4		T10	3
fifo_depth[15]	auto[1]	auto[1]	auto[0]	30576	1			T7	5		T8	4		T10	3
fifo_depth[15]	auto[1]	auto[1]	auto[1]	28919	1			T6	5		T7	3		T8	4
fifo_depth[16]	auto[0]	auto[0]	auto[0]	111754	1			T4	336		T5	4		T39	592
fifo_depth[16]	auto[0]	auto[0]	auto[1]	122103	1			T4	510		T5	1		T33	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	146139	1			T4	544		T5	5		T39	1399
fifo_depth[16]	auto[0]	auto[1]	auto[1]	126740	1			T4	1001		T5	4		T39	764
fifo_depth[16]	auto[1]	auto[0]	auto[0]	124373	1			T6	1		T4	704		T5	4
fifo_depth[16]	auto[1]	auto[0]	auto[1]	143001	1			T7	2		T10	1		T4	394
fifo_depth[16]	auto[1]	auto[1]	auto[0]	142994	1			T6	2		T7	2		T8	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	146226	1			T6	2		T4	2569		T5	3