Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	36207371	1			T14	8		T20	11		T21	4
all_pins[1]	36207371	1			T14	8		T20	11		T21	4
all_pins[2]	36207371	1			T14	8		T20	11		T21	4

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78178050	1			T14	22		T20	28		T21	10
values[0x1]	30444063	1			T14	2		T20	5		T21	2
transitions[0x0=>0x1]	26720533	1			T14	2		T20	4		T21	2
transitions[0x1=>0x0]	26720550	1			T14	2		T20	4		T21	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	36046510	1			T14	6		T20	9		T21	3
all_pins[0]	values[0x1]	160861	1			T14	2		T20	2		T21	1
all_pins[0]	transitions[0x0=>0x1]	160630	1			T14	2		T20	1		T21	1
all_pins[0]	transitions[0x1=>0x0]	13895876	1			T20	1		T59	1		T73	2
all_pins[1]	values[0x0]	19820259	1			T14	8		T20	10		T21	3
all_pins[1]	values[0x1]	16387112	1			T20	1		T21	1		T59	1
all_pins[1]	transitions[0x0=>0x1]	16262192	1			T20	1		T21	1		T59	1
all_pins[1]	transitions[0x1=>0x0]	35941	1			T14	2		T20	2		T21	1
all_pins[2]	values[0x0]	22311281	1			T14	8		T20	9		T21	4
all_pins[2]	values[0x1]	13896090	1			T20	2		T59	1		T73	2
all_pins[2]	transitions[0x0=>0x1]	10297711	1			T20	2		T59	1		T82	1
all_pins[2]	transitions[0x1=>0x0]	12788733	1			T20	1		T21	1		T59	1