Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4062 1 T14 7 T20 10 T21 4
all_values[1] 4062 1 T14 7 T20 10 T21 4
all_values[2] 4062 1 T14 7 T20 10 T21 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5777 1 T14 13 T20 19 T21 6
auto[1] 6409 1 T14 8 T20 11 T21 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4704 1 T14 11 T20 8 T21 8
auto[1] 7482 1 T14 10 T20 22 T21 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7017 1 T14 14 T20 16 T21 9
auto[1] 5169 1 T14 7 T20 14 T21 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 715 1 T14 2 T20 1 T21 2
all_values[0] auto[0] auto[0] auto[1] 403 1 T20 2 T23 1 T134 1
all_values[0] auto[0] auto[1] auto[0] 788 1 T14 2 T20 1 T73 2
all_values[0] auto[0] auto[1] auto[1] 391 1 T14 1 T20 1 T23 1
all_values[0] auto[1] auto[0] auto[1] 863 1 T14 1 T20 3 T21 2
all_values[0] auto[1] auto[1] auto[1] 902 1 T14 1 T20 2 T23 1
all_values[1] auto[0] auto[0] auto[0] 736 1 T14 1 T20 2 T23 2
all_values[1] auto[0] auto[0] auto[1] 379 1 T14 1 T20 2 T23 1
all_values[1] auto[0] auto[1] auto[0] 866 1 T14 2 T20 2 T21 2
all_values[1] auto[0] auto[1] auto[1] 363 1 T21 1 T59 1 T73 3
all_values[1] auto[1] auto[0] auto[1] 809 1 T14 1 T20 2 T23 1
all_values[1] auto[1] auto[1] auto[1] 909 1 T14 2 T20 2 T21 1
all_values[2] auto[0] auto[0] auto[0] 726 1 T14 4 T21 2 T23 1
all_values[2] auto[0] auto[0] auto[1] 372 1 T14 1 T20 3 T23 1
all_values[2] auto[0] auto[1] auto[0] 873 1 T20 2 T21 2 T23 1
all_values[2] auto[0] auto[1] auto[1] 405 1 T73 1 T134 1 T70 1
all_values[2] auto[1] auto[0] auto[1] 774 1 T14 2 T20 4 T23 1
all_values[2] auto[1] auto[1] auto[1] 912 1 T20 1 T59 3 T73 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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