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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.60 99.53 98.58 100.00 100.00 99.76 99.49 99.86


Total test records in report: 897
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T753 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2597392514 Jan 24 11:27:48 PM PST 24 Jan 24 11:35:19 PM PST 24 23021246349 ps
T754 /workspace/coverage/default/47.hmac_test_sha_vectors.3792650701 Jan 24 11:36:58 PM PST 24 Jan 24 11:43:00 PM PST 24 54240139358 ps
T755 /workspace/coverage/default/48.hmac_long_msg.2732291677 Jan 24 11:37:19 PM PST 24 Jan 24 11:37:43 PM PST 24 6307179997 ps
T756 /workspace/coverage/default/38.hmac_stress_all.895930068 Jan 24 11:34:55 PM PST 24 Jan 24 11:47:02 PM PST 24 246880720621 ps
T757 /workspace/coverage/default/11.hmac_back_pressure.982217181 Jan 24 11:27:35 PM PST 24 Jan 24 11:28:01 PM PST 24 13100974280 ps
T758 /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.2560034521 Jan 24 11:41:04 PM PST 24 Jan 24 11:48:56 PM PST 24 34193251726 ps
T759 /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.13388657 Jan 25 02:24:11 AM PST 24 Jan 25 02:40:43 AM PST 24 34169171152 ps
T760 /workspace/coverage/default/42.hmac_alert_test.2384220837 Jan 24 11:35:54 PM PST 24 Jan 24 11:35:55 PM PST 24 20940584 ps
T761 /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.654206944 Jan 25 12:53:03 AM PST 24 Jan 25 01:16:56 AM PST 24 300195767308 ps
T762 /workspace/coverage/default/7.hmac_burst_wr.2722414093 Jan 24 11:26:56 PM PST 24 Jan 24 11:27:22 PM PST 24 6349286615 ps
T763 /workspace/coverage/default/25.hmac_long_msg.216132394 Jan 24 11:47:45 PM PST 24 Jan 24 11:48:14 PM PST 24 512455552 ps
T764 /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2991271362 Jan 24 11:39:08 PM PST 24 Jan 24 11:51:13 PM PST 24 52959048524 ps
T765 /workspace/coverage/default/23.hmac_error.49415704 Jan 24 11:30:23 PM PST 24 Jan 24 11:32:24 PM PST 24 10078657897 ps
T766 /workspace/coverage/default/18.hmac_burst_wr.1472711641 Jan 25 01:10:38 AM PST 24 Jan 25 01:11:46 AM PST 24 1383217223 ps
T767 /workspace/coverage/default/47.hmac_datapath_stress.3459559929 Jan 24 11:36:58 PM PST 24 Jan 24 11:37:38 PM PST 24 3538457102 ps
T768 /workspace/coverage/default/2.hmac_test_sha_vectors.3914624117 Jan 24 11:25:55 PM PST 24 Jan 24 11:32:34 PM PST 24 31912959907 ps
T769 /workspace/coverage/default/13.hmac_test_sha_vectors.2534123794 Jan 25 02:46:55 AM PST 24 Jan 25 02:54:23 AM PST 24 159057002746 ps
T770 /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.1218915029 Jan 24 11:40:47 PM PST 24 Jan 25 12:41:14 AM PST 24 383590339202 ps
T771 /workspace/coverage/default/1.hmac_alert_test.1362575902 Jan 24 11:25:53 PM PST 24 Jan 24 11:26:01 PM PST 24 19301089 ps
T772 /workspace/coverage/default/23.hmac_burst_wr.3625648702 Jan 24 11:30:24 PM PST 24 Jan 24 11:31:21 PM PST 24 1185452381 ps
T773 /workspace/coverage/default/14.hmac_wipe_secret.3562866613 Jan 24 11:28:14 PM PST 24 Jan 24 11:29:07 PM PST 24 1216313564 ps
T774 /workspace/coverage/default/21.hmac_wipe_secret.790920835 Jan 24 11:29:42 PM PST 24 Jan 24 11:31:06 PM PST 24 7004668516 ps
T775 /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.4179199172 Jan 24 11:44:25 PM PST 24 Jan 25 12:09:20 AM PST 24 353181582661 ps
T776 /workspace/coverage/default/34.hmac_wipe_secret.1532253608 Jan 24 11:33:17 PM PST 24 Jan 24 11:34:31 PM PST 24 10980968416 ps
T777 /workspace/coverage/default/7.hmac_error.1491348489 Jan 24 11:26:56 PM PST 24 Jan 24 11:28:26 PM PST 24 11385027319 ps
T778 /workspace/coverage/default/26.hmac_smoke.3391114732 Jan 24 11:31:06 PM PST 24 Jan 24 11:31:09 PM PST 24 36639871 ps
T779 /workspace/coverage/default/20.hmac_burst_wr.1923660920 Jan 25 12:22:37 AM PST 24 Jan 25 12:23:15 AM PST 24 3562610505 ps
T780 /workspace/coverage/default/7.hmac_alert_test.1039575067 Jan 24 11:26:59 PM PST 24 Jan 24 11:27:04 PM PST 24 21428989 ps
T781 /workspace/coverage/default/46.hmac_back_pressure.1112575355 Jan 24 11:36:42 PM PST 24 Jan 24 11:36:55 PM PST 24 365427141 ps
T782 /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.39799585 Jan 24 11:27:16 PM PST 24 Jan 25 12:09:04 AM PST 24 175127967340 ps
T783 /workspace/coverage/default/30.hmac_alert_test.3368535353 Jan 24 11:32:16 PM PST 24 Jan 24 11:32:18 PM PST 24 12147147 ps
T784 /workspace/coverage/default/10.hmac_long_msg.3830197323 Jan 24 11:27:14 PM PST 24 Jan 24 11:27:52 PM PST 24 6619701819 ps
T785 /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.637593049 Jan 24 11:45:16 PM PST 24 Jan 25 12:23:18 AM PST 24 124774901947 ps
T786 /workspace/coverage/default/36.hmac_wipe_secret.2386862530 Jan 24 11:33:52 PM PST 24 Jan 24 11:34:07 PM PST 24 1635006216 ps
T787 /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.1949889179 Jan 25 12:55:08 AM PST 24 Jan 25 01:24:57 AM PST 24 362944792082 ps
T788 /workspace/coverage/default/25.hmac_test_hmac_vectors.789813045 Jan 24 11:31:08 PM PST 24 Jan 24 11:31:11 PM PST 24 78768409 ps
T789 /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.970785570 Jan 24 11:35:55 PM PST 24 Jan 24 11:52:37 PM PST 24 226449624246 ps
T790 /workspace/coverage/default/29.hmac_back_pressure.3854023506 Jan 24 11:32:03 PM PST 24 Jan 24 11:32:07 PM PST 24 90245753 ps
T791 /workspace/coverage/default/41.hmac_burst_wr.3828595915 Jan 24 11:35:37 PM PST 24 Jan 24 11:35:44 PM PST 24 591746199 ps
T792 /workspace/coverage/default/18.hmac_alert_test.3840927820 Jan 25 01:52:38 AM PST 24 Jan 25 01:52:40 AM PST 24 187839284 ps
T793 /workspace/coverage/default/33.hmac_smoke.2871416336 Jan 24 11:32:58 PM PST 24 Jan 24 11:33:00 PM PST 24 171151128 ps
T794 /workspace/coverage/default/39.hmac_datapath_stress.1608042838 Jan 24 11:34:52 PM PST 24 Jan 24 11:35:04 PM PST 24 207602116 ps
T795 /workspace/coverage/default/41.hmac_long_msg.4065730820 Jan 24 11:35:48 PM PST 24 Jan 24 11:37:22 PM PST 24 3456724633 ps
T796 /workspace/coverage/default/27.hmac_long_msg.1125850172 Jan 24 11:31:09 PM PST 24 Jan 24 11:31:31 PM PST 24 4408063708 ps
T797 /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1787670075 Jan 24 11:39:22 PM PST 24 Jan 25 12:00:51 AM PST 24 340779321680 ps
T798 /workspace/coverage/default/19.hmac_error.3233697173 Jan 24 11:29:23 PM PST 24 Jan 24 11:30:12 PM PST 24 11714379627 ps
T799 /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.907072039 Jan 24 11:39:38 PM PST 24 Jan 25 12:27:38 AM PST 24 174366431800 ps
T800 /workspace/coverage/default/48.hmac_stress_all.3810174495 Jan 24 11:37:17 PM PST 24 Jan 24 11:37:20 PM PST 24 93793852 ps
T801 /workspace/coverage/default/35.hmac_datapath_stress.1093755226 Jan 24 11:33:35 PM PST 24 Jan 24 11:35:35 PM PST 24 34776353485 ps
T802 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2247394372 Jan 24 11:44:07 PM PST 24 Jan 25 12:01:19 AM PST 24 22123552471 ps
T803 /workspace/coverage/default/27.hmac_burst_wr.2401401977 Jan 24 11:31:25 PM PST 24 Jan 24 11:31:34 PM PST 24 335098490 ps
T804 /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.56282597 Jan 24 11:38:31 PM PST 24 Jan 24 11:49:36 PM PST 24 213879811552 ps
T805 /workspace/coverage/default/7.hmac_stress_all.1528144172 Jan 24 11:26:57 PM PST 24 Jan 24 11:46:54 PM PST 24 233487149037 ps
T806 /workspace/coverage/default/31.hmac_long_msg.3937397690 Jan 24 11:32:20 PM PST 24 Jan 24 11:33:36 PM PST 24 75071032602 ps
T807 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.4285040498 Jan 24 11:42:54 PM PST 24 Jan 25 12:30:48 AM PST 24 572507550469 ps
T808 /workspace/coverage/default/18.hmac_stress_all.8769117 Jan 24 11:29:05 PM PST 24 Jan 24 11:30:11 PM PST 24 3107475773 ps
T809 /workspace/coverage/default/3.hmac_smoke.192756970 Jan 24 11:25:53 PM PST 24 Jan 24 11:26:04 PM PST 24 159566678 ps
T810 /workspace/coverage/default/21.hmac_back_pressure.3507097548 Jan 24 11:29:39 PM PST 24 Jan 24 11:30:05 PM PST 24 2449812454 ps
T811 /workspace/coverage/default/15.hmac_smoke.2509402932 Jan 24 11:28:12 PM PST 24 Jan 24 11:28:16 PM PST 24 917039798 ps
T812 /workspace/coverage/default/35.hmac_error.3820356719 Jan 24 11:33:35 PM PST 24 Jan 24 11:34:26 PM PST 24 1926371071 ps
T813 /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.195385369 Jan 24 11:30:02 PM PST 24 Jan 24 11:39:53 PM PST 24 30833727354 ps
T814 /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.224022965 Jan 24 11:41:06 PM PST 24 Jan 24 11:54:21 PM PST 24 30526844496 ps
T815 /workspace/coverage/default/28.hmac_alert_test.1131994396 Jan 24 11:31:45 PM PST 24 Jan 24 11:31:48 PM PST 24 14286976 ps
T816 /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.1234022934 Jan 24 11:38:31 PM PST 24 Jan 25 12:23:26 AM PST 24 52759539984 ps
T817 /workspace/coverage/default/49.hmac_datapath_stress.3362026488 Jan 24 11:37:29 PM PST 24 Jan 24 11:38:43 PM PST 24 2676069434 ps
T818 /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3590103532 Jan 24 11:35:18 PM PST 24 Jan 24 11:55:38 PM PST 24 759981326686 ps
T819 /workspace/coverage/default/24.hmac_test_sha_vectors.782597530 Jan 24 11:58:31 PM PST 24 Jan 25 12:06:32 AM PST 24 80941880532 ps
T820 /workspace/coverage/default/38.hmac_wipe_secret.1396391096 Jan 24 11:34:54 PM PST 24 Jan 24 11:35:49 PM PST 24 5141744911 ps
T821 /workspace/coverage/default/36.hmac_test_hmac_vectors.2638947156 Jan 24 11:33:53 PM PST 24 Jan 24 11:33:58 PM PST 24 32581968 ps
T822 /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.1996855012 Jan 24 11:38:54 PM PST 24 Jan 25 12:01:52 AM PST 24 48514048915 ps
T823 /workspace/coverage/default/12.hmac_long_msg.2009103656 Jan 24 11:27:43 PM PST 24 Jan 24 11:28:56 PM PST 24 5629454762 ps
T824 /workspace/coverage/default/32.hmac_datapath_stress.431328599 Jan 24 11:32:39 PM PST 24 Jan 24 11:34:23 PM PST 24 3925284956 ps
T825 /workspace/coverage/default/44.hmac_datapath_stress.403499707 Jan 25 12:25:34 AM PST 24 Jan 25 12:25:59 AM PST 24 323558358 ps
T826 /workspace/coverage/default/42.hmac_smoke.45904119 Jan 24 11:35:59 PM PST 24 Jan 24 11:36:05 PM PST 24 1334604422 ps
T827 /workspace/coverage/default/17.hmac_long_msg.1992116066 Jan 24 11:28:51 PM PST 24 Jan 24 11:29:56 PM PST 24 1107491434 ps
T828 /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.403940201 Jan 24 11:44:10 PM PST 24 Jan 25 12:03:44 AM PST 24 135199882961 ps
T829 /workspace/coverage/default/13.hmac_stress_all.1000088460 Jan 24 11:27:58 PM PST 24 Jan 24 11:40:22 PM PST 24 209512477085 ps
T830 /workspace/coverage/default/5.hmac_burst_wr.2608929651 Jan 24 11:26:20 PM PST 24 Jan 24 11:26:26 PM PST 24 935905307 ps
T831 /workspace/coverage/default/11.hmac_wipe_secret.2086837388 Jan 24 11:27:31 PM PST 24 Jan 24 11:28:17 PM PST 24 1036037572 ps
T832 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3618446057 Jan 24 12:58:51 PM PST 24 Jan 24 12:59:08 PM PST 24 141202676 ps
T833 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1308127282 Jan 24 12:58:40 PM PST 24 Jan 24 12:58:54 PM PST 24 14754373 ps
T834 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3253898149 Jan 24 12:58:50 PM PST 24 Jan 24 12:59:07 PM PST 24 34944452 ps
T835 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1590353704 Jan 24 12:58:10 PM PST 24 Jan 24 12:58:33 PM PST 24 94017433 ps
T836 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2992059845 Jan 24 12:58:56 PM PST 24 Jan 24 12:59:17 PM PST 24 24151405 ps
T837 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3795532661 Jan 24 12:58:26 PM PST 24 Jan 24 12:58:40 PM PST 24 155372827 ps
T838 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.566196293 Jan 24 12:58:55 PM PST 24 Jan 24 12:59:14 PM PST 24 46887078 ps
T839 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3839394287 Jan 24 12:57:52 PM PST 24 Jan 24 12:58:18 PM PST 24 191799841 ps
T840 /workspace/coverage/cover_reg_top/45.hmac_intr_test.268059143 Jan 24 01:39:20 PM PST 24 Jan 24 01:39:24 PM PST 24 15495450 ps
T841 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2272893412 Jan 24 12:57:52 PM PST 24 Jan 24 12:58:17 PM PST 24 121280834 ps
T842 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4155311237 Jan 24 12:58:34 PM PST 24 Jan 24 12:58:50 PM PST 24 612739236 ps
T843 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.788887934 Jan 24 12:57:52 PM PST 24 Jan 24 12:58:20 PM PST 24 144061477 ps
T844 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4187847994 Jan 24 12:57:55 PM PST 24 Jan 24 12:58:23 PM PST 24 29518921 ps
T845 /workspace/coverage/cover_reg_top/23.hmac_intr_test.500341080 Jan 24 12:58:59 PM PST 24 Jan 24 12:59:21 PM PST 24 37434569 ps
T846 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2378672374 Jan 24 12:57:46 PM PST 24 Jan 24 12:58:10 PM PST 24 80058292 ps
T847 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.197594078 Jan 24 12:58:38 PM PST 24 Jan 24 12:58:52 PM PST 24 278521437 ps
T848 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1117114355 Jan 24 12:58:12 PM PST 24 Jan 24 12:58:35 PM PST 24 151751258 ps
T849 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2999722571 Jan 24 12:58:28 PM PST 24 Jan 24 12:58:41 PM PST 24 63660406 ps
T136 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3462532150 Jan 24 01:03:26 PM PST 24 Jan 24 01:03:59 PM PST 24 624268228 ps
T850 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2014896013 Jan 24 12:58:38 PM PST 24 Jan 24 12:58:52 PM PST 24 381124408 ps
T851 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2830279460 Jan 24 12:58:24 PM PST 24 Jan 24 12:58:38 PM PST 24 45576266 ps
T852 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1869325059 Jan 24 12:58:57 PM PST 24 Jan 24 12:59:17 PM PST 24 15108036 ps
T138 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3350242377 Jan 24 12:58:20 PM PST 24 Jan 24 12:58:38 PM PST 24 508782366 ps
T853 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3949748645 Jan 24 12:58:51 PM PST 24 Jan 24 12:59:07 PM PST 24 47671554 ps
T854 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1808551387 Jan 24 01:15:07 PM PST 24 Jan 24 01:15:39 PM PST 24 23296819 ps
T855 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2317504194 Jan 24 12:58:26 PM PST 24 Jan 24 12:58:39 PM PST 24 16949128 ps
T856 /workspace/coverage/cover_reg_top/24.hmac_intr_test.294250511 Jan 24 12:58:57 PM PST 24 Jan 24 12:59:17 PM PST 24 50225767 ps
T857 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3178000225 Jan 24 12:58:12 PM PST 24 Jan 24 12:58:33 PM PST 24 15373154 ps
T858 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3519037142 Jan 24 12:58:28 PM PST 24 Jan 24 12:58:42 PM PST 24 662990085 ps
T859 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3863842361 Jan 24 12:57:55 PM PST 24 Jan 24 12:58:24 PM PST 24 616303722 ps
T860 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3590506793 Jan 24 12:58:26 PM PST 24 Jan 24 12:58:39 PM PST 24 20676257 ps
T861 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4042381113 Jan 24 12:58:21 PM PST 24 Jan 24 12:58:38 PM PST 24 365683014 ps
T862 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1511069153 Jan 24 12:58:20 PM PST 24 Jan 24 01:06:03 PM PST 24 32456236880 ps
T863 /workspace/coverage/cover_reg_top/16.hmac_intr_test.415749063 Jan 24 12:58:33 PM PST 24 Jan 24 12:58:45 PM PST 24 65039852 ps
T864 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.296947593 Jan 24 12:58:06 PM PST 24 Jan 24 12:58:30 PM PST 24 25736826 ps
T865 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1854583901 Jan 24 12:59:14 PM PST 24 Jan 24 12:59:38 PM PST 24 47567516 ps
T866 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2693912706 Jan 24 12:58:39 PM PST 24 Jan 24 12:58:54 PM PST 24 76011264 ps
T867 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2011696065 Jan 24 12:57:56 PM PST 24 Jan 24 12:58:24 PM PST 24 309658578 ps
T868 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3970200641 Jan 24 12:57:53 PM PST 24 Jan 24 12:58:19 PM PST 24 38187228 ps
T869 /workspace/coverage/cover_reg_top/31.hmac_intr_test.764780638 Jan 24 12:58:57 PM PST 24 Jan 24 12:59:17 PM PST 24 10557245 ps
T870 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3995021343 Jan 24 01:58:53 PM PST 24 Jan 24 01:59:02 PM PST 24 1826090733 ps
T871 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3148986673 Jan 24 12:58:44 PM PST 24 Jan 24 12:59:00 PM PST 24 207347086 ps
T872 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.106574557 Jan 24 01:15:14 PM PST 24 Jan 24 01:15:53 PM PST 24 140438060 ps
T873 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3775106985 Jan 24 12:59:12 PM PST 24 Jan 24 12:59:38 PM PST 24 14423881 ps
T874 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3460765226 Jan 24 01:39:58 PM PST 24 Jan 24 01:40:46 PM PST 24 119128092 ps
T875 /workspace/coverage/cover_reg_top/37.hmac_intr_test.4263725739 Jan 24 12:58:58 PM PST 24 Jan 24 12:59:18 PM PST 24 13737573 ps
T876 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3196919398 Jan 24 12:57:51 PM PST 24 Jan 24 12:58:17 PM PST 24 46548590 ps
T877 /workspace/coverage/cover_reg_top/14.hmac_intr_test.523779620 Jan 24 12:58:41 PM PST 24 Jan 24 12:58:54 PM PST 24 104287178 ps
T878 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2883682806 Jan 24 01:31:37 PM PST 24 Jan 24 01:32:29 PM PST 24 35897167 ps
T879 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3708168557 Jan 24 12:57:46 PM PST 24 Jan 24 01:00:47 PM PST 24 11539430513 ps
T880 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3963315282 Jan 24 12:58:21 PM PST 24 Jan 24 12:58:37 PM PST 24 46474879 ps
T881 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.985331640 Jan 24 12:57:54 PM PST 24 Jan 24 12:58:20 PM PST 24 12462153 ps
T882 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1910078863 Jan 24 12:57:51 PM PST 24 Jan 24 12:58:16 PM PST 24 57866155 ps
T883 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3011022409 Jan 24 12:57:38 PM PST 24 Jan 24 12:58:01 PM PST 24 14149045 ps
T884 /workspace/coverage/cover_reg_top/20.hmac_intr_test.633101006 Jan 24 12:58:57 PM PST 24 Jan 24 12:59:17 PM PST 24 100062048 ps
T885 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2537164469 Jan 24 12:58:57 PM PST 24 Jan 24 12:59:17 PM PST 24 19435024 ps
T886 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1548047916 Jan 24 12:58:39 PM PST 24 Jan 24 12:58:53 PM PST 24 68784213 ps
T887 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2192880132 Jan 24 12:57:54 PM PST 24 Jan 24 12:58:20 PM PST 24 15794872 ps
T888 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2580490447 Jan 24 12:57:47 PM PST 24 Jan 24 12:58:14 PM PST 24 350442876 ps
T889 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2427430403 Jan 24 12:58:37 PM PST 24 Jan 24 12:58:50 PM PST 24 22796035 ps
T890 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3402043425 Jan 24 12:57:38 PM PST 24 Jan 24 12:58:09 PM PST 24 828306907 ps
T891 /workspace/coverage/cover_reg_top/46.hmac_intr_test.232568428 Jan 24 12:59:13 PM PST 24 Jan 24 12:59:38 PM PST 24 12676105 ps
T892 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.471808715 Jan 24 12:57:54 PM PST 24 Jan 24 12:58:20 PM PST 24 62434399 ps
T893 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1180421386 Jan 24 12:58:30 PM PST 24 Jan 24 12:58:43 PM PST 24 76437258 ps
T894 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1108680361 Jan 24 12:58:56 PM PST 24 Jan 24 01:11:14 PM PST 24 471122830450 ps
T895 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4254003519 Jan 24 12:59:01 PM PST 24 Jan 24 12:59:27 PM PST 24 111564797 ps
T896 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2773764430 Jan 24 12:58:34 PM PST 24 Jan 24 12:58:48 PM PST 24 80592694 ps
T897 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.108681620 Jan 24 12:58:49 PM PST 24 Jan 24 12:59:08 PM PST 24 410294278 ps

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3276097041
Short name T12
Test name
Test status
Simulation time 511586711 ps
CPU time 2.55 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:17 PM PST 24
Peak memory 183632 kb
Host smart-4bc6f3f0-ae9f-4998-af94-9ae2282e88be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276097041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3276097041
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.906747203
Short name T4
Test name
Test status
Simulation time 77792570884 ps
CPU time 2137.4 seconds
Started Jan 24 11:40:00 PM PST 24
Finished Jan 25 12:15:43 AM PST 24
Peak memory 256300 kb
Host smart-41eae4fd-9575-4b06-b992-274035082440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906747203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.906747203
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.181312895
Short name T18
Test name
Test status
Simulation time 19354724468 ps
CPU time 246.63 seconds
Started Jan 24 12:58:38 PM PST 24
Finished Jan 24 01:02:57 PM PST 24
Peak memory 206488 kb
Host smart-28b35ae7-4643-4359-9c2c-4dfb9f46a134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181312895 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.181312895
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.931673938
Short name T59
Test name
Test status
Simulation time 31384122 ps
CPU time 0.58 seconds
Started Jan 24 12:57:47 PM PST 24
Finished Jan 24 12:58:11 PM PST 24
Peak memory 183184 kb
Host smart-4ac8c4ea-1242-4496-8eac-c066111463d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931673938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.931673938
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.950071312
Short name T60
Test name
Test status
Simulation time 496122052 ps
CPU time 2.51 seconds
Started Jan 24 01:29:52 PM PST 24
Finished Jan 24 01:30:14 PM PST 24
Peak memory 198084 kb
Host smart-442aac96-d618-4cdf-a7ae-06f585ea330d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950071312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.950071312
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.3393606074
Short name T95
Test name
Test status
Simulation time 422085855326 ps
CPU time 4881.66 seconds
Started Jan 24 11:40:01 PM PST 24
Finished Jan 25 01:01:28 AM PST 24
Peak memory 263152 kb
Host smart-80fbaf54-09cc-4892-b148-7580f65af18a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393606074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.3393606074
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.850376091
Short name T76
Test name
Test status
Simulation time 49272688 ps
CPU time 0.72 seconds
Started Jan 24 12:58:39 PM PST 24
Finished Jan 24 12:58:53 PM PST 24
Peak memory 194284 kb
Host smart-0022fa2c-a33c-4f93-b8bd-22e5cb8d8705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850376091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.850376091
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2886123342
Short name T93
Test name
Test status
Simulation time 488341624209 ps
CPU time 1992.34 seconds
Started Jan 24 11:25:55 PM PST 24
Finished Jan 24 11:59:15 PM PST 24
Peak memory 199184 kb
Host smart-a725eeb8-4d8d-4fba-b7fd-5f9f1538118c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886123342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2886123342
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3568569265
Short name T23
Test name
Test status
Simulation time 15638358 ps
CPU time 0.57 seconds
Started Jan 24 12:57:47 PM PST 24
Finished Jan 24 12:58:11 PM PST 24
Peak memory 183200 kb
Host smart-7d77b32c-f1cc-461d-bb52-39882c474742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568569265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3568569265
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3195659693
Short name T48
Test name
Test status
Simulation time 73369553 ps
CPU time 0.83 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:25:32 PM PST 24
Peak memory 215660 kb
Host smart-56c61b3b-8357-40ca-b640-968cc6137d5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195659693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3195659693
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.868349477
Short name T2
Test name
Test status
Simulation time 24125121509 ps
CPU time 358.78 seconds
Started Jan 24 11:40:47 PM PST 24
Finished Jan 24 11:46:47 PM PST 24
Peak memory 215744 kb
Host smart-0a35c337-0680-4514-a87c-9f9b39f19555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868349477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.868349477
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1059780312
Short name T147
Test name
Test status
Simulation time 62018159 ps
CPU time 0.57 seconds
Started Jan 24 12:57:54 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 183576 kb
Host smart-ed0a28cd-d3b2-4b97-b2a4-cd8af33a9120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059780312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1059780312
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1344470657
Short name T198
Test name
Test status
Simulation time 41672133 ps
CPU time 0.61 seconds
Started Jan 24 11:27:55 PM PST 24
Finished Jan 24 11:27:56 PM PST 24
Peak memory 192652 kb
Host smart-178a92e7-0463-47a6-80a1-a41394277236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344470657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1344470657
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2691349705
Short name T118
Test name
Test status
Simulation time 2790345984462 ps
CPU time 2146.97 seconds
Started Jan 24 11:38:11 PM PST 24
Finished Jan 25 12:14:04 AM PST 24
Peak memory 259800 kb
Host smart-1dc135c0-daaa-4350-ab2a-d8904f614b4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691349705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2691349705
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3350242377
Short name T138
Test name
Test status
Simulation time 508782366 ps
CPU time 2.57 seconds
Started Jan 24 12:58:20 PM PST 24
Finished Jan 24 12:58:38 PM PST 24
Peak memory 198056 kb
Host smart-1fa89ac7-4aae-4c2f-a59f-70064dbeb5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350242377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3350242377
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.1510759242
Short name T127
Test name
Test status
Simulation time 506986949150 ps
CPU time 5702.61 seconds
Started Jan 24 11:39:58 PM PST 24
Finished Jan 25 01:15:09 AM PST 24
Peak memory 262556 kb
Host smart-ba4cee64-809c-41f2-b25a-60011d54ffdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510759242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.1510759242
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.2388119606
Short name T109
Test name
Test status
Simulation time 350906286927 ps
CPU time 3572.87 seconds
Started Jan 24 11:38:49 PM PST 24
Finished Jan 25 12:38:24 AM PST 24
Peak memory 241788 kb
Host smart-386aeceb-199d-4e18-bada-cf33700186a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388119606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.2388119606
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2493642674
Short name T89
Test name
Test status
Simulation time 95002537 ps
CPU time 1.17 seconds
Started Jan 24 12:58:35 PM PST 24
Finished Jan 24 12:58:48 PM PST 24
Peak memory 196204 kb
Host smart-23a1acef-c28d-434b-a6b0-3e20385930a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493642674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2493642674
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3300482406
Short name T620
Test name
Test status
Simulation time 165390391753 ps
CPU time 2943.42 seconds
Started Jan 24 11:39:07 PM PST 24
Finished Jan 25 12:28:12 AM PST 24
Peak memory 248464 kb
Host smart-baf4c856-f6d4-4322-ab00-beff8c804280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300482406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3300482406
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.325672707
Short name T120
Test name
Test status
Simulation time 98796737576 ps
CPU time 1410.5 seconds
Started Jan 24 11:40:01 PM PST 24
Finished Jan 25 12:03:36 AM PST 24
Peak memory 247876 kb
Host smart-725ed6c9-95bd-41a9-865a-8e5eba92852b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325672707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.325672707
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.20952529
Short name T122
Test name
Test status
Simulation time 142844541982 ps
CPU time 1809.76 seconds
Started Jan 24 11:41:53 PM PST 24
Finished Jan 25 12:12:05 AM PST 24
Peak memory 234244 kb
Host smart-802ad2b0-4418-4341-97be-e64edc6a23e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20952529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.20952529
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3992456317
Short name T111
Test name
Test status
Simulation time 116786385111 ps
CPU time 2081.28 seconds
Started Jan 25 12:19:52 AM PST 24
Finished Jan 25 12:54:34 AM PST 24
Peak memory 215776 kb
Host smart-63719bb6-b1cb-4ce8-8e67-147eda85ac5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992456317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.3992456317
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.2802614892
Short name T130
Test name
Test status
Simulation time 160451784775 ps
CPU time 3871.47 seconds
Started Jan 24 11:38:11 PM PST 24
Finished Jan 25 12:42:49 AM PST 24
Peak memory 264324 kb
Host smart-dabcceb9-dc27-459c-952e-ffd624492af6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802614892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.2802614892
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2649359540
Short name T61
Test name
Test status
Simulation time 125258806 ps
CPU time 1.95 seconds
Started Jan 24 12:57:57 PM PST 24
Finished Jan 24 12:58:25 PM PST 24
Peak memory 197920 kb
Host smart-e384b648-738c-4f5c-8ed7-463a06eb9659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649359540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2649359540
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3839394287
Short name T839
Test name
Test status
Simulation time 191799841 ps
CPU time 1.85 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:18 PM PST 24
Peak memory 191856 kb
Host smart-23567305-965a-45cd-9431-660539140dfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839394287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3839394287
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3402043425
Short name T890
Test name
Test status
Simulation time 828306907 ps
CPU time 8.34 seconds
Started Jan 24 12:57:38 PM PST 24
Finished Jan 24 12:58:09 PM PST 24
Peak memory 191844 kb
Host smart-c25081ad-2886-4eba-a846-c4751e500db8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402043425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3402043425
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.407445650
Short name T65
Test name
Test status
Simulation time 89426231 ps
CPU time 0.65 seconds
Started Jan 24 12:57:35 PM PST 24
Finished Jan 24 12:57:59 PM PST 24
Peak memory 193724 kb
Host smart-8e6e1159-c264-4bcb-b682-7c4f3eda9c7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407445650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.407445650
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3708168557
Short name T879
Test name
Test status
Simulation time 11539430513 ps
CPU time 156.91 seconds
Started Jan 24 12:57:46 PM PST 24
Finished Jan 24 01:00:47 PM PST 24
Peak memory 206540 kb
Host smart-9c1d9361-277f-4258-8ae2-fe3b7bb35a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708168557 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3708168557
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.221552488
Short name T149
Test name
Test status
Simulation time 70912589 ps
CPU time 0.67 seconds
Started Jan 24 12:57:38 PM PST 24
Finished Jan 24 12:58:01 PM PST 24
Peak memory 194004 kb
Host smart-01d3a317-b3d5-41c0-8766-b92ba6229b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221552488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.221552488
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3011022409
Short name T883
Test name
Test status
Simulation time 14149045 ps
CPU time 0.59 seconds
Started Jan 24 12:57:38 PM PST 24
Finished Jan 24 12:58:01 PM PST 24
Peak memory 183460 kb
Host smart-92052c84-49c7-4e8a-b0f1-323438d12446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011022409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3011022409
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2272893412
Short name T841
Test name
Test status
Simulation time 121280834 ps
CPU time 1.29 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:17 PM PST 24
Peak memory 191840 kb
Host smart-ca16058f-7bc3-4658-a7d0-185773d71bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272893412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2272893412
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1802294353
Short name T153
Test name
Test status
Simulation time 483553030 ps
CPU time 2.78 seconds
Started Jan 24 12:57:38 PM PST 24
Finished Jan 24 12:58:04 PM PST 24
Peak memory 198356 kb
Host smart-9c5cb15f-6269-46b7-8f22-d6aa47d4f7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802294353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1802294353
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2106565572
Short name T19
Test name
Test status
Simulation time 147278690 ps
CPU time 2.45 seconds
Started Jan 24 12:57:36 PM PST 24
Finished Jan 24 12:58:01 PM PST 24
Peak memory 198032 kb
Host smart-617f1d4c-9d16-49ef-b107-d7ae1ec08c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106565572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2106565572
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2504407359
Short name T79
Test name
Test status
Simulation time 175022256 ps
CPU time 2.5 seconds
Started Jan 24 12:57:45 PM PST 24
Finished Jan 24 12:58:11 PM PST 24
Peak memory 191860 kb
Host smart-86c97ff5-664e-417b-bc12-41543ac4ecbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504407359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2504407359
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3995021343
Short name T870
Test name
Test status
Simulation time 1826090733 ps
CPU time 6.47 seconds
Started Jan 24 01:58:53 PM PST 24
Finished Jan 24 01:59:02 PM PST 24
Peak memory 191940 kb
Host smart-6f5c5e8e-5969-40e5-865c-7523c5a2beb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995021343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3995021343
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2298085935
Short name T143
Test name
Test status
Simulation time 19686362 ps
CPU time 0.69 seconds
Started Jan 24 12:57:50 PM PST 24
Finished Jan 24 12:58:15 PM PST 24
Peak memory 193588 kb
Host smart-4fb68dfe-05ab-4ab8-9666-bf26b8e67571
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298085935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2298085935
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3372174393
Short name T22
Test name
Test status
Simulation time 121080998 ps
CPU time 1.49 seconds
Started Jan 24 12:57:50 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 198244 kb
Host smart-b3ea09d7-5aea-45b8-bdf8-7ec517e1975c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372174393 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3372174393
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.176661950
Short name T17
Test name
Test status
Simulation time 17788531 ps
CPU time 0.65 seconds
Started Jan 24 12:57:55 PM PST 24
Finished Jan 24 12:58:21 PM PST 24
Peak memory 193532 kb
Host smart-dfb3a269-24fa-456c-a530-e65cb13ff077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176661950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.176661950
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2216033470
Short name T171
Test name
Test status
Simulation time 16029095 ps
CPU time 0.57 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 182364 kb
Host smart-f2f34fcd-f3c1-477d-a622-0f1476f3d250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216033470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2216033470
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1910078863
Short name T882
Test name
Test status
Simulation time 57866155 ps
CPU time 0.89 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 194768 kb
Host smart-062de730-aeae-42e5-a34e-2979d03ea0c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910078863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1910078863
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1250511659
Short name T26
Test name
Test status
Simulation time 59641131 ps
CPU time 1.07 seconds
Started Jan 24 12:57:53 PM PST 24
Finished Jan 24 12:58:18 PM PST 24
Peak memory 198172 kb
Host smart-8b875c11-d7bf-4c32-901d-bb139a418993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250511659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1250511659
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1740546165
Short name T72
Test name
Test status
Simulation time 45605297 ps
CPU time 1.13 seconds
Started Jan 24 12:57:53 PM PST 24
Finished Jan 24 12:58:18 PM PST 24
Peak memory 197732 kb
Host smart-d5aefe95-560e-403a-a798-40476fd7e299
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740546165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1740546165
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3970751928
Short name T160
Test name
Test status
Simulation time 17060809244 ps
CPU time 230.76 seconds
Started Jan 24 12:58:27 PM PST 24
Finished Jan 24 01:02:30 PM PST 24
Peak memory 206480 kb
Host smart-4a528935-3bfa-4f81-9319-97e133f527ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970751928 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3970751928
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2830279460
Short name T851
Test name
Test status
Simulation time 45576266 ps
CPU time 0.71 seconds
Started Jan 24 12:58:24 PM PST 24
Finished Jan 24 12:58:38 PM PST 24
Peak memory 194516 kb
Host smart-70b75230-86df-4c26-b9e4-85707495ce60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830279460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2830279460
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3090594215
Short name T158
Test name
Test status
Simulation time 32914020 ps
CPU time 0.58 seconds
Started Jan 24 12:58:19 PM PST 24
Finished Jan 24 12:58:36 PM PST 24
Peak memory 183484 kb
Host smart-e60464d0-6d36-4dcb-9c1e-d59abdcc0d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090594215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3090594215
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1180421386
Short name T893
Test name
Test status
Simulation time 76437258 ps
CPU time 1.15 seconds
Started Jan 24 12:58:30 PM PST 24
Finished Jan 24 12:58:43 PM PST 24
Peak memory 191824 kb
Host smart-359a8bb7-7b43-4af1-9d08-f9ed1e082b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180421386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1180421386
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.391780762
Short name T178
Test name
Test status
Simulation time 121044058 ps
CPU time 2.94 seconds
Started Jan 24 12:58:20 PM PST 24
Finished Jan 24 12:58:39 PM PST 24
Peak memory 198180 kb
Host smart-3dc93515-87bf-493c-8835-17517a278e17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391780762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.391780762
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.890982083
Short name T164
Test name
Test status
Simulation time 99147182 ps
CPU time 1.75 seconds
Started Jan 24 12:58:28 PM PST 24
Finished Jan 24 12:58:42 PM PST 24
Peak memory 197516 kb
Host smart-6d7a6f72-dca6-4641-a25e-2f760c3c343c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890982083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.890982083
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1301162887
Short name T30
Test name
Test status
Simulation time 74671838 ps
CPU time 1.83 seconds
Started Jan 24 12:58:25 PM PST 24
Finished Jan 24 12:58:40 PM PST 24
Peak memory 198332 kb
Host smart-07de9b05-e0ac-4721-b584-ccab4855722a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301162887 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1301162887
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3590506793
Short name T860
Test name
Test status
Simulation time 20676257 ps
CPU time 0.6 seconds
Started Jan 24 12:58:26 PM PST 24
Finished Jan 24 12:58:39 PM PST 24
Peak memory 193588 kb
Host smart-6f7d062c-e02c-436a-b792-92f008c8e1aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590506793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3590506793
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3491487254
Short name T155
Test name
Test status
Simulation time 25142965 ps
CPU time 0.59 seconds
Started Jan 24 12:58:25 PM PST 24
Finished Jan 24 12:58:38 PM PST 24
Peak memory 183532 kb
Host smart-9c470b69-be2b-4916-9d7c-1aed9b22b8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491487254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3491487254
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2999722571
Short name T849
Test name
Test status
Simulation time 63660406 ps
CPU time 1.35 seconds
Started Jan 24 12:58:28 PM PST 24
Finished Jan 24 12:58:41 PM PST 24
Peak memory 191876 kb
Host smart-c5fe0733-9a85-458d-a2a0-35b877335b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999722571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2999722571
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4042381113
Short name T861
Test name
Test status
Simulation time 365683014 ps
CPU time 1.98 seconds
Started Jan 24 12:58:21 PM PST 24
Finished Jan 24 12:58:38 PM PST 24
Peak memory 198364 kb
Host smart-076cb1ab-89bc-4769-a7fc-ad359a58e6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042381113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4042381113
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2427430403
Short name T889
Test name
Test status
Simulation time 22796035 ps
CPU time 0.75 seconds
Started Jan 24 12:58:37 PM PST 24
Finished Jan 24 12:58:50 PM PST 24
Peak memory 194776 kb
Host smart-7fd614cb-3ffe-445f-bdf1-878cd09a3454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427430403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2427430403
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1308127282
Short name T833
Test name
Test status
Simulation time 14754373 ps
CPU time 0.61 seconds
Started Jan 24 12:58:40 PM PST 24
Finished Jan 24 12:58:54 PM PST 24
Peak memory 183524 kb
Host smart-1daa85e0-d20f-4116-baa6-4b6b92912084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308127282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1308127282
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.197594078
Short name T847
Test name
Test status
Simulation time 278521437 ps
CPU time 0.96 seconds
Started Jan 24 12:58:38 PM PST 24
Finished Jan 24 12:58:52 PM PST 24
Peak memory 191884 kb
Host smart-66ead56a-71be-4ea5-b9fb-8069e7c2ec33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197594078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.197594078
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.344295629
Short name T62
Test name
Test status
Simulation time 274620582 ps
CPU time 3.69 seconds
Started Jan 24 12:58:28 PM PST 24
Finished Jan 24 12:58:44 PM PST 24
Peak memory 198228 kb
Host smart-c32862e9-4bb6-44cf-abc5-0f8d8f14826c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344295629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.344295629
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3519037142
Short name T858
Test name
Test status
Simulation time 662990085 ps
CPU time 1.91 seconds
Started Jan 24 12:58:28 PM PST 24
Finished Jan 24 12:58:42 PM PST 24
Peak memory 197964 kb
Host smart-ab05b98d-8e00-46b4-849d-5b14c134cdbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519037142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3519037142
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2218037779
Short name T13
Test name
Test status
Simulation time 64844357 ps
CPU time 1.56 seconds
Started Jan 24 12:58:35 PM PST 24
Finished Jan 24 12:58:49 PM PST 24
Peak memory 198196 kb
Host smart-f5fd27a5-1475-48ba-827a-fd5245722970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218037779 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2218037779
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2305835503
Short name T154
Test name
Test status
Simulation time 47245758 ps
CPU time 0.57 seconds
Started Jan 24 12:58:37 PM PST 24
Finished Jan 24 12:58:50 PM PST 24
Peak memory 183364 kb
Host smart-21875788-8c93-492b-a920-2c4991353768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305835503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2305835503
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1438453598
Short name T29
Test name
Test status
Simulation time 395974387 ps
CPU time 1.37 seconds
Started Jan 24 12:58:41 PM PST 24
Finished Jan 24 12:58:55 PM PST 24
Peak memory 198152 kb
Host smart-f269b39a-9c52-40d4-ad30-b967c5d145d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438453598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1438453598
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1419951664
Short name T150
Test name
Test status
Simulation time 114319623 ps
CPU time 2.27 seconds
Started Jan 24 12:58:37 PM PST 24
Finished Jan 24 12:58:51 PM PST 24
Peak memory 197888 kb
Host smart-3417ea97-c3fc-4abe-b41e-e105ee241add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419951664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1419951664
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.871202720
Short name T24
Test name
Test status
Simulation time 67633293 ps
CPU time 1.01 seconds
Started Jan 24 12:58:36 PM PST 24
Finished Jan 24 12:58:49 PM PST 24
Peak memory 198020 kb
Host smart-e9e443c1-b07e-4ce4-aab6-09b5a2697931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871202720 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.871202720
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1113477658
Short name T177
Test name
Test status
Simulation time 94438338 ps
CPU time 0.73 seconds
Started Jan 24 12:58:36 PM PST 24
Finished Jan 24 12:58:48 PM PST 24
Peak memory 193936 kb
Host smart-6036e4ad-f706-411a-b645-126ee8d93ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113477658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1113477658
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.523779620
Short name T877
Test name
Test status
Simulation time 104287178 ps
CPU time 0.57 seconds
Started Jan 24 12:58:41 PM PST 24
Finished Jan 24 12:58:54 PM PST 24
Peak memory 183272 kb
Host smart-9389b2a1-c22a-4b0d-baa0-454748734d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523779620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.523779620
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1316238412
Short name T85
Test name
Test status
Simulation time 81708013 ps
CPU time 1.4 seconds
Started Jan 24 12:58:41 PM PST 24
Finished Jan 24 12:58:55 PM PST 24
Peak memory 191804 kb
Host smart-03ccd694-80d9-477e-a52b-70c743d6c574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316238412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1316238412
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4155311237
Short name T842
Test name
Test status
Simulation time 612739236 ps
CPU time 2.94 seconds
Started Jan 24 12:58:34 PM PST 24
Finished Jan 24 12:58:50 PM PST 24
Peak memory 198308 kb
Host smart-90ab4f4a-0bba-4e6e-868f-1cdb612360c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155311237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4155311237
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1227572263
Short name T137
Test name
Test status
Simulation time 1158300702 ps
CPU time 1.76 seconds
Started Jan 24 12:58:35 PM PST 24
Finished Jan 24 12:58:49 PM PST 24
Peak memory 197788 kb
Host smart-c16797f3-887d-47b8-8776-736541515103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227572263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1227572263
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2693912706
Short name T866
Test name
Test status
Simulation time 76011264 ps
CPU time 1.71 seconds
Started Jan 24 12:58:39 PM PST 24
Finished Jan 24 12:58:54 PM PST 24
Peak memory 198280 kb
Host smart-7e994f51-ee3f-4cee-91b4-20cf671455b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693912706 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2693912706
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.711634056
Short name T80
Test name
Test status
Simulation time 69143304 ps
CPU time 0.69 seconds
Started Jan 24 12:58:39 PM PST 24
Finished Jan 24 12:58:53 PM PST 24
Peak memory 194428 kb
Host smart-aa07d5af-ad76-439c-92b7-4f8a174d4bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711634056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.711634056
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.243881519
Short name T156
Test name
Test status
Simulation time 55068364 ps
CPU time 0.61 seconds
Started Jan 24 12:58:34 PM PST 24
Finished Jan 24 12:58:48 PM PST 24
Peak memory 183388 kb
Host smart-b00457a2-f8db-4e9b-9b3d-5b2dd82fc37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243881519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.243881519
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2773764430
Short name T896
Test name
Test status
Simulation time 80592694 ps
CPU time 1.31 seconds
Started Jan 24 12:58:34 PM PST 24
Finished Jan 24 12:58:48 PM PST 24
Peak memory 191824 kb
Host smart-124cce5e-bf04-4b50-bcbd-056146b3beea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773764430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2773764430
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3798310277
Short name T168
Test name
Test status
Simulation time 592700682 ps
CPU time 2.8 seconds
Started Jan 24 12:58:41 PM PST 24
Finished Jan 24 12:58:57 PM PST 24
Peak memory 198228 kb
Host smart-e9fc8822-80a9-4b63-9ae0-7424ab83fdaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798310277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3798310277
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.371451982
Short name T71
Test name
Test status
Simulation time 288083612 ps
CPU time 1.9 seconds
Started Jan 24 12:58:39 PM PST 24
Finished Jan 24 12:58:54 PM PST 24
Peak memory 197920 kb
Host smart-29180d2f-14d7-4342-b4c9-674f54a5afd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371451982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.371451982
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2502376512
Short name T27
Test name
Test status
Simulation time 55170419959 ps
CPU time 509.73 seconds
Started Jan 24 12:58:44 PM PST 24
Finished Jan 24 01:07:28 PM PST 24
Peak memory 210732 kb
Host smart-b9ce6a21-31ee-4b61-b6c0-b0bec198f971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502376512 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2502376512
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1548047916
Short name T886
Test name
Test status
Simulation time 68784213 ps
CPU time 0.71 seconds
Started Jan 24 12:58:39 PM PST 24
Finished Jan 24 12:58:53 PM PST 24
Peak memory 194096 kb
Host smart-ca9146b5-d589-444e-ac96-c70d38c154e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548047916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1548047916
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.415749063
Short name T863
Test name
Test status
Simulation time 65039852 ps
CPU time 0.55 seconds
Started Jan 24 12:58:33 PM PST 24
Finished Jan 24 12:58:45 PM PST 24
Peak memory 183556 kb
Host smart-0d329c1c-8c75-46dc-9e35-55c97025cf11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415749063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.415749063
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.292453174
Short name T88
Test name
Test status
Simulation time 30266470 ps
CPU time 1.24 seconds
Started Jan 24 12:58:48 PM PST 24
Finished Jan 24 12:59:05 PM PST 24
Peak memory 196480 kb
Host smart-c3f1d8d6-5c77-4622-b57a-fe1c470db712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292453174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.292453174
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3550124853
Short name T170
Test name
Test status
Simulation time 863707369 ps
CPU time 2.73 seconds
Started Jan 24 12:58:37 PM PST 24
Finished Jan 24 12:58:52 PM PST 24
Peak memory 198292 kb
Host smart-350eddfd-ce06-4a32-9aae-6f872c7610bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550124853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3550124853
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2014896013
Short name T850
Test name
Test status
Simulation time 381124408 ps
CPU time 1.83 seconds
Started Jan 24 12:58:38 PM PST 24
Finished Jan 24 12:58:52 PM PST 24
Peak memory 197868 kb
Host smart-b835d467-6859-4c18-a4ae-82694c169fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014896013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2014896013
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3618446057
Short name T832
Test name
Test status
Simulation time 141202676 ps
CPU time 1.8 seconds
Started Jan 24 12:58:51 PM PST 24
Finished Jan 24 12:59:08 PM PST 24
Peak memory 198392 kb
Host smart-f07cc9a8-d04e-47c8-a5db-1864b16e23d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618446057 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3618446057
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3378381715
Short name T78
Test name
Test status
Simulation time 20720539 ps
CPU time 0.68 seconds
Started Jan 24 12:58:43 PM PST 24
Finished Jan 24 12:58:58 PM PST 24
Peak memory 193952 kb
Host smart-f32b40f1-e643-4e0a-9f32-a93e39a6b789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378381715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3378381715
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3253898149
Short name T834
Test name
Test status
Simulation time 34944452 ps
CPU time 0.57 seconds
Started Jan 24 12:58:50 PM PST 24
Finished Jan 24 12:59:07 PM PST 24
Peak memory 183568 kb
Host smart-64820dbf-38eb-4ef1-bb3d-3821ece00b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253898149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3253898149
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3949748645
Short name T853
Test name
Test status
Simulation time 47671554 ps
CPU time 0.83 seconds
Started Jan 24 12:58:51 PM PST 24
Finished Jan 24 12:59:07 PM PST 24
Peak memory 195056 kb
Host smart-a64c777e-bb57-4c74-97eb-12099f28848d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949748645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3949748645
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.108681620
Short name T897
Test name
Test status
Simulation time 410294278 ps
CPU time 2.63 seconds
Started Jan 24 12:58:49 PM PST 24
Finished Jan 24 12:59:08 PM PST 24
Peak memory 198332 kb
Host smart-085e3114-b3ba-4834-a42d-2644e1731651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108681620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.108681620
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1982318292
Short name T15
Test name
Test status
Simulation time 155124231 ps
CPU time 2.51 seconds
Started Jan 24 12:58:50 PM PST 24
Finished Jan 24 12:59:09 PM PST 24
Peak memory 198012 kb
Host smart-373abf23-b0ea-4ba3-9a54-1ed9c667ec70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982318292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1982318292
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1108680361
Short name T894
Test name
Test status
Simulation time 471122830450 ps
CPU time 717.75 seconds
Started Jan 24 12:58:56 PM PST 24
Finished Jan 24 01:11:14 PM PST 24
Peak memory 207172 kb
Host smart-d693a307-e55f-425d-8c5f-50c757521b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108680361 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1108680361
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3396020622
Short name T175
Test name
Test status
Simulation time 28749512 ps
CPU time 0.62 seconds
Started Jan 24 12:58:42 PM PST 24
Finished Jan 24 12:58:56 PM PST 24
Peak memory 193816 kb
Host smart-21bf65a2-2456-4a01-a793-38b492a6d88f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396020622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3396020622
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3950295438
Short name T134
Test name
Test status
Simulation time 71754900 ps
CPU time 0.59 seconds
Started Jan 24 12:58:45 PM PST 24
Finished Jan 24 12:58:59 PM PST 24
Peak memory 183576 kb
Host smart-a9e5d090-9029-49bd-b343-552f43823152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950295438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3950295438
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3148986673
Short name T871
Test name
Test status
Simulation time 207347086 ps
CPU time 1.37 seconds
Started Jan 24 12:58:44 PM PST 24
Finished Jan 24 12:59:00 PM PST 24
Peak memory 191908 kb
Host smart-043f69d6-acb5-4e58-a725-70085341ffae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148986673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3148986673
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2839153403
Short name T179
Test name
Test status
Simulation time 412478059 ps
CPU time 3.65 seconds
Started Jan 24 12:58:51 PM PST 24
Finished Jan 24 12:59:11 PM PST 24
Peak memory 198380 kb
Host smart-0e8dbab8-64b3-400d-8972-79d1a4073181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839153403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2839153403
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3113274528
Short name T152
Test name
Test status
Simulation time 263474803 ps
CPU time 1.72 seconds
Started Jan 24 12:58:49 PM PST 24
Finished Jan 24 12:59:07 PM PST 24
Peak memory 197840 kb
Host smart-4357e96d-e373-4c7a-9ffd-88f2378d38e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113274528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3113274528
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.335522507
Short name T167
Test name
Test status
Simulation time 33655403 ps
CPU time 1.44 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 198212 kb
Host smart-a62ee3c8-7aab-4e07-b4be-938dab33dcae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335522507 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.335522507
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2041824765
Short name T77
Test name
Test status
Simulation time 158270958 ps
CPU time 0.73 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 194188 kb
Host smart-35f335f2-fe5b-4982-8514-bc4d308f11fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041824765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2041824765
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2883682806
Short name T878
Test name
Test status
Simulation time 35897167 ps
CPU time 0.6 seconds
Started Jan 24 01:31:37 PM PST 24
Finished Jan 24 01:32:29 PM PST 24
Peak memory 183608 kb
Host smart-60b5199b-d66b-4710-818a-f868308b289c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883682806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2883682806
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.566196293
Short name T838
Test name
Test status
Simulation time 46887078 ps
CPU time 0.75 seconds
Started Jan 24 12:58:55 PM PST 24
Finished Jan 24 12:59:14 PM PST 24
Peak memory 191684 kb
Host smart-2ba24a9d-04f1-42a9-9d15-cd10c51ae3b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566196293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.566196293
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3581521853
Short name T63
Test name
Test status
Simulation time 498626902 ps
CPU time 3.61 seconds
Started Jan 24 12:58:58 PM PST 24
Finished Jan 24 12:59:21 PM PST 24
Peak memory 198196 kb
Host smart-7542da13-5cb5-444f-afe4-e4290feb5426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581521853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3581521853
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2694478105
Short name T135
Test name
Test status
Simulation time 111372560 ps
CPU time 1.94 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 197864 kb
Host smart-0edcaa75-f2fe-4461-a1e0-7c5b07149ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694478105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2694478105
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.912161560
Short name T44
Test name
Test status
Simulation time 130276432 ps
CPU time 2.57 seconds
Started Jan 24 12:57:50 PM PST 24
Finished Jan 24 12:58:17 PM PST 24
Peak memory 191736 kb
Host smart-9ecf7237-fb9d-430d-b62b-ef6f32a6052f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912161560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.912161560
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2580490447
Short name T888
Test name
Test status
Simulation time 350442876 ps
CPU time 3.59 seconds
Started Jan 24 12:57:47 PM PST 24
Finished Jan 24 12:58:14 PM PST 24
Peak memory 191892 kb
Host smart-fb0b68ec-0405-40ff-acb7-9c676f97070e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580490447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2580490447
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2378672374
Short name T846
Test name
Test status
Simulation time 80058292 ps
CPU time 0.68 seconds
Started Jan 24 12:57:46 PM PST 24
Finished Jan 24 12:58:10 PM PST 24
Peak memory 193868 kb
Host smart-662a659a-971d-4734-b433-1778017b5ff1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378672374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2378672374
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4283902016
Short name T146
Test name
Test status
Simulation time 44439294 ps
CPU time 0.93 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 197916 kb
Host smart-6a79bc5f-9bec-447a-8727-787d08c345da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283902016 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4283902016
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2426834093
Short name T86
Test name
Test status
Simulation time 18629989 ps
CPU time 0.62 seconds
Started Jan 24 01:03:38 PM PST 24
Finished Jan 24 01:04:13 PM PST 24
Peak memory 193800 kb
Host smart-c1d73a39-aad1-47d4-866a-d1e6ae2ac643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426834093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2426834093
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.596521777
Short name T82
Test name
Test status
Simulation time 14854114 ps
CPU time 0.6 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 182512 kb
Host smart-f9563cb6-d1d2-41dd-9fa7-9418542061a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596521777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.596521777
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3732380855
Short name T87
Test name
Test status
Simulation time 79793515 ps
CPU time 0.82 seconds
Started Jan 24 12:57:54 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 191772 kb
Host smart-d410f127-3840-42d4-85fa-6b979b49e990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732380855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3732380855
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.787205204
Short name T172
Test name
Test status
Simulation time 227770821 ps
CPU time 1.78 seconds
Started Jan 24 12:57:48 PM PST 24
Finished Jan 24 12:58:12 PM PST 24
Peak memory 198356 kb
Host smart-8b517b83-9e90-4103-bb3f-0f39695dd42f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787205204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.787205204
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.633101006
Short name T884
Test name
Test status
Simulation time 100062048 ps
CPU time 0.58 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183464 kb
Host smart-d737d3d0-bf58-44a1-9000-df7502d349e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633101006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.633101006
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.950023006
Short name T159
Test name
Test status
Simulation time 16473708 ps
CPU time 0.6 seconds
Started Jan 24 12:58:58 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 183396 kb
Host smart-6a21523b-dbbb-4e39-bf4a-62429cf6e868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950023006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.950023006
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3909101683
Short name T162
Test name
Test status
Simulation time 30320802 ps
CPU time 0.57 seconds
Started Jan 24 12:58:58 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 183540 kb
Host smart-69b12f37-199a-4475-9d05-b402926e4a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909101683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3909101683
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.500341080
Short name T845
Test name
Test status
Simulation time 37434569 ps
CPU time 0.6 seconds
Started Jan 24 12:58:59 PM PST 24
Finished Jan 24 12:59:21 PM PST 24
Peak memory 183548 kb
Host smart-393b225e-d26c-4359-bcf2-2733ae95af73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500341080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.500341080
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.294250511
Short name T856
Test name
Test status
Simulation time 50225767 ps
CPU time 0.57 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183284 kb
Host smart-91b6cc09-3a03-4131-939f-c4e8d6891133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294250511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.294250511
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1869325059
Short name T852
Test name
Test status
Simulation time 15108036 ps
CPU time 0.57 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183380 kb
Host smart-45852f1d-e3ed-4cdb-b60d-1df4b8375041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869325059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1869325059
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2992059845
Short name T836
Test name
Test status
Simulation time 24151405 ps
CPU time 0.61 seconds
Started Jan 24 12:58:56 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183492 kb
Host smart-168ce8f2-14b8-44b1-8cef-8042f6d1b97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992059845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2992059845
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3030405802
Short name T169
Test name
Test status
Simulation time 14212717 ps
CPU time 0.62 seconds
Started Jan 24 12:59:03 PM PST 24
Finished Jan 24 12:59:28 PM PST 24
Peak memory 183560 kb
Host smart-6e2b41d7-d4e2-4f2b-a34b-425c6d3e9206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030405802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3030405802
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3484792573
Short name T174
Test name
Test status
Simulation time 23793234 ps
CPU time 0.62 seconds
Started Jan 24 12:59:01 PM PST 24
Finished Jan 24 12:59:25 PM PST 24
Peak memory 183532 kb
Host smart-23ac591f-2417-48c9-9e5c-ba4edcf91083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484792573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3484792573
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.552478155
Short name T69
Test name
Test status
Simulation time 43487019 ps
CPU time 0.64 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183492 kb
Host smart-dbde62da-c9d0-41b2-9633-41b686ac2c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552478155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.552478155
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.471808715
Short name T892
Test name
Test status
Simulation time 62434399 ps
CPU time 1.27 seconds
Started Jan 24 12:57:54 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 183744 kb
Host smart-bdc5badd-6069-419a-a2b8-65051608a4a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471808715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.471808715
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2625654391
Short name T180
Test name
Test status
Simulation time 445715916 ps
CPU time 6.36 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:21 PM PST 24
Peak memory 195796 kb
Host smart-9df820c5-68a1-4dc1-96f1-ead2a60b5038
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625654391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2625654391
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4235338931
Short name T67
Test name
Test status
Simulation time 97861076 ps
CPU time 0.74 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 193816 kb
Host smart-719395bc-1766-4598-8108-0f5dd65b6650
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235338931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4235338931
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1310141614
Short name T140
Test name
Test status
Simulation time 80861083 ps
CPU time 0.95 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 198112 kb
Host smart-f3cbc2a8-711e-459a-a2e7-4c0bfbeec4ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310141614 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1310141614
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.985331640
Short name T881
Test name
Test status
Simulation time 12462153 ps
CPU time 0.61 seconds
Started Jan 24 12:57:54 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 193656 kb
Host smart-25f62c6a-adf2-43f0-a52c-8ec3af41c78b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985331640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.985331640
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2106201438
Short name T68
Test name
Test status
Simulation time 107318981 ps
CPU time 1.08 seconds
Started Jan 24 12:57:49 PM PST 24
Finished Jan 24 12:58:14 PM PST 24
Peak memory 191860 kb
Host smart-cb21a495-b2e1-403c-bfbf-917edaff821d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106201438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2106201438
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.788887934
Short name T843
Test name
Test status
Simulation time 144061477 ps
CPU time 3.16 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 198348 kb
Host smart-f1fd2d53-8028-43b7-b40e-c2a157bb1294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788887934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.788887934
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1219691415
Short name T74
Test name
Test status
Simulation time 47424006 ps
CPU time 1.18 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:17 PM PST 24
Peak memory 197516 kb
Host smart-c01130a9-8352-4de8-8cd9-3a934abbbae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219691415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1219691415
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3469382970
Short name T151
Test name
Test status
Simulation time 63628503 ps
CPU time 0.59 seconds
Started Jan 24 12:59:05 PM PST 24
Finished Jan 24 12:59:33 PM PST 24
Peak memory 183096 kb
Host smart-64b8def9-89bb-49c1-80d1-9954ccd66de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469382970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3469382970
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.764780638
Short name T869
Test name
Test status
Simulation time 10557245 ps
CPU time 0.56 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183484 kb
Host smart-dbd10037-8afb-44db-ad88-41923eed38aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764780638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.764780638
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3479259058
Short name T148
Test name
Test status
Simulation time 13615887 ps
CPU time 0.58 seconds
Started Jan 24 12:58:56 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183492 kb
Host smart-eba15a67-c7ea-4714-98f7-31d528f5a7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479259058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3479259058
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3206980183
Short name T20
Test name
Test status
Simulation time 45457102 ps
CPU time 0.63 seconds
Started Jan 24 12:59:01 PM PST 24
Finished Jan 24 12:59:27 PM PST 24
Peak memory 183536 kb
Host smart-c8e5af36-2a7b-489d-82b6-285969f3b9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206980183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3206980183
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1776564190
Short name T163
Test name
Test status
Simulation time 44832698 ps
CPU time 0.61 seconds
Started Jan 24 12:59:01 PM PST 24
Finished Jan 24 12:59:27 PM PST 24
Peak memory 183524 kb
Host smart-53d1f38d-099b-4da8-811a-ebc692c15ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776564190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1776564190
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.802604561
Short name T70
Test name
Test status
Simulation time 13326251 ps
CPU time 0.57 seconds
Started Jan 24 01:12:38 PM PST 24
Finished Jan 24 01:13:31 PM PST 24
Peak memory 183552 kb
Host smart-a02f1c5d-5312-4eac-8d93-68d191b04592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802604561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.802604561
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2449495128
Short name T145
Test name
Test status
Simulation time 26731281 ps
CPU time 0.56 seconds
Started Jan 24 12:58:58 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 183444 kb
Host smart-fef1024a-94a8-44b0-b848-312fde577be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449495128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2449495128
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.4263725739
Short name T875
Test name
Test status
Simulation time 13737573 ps
CPU time 0.56 seconds
Started Jan 24 12:58:58 PM PST 24
Finished Jan 24 12:59:18 PM PST 24
Peak memory 183444 kb
Host smart-26d9e195-d1d8-4b01-93d3-2a383504eb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263725739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.4263725739
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.89513573
Short name T21
Test name
Test status
Simulation time 42762105 ps
CPU time 0.59 seconds
Started Jan 24 12:59:03 PM PST 24
Finished Jan 24 12:59:28 PM PST 24
Peak memory 183536 kb
Host smart-29d7254d-4c90-4baa-b4d1-b9d101345768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89513573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.89513573
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3738660689
Short name T142
Test name
Test status
Simulation time 12219920 ps
CPU time 0.56 seconds
Started Jan 24 01:08:27 PM PST 24
Finished Jan 24 01:09:01 PM PST 24
Peak memory 183608 kb
Host smart-2205529b-dace-4057-ad19-9616af63d43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738660689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3738660689
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3060106427
Short name T83
Test name
Test status
Simulation time 293455047 ps
CPU time 3.16 seconds
Started Jan 24 12:57:52 PM PST 24
Finished Jan 24 12:58:19 PM PST 24
Peak memory 191820 kb
Host smart-b17659a3-7fa6-4d19-acb4-2145e39f31bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060106427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3060106427
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3991115631
Short name T84
Test name
Test status
Simulation time 112722528 ps
CPU time 0.74 seconds
Started Jan 24 12:57:48 PM PST 24
Finished Jan 24 12:58:11 PM PST 24
Peak memory 193964 kb
Host smart-826f3d08-fe45-46ec-b1f4-997e737838ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991115631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3991115631
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3970200641
Short name T868
Test name
Test status
Simulation time 38187228 ps
CPU time 1.55 seconds
Started Jan 24 12:57:53 PM PST 24
Finished Jan 24 12:58:19 PM PST 24
Peak memory 198316 kb
Host smart-6ca69cc6-2ad2-4ee9-8b47-c82120beb018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970200641 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3970200641
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.604515755
Short name T66
Test name
Test status
Simulation time 40372071 ps
CPU time 0.64 seconds
Started Jan 24 12:57:46 PM PST 24
Finished Jan 24 12:58:10 PM PST 24
Peak memory 194044 kb
Host smart-9aa40f34-7b79-4928-b17f-2732fa57e079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604515755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.604515755
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4187847994
Short name T844
Test name
Test status
Simulation time 29518921 ps
CPU time 1.27 seconds
Started Jan 24 12:57:55 PM PST 24
Finished Jan 24 12:58:23 PM PST 24
Peak memory 191880 kb
Host smart-c5359e75-c913-4fb2-8234-0bd4503223f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187847994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4187847994
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3196919398
Short name T876
Test name
Test status
Simulation time 46548590 ps
CPU time 2.42 seconds
Started Jan 24 12:57:51 PM PST 24
Finished Jan 24 12:58:17 PM PST 24
Peak memory 198312 kb
Host smart-1701c8e9-453a-4a8f-b370-bb48223400f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196919398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3196919398
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.106574557
Short name T872
Test name
Test status
Simulation time 140438060 ps
CPU time 1.27 seconds
Started Jan 24 01:15:14 PM PST 24
Finished Jan 24 01:15:53 PM PST 24
Peak memory 197796 kb
Host smart-dc8a8477-f766-499a-af21-7ab9a5001422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106574557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.106574557
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.52645981
Short name T173
Test name
Test status
Simulation time 46021421 ps
CPU time 0.62 seconds
Started Jan 24 12:59:03 PM PST 24
Finished Jan 24 12:59:28 PM PST 24
Peak memory 183536 kb
Host smart-81a64a51-543b-4538-b701-932b779ec9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52645981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.52645981
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2537164469
Short name T885
Test name
Test status
Simulation time 19435024 ps
CPU time 0.65 seconds
Started Jan 24 12:58:57 PM PST 24
Finished Jan 24 12:59:17 PM PST 24
Peak memory 183484 kb
Host smart-245d1d65-840f-4f2e-92f8-e34f297f29ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537164469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2537164469
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1301661917
Short name T73
Test name
Test status
Simulation time 13257032 ps
CPU time 0.57 seconds
Started Jan 24 01:19:56 PM PST 24
Finished Jan 24 01:21:00 PM PST 24
Peak memory 183592 kb
Host smart-8530b069-9b4e-492d-bc27-578e69acfb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301661917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1301661917
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4262018424
Short name T141
Test name
Test status
Simulation time 38389856 ps
CPU time 0.57 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:42 PM PST 24
Peak memory 183536 kb
Host smart-b4af48d8-e437-42f3-83eb-42906c237dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262018424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4262018424
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3895323242
Short name T144
Test name
Test status
Simulation time 14647812 ps
CPU time 0.61 seconds
Started Jan 24 12:59:05 PM PST 24
Finished Jan 24 12:59:33 PM PST 24
Peak memory 183132 kb
Host smart-5da3b921-a6e4-4325-8e2c-9422aacdfdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895323242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3895323242
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.268059143
Short name T840
Test name
Test status
Simulation time 15495450 ps
CPU time 0.62 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:39:24 PM PST 24
Peak memory 183608 kb
Host smart-e3bb63f1-ad6f-41ac-9d57-b972632dd4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268059143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.268059143
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.232568428
Short name T891
Test name
Test status
Simulation time 12676105 ps
CPU time 0.59 seconds
Started Jan 24 12:59:13 PM PST 24
Finished Jan 24 12:59:38 PM PST 24
Peak memory 183568 kb
Host smart-74b38a25-2134-4ae0-bf0f-6806ff0aad0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232568428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.232568428
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1854583901
Short name T865
Test name
Test status
Simulation time 47567516 ps
CPU time 0.6 seconds
Started Jan 24 12:59:14 PM PST 24
Finished Jan 24 12:59:38 PM PST 24
Peak memory 183532 kb
Host smart-29ad1724-d599-447e-b3fe-3c12bb9e4633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854583901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1854583901
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4254003519
Short name T895
Test name
Test status
Simulation time 111564797 ps
CPU time 0.63 seconds
Started Jan 24 12:59:01 PM PST 24
Finished Jan 24 12:59:27 PM PST 24
Peak memory 183556 kb
Host smart-a67c22f8-0368-4932-8829-8d9b6bcb8bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254003519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4254003519
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3775106985
Short name T873
Test name
Test status
Simulation time 14423881 ps
CPU time 0.57 seconds
Started Jan 24 12:59:12 PM PST 24
Finished Jan 24 12:59:38 PM PST 24
Peak memory 183536 kb
Host smart-10b693b4-cb24-487e-a0df-71ea4e7afacc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775106985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3775106985
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2192880132
Short name T887
Test name
Test status
Simulation time 15794872 ps
CPU time 1.09 seconds
Started Jan 24 12:57:54 PM PST 24
Finished Jan 24 12:58:20 PM PST 24
Peak memory 198116 kb
Host smart-9dc8d901-ee11-4d1d-8885-ff6526b0c985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192880132 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2192880132
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2770710419
Short name T75
Test name
Test status
Simulation time 22782987 ps
CPU time 0.68 seconds
Started Jan 24 01:43:22 PM PST 24
Finished Jan 24 01:43:42 PM PST 24
Peak memory 194148 kb
Host smart-e9b5f998-afa6-4f2e-9438-6c976dd35329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770710419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2770710419
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2011696065
Short name T867
Test name
Test status
Simulation time 309658578 ps
CPU time 1.4 seconds
Started Jan 24 12:57:56 PM PST 24
Finished Jan 24 12:58:24 PM PST 24
Peak memory 191656 kb
Host smart-49d41354-5cef-4a5a-b0b6-04a15266b069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011696065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2011696065
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3863842361
Short name T859
Test name
Test status
Simulation time 616303722 ps
CPU time 2.47 seconds
Started Jan 24 12:57:55 PM PST 24
Finished Jan 24 12:58:24 PM PST 24
Peak memory 198344 kb
Host smart-7921551c-7460-4350-85a3-77bafa062211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863842361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3863842361
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3210318024
Short name T176
Test name
Test status
Simulation time 191243026 ps
CPU time 1.86 seconds
Started Jan 24 12:57:57 PM PST 24
Finished Jan 24 12:58:25 PM PST 24
Peak memory 197708 kb
Host smart-c151c19f-9a57-4963-9413-33be9f60eb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210318024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3210318024
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1808551387
Short name T854
Test name
Test status
Simulation time 23296819 ps
CPU time 0.93 seconds
Started Jan 24 01:15:07 PM PST 24
Finished Jan 24 01:15:39 PM PST 24
Peak memory 198244 kb
Host smart-0ddcfd53-c379-4ce5-bf8e-ea58d34a63fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808551387 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1808551387
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1173151860
Short name T16
Test name
Test status
Simulation time 13745726 ps
CPU time 0.59 seconds
Started Jan 24 12:57:56 PM PST 24
Finished Jan 24 12:58:23 PM PST 24
Peak memory 193448 kb
Host smart-42b9b6b6-cdcb-48d3-8854-f004ed2c9ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173151860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1173151860
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.935873585
Short name T166
Test name
Test status
Simulation time 37543665 ps
CPU time 0.59 seconds
Started Jan 24 01:19:53 PM PST 24
Finished Jan 24 01:20:55 PM PST 24
Peak memory 183564 kb
Host smart-d562ba1d-ac9d-4dac-be15-d63ab9e1f9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935873585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.935873585
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3460765226
Short name T874
Test name
Test status
Simulation time 119128092 ps
CPU time 0.77 seconds
Started Jan 24 01:39:58 PM PST 24
Finished Jan 24 01:40:46 PM PST 24
Peak memory 191808 kb
Host smart-54dbe848-2b06-4dd4-9cee-b31123f3d7e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460765226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3460765226
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3838840181
Short name T181
Test name
Test status
Simulation time 526825814 ps
CPU time 2.77 seconds
Started Jan 24 01:14:34 PM PST 24
Finished Jan 24 01:15:02 PM PST 24
Peak memory 198460 kb
Host smart-19467c2d-bb62-4acb-957d-a40988238546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838840181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3838840181
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.875741782
Short name T25
Test name
Test status
Simulation time 20624058 ps
CPU time 1.07 seconds
Started Jan 24 12:58:05 PM PST 24
Finished Jan 24 12:58:29 PM PST 24
Peak memory 198144 kb
Host smart-164d62c5-1bfd-4d1d-8c26-73428881d94f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875741782 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.875741782
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.804117648
Short name T64
Test name
Test status
Simulation time 81071973 ps
CPU time 0.72 seconds
Started Jan 24 12:58:04 PM PST 24
Finished Jan 24 12:58:28 PM PST 24
Peak memory 194344 kb
Host smart-2ab93931-3745-427c-abad-2075b4d5f645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804117648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.804117648
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.19190986
Short name T14
Test name
Test status
Simulation time 20703249 ps
CPU time 0.58 seconds
Started Jan 24 01:03:42 PM PST 24
Finished Jan 24 01:04:23 PM PST 24
Peak memory 183560 kb
Host smart-8e27da99-23cd-457a-9d2e-66795145b2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.19190986
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1590353704
Short name T835
Test name
Test status
Simulation time 94017433 ps
CPU time 1.1 seconds
Started Jan 24 12:58:10 PM PST 24
Finished Jan 24 12:58:33 PM PST 24
Peak memory 191968 kb
Host smart-3b8b6fad-bc88-4b87-aad7-6794f7596399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590353704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1590353704
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3143507948
Short name T157
Test name
Test status
Simulation time 121457790 ps
CPU time 2.63 seconds
Started Jan 24 01:15:38 PM PST 24
Finished Jan 24 01:16:28 PM PST 24
Peak memory 198380 kb
Host smart-6c5864c7-fe4a-432c-938e-de3e3f0bc6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143507948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3143507948
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3462532150
Short name T136
Test name
Test status
Simulation time 624268228 ps
CPU time 2.42 seconds
Started Jan 24 01:03:26 PM PST 24
Finished Jan 24 01:03:59 PM PST 24
Peak memory 198140 kb
Host smart-a474aab5-2cf5-449c-86d9-e0e96df49b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462532150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3462532150
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.296947593
Short name T864
Test name
Test status
Simulation time 25736826 ps
CPU time 1.06 seconds
Started Jan 24 12:58:06 PM PST 24
Finished Jan 24 12:58:30 PM PST 24
Peak memory 198016 kb
Host smart-4d9a998f-91bc-4a13-bece-fed654c04364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296947593 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.296947593
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2645644749
Short name T81
Test name
Test status
Simulation time 40205187 ps
CPU time 0.62 seconds
Started Jan 24 01:36:54 PM PST 24
Finished Jan 24 01:37:32 PM PST 24
Peak memory 193580 kb
Host smart-6c18affc-cbc8-462a-803f-f9096784ad0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645644749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2645644749
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3178000225
Short name T857
Test name
Test status
Simulation time 15373154 ps
CPU time 0.54 seconds
Started Jan 24 12:58:12 PM PST 24
Finished Jan 24 12:58:33 PM PST 24
Peak memory 183484 kb
Host smart-8d651615-33a0-493a-88f6-0d1e6023bf04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178000225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3178000225
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1858513898
Short name T90
Test name
Test status
Simulation time 16178880 ps
CPU time 0.76 seconds
Started Jan 24 12:58:08 PM PST 24
Finished Jan 24 12:58:30 PM PST 24
Peak memory 195056 kb
Host smart-bfbff4c4-fd05-4409-851f-c69510d3fe51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858513898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1858513898
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4180964207
Short name T28
Test name
Test status
Simulation time 46711753 ps
CPU time 2.09 seconds
Started Jan 24 12:58:07 PM PST 24
Finished Jan 24 12:58:32 PM PST 24
Peak memory 198356 kb
Host smart-25daaf75-02c7-4a02-932d-c8cedd438ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180964207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4180964207
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4048608103
Short name T165
Test name
Test status
Simulation time 1569992904 ps
CPU time 1.95 seconds
Started Jan 24 12:58:05 PM PST 24
Finished Jan 24 12:58:30 PM PST 24
Peak memory 197988 kb
Host smart-f05c51d7-8b8d-4205-992f-03c6d8d42f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048608103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4048608103
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1511069153
Short name T862
Test name
Test status
Simulation time 32456236880 ps
CPU time 447.34 seconds
Started Jan 24 12:58:20 PM PST 24
Finished Jan 24 01:06:03 PM PST 24
Peak memory 208256 kb
Host smart-cec53540-a3f3-48f0-9455-5424b2f9eead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511069153 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1511069153
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2317504194
Short name T855
Test name
Test status
Simulation time 16949128 ps
CPU time 0.67 seconds
Started Jan 24 12:58:26 PM PST 24
Finished Jan 24 12:58:39 PM PST 24
Peak memory 194024 kb
Host smart-53830289-516c-4be3-a5b5-96dc5e6cd70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317504194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2317504194
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3746313931
Short name T161
Test name
Test status
Simulation time 47163936 ps
CPU time 0.59 seconds
Started Jan 24 12:58:20 PM PST 24
Finished Jan 24 12:58:37 PM PST 24
Peak memory 183484 kb
Host smart-9d2c5a09-b585-4d17-a99f-d7675a0879e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746313931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3746313931
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3963315282
Short name T880
Test name
Test status
Simulation time 46474879 ps
CPU time 1.06 seconds
Started Jan 24 12:58:21 PM PST 24
Finished Jan 24 12:58:37 PM PST 24
Peak memory 191912 kb
Host smart-eefe0157-3014-457f-ac91-a814c123852e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963315282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3963315282
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1117114355
Short name T848
Test name
Test status
Simulation time 151751258 ps
CPU time 3.08 seconds
Started Jan 24 12:58:12 PM PST 24
Finished Jan 24 12:58:35 PM PST 24
Peak memory 198308 kb
Host smart-da26f2c2-3b08-44b8-a08d-42a0ae9e5d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117114355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1117114355
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3795532661
Short name T837
Test name
Test status
Simulation time 155372827 ps
CPU time 1.76 seconds
Started Jan 24 12:58:26 PM PST 24
Finished Jan 24 12:58:40 PM PST 24
Peak memory 197940 kb
Host smart-eecece6b-c0fc-4c3b-a6d0-9ed7bb2a38b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795532661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3795532661
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2289948264
Short name T659
Test name
Test status
Simulation time 17018287 ps
CPU time 0.6 seconds
Started Jan 24 11:25:11 PM PST 24
Finished Jan 24 11:25:15 PM PST 24
Peak memory 193332 kb
Host smart-bbe72b58-8219-43a5-9bbe-0223c03eb563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289948264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2289948264
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2072224670
Short name T529
Test name
Test status
Simulation time 786615962 ps
CPU time 10.81 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:25:42 PM PST 24
Peak memory 206964 kb
Host smart-efb3e155-b027-4631-a0eb-04fb3d1e28b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072224670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2072224670
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.378424575
Short name T677
Test name
Test status
Simulation time 292986283 ps
CPU time 7.21 seconds
Started Jan 24 11:25:10 PM PST 24
Finished Jan 24 11:25:21 PM PST 24
Peak memory 199100 kb
Host smart-988f5887-b6bf-4add-9e24-7dbebbab69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378424575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.378424575
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3980148578
Short name T96
Test name
Test status
Simulation time 1378057275 ps
CPU time 69.94 seconds
Started Jan 24 11:25:08 PM PST 24
Finished Jan 24 11:26:19 PM PST 24
Peak memory 199124 kb
Host smart-63b93267-f01d-475b-b4c1-bb60ad3c73fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980148578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3980148578
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1144579228
Short name T223
Test name
Test status
Simulation time 34531377520 ps
CPU time 105.69 seconds
Started Jan 25 01:53:06 AM PST 24
Finished Jan 25 01:54:56 AM PST 24
Peak memory 199224 kb
Host smart-2871abdf-2a69-4100-9d6b-f3a7e48cf307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144579228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1144579228
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.489890547
Short name T609
Test name
Test status
Simulation time 1160514279 ps
CPU time 21.29 seconds
Started Jan 25 02:48:13 AM PST 24
Finished Jan 25 02:48:35 AM PST 24
Peak memory 199160 kb
Host smart-52a6f556-bccd-40f0-9edc-c0b34cd54135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489890547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.489890547
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1345301368
Short name T323
Test name
Test status
Simulation time 78142370 ps
CPU time 2.11 seconds
Started Jan 24 11:24:57 PM PST 24
Finished Jan 24 11:25:01 PM PST 24
Peak memory 198984 kb
Host smart-16da614a-e3a4-4693-8523-d85419feb13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345301368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1345301368
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.211388571
Short name T522
Test name
Test status
Simulation time 191085132445 ps
CPU time 827.99 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:39:20 PM PST 24
Peak memory 199120 kb
Host smart-7cb47fe2-36a6-4e27-8d58-e0e78bec9e52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211388571 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.211388571
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3664780381
Short name T286
Test name
Test status
Simulation time 35810891398 ps
CPU time 1139.61 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:44:31 PM PST 24
Peak memory 226512 kb
Host smart-0da56c73-2699-47c6-870b-27950e06617c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664780381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3664780381
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.78113860
Short name T545
Test name
Test status
Simulation time 65452631 ps
CPU time 1.18 seconds
Started Jan 24 11:25:06 PM PST 24
Finished Jan 24 11:25:09 PM PST 24
Peak memory 197612 kb
Host smart-ffe4ed0d-e230-48dc-8ce6-3d402d5ae671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78113860 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.hmac_test_hmac_vectors.78113860
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3202423418
Short name T525
Test name
Test status
Simulation time 99584945104 ps
CPU time 467.78 seconds
Started Jan 25 01:24:47 AM PST 24
Finished Jan 25 01:32:35 AM PST 24
Peak memory 199216 kb
Host smart-4577ef47-69f3-40f0-a969-8f778e60129a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202423418 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.3202423418
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4113056438
Short name T718
Test name
Test status
Simulation time 499836170 ps
CPU time 3.29 seconds
Started Jan 24 11:25:07 PM PST 24
Finished Jan 24 11:25:11 PM PST 24
Peak memory 199084 kb
Host smart-8bdebfca-b909-4bcd-8d79-840d9ca4ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113056438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4113056438
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1362575902
Short name T771
Test name
Test status
Simulation time 19301089 ps
CPU time 0.57 seconds
Started Jan 24 11:25:53 PM PST 24
Finished Jan 24 11:26:01 PM PST 24
Peak memory 193568 kb
Host smart-e72a3bcb-2a2a-4908-b784-08a482493c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362575902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1362575902
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4027646625
Short name T494
Test name
Test status
Simulation time 1215867960 ps
CPU time 42.68 seconds
Started Jan 25 12:47:59 AM PST 24
Finished Jan 25 12:48:43 AM PST 24
Peak memory 231960 kb
Host smart-f4e7556a-5389-4290-82eb-062b07c170ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027646625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4027646625
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2894269964
Short name T503
Test name
Test status
Simulation time 13333217157 ps
CPU time 18.3 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:25:50 PM PST 24
Peak memory 199036 kb
Host smart-d554e777-677d-4179-b70a-271ad9fff6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894269964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2894269964
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1392135901
Short name T427
Test name
Test status
Simulation time 6114770248 ps
CPU time 97.09 seconds
Started Jan 25 01:26:15 AM PST 24
Finished Jan 25 01:27:53 AM PST 24
Peak memory 199280 kb
Host smart-c160735d-2010-4503-9424-ebe85aadc1df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392135901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1392135901
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2531434323
Short name T533
Test name
Test status
Simulation time 3976509110 ps
CPU time 16.07 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:25:48 PM PST 24
Peak memory 199108 kb
Host smart-848f5d59-52bf-4d28-ad87-6f09962beb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531434323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2531434323
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.485598213
Short name T275
Test name
Test status
Simulation time 8209501689 ps
CPU time 39.33 seconds
Started Jan 24 11:25:09 PM PST 24
Finished Jan 24 11:25:49 PM PST 24
Peak memory 199172 kb
Host smart-50dc803d-a2d4-48f5-98a1-b752b1b1f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485598213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.485598213
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.859878919
Short name T47
Test name
Test status
Simulation time 1171116924 ps
CPU time 0.97 seconds
Started Jan 25 12:17:59 AM PST 24
Finished Jan 25 12:18:01 AM PST 24
Peak memory 217188 kb
Host smart-961b352a-cb23-4df9-b11c-8b093c77e3c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859878919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.859878919
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1177608813
Short name T666
Test name
Test status
Simulation time 50565445 ps
CPU time 1.32 seconds
Started Jan 24 11:25:11 PM PST 24
Finished Jan 24 11:25:16 PM PST 24
Peak memory 197664 kb
Host smart-9827b650-f4ab-4092-8d73-c4b509438cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177608813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1177608813
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.131334681
Short name T733
Test name
Test status
Simulation time 213158598667 ps
CPU time 800.2 seconds
Started Jan 25 01:17:20 AM PST 24
Finished Jan 25 01:30:41 AM PST 24
Peak memory 199236 kb
Host smart-16b47805-c1e9-4140-ab6f-a8fd37918fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131334681 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.131334681
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.443918669
Short name T593
Test name
Test status
Simulation time 70833027491 ps
CPU time 1439.46 seconds
Started Jan 25 02:24:11 AM PST 24
Finished Jan 25 02:48:12 AM PST 24
Peak memory 223948 kb
Host smart-7d0e0911-1a58-43d1-a3f0-1d408230de7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443918669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.443918669
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3441269011
Short name T493
Test name
Test status
Simulation time 61995550 ps
CPU time 1.17 seconds
Started Jan 24 11:25:20 PM PST 24
Finished Jan 24 11:25:33 PM PST 24
Peak memory 197936 kb
Host smart-148d84f1-8361-48e3-a4c7-d77aaa577bd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441269011 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3441269011
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.742262364
Short name T540
Test name
Test status
Simulation time 8145686229 ps
CPU time 418.89 seconds
Started Jan 25 04:30:56 AM PST 24
Finished Jan 25 04:38:07 AM PST 24
Peak memory 199168 kb
Host smart-99d991bf-c202-42d4-93f2-3116de5d8bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742262364 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_sha_vectors.742262364
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.625093899
Short name T398
Test name
Test status
Simulation time 8034865265 ps
CPU time 38.96 seconds
Started Jan 25 12:42:12 AM PST 24
Finished Jan 25 12:42:52 AM PST 24
Peak memory 199188 kb
Host smart-994ca1db-1440-491d-a4e1-6ebb638953fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625093899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.625093899
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2615251752
Short name T742
Test name
Test status
Simulation time 88934033 ps
CPU time 0.57 seconds
Started Jan 24 11:27:33 PM PST 24
Finished Jan 24 11:27:36 PM PST 24
Peak memory 192536 kb
Host smart-7b8f702e-4ed8-416c-8c5d-1c31acc8fa6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615251752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2615251752
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.423953902
Short name T472
Test name
Test status
Simulation time 957226774 ps
CPU time 14.85 seconds
Started Jan 24 11:27:16 PM PST 24
Finished Jan 24 11:27:32 PM PST 24
Peak memory 214616 kb
Host smart-8a447c57-6eed-4b9f-9470-ddc1849f298d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423953902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.423953902
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.757622365
Short name T613
Test name
Test status
Simulation time 1572847600 ps
CPU time 19.08 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:27:34 PM PST 24
Peak memory 199176 kb
Host smart-ebde91fb-631f-4715-90cb-7248d99237c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757622365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.757622365
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4294378510
Short name T373
Test name
Test status
Simulation time 260946801 ps
CPU time 14.34 seconds
Started Jan 25 01:00:50 AM PST 24
Finished Jan 25 01:01:05 AM PST 24
Peak memory 199152 kb
Host smart-ac3dcf0d-36c1-41ce-90fe-a52fa9782ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294378510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4294378510
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.894788727
Short name T393
Test name
Test status
Simulation time 4616430387 ps
CPU time 22.35 seconds
Started Jan 24 11:36:42 PM PST 24
Finished Jan 24 11:37:08 PM PST 24
Peak memory 199164 kb
Host smart-244d8677-dc96-4ae4-9845-012e04d5eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894788727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.894788727
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3830197323
Short name T784
Test name
Test status
Simulation time 6619701819 ps
CPU time 36.53 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:27:52 PM PST 24
Peak memory 199196 kb
Host smart-44694b61-bb8d-489d-a0c3-3fdc5bc36881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830197323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3830197323
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3697169409
Short name T670
Test name
Test status
Simulation time 970181654 ps
CPU time 2.19 seconds
Started Jan 24 11:27:13 PM PST 24
Finished Jan 24 11:27:17 PM PST 24
Peak memory 198512 kb
Host smart-57eb3fad-6251-4541-9a6e-fda2b6c6ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697169409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3697169409
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1912143526
Short name T685
Test name
Test status
Simulation time 189771856887 ps
CPU time 1086.28 seconds
Started Jan 24 11:27:32 PM PST 24
Finished Jan 24 11:45:39 PM PST 24
Peak memory 223848 kb
Host smart-56875dcc-2ec7-4ae0-858f-a3f68407ef8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912143526 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1912143526
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1157023045
Short name T254
Test name
Test status
Simulation time 527782407700 ps
CPU time 2065.19 seconds
Started Jan 24 11:27:28 PM PST 24
Finished Jan 25 12:01:54 AM PST 24
Peak memory 264932 kb
Host smart-a2f83681-b891-4b19-86b1-037a471f58d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157023045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.1157023045
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3681660893
Short name T226
Test name
Test status
Simulation time 105294193 ps
CPU time 1.08 seconds
Started Jan 24 11:27:33 PM PST 24
Finished Jan 24 11:27:35 PM PST 24
Peak memory 198248 kb
Host smart-88c0ca17-4fd5-4a7c-8011-88611ae8fe08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681660893 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3681660893
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3168327753
Short name T329
Test name
Test status
Simulation time 35658011725 ps
CPU time 401.47 seconds
Started Jan 24 11:27:35 PM PST 24
Finished Jan 24 11:34:18 PM PST 24
Peak memory 199156 kb
Host smart-548b739c-f6f1-4679-b488-1558824ce7a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168327753 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.3168327753
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1024356448
Short name T372
Test name
Test status
Simulation time 4448424145 ps
CPU time 70.73 seconds
Started Jan 24 11:27:34 PM PST 24
Finished Jan 24 11:28:46 PM PST 24
Peak memory 199172 kb
Host smart-a1659ea1-e43a-4458-8cda-47f9e0b40501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024356448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1024356448
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.309407810
Short name T101
Test name
Test status
Simulation time 102538571446 ps
CPU time 537.13 seconds
Started Jan 25 12:16:25 AM PST 24
Finished Jan 25 12:25:23 AM PST 24
Peak memory 207652 kb
Host smart-f24555be-9fd6-41c0-886d-b699b66ebb0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309407810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.309407810
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2199480630
Short name T590
Test name
Test status
Simulation time 107176708619 ps
CPU time 1781.96 seconds
Started Jan 25 03:13:00 AM PST 24
Finished Jan 25 03:42:43 AM PST 24
Peak memory 246800 kb
Host smart-5f0dcf6b-761d-4b11-b824-fa14e9aaa1f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199480630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.2199480630
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.201441137
Short name T633
Test name
Test status
Simulation time 90791640249 ps
CPU time 340.75 seconds
Started Jan 24 11:39:07 PM PST 24
Finished Jan 24 11:44:49 PM PST 24
Peak memory 240340 kb
Host smart-c6bbbd61-4fa5-47da-9978-1db5cff8dcd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201441137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.201441137
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.2991271362
Short name T764
Test name
Test status
Simulation time 52959048524 ps
CPU time 724.02 seconds
Started Jan 24 11:39:08 PM PST 24
Finished Jan 24 11:51:13 PM PST 24
Peak memory 214820 kb
Host smart-7396f9a5-0a8b-4cb6-a9ab-051f9ee8c126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991271362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.2991271362
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1815611300
Short name T635
Test name
Test status
Simulation time 248948448276 ps
CPU time 971.3 seconds
Started Jan 24 11:39:04 PM PST 24
Finished Jan 24 11:55:16 PM PST 24
Peak memory 246860 kb
Host smart-c64356fa-8322-4fe5-a945-74747b686dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815611300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.1815611300
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.3647086160
Short name T348
Test name
Test status
Simulation time 432060389003 ps
CPU time 1825.59 seconds
Started Jan 24 11:39:03 PM PST 24
Finished Jan 25 12:09:30 AM PST 24
Peak memory 248520 kb
Host smart-199f1df3-0bae-4f04-8d0b-7dc2272bad33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647086160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.3647086160
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.595482433
Short name T457
Test name
Test status
Simulation time 82321000733 ps
CPU time 3868.32 seconds
Started Jan 24 11:39:07 PM PST 24
Finished Jan 25 12:43:37 AM PST 24
Peak memory 273112 kb
Host smart-36985267-f272-44ae-8751-a6c617499d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595482433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.595482433
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2760821907
Short name T409
Test name
Test status
Simulation time 1236474605589 ps
CPU time 2793.39 seconds
Started Jan 25 04:03:05 AM PST 24
Finished Jan 25 04:49:41 AM PST 24
Peak memory 256712 kb
Host smart-15baa970-f7ae-41a3-9186-7c0de5458020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760821907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.2760821907
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3836772679
Short name T119
Test name
Test status
Simulation time 84149039736 ps
CPU time 2473.12 seconds
Started Jan 24 11:39:18 PM PST 24
Finished Jan 25 12:20:32 AM PST 24
Peak memory 243160 kb
Host smart-1125e2d0-fc4f-419f-8230-bcc12e1b1a9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836772679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.3836772679
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1374000285
Short name T717
Test name
Test status
Simulation time 24619435 ps
CPU time 0.57 seconds
Started Jan 24 11:27:48 PM PST 24
Finished Jan 24 11:27:49 PM PST 24
Peak memory 193556 kb
Host smart-c16d697e-8939-428e-9a13-cb06eec69fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374000285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1374000285
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.982217181
Short name T757
Test name
Test status
Simulation time 13100974280 ps
CPU time 24 seconds
Started Jan 24 11:27:35 PM PST 24
Finished Jan 24 11:28:01 PM PST 24
Peak memory 215124 kb
Host smart-2a45beff-7a68-4131-ac20-103cf5ed705b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982217181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.982217181
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1958787859
Short name T704
Test name
Test status
Simulation time 8064899994 ps
CPU time 22.39 seconds
Started Jan 24 11:27:31 PM PST 24
Finished Jan 24 11:27:54 PM PST 24
Peak memory 199232 kb
Host smart-86b28762-3509-4b19-9773-b8b6ffbac75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958787859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1958787859
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2837338385
Short name T34
Test name
Test status
Simulation time 2505127091 ps
CPU time 62.99 seconds
Started Jan 24 11:27:33 PM PST 24
Finished Jan 24 11:28:37 PM PST 24
Peak memory 199212 kb
Host smart-388b6cdf-5385-4ee5-a35a-59c3732bc6fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837338385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2837338385
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2908377236
Short name T662
Test name
Test status
Simulation time 88525309218 ps
CPU time 163.26 seconds
Started Jan 24 11:27:32 PM PST 24
Finished Jan 24 11:30:16 PM PST 24
Peak memory 199212 kb
Host smart-4dbd8fed-3ea1-4be7-8b43-ee2f7653775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908377236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2908377236
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3091557871
Short name T196
Test name
Test status
Simulation time 21348884071 ps
CPU time 61.44 seconds
Started Jan 24 11:27:33 PM PST 24
Finished Jan 24 11:28:36 PM PST 24
Peak memory 199212 kb
Host smart-abeeb1de-3433-4d39-8b22-16389a3e5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091557871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3091557871
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.578240687
Short name T230
Test name
Test status
Simulation time 68893223 ps
CPU time 1.94 seconds
Started Jan 24 11:27:34 PM PST 24
Finished Jan 24 11:27:38 PM PST 24
Peak memory 198844 kb
Host smart-8171eb6b-f344-48ed-8117-507f2814acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578240687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.578240687
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2177379261
Short name T696
Test name
Test status
Simulation time 26458767689 ps
CPU time 533.29 seconds
Started Jan 25 12:48:16 AM PST 24
Finished Jan 25 12:57:11 AM PST 24
Peak memory 207484 kb
Host smart-313a0275-5332-4c00-9438-e6dd7ea8f438
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177379261 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2177379261
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.4098168569
Short name T91
Test name
Test status
Simulation time 130251626960 ps
CPU time 980.9 seconds
Started Jan 24 11:27:46 PM PST 24
Finished Jan 24 11:44:08 PM PST 24
Peak memory 247728 kb
Host smart-7876013d-7448-472c-9608-0ecd61ab1876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098168569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.4098168569
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2491901851
Short name T459
Test name
Test status
Simulation time 160688295 ps
CPU time 0.95 seconds
Started Jan 24 11:27:52 PM PST 24
Finished Jan 24 11:27:54 PM PST 24
Peak memory 196384 kb
Host smart-b24bc312-99ce-4267-8954-81bd0848384a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491901851 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2491901851
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2471838987
Short name T414
Test name
Test status
Simulation time 6877481953 ps
CPU time 353.08 seconds
Started Jan 24 11:27:45 PM PST 24
Finished Jan 24 11:33:40 PM PST 24
Peak memory 199144 kb
Host smart-0dd7c0c4-3e52-46df-a218-da907305334c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471838987 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2471838987
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2086837388
Short name T831
Test name
Test status
Simulation time 1036037572 ps
CPU time 44.49 seconds
Started Jan 24 11:27:31 PM PST 24
Finished Jan 24 11:28:17 PM PST 24
Peak memory 199164 kb
Host smart-bde585fe-e449-4b0c-8e7e-ec6522a6bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086837388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2086837388
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2192974088
Short name T98
Test name
Test status
Simulation time 43837018534 ps
CPU time 478.09 seconds
Started Jan 24 11:39:22 PM PST 24
Finished Jan 24 11:47:21 PM PST 24
Peak memory 224016 kb
Host smart-f3ad7a4e-0b0d-4907-bc5f-75b9c252c79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192974088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.2192974088
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1865774556
Short name T734
Test name
Test status
Simulation time 318931323371 ps
CPU time 3721.44 seconds
Started Jan 24 11:39:16 PM PST 24
Finished Jan 25 12:41:19 AM PST 24
Peak memory 264260 kb
Host smart-09efa964-e7f5-4769-9489-d00c2873efc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865774556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.1865774556
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.353158844
Short name T748
Test name
Test status
Simulation time 411077759627 ps
CPU time 558.4 seconds
Started Jan 24 11:39:17 PM PST 24
Finished Jan 24 11:48:37 PM PST 24
Peak memory 223904 kb
Host smart-7806c971-679d-4f9d-8ead-f93b21e7c3eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353158844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.353158844
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.3109502714
Short name T674
Test name
Test status
Simulation time 161604049524 ps
CPU time 2403.37 seconds
Started Jan 24 11:39:15 PM PST 24
Finished Jan 25 12:19:20 AM PST 24
Peak memory 264372 kb
Host smart-c081c7fa-724b-44b8-a9b5-7844553d8e55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109502714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.3109502714
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3115960416
Short name T642
Test name
Test status
Simulation time 259454120524 ps
CPU time 1081.53 seconds
Started Jan 24 11:39:16 PM PST 24
Finished Jan 24 11:57:18 PM PST 24
Peak memory 248548 kb
Host smart-f45216ae-cb44-4192-9ece-33cbaaa46f38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115960416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.3115960416
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1787670075
Short name T797
Test name
Test status
Simulation time 340779321680 ps
CPU time 1287.37 seconds
Started Jan 24 11:39:22 PM PST 24
Finished Jan 25 12:00:51 AM PST 24
Peak memory 248592 kb
Host smart-334ae943-6a29-4e49-899d-e2a70b4d12d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787670075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.1787670075
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.2287903121
Short name T436
Test name
Test status
Simulation time 215998104807 ps
CPU time 1372.49 seconds
Started Jan 24 11:39:21 PM PST 24
Finished Jan 25 12:02:15 AM PST 24
Peak memory 230800 kb
Host smart-beba6e47-3241-403e-b7be-577c8d197c65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287903121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.2287903121
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.1751383311
Short name T690
Test name
Test status
Simulation time 1498312876544 ps
CPU time 5501.88 seconds
Started Jan 24 11:39:37 PM PST 24
Finished Jan 25 01:11:21 AM PST 24
Peak memory 248584 kb
Host smart-0f7a2921-f9f2-4f6d-8d26-6ccb269300e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751383311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.1751383311
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.3198057289
Short name T492
Test name
Test status
Simulation time 220249960659 ps
CPU time 1081.8 seconds
Started Jan 24 11:39:35 PM PST 24
Finished Jan 24 11:57:37 PM PST 24
Peak memory 215632 kb
Host smart-58ea539b-b142-466c-b984-01807fad82bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198057289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.3198057289
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3057735799
Short name T477
Test name
Test status
Simulation time 24615014 ps
CPU time 0.61 seconds
Started Jan 25 03:37:02 AM PST 24
Finished Jan 25 03:37:03 AM PST 24
Peak memory 193564 kb
Host smart-ab0c67ff-0085-4b16-a07c-c4d8d7db25a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057735799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3057735799
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3169129279
Short name T556
Test name
Test status
Simulation time 1318591112 ps
CPU time 40.69 seconds
Started Jan 24 11:27:48 PM PST 24
Finished Jan 24 11:28:30 PM PST 24
Peak memory 215124 kb
Host smart-ade9cec9-d834-413f-909a-58c25e851f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169129279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3169129279
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.793953985
Short name T723
Test name
Test status
Simulation time 791566781 ps
CPU time 8.56 seconds
Started Jan 25 01:11:09 AM PST 24
Finished Jan 25 01:11:19 AM PST 24
Peak memory 199160 kb
Host smart-950960e6-6fc7-495e-885b-4474b5ede1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793953985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.793953985
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2444977434
Short name T711
Test name
Test status
Simulation time 13054986581 ps
CPU time 52.71 seconds
Started Jan 24 11:27:41 PM PST 24
Finished Jan 24 11:28:36 PM PST 24
Peak memory 199164 kb
Host smart-8e15b7dd-e6e3-4299-9dec-a166dc1bf275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444977434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2444977434
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1658500000
Short name T416
Test name
Test status
Simulation time 705926654 ps
CPU time 37.7 seconds
Started Jan 25 12:42:46 AM PST 24
Finished Jan 25 12:43:25 AM PST 24
Peak memory 199188 kb
Host smart-07ff6bb7-a76f-4878-9426-99b3a5fee10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658500000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1658500000
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2009103656
Short name T823
Test name
Test status
Simulation time 5629454762 ps
CPU time 71.11 seconds
Started Jan 24 11:27:43 PM PST 24
Finished Jan 24 11:28:56 PM PST 24
Peak memory 199200 kb
Host smart-351b6cab-8a18-4129-938b-7e248bf844e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009103656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2009103656
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3646002421
Short name T732
Test name
Test status
Simulation time 487145029 ps
CPU time 1.96 seconds
Started Jan 24 11:27:46 PM PST 24
Finished Jan 24 11:27:49 PM PST 24
Peak memory 198628 kb
Host smart-8090b16f-511a-4960-a894-f3b036a7adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646002421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3646002421
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1848136868
Short name T507
Test name
Test status
Simulation time 48647792178 ps
CPU time 613.72 seconds
Started Jan 24 11:27:54 PM PST 24
Finished Jan 24 11:38:09 PM PST 24
Peak memory 198688 kb
Host smart-b39168f2-3440-4df6-8343-8b9d28fa8639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848136868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1848136868
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2597392514
Short name T753
Test name
Test status
Simulation time 23021246349 ps
CPU time 449.86 seconds
Started Jan 24 11:27:48 PM PST 24
Finished Jan 24 11:35:19 PM PST 24
Peak memory 207548 kb
Host smart-0c40a1e7-1e83-49fc-b053-e5c69c262115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597392514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.2597392514
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3545715555
Short name T689
Test name
Test status
Simulation time 225676568 ps
CPU time 1 seconds
Started Jan 25 02:06:12 AM PST 24
Finished Jan 25 02:06:16 AM PST 24
Peak memory 196220 kb
Host smart-2722a016-079a-4898-96c4-d2f0f40949c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545715555 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3545715555
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.437862550
Short name T537
Test name
Test status
Simulation time 18001414488 ps
CPU time 447.32 seconds
Started Jan 24 11:27:43 PM PST 24
Finished Jan 24 11:35:13 PM PST 24
Peak memory 199128 kb
Host smart-2edbfa23-932c-409c-bfb1-0049e0ad405c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437862550 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.hmac_test_sha_vectors.437862550
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.898669619
Short name T235
Test name
Test status
Simulation time 7378358609 ps
CPU time 26.76 seconds
Started Jan 24 11:27:54 PM PST 24
Finished Jan 24 11:28:22 PM PST 24
Peak memory 198656 kb
Host smart-74b77132-475e-462e-bfc2-19f3a4cde8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898669619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.898669619
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2251177221
Short name T615
Test name
Test status
Simulation time 22899043392 ps
CPU time 911.45 seconds
Started Jan 24 11:39:34 PM PST 24
Finished Jan 24 11:54:46 PM PST 24
Peak memory 212252 kb
Host smart-008ab914-6809-4776-8ae6-a215e5e301a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251177221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2251177221
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.131769114
Short name T232
Test name
Test status
Simulation time 75870104077 ps
CPU time 774 seconds
Started Jan 25 12:05:03 AM PST 24
Finished Jan 25 12:17:59 AM PST 24
Peak memory 208456 kb
Host smart-a4b4f8f9-32c6-452d-bf37-3c37f2dff2c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131769114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.131769114
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.490726967
Short name T379
Test name
Test status
Simulation time 85357841631 ps
CPU time 1986.26 seconds
Started Jan 25 12:01:56 AM PST 24
Finished Jan 25 12:35:03 AM PST 24
Peak memory 241332 kb
Host smart-336458e2-93f8-4af7-8cc2-5098d3d66565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490726967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.490726967
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3024915646
Short name T676
Test name
Test status
Simulation time 99173188309 ps
CPU time 390.5 seconds
Started Jan 24 11:39:35 PM PST 24
Finished Jan 24 11:46:06 PM PST 24
Peak memory 240336 kb
Host smart-30a8bdf8-d22b-4153-bc19-b420506207d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024915646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3024915646
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.654206944
Short name T761
Test name
Test status
Simulation time 300195767308 ps
CPU time 1430.91 seconds
Started Jan 25 12:53:03 AM PST 24
Finished Jan 25 01:16:56 AM PST 24
Peak memory 256740 kb
Host smart-de56e6d3-ba14-4235-ac8f-b26d11efbe71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654206944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.654206944
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.4074504569
Short name T475
Test name
Test status
Simulation time 144844624965 ps
CPU time 517.1 seconds
Started Jan 24 11:39:34 PM PST 24
Finished Jan 24 11:48:12 PM PST 24
Peak memory 223988 kb
Host smart-1f6029b8-bb10-4eed-b25f-32ad287304b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074504569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.4074504569
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.860045174
Short name T530
Test name
Test status
Simulation time 51547927613 ps
CPU time 513.37 seconds
Started Jan 24 11:39:36 PM PST 24
Finished Jan 24 11:48:10 PM PST 24
Peak memory 228868 kb
Host smart-fe6fb69f-0ae4-4098-a5d5-b8979752991a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860045174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.860045174
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.907072039
Short name T799
Test name
Test status
Simulation time 174366431800 ps
CPU time 2878.73 seconds
Started Jan 24 11:39:38 PM PST 24
Finished Jan 25 12:27:38 AM PST 24
Peak memory 248576 kb
Host smart-cafebae4-f68d-415f-91de-a777a38945b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907072039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.907072039
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.1290406263
Short name T41
Test name
Test status
Simulation time 22655360585 ps
CPU time 1129.23 seconds
Started Jan 25 03:14:59 AM PST 24
Finished Jan 25 03:33:54 AM PST 24
Peak memory 215776 kb
Host smart-9ab78509-02a4-4203-ac8e-7b2e363b1050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290406263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.1290406263
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1888126073
Short name T310
Test name
Test status
Simulation time 121050004 ps
CPU time 3.91 seconds
Started Jan 24 11:27:42 PM PST 24
Finished Jan 24 11:27:48 PM PST 24
Peak memory 207328 kb
Host smart-6ac67030-969b-4a23-9210-42782ab97037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888126073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1888126073
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1675578746
Short name T563
Test name
Test status
Simulation time 5992534802 ps
CPU time 51.8 seconds
Started Jan 25 01:28:59 AM PST 24
Finished Jan 25 01:29:52 AM PST 24
Peak memory 199248 kb
Host smart-61e06771-cca1-4c9f-8704-779d8544024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675578746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1675578746
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.915814358
Short name T364
Test name
Test status
Simulation time 285533777 ps
CPU time 14.44 seconds
Started Jan 24 11:27:43 PM PST 24
Finished Jan 24 11:28:00 PM PST 24
Peak memory 198912 kb
Host smart-aaae45d4-c45f-4ca5-be3b-5effd0bb4f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915814358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.915814358
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.10551899
Short name T566
Test name
Test status
Simulation time 1653502764 ps
CPU time 40.74 seconds
Started Jan 24 11:41:51 PM PST 24
Finished Jan 24 11:42:32 PM PST 24
Peak memory 199164 kb
Host smart-07628ed0-9b90-40a5-a951-7c93b61b8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10551899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.10551899
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2323115899
Short name T546
Test name
Test status
Simulation time 6469658165 ps
CPU time 110.92 seconds
Started Jan 24 11:27:54 PM PST 24
Finished Jan 24 11:29:45 PM PST 24
Peak memory 199200 kb
Host smart-52b02d60-8abe-4a66-9173-e53878e1bda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323115899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2323115899
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2098914690
Short name T438
Test name
Test status
Simulation time 997384502 ps
CPU time 3.09 seconds
Started Jan 25 02:06:52 AM PST 24
Finished Jan 25 02:07:00 AM PST 24
Peak memory 199040 kb
Host smart-b80671e7-d164-49b1-9737-7b44496c2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098914690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2098914690
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1000088460
Short name T829
Test name
Test status
Simulation time 209512477085 ps
CPU time 740.11 seconds
Started Jan 24 11:27:58 PM PST 24
Finished Jan 24 11:40:22 PM PST 24
Peak memory 229176 kb
Host smart-38647277-1a30-4b2c-88f8-165a3596bd7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000088460 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1000088460
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2641888654
Short name T430
Test name
Test status
Simulation time 63764607855 ps
CPU time 401.01 seconds
Started Jan 24 11:27:55 PM PST 24
Finished Jan 24 11:34:37 PM PST 24
Peak memory 214816 kb
Host smart-0fed3414-b259-44ad-8329-f05eafc4c3c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641888654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2641888654
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.606884268
Short name T549
Test name
Test status
Simulation time 60538762 ps
CPU time 1.18 seconds
Started Jan 24 11:27:54 PM PST 24
Finished Jan 24 11:27:56 PM PST 24
Peak memory 197404 kb
Host smart-eb406ca1-d3b5-49ab-a760-ca240ed3f9c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606884268 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.606884268
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2534123794
Short name T769
Test name
Test status
Simulation time 159057002746 ps
CPU time 442.84 seconds
Started Jan 25 02:46:55 AM PST 24
Finished Jan 25 02:54:23 AM PST 24
Peak memory 199180 kb
Host smart-00c0beb3-ae27-4942-be47-52b68fe551b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534123794 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.2534123794
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3621252671
Short name T301
Test name
Test status
Simulation time 799131731 ps
CPU time 14.54 seconds
Started Jan 24 11:27:53 PM PST 24
Finished Jan 24 11:28:08 PM PST 24
Peak memory 199060 kb
Host smart-5c0fc204-d880-434b-b354-31daf38a3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621252671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3621252671
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.293751678
Short name T574
Test name
Test status
Simulation time 35828329115 ps
CPU time 1995.96 seconds
Started Jan 24 11:40:01 PM PST 24
Finished Jan 25 12:13:23 AM PST 24
Peak memory 237744 kb
Host smart-e6bcc2e5-9a7d-477e-95a4-77c14762569e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293751678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.293751678
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.3441995976
Short name T607
Test name
Test status
Simulation time 66612324255 ps
CPU time 1263.98 seconds
Started Jan 24 11:39:59 PM PST 24
Finished Jan 25 12:01:10 AM PST 24
Peak memory 226076 kb
Host smart-07407f56-e2e8-41ff-87bf-2521890e7dfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441995976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.3441995976
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.4069578338
Short name T117
Test name
Test status
Simulation time 24445944684 ps
CPU time 530.82 seconds
Started Jan 25 12:12:45 AM PST 24
Finished Jan 25 12:21:37 AM PST 24
Peak memory 223980 kb
Host smart-dbff0a92-d457-4427-92c9-596b33ed8f02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069578338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.4069578338
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.3369953928
Short name T610
Test name
Test status
Simulation time 210471754182 ps
CPU time 882.05 seconds
Started Jan 24 11:48:54 PM PST 24
Finished Jan 25 12:03:37 AM PST 24
Peak memory 232152 kb
Host smart-8480e133-c7b1-41b0-8b9b-825345de1b76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369953928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.3369953928
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3778891963
Short name T295
Test name
Test status
Simulation time 75501145625 ps
CPU time 1518.8 seconds
Started Jan 24 11:40:00 PM PST 24
Finished Jan 25 12:05:24 AM PST 24
Peak memory 241304 kb
Host smart-9d9409f8-857a-45e0-b610-b5e9ca34bf80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778891963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3778891963
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.1218915029
Short name T770
Test name
Test status
Simulation time 383590339202 ps
CPU time 3625.45 seconds
Started Jan 24 11:40:47 PM PST 24
Finished Jan 25 12:41:14 AM PST 24
Peak memory 256724 kb
Host smart-55e1125e-0737-4518-a9c7-99a47df7a0f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218915029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.1218915029
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1455473977
Short name T352
Test name
Test status
Simulation time 13676122 ps
CPU time 0.61 seconds
Started Jan 25 04:13:55 AM PST 24
Finished Jan 25 04:14:03 AM PST 24
Peak memory 193596 kb
Host smart-0b430f92-9fbd-49b6-8663-db209db2fa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455473977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1455473977
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3945845931
Short name T334
Test name
Test status
Simulation time 3201561644 ps
CPU time 25.7 seconds
Started Jan 25 01:23:24 AM PST 24
Finished Jan 25 01:23:51 AM PST 24
Peak memory 207424 kb
Host smart-b7f12279-cfc8-4612-b83b-c831e9f69dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945845931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3945845931
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3384263186
Short name T605
Test name
Test status
Simulation time 3492993661 ps
CPU time 31.86 seconds
Started Jan 24 11:28:17 PM PST 24
Finished Jan 24 11:28:49 PM PST 24
Peak memory 199200 kb
Host smart-bdab88d4-612b-4939-9a29-0d00b180eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384263186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3384263186
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4200787770
Short name T8
Test name
Test status
Simulation time 5740249659 ps
CPU time 81.12 seconds
Started Jan 25 12:40:40 AM PST 24
Finished Jan 25 12:42:02 AM PST 24
Peak memory 199228 kb
Host smart-3c760a8b-7264-4849-967d-8ded925f70f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200787770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4200787770
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4282511018
Short name T657
Test name
Test status
Simulation time 5501965156 ps
CPU time 81.13 seconds
Started Jan 25 02:31:02 AM PST 24
Finished Jan 25 02:32:28 AM PST 24
Peak memory 199236 kb
Host smart-31d50074-fe24-4096-8ab1-46e86305531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282511018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4282511018
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2378990538
Short name T675
Test name
Test status
Simulation time 3124660993 ps
CPU time 20.75 seconds
Started Jan 24 11:27:57 PM PST 24
Finished Jan 24 11:28:20 PM PST 24
Peak memory 199172 kb
Host smart-879f9a7e-4495-4db1-8516-342f5536e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378990538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2378990538
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.988872573
Short name T466
Test name
Test status
Simulation time 614199029 ps
CPU time 1.97 seconds
Started Jan 24 11:27:56 PM PST 24
Finished Jan 24 11:28:00 PM PST 24
Peak memory 198860 kb
Host smart-18ab1eaf-d3b9-4811-abf8-d0343d79dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988872573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.988872573
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.486039307
Short name T655
Test name
Test status
Simulation time 15368770311 ps
CPU time 97.89 seconds
Started Jan 24 11:28:09 PM PST 24
Finished Jan 24 11:29:49 PM PST 24
Peak memory 199220 kb
Host smart-9dfbf553-ef6a-4e87-9462-8e0828beda27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486039307 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.486039307
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2705169553
Short name T652
Test name
Test status
Simulation time 55135402434 ps
CPU time 519.27 seconds
Started Jan 24 11:28:11 PM PST 24
Finished Jan 24 11:36:52 PM PST 24
Peak memory 231116 kb
Host smart-3fc4061e-85e3-46f9-9466-fd054e50d58f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705169553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2705169553
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2692974768
Short name T383
Test name
Test status
Simulation time 100543737 ps
CPU time 1.09 seconds
Started Jan 25 12:09:48 AM PST 24
Finished Jan 25 12:09:50 AM PST 24
Peak memory 197172 kb
Host smart-4e616136-c02a-46e8-bbdd-19014034bbe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692974768 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2692974768
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3196785877
Short name T327
Test name
Test status
Simulation time 172850843772 ps
CPU time 438.22 seconds
Started Jan 24 11:28:10 PM PST 24
Finished Jan 24 11:35:31 PM PST 24
Peak memory 198896 kb
Host smart-dfdceb9e-0b35-447c-818f-41dee2104bdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196785877 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.3196785877
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3562866613
Short name T773
Test name
Test status
Simulation time 1216313564 ps
CPU time 51.47 seconds
Started Jan 24 11:28:14 PM PST 24
Finished Jan 24 11:29:07 PM PST 24
Peak memory 199124 kb
Host smart-31f013e5-efa4-4bb5-b18a-313e330bae54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562866613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3562866613
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.1899658415
Short name T381
Test name
Test status
Simulation time 56119994482 ps
CPU time 1180.57 seconds
Started Jan 24 11:40:46 PM PST 24
Finished Jan 25 12:00:28 AM PST 24
Peak memory 243328 kb
Host smart-41750686-11eb-44bb-a60b-2b3ce4390ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899658415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.1899658415
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.3480688082
Short name T714
Test name
Test status
Simulation time 1371640839675 ps
CPU time 1732.95 seconds
Started Jan 24 11:40:48 PM PST 24
Finished Jan 25 12:09:42 AM PST 24
Peak memory 241388 kb
Host smart-5ea7c536-c36c-4b16-81c4-a3de61d55995
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480688082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.3480688082
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.224022965
Short name T814
Test name
Test status
Simulation time 30526844496 ps
CPU time 790.53 seconds
Started Jan 24 11:41:06 PM PST 24
Finished Jan 24 11:54:21 PM PST 24
Peak memory 248452 kb
Host smart-02745771-0d40-4f10-90a3-b192886d5d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224022965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.224022965
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3559258461
Short name T124
Test name
Test status
Simulation time 112541422531 ps
CPU time 1671.11 seconds
Started Jan 24 11:41:05 PM PST 24
Finished Jan 25 12:09:00 AM PST 24
Peak memory 242416 kb
Host smart-e582d954-35f9-4175-8c6a-6036179f8b2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559258461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.3559258461
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.2524827466
Short name T411
Test name
Test status
Simulation time 104467273922 ps
CPU time 321.12 seconds
Started Jan 24 11:41:07 PM PST 24
Finished Jan 24 11:46:33 PM PST 24
Peak memory 223932 kb
Host smart-9e474660-648a-4021-8195-c08c94079cdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524827466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.2524827466
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.655687579
Short name T573
Test name
Test status
Simulation time 35092032557 ps
CPU time 261.47 seconds
Started Jan 24 11:41:08 PM PST 24
Finished Jan 24 11:45:34 PM PST 24
Peak memory 218848 kb
Host smart-3e0634a1-74da-4400-8ba1-ae22a355cca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655687579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.655687579
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.13388657
Short name T759
Test name
Test status
Simulation time 34169171152 ps
CPU time 991.14 seconds
Started Jan 25 02:24:11 AM PST 24
Finished Jan 25 02:40:43 AM PST 24
Peak memory 213776 kb
Host smart-b13a4697-e543-4cfc-a62c-52918c26771b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13388657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.13388657
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.253021422
Short name T328
Test name
Test status
Simulation time 14571404 ps
CPU time 0.61 seconds
Started Jan 24 11:28:30 PM PST 24
Finished Jan 24 11:28:31 PM PST 24
Peak memory 193420 kb
Host smart-6e3bf93c-1e06-48a4-a0ac-8cbfd048e995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253021422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.253021422
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3437671589
Short name T262
Test name
Test status
Simulation time 852076468 ps
CPU time 25.34 seconds
Started Jan 24 11:28:14 PM PST 24
Finished Jan 24 11:28:41 PM PST 24
Peak memory 207372 kb
Host smart-6a9fd7ed-6705-4c26-88cb-2c4120337091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437671589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3437671589
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2209136777
Short name T603
Test name
Test status
Simulation time 2580668614 ps
CPU time 32.67 seconds
Started Jan 24 11:28:14 PM PST 24
Finished Jan 24 11:28:48 PM PST 24
Peak memory 199184 kb
Host smart-35de8b04-a1fc-4b86-8b71-f9c7df4bca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209136777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2209136777
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3081761708
Short name T361
Test name
Test status
Simulation time 3707565955 ps
CPU time 97.58 seconds
Started Jan 24 11:28:12 PM PST 24
Finished Jan 24 11:29:51 PM PST 24
Peak memory 199216 kb
Host smart-dcea0963-1de8-4ea7-a6fd-459b8fa3daac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081761708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3081761708
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1123888077
Short name T683
Test name
Test status
Simulation time 6955125840 ps
CPU time 17.68 seconds
Started Jan 24 11:28:11 PM PST 24
Finished Jan 24 11:28:31 PM PST 24
Peak memory 199212 kb
Host smart-51afb4dd-5e18-4459-9d17-2966cf4d9177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123888077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1123888077
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2506119793
Short name T721
Test name
Test status
Simulation time 5173769357 ps
CPU time 16.55 seconds
Started Jan 25 01:44:34 AM PST 24
Finished Jan 25 01:44:52 AM PST 24
Peak memory 199244 kb
Host smart-bccde5b7-f90c-435f-9e8d-63016e20dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506119793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2506119793
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2509402932
Short name T811
Test name
Test status
Simulation time 917039798 ps
CPU time 2.28 seconds
Started Jan 24 11:28:12 PM PST 24
Finished Jan 24 11:28:16 PM PST 24
Peak memory 199000 kb
Host smart-5c3fac43-aa10-4ed7-9dfd-bece71ec5f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509402932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2509402932
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3599809216
Short name T115
Test name
Test status
Simulation time 56183528492 ps
CPU time 813.82 seconds
Started Jan 24 11:28:33 PM PST 24
Finished Jan 24 11:42:07 PM PST 24
Peak memory 230220 kb
Host smart-58e171f6-44e7-48f6-bedb-27562b83ca21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599809216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3599809216
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1505204027
Short name T638
Test name
Test status
Simulation time 216713668340 ps
CPU time 274.04 seconds
Started Jan 24 11:28:30 PM PST 24
Finished Jan 24 11:33:05 PM PST 24
Peak memory 207580 kb
Host smart-e4cc4cdd-606f-4da3-aa77-cd098204a512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505204027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.1505204027
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2857398739
Short name T207
Test name
Test status
Simulation time 129550655 ps
CPU time 0.89 seconds
Started Jan 24 11:28:10 PM PST 24
Finished Jan 24 11:28:13 PM PST 24
Peak memory 196584 kb
Host smart-00ad4b59-aff0-4aed-baf7-54e75d8eb2bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857398739 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2857398739
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.403234870
Short name T442
Test name
Test status
Simulation time 136087104477 ps
CPU time 432.46 seconds
Started Jan 24 11:28:12 PM PST 24
Finished Jan 24 11:35:27 PM PST 24
Peak memory 199180 kb
Host smart-7685fbbe-6f3f-484a-9b3c-a9d6baaed6bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403234870 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.hmac_test_sha_vectors.403234870
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.526076354
Short name T737
Test name
Test status
Simulation time 8593231626 ps
CPU time 27.74 seconds
Started Jan 24 11:28:12 PM PST 24
Finished Jan 24 11:28:41 PM PST 24
Peak memory 199240 kb
Host smart-f3df5f5d-6d3a-4a79-8831-9912203ee777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526076354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.526076354
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.2560034521
Short name T758
Test name
Test status
Simulation time 34193251726 ps
CPU time 467.88 seconds
Started Jan 24 11:41:04 PM PST 24
Finished Jan 24 11:48:56 PM PST 24
Peak memory 231792 kb
Host smart-9167d96d-af8c-4c79-84ca-0c24513282c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560034521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.2560034521
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.3089570092
Short name T625
Test name
Test status
Simulation time 99396593457 ps
CPU time 1250.57 seconds
Started Jan 24 11:41:06 PM PST 24
Finished Jan 25 12:02:03 AM PST 24
Peak memory 242040 kb
Host smart-8c62c4fc-8128-43bb-be03-6dcf29a38b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089570092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.3089570092
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.3649372933
Short name T568
Test name
Test status
Simulation time 265845805116 ps
CPU time 2714.94 seconds
Started Jan 24 11:41:23 PM PST 24
Finished Jan 25 12:26:40 AM PST 24
Peak memory 256528 kb
Host smart-9828f970-0488-4cad-9cf2-439ed7d3df70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649372933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.3649372933
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3139514190
Short name T600
Test name
Test status
Simulation time 150192258591 ps
CPU time 5298.79 seconds
Started Jan 24 11:41:23 PM PST 24
Finished Jan 25 01:09:44 AM PST 24
Peak memory 273132 kb
Host smart-1adb2ffb-24f9-48f6-8112-756e8dd31454
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139514190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.3139514190
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2942359916
Short name T483
Test name
Test status
Simulation time 53639879281 ps
CPU time 518.9 seconds
Started Jan 24 11:41:22 PM PST 24
Finished Jan 24 11:50:03 PM PST 24
Peak memory 215768 kb
Host smart-a05c0e08-9950-4932-94fa-7586a3022e7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942359916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2942359916
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.4116042715
Short name T580
Test name
Test status
Simulation time 192103007897 ps
CPU time 763.56 seconds
Started Jan 24 11:41:22 PM PST 24
Finished Jan 24 11:54:08 PM PST 24
Peak memory 240424 kb
Host smart-2e37fd64-3d96-4656-add4-613a9cd3ab66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116042715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.4116042715
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.2634290812
Short name T304
Test name
Test status
Simulation time 231786285530 ps
CPU time 841.36 seconds
Started Jan 24 11:41:23 PM PST 24
Finished Jan 24 11:55:26 PM PST 24
Peak memory 223964 kb
Host smart-0039afd0-a262-4211-9d98-aa4c2955a9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634290812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.2634290812
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.4194071439
Short name T559
Test name
Test status
Simulation time 36886964325 ps
CPU time 610.57 seconds
Started Jan 24 11:41:38 PM PST 24
Finished Jan 24 11:51:50 PM PST 24
Peak memory 239488 kb
Host smart-cc275dd6-4a21-4044-a7b0-112923dea407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194071439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.4194071439
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.289278972
Short name T434
Test name
Test status
Simulation time 44120102803 ps
CPU time 910.38 seconds
Started Jan 24 11:41:36 PM PST 24
Finished Jan 24 11:56:47 PM PST 24
Peak memory 215744 kb
Host smart-4e36aa08-5f56-447a-9334-e5ec87a746b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289278972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.289278972
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3309861352
Short name T645
Test name
Test status
Simulation time 290426133340 ps
CPU time 1535.31 seconds
Started Jan 24 11:41:38 PM PST 24
Finished Jan 25 12:07:15 AM PST 24
Peak memory 248492 kb
Host smart-c2794b96-be41-4a52-9812-f4f78600b116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309861352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3309861352
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.543084220
Short name T433
Test name
Test status
Simulation time 52397522 ps
CPU time 0.59 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:28:55 PM PST 24
Peak memory 192596 kb
Host smart-f241b5cb-6743-48c0-b127-52b2b9d12c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543084220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.543084220
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2944399972
Short name T234
Test name
Test status
Simulation time 738218859 ps
CPU time 22.76 seconds
Started Jan 24 11:28:31 PM PST 24
Finished Jan 24 11:28:55 PM PST 24
Peak memory 207332 kb
Host smart-a4dc34ec-0db0-4e3d-808c-ff892cbf2802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944399972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2944399972
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.633280016
Short name T133
Test name
Test status
Simulation time 1922813843 ps
CPU time 22.74 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:29:18 PM PST 24
Peak memory 199184 kb
Host smart-8166bafb-621a-4053-9ded-63dd85ea8ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633280016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.633280016
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3045299967
Short name T622
Test name
Test status
Simulation time 5394118957 ps
CPU time 63.46 seconds
Started Jan 24 11:28:30 PM PST 24
Finished Jan 24 11:29:35 PM PST 24
Peak memory 199220 kb
Host smart-4bc6b92e-ab42-4f18-a756-f389efc9caaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045299967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3045299967
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.61622203
Short name T440
Test name
Test status
Simulation time 908241148 ps
CPU time 4.24 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:28:58 PM PST 24
Peak memory 199064 kb
Host smart-483e4b6a-ae09-484f-b4a8-abede8031af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61622203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.61622203
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1735153929
Short name T460
Test name
Test status
Simulation time 7673839778 ps
CPU time 109.41 seconds
Started Jan 24 11:28:30 PM PST 24
Finished Jan 24 11:30:21 PM PST 24
Peak memory 199256 kb
Host smart-c9e6ac6d-683a-4edc-8be1-cfac381a76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735153929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1735153929
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.859474874
Short name T535
Test name
Test status
Simulation time 137931777 ps
CPU time 1.91 seconds
Started Jan 24 11:28:32 PM PST 24
Finished Jan 24 11:28:34 PM PST 24
Peak memory 197976 kb
Host smart-82cddeae-59f4-42f6-8c8d-eee677b8718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859474874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.859474874
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.135879676
Short name T125
Test name
Test status
Simulation time 16455847673 ps
CPU time 778.92 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:41:53 PM PST 24
Peak memory 224824 kb
Host smart-aaca66e9-7f8d-4421-8185-efb4534976be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135879676 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.135879676
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.3396109325
Short name T260
Test name
Test status
Simulation time 82342001447 ps
CPU time 926.3 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:44:22 PM PST 24
Peak memory 215280 kb
Host smart-60d4ea81-1156-49ca-b84f-5e2f6fe758a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396109325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.3396109325
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2297293951
Short name T370
Test name
Test status
Simulation time 123204335 ps
CPU time 1.17 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:28:55 PM PST 24
Peak memory 198140 kb
Host smart-c5e1525e-df8e-413a-897f-b26f76aca4cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297293951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2297293951
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3852501658
Short name T344
Test name
Test status
Simulation time 24415249329 ps
CPU time 405.3 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:35:41 PM PST 24
Peak memory 199112 kb
Host smart-69a0f53a-3637-4a7f-983c-7e6b58aac083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852501658 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.3852501658
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2817811605
Short name T656
Test name
Test status
Simulation time 4596476650 ps
CPU time 39.11 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:29:33 PM PST 24
Peak memory 199212 kb
Host smart-d4d3ceee-0ded-419b-b23d-6117fba8359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817811605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2817811605
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.2096543098
Short name T524
Test name
Test status
Simulation time 272062770575 ps
CPU time 946.5 seconds
Started Jan 24 11:41:55 PM PST 24
Finished Jan 24 11:57:43 PM PST 24
Peak memory 232152 kb
Host smart-8924b09a-f5f5-496d-8d24-d61c8ba2f77b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096543098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.2096543098
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.1306035429
Short name T347
Test name
Test status
Simulation time 64531460769 ps
CPU time 948.69 seconds
Started Jan 24 11:41:58 PM PST 24
Finished Jan 24 11:57:49 PM PST 24
Peak memory 239344 kb
Host smart-d541cab8-7ced-4aff-9755-e9ef58e0bb3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306035429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.1306035429
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.2733678099
Short name T291
Test name
Test status
Simulation time 333842305817 ps
CPU time 3211.19 seconds
Started Jan 24 11:41:58 PM PST 24
Finished Jan 25 12:35:31 AM PST 24
Peak memory 231876 kb
Host smart-33b2d7b3-6a6d-4e5e-b8db-75dba000c6b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733678099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.2733678099
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.1179090134
Short name T305
Test name
Test status
Simulation time 69595361355 ps
CPU time 837.8 seconds
Started Jan 24 11:42:07 PM PST 24
Finished Jan 24 11:56:06 PM PST 24
Peak memory 215700 kb
Host smart-da77cb49-b185-429d-ba6d-c4435ab19b2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179090134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.1179090134
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.509074951
Short name T581
Test name
Test status
Simulation time 436130269708 ps
CPU time 1459.77 seconds
Started Jan 24 11:42:07 PM PST 24
Finished Jan 25 12:06:28 AM PST 24
Peak memory 228996 kb
Host smart-da78c787-883a-42dd-bd3e-b21ab06dea64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509074951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.509074951
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.1949889179
Short name T787
Test name
Test status
Simulation time 362944792082 ps
CPU time 1787.42 seconds
Started Jan 25 12:55:08 AM PST 24
Finished Jan 25 01:24:57 AM PST 24
Peak memory 248560 kb
Host smart-00c0be19-825a-4bb4-b063-9e74d3098812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949889179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.1949889179
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.991619225
Short name T602
Test name
Test status
Simulation time 97250669406 ps
CPU time 802.09 seconds
Started Jan 24 11:42:43 PM PST 24
Finished Jan 24 11:56:06 PM PST 24
Peak memory 242336 kb
Host smart-dd5fa12f-e2eb-43dd-97a7-f1be5d2d8582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991619225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.991619225
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1644018315
Short name T114
Test name
Test status
Simulation time 114423669357 ps
CPU time 450.66 seconds
Started Jan 24 11:42:39 PM PST 24
Finished Jan 24 11:50:10 PM PST 24
Peak memory 232120 kb
Host smart-26595fd1-009f-4417-ae54-8452bbfaf82b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644018315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1644018315
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.262646007
Short name T463
Test name
Test status
Simulation time 117987632902 ps
CPU time 1381.23 seconds
Started Jan 25 03:03:23 AM PST 24
Finished Jan 25 03:26:27 AM PST 24
Peak memory 232156 kb
Host smart-b144e4af-51df-4c69-99d1-0c5f33bca5d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262646007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.262646007
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1448260550
Short name T470
Test name
Test status
Simulation time 28645745 ps
CPU time 0.57 seconds
Started Jan 24 11:28:50 PM PST 24
Finished Jan 24 11:28:55 PM PST 24
Peak memory 193548 kb
Host smart-30e129f2-6668-4a10-9b61-806601f1d687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448260550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1448260550
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.740573942
Short name T661
Test name
Test status
Simulation time 554599433 ps
CPU time 9.15 seconds
Started Jan 24 11:28:48 PM PST 24
Finished Jan 24 11:29:00 PM PST 24
Peak memory 215576 kb
Host smart-a89dfa1b-115f-427d-82d7-d6a1263796ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740573942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.740573942
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3680404252
Short name T318
Test name
Test status
Simulation time 212451139 ps
CPU time 4.74 seconds
Started Jan 24 11:28:49 PM PST 24
Finished Jan 24 11:28:58 PM PST 24
Peak memory 199140 kb
Host smart-78175a0a-4d4f-46f7-b3af-c1b999aa922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680404252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3680404252
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2225515675
Short name T184
Test name
Test status
Simulation time 2014761828 ps
CPU time 25.85 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:29:21 PM PST 24
Peak memory 199080 kb
Host smart-4affdf7f-fdcd-4471-9f34-fb19e363d051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225515675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2225515675
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.411846540
Short name T458
Test name
Test status
Simulation time 27184804204 ps
CPU time 115.57 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:30:51 PM PST 24
Peak memory 199124 kb
Host smart-18d7353f-3cf5-4943-b4e4-24b941d2f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411846540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.411846540
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1992116066
Short name T827
Test name
Test status
Simulation time 1107491434 ps
CPU time 60.73 seconds
Started Jan 24 11:28:51 PM PST 24
Finished Jan 24 11:29:56 PM PST 24
Peak memory 199112 kb
Host smart-966ff97d-df66-4111-95cf-e2d0aef1891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992116066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1992116066
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2583193684
Short name T201
Test name
Test status
Simulation time 729473469 ps
CPU time 3.9 seconds
Started Jan 24 11:28:49 PM PST 24
Finished Jan 24 11:28:57 PM PST 24
Peak memory 199108 kb
Host smart-bb31be3e-7875-41b7-af48-57bea7ac67fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583193684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2583193684
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1622647280
Short name T576
Test name
Test status
Simulation time 44495955170 ps
CPU time 728.31 seconds
Started Jan 24 11:28:54 PM PST 24
Finished Jan 24 11:41:05 PM PST 24
Peak memory 199212 kb
Host smart-df60a403-86a6-43a1-865e-b5ce46392853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622647280 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1622647280
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.547345905
Short name T514
Test name
Test status
Simulation time 15067796983 ps
CPU time 768.12 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:41:44 PM PST 24
Peak memory 220184 kb
Host smart-7082ce01-4dba-46cb-b0a3-ebbd68a431b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547345905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.547345905
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1959517313
Short name T239
Test name
Test status
Simulation time 153196807 ps
CPU time 0.99 seconds
Started Jan 24 11:28:54 PM PST 24
Finished Jan 24 11:28:57 PM PST 24
Peak memory 196888 kb
Host smart-834113c4-0aa1-40a9-8448-27bf1e0f8950
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959517313 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1959517313
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.216083157
Short name T570
Test name
Test status
Simulation time 4758479774 ps
CPU time 54.88 seconds
Started Jan 24 11:28:52 PM PST 24
Finished Jan 24 11:29:50 PM PST 24
Peak memory 199228 kb
Host smart-5eb2daeb-b62c-43e1-b2ac-13ab4a5c9a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216083157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.216083157
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.4285040498
Short name T807
Test name
Test status
Simulation time 572507550469 ps
CPU time 2872.31 seconds
Started Jan 24 11:42:54 PM PST 24
Finished Jan 25 12:30:48 AM PST 24
Peak memory 225972 kb
Host smart-d83d5981-52a3-402a-a073-36a42f2fe857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285040498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.4285040498
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.618875059
Short name T319
Test name
Test status
Simulation time 52719949565 ps
CPU time 278.84 seconds
Started Jan 25 12:50:15 AM PST 24
Finished Jan 25 12:54:56 AM PST 24
Peak memory 215740 kb
Host smart-8cd715d5-b7d3-42bc-8e1f-2212a50d5933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618875059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.618875059
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1172673689
Short name T423
Test name
Test status
Simulation time 216701211349 ps
CPU time 2584.92 seconds
Started Jan 24 11:42:52 PM PST 24
Finished Jan 25 12:25:58 AM PST 24
Peak memory 248552 kb
Host smart-efd746b2-6dc8-417a-8df9-b30d273c4586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172673689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.1172673689
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.2252563158
Short name T604
Test name
Test status
Simulation time 184061429088 ps
CPU time 626.27 seconds
Started Jan 24 11:42:55 PM PST 24
Finished Jan 24 11:53:22 PM PST 24
Peak memory 223936 kb
Host smart-5e65d53c-fa94-441c-845e-ad18b1ba1b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252563158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.2252563158
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.1631363317
Short name T497
Test name
Test status
Simulation time 189303202721 ps
CPU time 2465.23 seconds
Started Jan 25 01:51:55 AM PST 24
Finished Jan 25 02:33:07 AM PST 24
Peak memory 215460 kb
Host smart-38a9dbb3-fdf5-47a7-99dd-a3759c948e66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631363317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.1631363317
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.2150761466
Short name T252
Test name
Test status
Simulation time 50962704827 ps
CPU time 1847.61 seconds
Started Jan 25 12:57:45 AM PST 24
Finished Jan 25 01:28:34 AM PST 24
Peak memory 248492 kb
Host smart-c0691867-5b0b-4c51-8e35-1dc437b291b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150761466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.2150761466
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2706599494
Short name T697
Test name
Test status
Simulation time 31979099436 ps
CPU time 1455.42 seconds
Started Jan 24 11:43:26 PM PST 24
Finished Jan 25 12:07:44 AM PST 24
Peak memory 208248 kb
Host smart-f8d8983c-f351-4444-8901-a77571050a5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706599494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2706599494
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.432590094
Short name T35
Test name
Test status
Simulation time 125166481235 ps
CPU time 882.24 seconds
Started Jan 24 11:43:43 PM PST 24
Finished Jan 24 11:58:30 PM PST 24
Peak memory 247452 kb
Host smart-c0c13f14-4693-4338-be4d-559d61a51da2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432590094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.432590094
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.1652813300
Short name T336
Test name
Test status
Simulation time 20559323999 ps
CPU time 148.86 seconds
Started Jan 24 11:43:42 PM PST 24
Finished Jan 24 11:46:16 PM PST 24
Peak memory 199328 kb
Host smart-69039c21-74e2-49f3-86b6-aaf23685fd36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652813300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.1652813300
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3840927820
Short name T792
Test name
Test status
Simulation time 187839284 ps
CPU time 0.64 seconds
Started Jan 25 01:52:38 AM PST 24
Finished Jan 25 01:52:40 AM PST 24
Peak memory 193364 kb
Host smart-3714041f-f492-4798-9a40-f7a68ef8024f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840927820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3840927820
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3931513727
Short name T388
Test name
Test status
Simulation time 1245039076 ps
CPU time 24.7 seconds
Started Jan 25 03:38:04 AM PST 24
Finished Jan 25 03:38:31 AM PST 24
Peak memory 213592 kb
Host smart-9e16e4fe-b4b7-43a4-b505-9ba82fe16db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931513727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3931513727
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1472711641
Short name T766
Test name
Test status
Simulation time 1383217223 ps
CPU time 65.96 seconds
Started Jan 25 01:10:38 AM PST 24
Finished Jan 25 01:11:46 AM PST 24
Peak memory 199164 kb
Host smart-34c30297-1503-4969-911f-1e77175a3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472711641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1472711641
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3506179842
Short name T330
Test name
Test status
Simulation time 6014075392 ps
CPU time 81.38 seconds
Started Jan 24 11:29:01 PM PST 24
Finished Jan 24 11:30:25 PM PST 24
Peak memory 199228 kb
Host smart-2835cf06-865e-425f-a855-0cc0962bfc2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506179842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3506179842
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4182918092
Short name T270
Test name
Test status
Simulation time 1078158734 ps
CPU time 13.46 seconds
Started Jan 24 11:29:04 PM PST 24
Finished Jan 24 11:29:20 PM PST 24
Peak memory 199020 kb
Host smart-5f021dee-8fb9-473d-ad2b-f9cda57c1eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182918092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4182918092
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1651154266
Short name T279
Test name
Test status
Simulation time 6379584961 ps
CPU time 117.25 seconds
Started Jan 24 11:28:49 PM PST 24
Finished Jan 24 11:30:51 PM PST 24
Peak memory 199160 kb
Host smart-e30bbd7d-b24f-4608-98b8-50a25c418f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651154266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1651154266
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1722504090
Short name T587
Test name
Test status
Simulation time 301614727 ps
CPU time 4.1 seconds
Started Jan 24 11:28:48 PM PST 24
Finished Jan 24 11:28:57 PM PST 24
Peak memory 198896 kb
Host smart-738e4dbb-7e00-47c5-ba3e-2dbf4161c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722504090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1722504090
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.8769117
Short name T808
Test name
Test status
Simulation time 3107475773 ps
CPU time 64.1 seconds
Started Jan 24 11:29:05 PM PST 24
Finished Jan 24 11:30:11 PM PST 24
Peak memory 207424 kb
Host smart-bc1e8354-30e2-4345-9558-713e840bdc26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8769117 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.8769117
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.1884984500
Short name T624
Test name
Test status
Simulation time 155648400739 ps
CPU time 1228.53 seconds
Started Jan 24 11:29:06 PM PST 24
Finished Jan 24 11:49:36 PM PST 24
Peak memory 232124 kb
Host smart-6223ae23-099a-449f-9a88-361d9d4d2f25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884984500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.1884984500
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1918593583
Short name T491
Test name
Test status
Simulation time 125230278 ps
CPU time 1.17 seconds
Started Jan 24 11:29:07 PM PST 24
Finished Jan 24 11:29:10 PM PST 24
Peak memory 198436 kb
Host smart-867f0978-9b7b-40ff-8dea-c2e84594c776
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918593583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1918593583
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2463560600
Short name T322
Test name
Test status
Simulation time 27470655116 ps
CPU time 395.02 seconds
Started Jan 25 01:26:16 AM PST 24
Finished Jan 25 01:32:52 AM PST 24
Peak memory 199180 kb
Host smart-d6177dd6-ffa7-4cf1-9594-823c65ed677d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463560600 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.2463560600
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1299736491
Short name T707
Test name
Test status
Simulation time 11586788337 ps
CPU time 43.44 seconds
Started Jan 24 11:29:03 PM PST 24
Finished Jan 24 11:29:48 PM PST 24
Peak memory 199216 kb
Host smart-d4c95d93-7d83-4c68-8c6f-bd4e76a61d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299736491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1299736491
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.840443519
Short name T241
Test name
Test status
Simulation time 81192155582 ps
CPU time 855.2 seconds
Started Jan 24 11:43:53 PM PST 24
Finished Jan 24 11:58:10 PM PST 24
Peak memory 248468 kb
Host smart-f087c0b3-5ede-431e-8a4d-f6776c687d9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840443519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.840443519
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.403940201
Short name T828
Test name
Test status
Simulation time 135199882961 ps
CPU time 1172.79 seconds
Started Jan 24 11:44:10 PM PST 24
Finished Jan 25 12:03:44 AM PST 24
Peak memory 232128 kb
Host smart-014f32b7-742f-4b9f-b6ae-0d85f89c7217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403940201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.403940201
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2247394372
Short name T802
Test name
Test status
Simulation time 22123552471 ps
CPU time 1031.38 seconds
Started Jan 24 11:44:07 PM PST 24
Finished Jan 25 12:01:19 AM PST 24
Peak memory 215772 kb
Host smart-88ac0df0-195d-45c4-afba-06b193596b9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247394372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.2247394372
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.4213619990
Short name T513
Test name
Test status
Simulation time 9293019416 ps
CPU time 89.67 seconds
Started Jan 24 11:44:23 PM PST 24
Finished Jan 24 11:45:53 PM PST 24
Peak memory 210920 kb
Host smart-11045c6c-c253-4d94-9dae-e9029bf2dc6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213619990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.4213619990
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.616197768
Short name T102
Test name
Test status
Simulation time 62295668428 ps
CPU time 1604.82 seconds
Started Jan 24 11:44:23 PM PST 24
Finished Jan 25 12:11:09 AM PST 24
Peak memory 225996 kb
Host smart-8888f8c4-4e92-4437-9a01-6eba2cf85a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616197768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.616197768
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.4179199172
Short name T775
Test name
Test status
Simulation time 353181582661 ps
CPU time 1492.97 seconds
Started Jan 24 11:44:25 PM PST 24
Finished Jan 25 12:09:20 AM PST 24
Peak memory 223944 kb
Host smart-03091bad-bda2-47ce-86a4-59e10506758d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179199172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.4179199172
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.3046581523
Short name T454
Test name
Test status
Simulation time 31660615715 ps
CPU time 1509.28 seconds
Started Jan 24 11:44:47 PM PST 24
Finished Jan 25 12:10:02 AM PST 24
Peak memory 213012 kb
Host smart-0b03d79b-89ce-4ca1-919c-a27544524411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046581523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.3046581523
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2711778511
Short name T282
Test name
Test status
Simulation time 11459339 ps
CPU time 0.59 seconds
Started Jan 24 11:29:23 PM PST 24
Finished Jan 24 11:29:27 PM PST 24
Peak memory 192604 kb
Host smart-d3299026-ec43-4b3b-a0e0-18afe5323c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711778511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2711778511
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2014889904
Short name T432
Test name
Test status
Simulation time 1201477370 ps
CPU time 34.56 seconds
Started Jan 24 11:29:22 PM PST 24
Finished Jan 24 11:30:01 PM PST 24
Peak memory 207336 kb
Host smart-e515d7f0-2241-4c73-8e60-5b3cdc194225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014889904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2014889904
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.469016503
Short name T349
Test name
Test status
Simulation time 6969427534 ps
CPU time 43.89 seconds
Started Jan 24 11:29:26 PM PST 24
Finished Jan 24 11:30:15 PM PST 24
Peak memory 199220 kb
Host smart-b853a188-1a7c-4643-84cb-481380a82632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469016503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.469016503
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.347778726
Short name T191
Test name
Test status
Simulation time 3357028470 ps
CPU time 86.5 seconds
Started Jan 24 11:29:26 PM PST 24
Finished Jan 24 11:30:58 PM PST 24
Peak memory 199252 kb
Host smart-44e99910-1320-48c2-bf8c-1d4cb7e685dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347778726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.347778726
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3233697173
Short name T798
Test name
Test status
Simulation time 11714379627 ps
CPU time 45.52 seconds
Started Jan 24 11:29:23 PM PST 24
Finished Jan 24 11:30:12 PM PST 24
Peak memory 199180 kb
Host smart-4d89b903-b97f-49f2-a8b8-6c160bb21619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233697173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3233697173
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.773635638
Short name T333
Test name
Test status
Simulation time 11724710023 ps
CPU time 29.03 seconds
Started Jan 24 11:29:07 PM PST 24
Finished Jan 24 11:29:37 PM PST 24
Peak memory 199140 kb
Host smart-3ab8ffcd-d75e-4193-b2fd-3d6374c3ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773635638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.773635638
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.127838362
Short name T598
Test name
Test status
Simulation time 154220917 ps
CPU time 4.67 seconds
Started Jan 25 02:03:02 AM PST 24
Finished Jan 25 02:03:10 AM PST 24
Peak memory 199196 kb
Host smart-28973024-3189-4229-a60c-6b51a795a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127838362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.127838362
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1921389385
Short name T106
Test name
Test status
Simulation time 82894831445 ps
CPU time 1065.75 seconds
Started Jan 24 11:29:24 PM PST 24
Finished Jan 24 11:47:13 PM PST 24
Peak memory 234020 kb
Host smart-c5eda724-6b2e-47cf-bc87-f4cf77025e5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921389385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1921389385
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1757735684
Short name T724
Test name
Test status
Simulation time 317648567358 ps
CPU time 1115.12 seconds
Started Jan 24 11:29:24 PM PST 24
Finished Jan 24 11:48:02 PM PST 24
Peak memory 263108 kb
Host smart-43fe0ad4-7ea7-47b2-a3ca-5b19752576f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757735684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1757735684
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.847779680
Short name T741
Test name
Test status
Simulation time 351824846 ps
CPU time 0.91 seconds
Started Jan 24 11:29:23 PM PST 24
Finished Jan 24 11:29:27 PM PST 24
Peak memory 196880 kb
Host smart-3243ffce-815c-479f-9c14-4b9f35b8523b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847779680 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.847779680
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.203523688
Short name T197
Test name
Test status
Simulation time 82690883213 ps
CPU time 485.94 seconds
Started Jan 24 11:29:23 PM PST 24
Finished Jan 24 11:37:33 PM PST 24
Peak memory 199184 kb
Host smart-f71c3634-b2ca-43ce-bc0d-71f5462b3e4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203523688 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_sha_vectors.203523688
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2932241565
Short name T743
Test name
Test status
Simulation time 1446443417 ps
CPU time 31.89 seconds
Started Jan 24 11:29:25 PM PST 24
Finished Jan 24 11:29:59 PM PST 24
Peak memory 199144 kb
Host smart-ac90342a-404c-4451-a6d1-9e357d2250eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932241565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2932241565
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.74589422
Short name T687
Test name
Test status
Simulation time 36608051658 ps
CPU time 486.17 seconds
Started Jan 24 11:45:03 PM PST 24
Finished Jan 24 11:53:11 PM PST 24
Peak memory 234168 kb
Host smart-a392a783-9245-4e9a-b97d-0fb570e13c1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74589422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.74589422
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.1956876911
Short name T107
Test name
Test status
Simulation time 50368292273 ps
CPU time 2721.72 seconds
Started Jan 24 11:45:02 PM PST 24
Finished Jan 25 12:30:26 AM PST 24
Peak memory 245704 kb
Host smart-4f53467b-335a-4ce2-9b96-232dea7a109d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956876911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.1956876911
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.310264652
Short name T100
Test name
Test status
Simulation time 88825488899 ps
CPU time 355.96 seconds
Started Jan 24 11:45:03 PM PST 24
Finished Jan 24 11:51:01 PM PST 24
Peak memory 238476 kb
Host smart-3de81b8d-e208-4564-b608-925204bc0a78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310264652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.310264652
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.4267049239
Short name T283
Test name
Test status
Simulation time 50400823272 ps
CPU time 2683.08 seconds
Started Jan 24 11:45:02 PM PST 24
Finished Jan 25 12:29:48 AM PST 24
Peak memory 243804 kb
Host smart-0cc7555d-2dfb-40d5-a509-bd3e05ef195d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267049239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.4267049239
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.359994408
Short name T5
Test name
Test status
Simulation time 51013535150 ps
CPU time 2978.37 seconds
Started Jan 25 01:17:15 AM PST 24
Finished Jan 25 02:06:55 AM PST 24
Peak memory 248536 kb
Host smart-cb0c0e21-ff50-430e-b969-3b07b3f0b1be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359994408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.359994408
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.637593049
Short name T785
Test name
Test status
Simulation time 124774901947 ps
CPU time 2281.34 seconds
Started Jan 24 11:45:16 PM PST 24
Finished Jan 25 12:23:18 AM PST 24
Peak memory 248512 kb
Host smart-bab57263-305e-436c-a229-7a3553fda657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637593049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.637593049
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.694367841
Short name T700
Test name
Test status
Simulation time 155103072350 ps
CPU time 1109.67 seconds
Started Jan 24 11:45:14 PM PST 24
Finished Jan 25 12:03:45 AM PST 24
Peak memory 214388 kb
Host smart-e0630dbd-1e37-4cc7-9e68-dc4e6866698c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694367841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.694367841
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.1818605901
Short name T289
Test name
Test status
Simulation time 475263087853 ps
CPU time 1322.15 seconds
Started Jan 25 02:35:34 AM PST 24
Finished Jan 25 02:57:44 AM PST 24
Peak memory 245528 kb
Host smart-78891470-efd2-4793-946f-1987c1674323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818605901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.1818605901
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3821528448
Short name T554
Test name
Test status
Simulation time 60233105825 ps
CPU time 1084.22 seconds
Started Jan 25 12:09:02 AM PST 24
Finished Jan 25 12:27:07 AM PST 24
Peak memory 245900 kb
Host smart-25850c39-2bc9-4133-af7e-a75b6ba40631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821528448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3821528448
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.854578062
Short name T316
Test name
Test status
Simulation time 138527245981 ps
CPU time 1039.12 seconds
Started Jan 24 11:45:38 PM PST 24
Finished Jan 25 12:02:59 AM PST 24
Peak memory 223896 kb
Host smart-34440429-0e4b-402f-99ba-068e65453a24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854578062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.854578062
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3039072844
Short name T413
Test name
Test status
Simulation time 42714492 ps
CPU time 0.58 seconds
Started Jan 24 11:25:59 PM PST 24
Finished Jan 24 11:26:04 PM PST 24
Peak memory 192596 kb
Host smart-3caecf3a-5c01-426a-8c46-088e2790fb5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039072844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3039072844
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1525115314
Short name T40
Test name
Test status
Simulation time 6570697282 ps
CPU time 68.15 seconds
Started Jan 24 11:25:59 PM PST 24
Finished Jan 24 11:27:12 PM PST 24
Peak memory 240176 kb
Host smart-5440e0e4-d88e-4ca2-8240-0cbb4c92e7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525115314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1525115314
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2137788878
Short name T346
Test name
Test status
Simulation time 5571865488 ps
CPU time 41.06 seconds
Started Jan 24 11:25:57 PM PST 24
Finished Jan 24 11:26:44 PM PST 24
Peak memory 199216 kb
Host smart-379e3e21-a32d-4612-82cc-a3f72fccc7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137788878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2137788878
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.957883654
Short name T267
Test name
Test status
Simulation time 3726716149 ps
CPU time 97.09 seconds
Started Jan 24 11:25:57 PM PST 24
Finished Jan 24 11:27:40 PM PST 24
Peak memory 199208 kb
Host smart-1d86746c-40b3-43be-be03-4428a6962181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957883654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.957883654
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2817744839
Short name T406
Test name
Test status
Simulation time 9366316883 ps
CPU time 115.03 seconds
Started Jan 24 11:25:55 PM PST 24
Finished Jan 24 11:27:57 PM PST 24
Peak memory 199252 kb
Host smart-9b892fe6-8cad-4ac9-b244-b87a0b120a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817744839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2817744839
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3633243412
Short name T220
Test name
Test status
Simulation time 131820968093 ps
CPU time 86.97 seconds
Started Jan 24 11:25:56 PM PST 24
Finished Jan 24 11:27:29 PM PST 24
Peak memory 199236 kb
Host smart-a44880ae-06ca-49c4-ae6e-4c2978df3403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633243412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3633243412
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1849271657
Short name T45
Test name
Test status
Simulation time 307259944 ps
CPU time 0.95 seconds
Started Jan 24 11:25:54 PM PST 24
Finished Jan 24 11:26:03 PM PST 24
Peak memory 217156 kb
Host smart-d5883a89-dbe1-45bf-9503-1c3c421fdd3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849271657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1849271657
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1574987599
Short name T247
Test name
Test status
Simulation time 450694588 ps
CPU time 4.87 seconds
Started Jan 24 11:25:57 PM PST 24
Finished Jan 24 11:26:07 PM PST 24
Peak memory 199164 kb
Host smart-1169a7d7-6eb1-48d0-84a2-bceb59e48ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574987599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1574987599
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2802808922
Short name T552
Test name
Test status
Simulation time 123347931057 ps
CPU time 2398.02 seconds
Started Jan 24 11:25:53 PM PST 24
Finished Jan 25 12:06:00 AM PST 24
Peak memory 256692 kb
Host smart-ec9d0cc1-1df7-4e13-b9ac-e6a3bdb7ae6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802808922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2802808922
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1781974092
Short name T679
Test name
Test status
Simulation time 29905238 ps
CPU time 1.11 seconds
Started Jan 24 11:25:59 PM PST 24
Finished Jan 24 11:26:06 PM PST 24
Peak memory 197756 kb
Host smart-8ae6a75c-0118-45e4-8705-11046b5bce16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781974092 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1781974092
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3914624117
Short name T768
Test name
Test status
Simulation time 31912959907 ps
CPU time 391.66 seconds
Started Jan 24 11:25:55 PM PST 24
Finished Jan 24 11:32:34 PM PST 24
Peak memory 199184 kb
Host smart-ad7fa32a-eddd-403e-921c-e007e88d5c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914624117 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.3914624117
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3880143880
Short name T471
Test name
Test status
Simulation time 8553834800 ps
CPU time 76.28 seconds
Started Jan 24 11:25:58 PM PST 24
Finished Jan 24 11:27:20 PM PST 24
Peak memory 199240 kb
Host smart-57fb3cdf-e65c-451a-b1fa-6c13ada06183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880143880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3880143880
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1045527554
Short name T53
Test name
Test status
Simulation time 26821455 ps
CPU time 0.61 seconds
Started Jan 24 11:58:33 PM PST 24
Finished Jan 24 11:58:34 PM PST 24
Peak memory 192596 kb
Host smart-368ad2a3-f3f6-4c33-8bd5-0d2ffeb8474b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045527554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1045527554
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1778354710
Short name T338
Test name
Test status
Simulation time 9196506580 ps
CPU time 46.92 seconds
Started Jan 24 11:29:22 PM PST 24
Finished Jan 24 11:30:14 PM PST 24
Peak memory 229464 kb
Host smart-fce09e89-efa2-4d53-b13f-a844396c83b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778354710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1778354710
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1923660920
Short name T779
Test name
Test status
Simulation time 3562610505 ps
CPU time 36.32 seconds
Started Jan 25 12:22:37 AM PST 24
Finished Jan 25 12:23:15 AM PST 24
Peak memory 199228 kb
Host smart-413249dd-8da3-49eb-b1b3-0696ef7f5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923660920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1923660920
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3374049933
Short name T501
Test name
Test status
Simulation time 462275297 ps
CPU time 6.5 seconds
Started Jan 25 04:09:52 AM PST 24
Finished Jan 25 04:09:59 AM PST 24
Peak memory 199132 kb
Host smart-63cf239e-afdc-4f2c-b4c4-3a45361b2a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374049933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3374049933
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2993669045
Short name T395
Test name
Test status
Simulation time 19262721169 ps
CPU time 113.64 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:31:37 PM PST 24
Peak memory 199200 kb
Host smart-7d6b02ab-2c03-49ae-b59b-f67344c2874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993669045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2993669045
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2797360695
Short name T449
Test name
Test status
Simulation time 8643861537 ps
CPU time 53.16 seconds
Started Jan 24 11:29:25 PM PST 24
Finished Jan 24 11:30:21 PM PST 24
Peak memory 199212 kb
Host smart-4b1e0649-4b3a-4283-92d3-547a196d669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797360695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2797360695
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1004095341
Short name T560
Test name
Test status
Simulation time 353578593 ps
CPU time 2.4 seconds
Started Jan 24 11:29:24 PM PST 24
Finished Jan 24 11:29:29 PM PST 24
Peak memory 198840 kb
Host smart-044ac3ee-6254-4914-9314-bbe64c984740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004095341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1004095341
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1601745152
Short name T640
Test name
Test status
Simulation time 180759935 ps
CPU time 4.37 seconds
Started Jan 24 11:44:43 PM PST 24
Finished Jan 24 11:44:50 PM PST 24
Peak memory 199176 kb
Host smart-c2d220bb-201b-43f4-ad1e-7a0ec3c5cf9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601745152 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1601745152
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3448105829
Short name T473
Test name
Test status
Simulation time 71944516078 ps
CPU time 272.36 seconds
Started Jan 25 03:37:30 AM PST 24
Finished Jan 25 03:42:10 AM PST 24
Peak memory 214576 kb
Host smart-c328ce32-fe9c-43d0-b996-3c5c734f1741
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448105829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.3448105829
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.108615143
Short name T637
Test name
Test status
Simulation time 537297583 ps
CPU time 1.25 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:29:44 PM PST 24
Peak memory 198168 kb
Host smart-2c3bcbd1-afd9-4de2-9a2f-6d4c86fd4391
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108615143 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.108615143
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1372961490
Short name T589
Test name
Test status
Simulation time 100540340798 ps
CPU time 411.73 seconds
Started Jan 24 11:29:28 PM PST 24
Finished Jan 24 11:36:24 PM PST 24
Peak memory 199176 kb
Host smart-f5a66816-7abc-4d1d-a43b-5477448db8b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372961490 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.1372961490
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.436050179
Short name T261
Test name
Test status
Simulation time 1105861730 ps
CPU time 43.39 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:30:26 PM PST 24
Peak memory 199088 kb
Host smart-16227c43-5dd2-4695-9787-0158c557aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436050179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.436050179
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3043185636
Short name T571
Test name
Test status
Simulation time 33235335 ps
CPU time 0.62 seconds
Started Jan 24 11:30:04 PM PST 24
Finished Jan 24 11:30:14 PM PST 24
Peak memory 193416 kb
Host smart-33ff2efa-c06e-482f-8cdd-3fac40d14b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043185636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3043185636
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3507097548
Short name T810
Test name
Test status
Simulation time 2449812454 ps
CPU time 23.9 seconds
Started Jan 24 11:29:39 PM PST 24
Finished Jan 24 11:30:05 PM PST 24
Peak memory 217672 kb
Host smart-5c8e0ccc-b7a0-4e76-a9f1-1d6bdd1d262c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507097548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3507097548
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3512666259
Short name T415
Test name
Test status
Simulation time 10614467108 ps
CPU time 44.85 seconds
Started Jan 24 11:29:39 PM PST 24
Finished Jan 24 11:30:25 PM PST 24
Peak memory 199220 kb
Host smart-205871fb-d1c6-48a2-8846-cbce3bed0b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512666259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3512666259
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3726532585
Short name T58
Test name
Test status
Simulation time 393573846 ps
CPU time 25.25 seconds
Started Jan 25 12:17:43 AM PST 24
Finished Jan 25 12:18:10 AM PST 24
Peak memory 199096 kb
Host smart-a100e42d-f0d4-472b-8857-e71ca9d9dc3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726532585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3726532585
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3624837766
Short name T50
Test name
Test status
Simulation time 22224524336 ps
CPU time 64.26 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:30:47 PM PST 24
Peak memory 199168 kb
Host smart-33502abf-058d-45ca-8189-410afc28d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624837766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3624837766
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2429424097
Short name T378
Test name
Test status
Simulation time 155950475 ps
CPU time 8.53 seconds
Started Jan 25 12:17:51 AM PST 24
Finished Jan 25 12:18:01 AM PST 24
Peak memory 199164 kb
Host smart-8b7e1e03-77b5-4db7-89ec-7faa5150716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429424097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2429424097
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3013881558
Short name T343
Test name
Test status
Simulation time 1324138832 ps
CPU time 3.72 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:29:46 PM PST 24
Peak memory 198972 kb
Host smart-7af17777-49f3-4e07-8805-30423ace5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013881558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3013881558
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2393637637
Short name T407
Test name
Test status
Simulation time 32481976060 ps
CPU time 787.74 seconds
Started Jan 24 11:30:01 PM PST 24
Finished Jan 24 11:43:18 PM PST 24
Peak memory 223788 kb
Host smart-8ed4fc43-f973-4f62-9eed-c2e42c986e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393637637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2393637637
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.1628015308
Short name T97
Test name
Test status
Simulation time 63110811035 ps
CPU time 861.44 seconds
Started Jan 24 11:30:04 PM PST 24
Finished Jan 24 11:44:35 PM PST 24
Peak memory 241192 kb
Host smart-d6b2697d-fa35-46ca-b271-5e1921884f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628015308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.1628015308
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.122100435
Short name T591
Test name
Test status
Simulation time 132018495 ps
CPU time 0.92 seconds
Started Jan 24 11:29:59 PM PST 24
Finished Jan 24 11:30:04 PM PST 24
Peak memory 196144 kb
Host smart-1fd80548-52e2-41aa-8f01-005148399982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122100435 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.122100435
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.13122796
Short name T516
Test name
Test status
Simulation time 62718089253 ps
CPU time 457.76 seconds
Started Jan 24 11:30:02 PM PST 24
Finished Jan 24 11:37:49 PM PST 24
Peak memory 199124 kb
Host smart-f23d33e2-86c7-4fa1-893e-01098b624049
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13122796 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.hmac_test_sha_vectors.13122796
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.790920835
Short name T774
Test name
Test status
Simulation time 7004668516 ps
CPU time 83.4 seconds
Started Jan 24 11:29:42 PM PST 24
Finished Jan 24 11:31:06 PM PST 24
Peak memory 199208 kb
Host smart-1f4d9c32-78a5-4220-b4cb-91159c76e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790920835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.790920835
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1786880069
Short name T11
Test name
Test status
Simulation time 30685653 ps
CPU time 0.62 seconds
Started Jan 24 11:29:58 PM PST 24
Finished Jan 24 11:30:03 PM PST 24
Peak memory 192620 kb
Host smart-675baec5-04df-488f-8a98-a6021521701c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786880069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1786880069
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.118441145
Short name T31
Test name
Test status
Simulation time 2023082474 ps
CPU time 33.61 seconds
Started Jan 24 11:30:00 PM PST 24
Finished Jan 24 11:30:42 PM PST 24
Peak memory 231840 kb
Host smart-06f9159a-b7f3-4a5b-acd1-9734c8c95c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118441145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.118441145
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2030171986
Short name T616
Test name
Test status
Simulation time 4634364604 ps
CPU time 50.56 seconds
Started Jan 24 11:29:59 PM PST 24
Finished Jan 24 11:30:59 PM PST 24
Peak memory 199232 kb
Host smart-435ed106-86f3-4907-8535-8d9fd271744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030171986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2030171986
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2895157378
Short name T486
Test name
Test status
Simulation time 210685408 ps
CPU time 11.12 seconds
Started Jan 24 11:29:59 PM PST 24
Finished Jan 24 11:30:14 PM PST 24
Peak memory 199184 kb
Host smart-16c2c95d-a443-4175-b04f-1bbe5a9b81fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895157378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2895157378
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2703986688
Short name T729
Test name
Test status
Simulation time 31396348797 ps
CPU time 119.63 seconds
Started Jan 24 11:30:04 PM PST 24
Finished Jan 24 11:32:13 PM PST 24
Peak memory 199208 kb
Host smart-247cfafc-d628-4988-86eb-9454394435d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703986688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2703986688
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1943396778
Short name T131
Test name
Test status
Simulation time 5876676039 ps
CPU time 107.3 seconds
Started Jan 24 11:30:00 PM PST 24
Finished Jan 24 11:31:56 PM PST 24
Peak memory 199180 kb
Host smart-569c6a90-758e-436a-b0e5-2770a871fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943396778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1943396778
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.367480991
Short name T271
Test name
Test status
Simulation time 677301711 ps
CPU time 4.17 seconds
Started Jan 24 11:30:01 PM PST 24
Finished Jan 24 11:30:14 PM PST 24
Peak memory 199180 kb
Host smart-4b0a04ad-45df-4e87-b309-40039bebe9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367480991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.367480991
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2870512887
Short name T474
Test name
Test status
Simulation time 211641862588 ps
CPU time 877.97 seconds
Started Jan 24 11:30:00 PM PST 24
Finished Jan 24 11:44:46 PM PST 24
Peak memory 199228 kb
Host smart-9fedbb8e-c556-4e01-9dcd-a81a87d601c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870512887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2870512887
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.195385369
Short name T813
Test name
Test status
Simulation time 30833727354 ps
CPU time 581.23 seconds
Started Jan 24 11:30:02 PM PST 24
Finished Jan 24 11:39:53 PM PST 24
Peak memory 207548 kb
Host smart-3ef76cac-1c90-4657-be91-d76c17e386a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195385369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.195385369
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.372644186
Short name T517
Test name
Test status
Simulation time 250010246 ps
CPU time 1.07 seconds
Started Jan 24 11:30:02 PM PST 24
Finished Jan 24 11:30:12 PM PST 24
Peak memory 198356 kb
Host smart-21e3a8c1-452b-4603-a4ed-76ea2833eebd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372644186 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.372644186
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3376208527
Short name T450
Test name
Test status
Simulation time 53286758979 ps
CPU time 466.26 seconds
Started Jan 24 11:30:00 PM PST 24
Finished Jan 24 11:37:55 PM PST 24
Peak memory 199084 kb
Host smart-df5b80bf-4ce5-4f0a-8e64-4edde311dad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376208527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3376208527
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2174482811
Short name T701
Test name
Test status
Simulation time 698832269 ps
CPU time 9.29 seconds
Started Jan 24 11:30:02 PM PST 24
Finished Jan 24 11:30:20 PM PST 24
Peak memory 199108 kb
Host smart-e1a18763-9a00-46da-ab1f-a588a2e3e09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174482811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2174482811
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.286369334
Short name T705
Test name
Test status
Simulation time 36678146 ps
CPU time 0.62 seconds
Started Jan 25 01:03:23 AM PST 24
Finished Jan 25 01:03:25 AM PST 24
Peak memory 192616 kb
Host smart-26294caf-3fd6-48df-bbeb-dc0eaf262c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286369334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.286369334
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.203929509
Short name T736
Test name
Test status
Simulation time 755611261 ps
CPU time 27.37 seconds
Started Jan 24 11:30:31 PM PST 24
Finished Jan 24 11:31:00 PM PST 24
Peak memory 229316 kb
Host smart-b265c007-0ecf-4d13-897a-739337f68467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203929509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.203929509
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3625648702
Short name T772
Test name
Test status
Simulation time 1185452381 ps
CPU time 54.26 seconds
Started Jan 24 11:30:24 PM PST 24
Finished Jan 24 11:31:21 PM PST 24
Peak memory 199184 kb
Host smart-a88836f7-5bf2-4eef-8cdf-ec91d63f01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625648702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3625648702
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.296172841
Short name T499
Test name
Test status
Simulation time 502340511 ps
CPU time 27.23 seconds
Started Jan 24 11:30:31 PM PST 24
Finished Jan 24 11:31:00 PM PST 24
Peak memory 199124 kb
Host smart-98479125-c709-492e-8fd4-308adb5d1334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296172841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.296172841
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.49415704
Short name T765
Test name
Test status
Simulation time 10078657897 ps
CPU time 117.9 seconds
Started Jan 24 11:30:23 PM PST 24
Finished Jan 24 11:32:24 PM PST 24
Peak memory 199208 kb
Host smart-fdb2385d-9d45-458c-8840-fea3815c6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49415704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.49415704
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3473273671
Short name T444
Test name
Test status
Simulation time 11952535136 ps
CPU time 83.53 seconds
Started Jan 24 11:30:23 PM PST 24
Finished Jan 24 11:31:50 PM PST 24
Peak memory 199240 kb
Host smart-6a11cdd8-e510-43c8-9aee-0ecb82f00636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473273671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3473273671
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4238616551
Short name T389
Test name
Test status
Simulation time 183770108 ps
CPU time 4.29 seconds
Started Jan 24 11:30:00 PM PST 24
Finished Jan 24 11:30:13 PM PST 24
Peak memory 199160 kb
Host smart-1a246cc9-4fd4-46f9-8fcc-54ebc94baf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238616551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4238616551
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.945964801
Short name T55
Test name
Test status
Simulation time 8058917041 ps
CPU time 387.64 seconds
Started Jan 24 11:30:32 PM PST 24
Finished Jan 24 11:37:01 PM PST 24
Peak memory 199208 kb
Host smart-17645930-ccac-4242-a1dd-1035dbb0c7a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945964801 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.945964801
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.1541345670
Short name T521
Test name
Test status
Simulation time 41611798154 ps
CPU time 683.22 seconds
Started Jan 24 11:30:32 PM PST 24
Finished Jan 24 11:41:57 PM PST 24
Peak memory 240372 kb
Host smart-cffb1118-8c77-4482-8e8e-79aa02b7c46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541345670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.1541345670
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3312944319
Short name T315
Test name
Test status
Simulation time 265451467 ps
CPU time 1.13 seconds
Started Jan 24 11:30:32 PM PST 24
Finished Jan 24 11:30:35 PM PST 24
Peak memory 198488 kb
Host smart-76c40e2e-60eb-4ff9-bcb7-5a50ef1dca83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312944319 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.3312944319
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3054476730
Short name T320
Test name
Test status
Simulation time 33579128729 ps
CPU time 97.31 seconds
Started Jan 24 11:30:30 PM PST 24
Finished Jan 24 11:32:09 PM PST 24
Peak memory 199224 kb
Host smart-35f78c7a-bec5-45e0-9718-c843b7a0ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054476730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3054476730
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.660369965
Short name T426
Test name
Test status
Simulation time 17740743 ps
CPU time 0.58 seconds
Started Jan 24 11:30:39 PM PST 24
Finished Jan 24 11:30:41 PM PST 24
Peak memory 193584 kb
Host smart-0e755828-6fb2-41ba-986e-5c0fb7a5a008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660369965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.660369965
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1460014638
Short name T285
Test name
Test status
Simulation time 1487374720 ps
CPU time 50.4 seconds
Started Jan 24 11:30:41 PM PST 24
Finished Jan 24 11:31:33 PM PST 24
Peak memory 215572 kb
Host smart-2541c63a-484f-4eb4-ae15-674775a3c5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460014638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1460014638
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.669388965
Short name T210
Test name
Test status
Simulation time 19315756892 ps
CPU time 19.28 seconds
Started Jan 25 12:06:55 AM PST 24
Finished Jan 25 12:07:16 AM PST 24
Peak memory 199208 kb
Host smart-f492a13a-ef99-4919-a7ce-7fe1cd6a9663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669388965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.669388965
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.739864631
Short name T526
Test name
Test status
Simulation time 10790909787 ps
CPU time 153.04 seconds
Started Jan 25 01:32:53 AM PST 24
Finished Jan 25 01:35:27 AM PST 24
Peak memory 199192 kb
Host smart-f11a075e-e17b-48c1-bdbb-1c3ed644eba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739864631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.739864631
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4033039439
Short name T452
Test name
Test status
Simulation time 9797042665 ps
CPU time 124.41 seconds
Started Jan 24 11:30:42 PM PST 24
Finished Jan 24 11:32:48 PM PST 24
Peak memory 199208 kb
Host smart-5ed8cb20-09c0-4102-ba44-3b8d1d916dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033039439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4033039439
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.324413788
Short name T419
Test name
Test status
Simulation time 6693648597 ps
CPU time 42.03 seconds
Started Jan 25 03:12:03 AM PST 24
Finished Jan 25 03:12:46 AM PST 24
Peak memory 199200 kb
Host smart-72a27dcb-bb80-409d-acda-8d0066854510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324413788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.324413788
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.276614932
Short name T562
Test name
Test status
Simulation time 208671715 ps
CPU time 2.62 seconds
Started Jan 24 11:30:42 PM PST 24
Finished Jan 24 11:30:47 PM PST 24
Peak memory 198980 kb
Host smart-223fc86c-4f2c-4b78-b0de-1e8a09ef46ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276614932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.276614932
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.332092602
Short name T648
Test name
Test status
Simulation time 570597184734 ps
CPU time 1711.68 seconds
Started Jan 24 11:30:37 PM PST 24
Finished Jan 24 11:59:10 PM PST 24
Peak memory 226108 kb
Host smart-9233f856-f9c4-43e0-97d1-b1bc1a0de738
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332092602 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.332092602
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.3291490255
Short name T636
Test name
Test status
Simulation time 135299421057 ps
CPU time 2076.97 seconds
Started Jan 25 02:39:59 AM PST 24
Finished Jan 25 03:14:38 AM PST 24
Peak memory 231996 kb
Host smart-33e30e52-c6b9-4929-9eef-5cdfd013aa81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291490255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.3291490255
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3033485452
Short name T306
Test name
Test status
Simulation time 29031491 ps
CPU time 0.98 seconds
Started Jan 24 11:30:41 PM PST 24
Finished Jan 24 11:30:43 PM PST 24
Peak memory 196428 kb
Host smart-d651cfac-b1e2-408c-a486-1d842536e84f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033485452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3033485452
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.782597530
Short name T819
Test name
Test status
Simulation time 80941880532 ps
CPU time 479.9 seconds
Started Jan 24 11:58:31 PM PST 24
Finished Jan 25 12:06:32 AM PST 24
Peak memory 199188 kb
Host smart-a1c5413d-cfbb-4279-a359-702cb9ae735c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782597530 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.hmac_test_sha_vectors.782597530
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3346600606
Short name T538
Test name
Test status
Simulation time 1452107732 ps
CPU time 59.66 seconds
Started Jan 25 02:48:03 AM PST 24
Finished Jan 25 02:49:04 AM PST 24
Peak memory 199160 kb
Host smart-9e2fa2c7-63da-49d7-88ff-754629ef0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346600606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3346600606
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1615047815
Short name T490
Test name
Test status
Simulation time 22560983 ps
CPU time 0.57 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:31:12 PM PST 24
Peak memory 193560 kb
Host smart-09714f32-d8ac-4d96-80bb-b73205fb79ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615047815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1615047815
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.17061289
Short name T510
Test name
Test status
Simulation time 1693352741 ps
CPU time 28.03 seconds
Started Jan 24 11:30:51 PM PST 24
Finished Jan 24 11:31:20 PM PST 24
Peak memory 215528 kb
Host smart-9a69af8f-748c-4669-98c9-06b0ecda1b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17061289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.17061289
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3461235099
Short name T277
Test name
Test status
Simulation time 859454914 ps
CPU time 19.34 seconds
Started Jan 24 11:30:52 PM PST 24
Finished Jan 24 11:31:13 PM PST 24
Peak memory 199164 kb
Host smart-9d71e6d9-3f94-41de-9027-aa2b1a9a542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461235099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3461235099
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1355805566
Short name T408
Test name
Test status
Simulation time 4001181050 ps
CPU time 108.14 seconds
Started Jan 24 11:30:49 PM PST 24
Finished Jan 24 11:32:39 PM PST 24
Peak memory 199224 kb
Host smart-24ad4ca6-a6ae-48b1-ad42-8590cfb259d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355805566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1355805566
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.551553953
Short name T238
Test name
Test status
Simulation time 2969728152 ps
CPU time 77.74 seconds
Started Jan 24 11:30:52 PM PST 24
Finished Jan 24 11:32:11 PM PST 24
Peak memory 199192 kb
Host smart-6276f544-1e2a-4283-8159-3626a4f0b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551553953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.551553953
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.216132394
Short name T763
Test name
Test status
Simulation time 512455552 ps
CPU time 27.55 seconds
Started Jan 24 11:47:45 PM PST 24
Finished Jan 24 11:48:14 PM PST 24
Peak memory 199104 kb
Host smart-57c2f968-ae99-48bf-b4e8-be54131985cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216132394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.216132394
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4144953335
Short name T339
Test name
Test status
Simulation time 169862832 ps
CPU time 1.59 seconds
Started Jan 25 01:39:18 AM PST 24
Finished Jan 25 01:39:21 AM PST 24
Peak memory 198504 kb
Host smart-6386c304-6285-4a2a-ae40-bb4392aed73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144953335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4144953335
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.849270133
Short name T641
Test name
Test status
Simulation time 95466145513 ps
CPU time 587.79 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:41:00 PM PST 24
Peak memory 199232 kb
Host smart-c356afcf-81ad-4171-a676-9c237b4c543a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849270133 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.849270133
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2941586694
Short name T441
Test name
Test status
Simulation time 140735053690 ps
CPU time 2324.85 seconds
Started Jan 25 05:21:47 AM PST 24
Finished Jan 25 06:00:38 AM PST 24
Peak memory 245384 kb
Host smart-7693a698-025f-499c-936f-d69726673864
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941586694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.2941586694
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.789813045
Short name T788
Test name
Test status
Simulation time 78768409 ps
CPU time 1 seconds
Started Jan 24 11:31:08 PM PST 24
Finished Jan 24 11:31:11 PM PST 24
Peak memory 195956 kb
Host smart-150d75e3-02e1-42be-83f3-6cde4880451d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789813045 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.789813045
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1676537597
Short name T54
Test name
Test status
Simulation time 39480239254 ps
CPU time 452.72 seconds
Started Jan 25 06:53:54 AM PST 24
Finished Jan 25 07:01:28 AM PST 24
Peak memory 199288 kb
Host smart-3e2677a3-a327-46ab-a2c2-3961ccd2bfb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676537597 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.1676537597
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2680521903
Short name T582
Test name
Test status
Simulation time 1242651813 ps
CPU time 42.83 seconds
Started Jan 25 01:20:27 AM PST 24
Finished Jan 25 01:21:11 AM PST 24
Peak memory 199188 kb
Host smart-5f358bd1-78c9-48bf-934e-c2156a4a9c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680521903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2680521903
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4180277692
Short name T611
Test name
Test status
Simulation time 13578616 ps
CPU time 0.57 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:31:12 PM PST 24
Peak memory 192568 kb
Host smart-1c9ed4c9-8bd2-4529-bcd7-6085b586bb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180277692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4180277692
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3014192114
Short name T678
Test name
Test status
Simulation time 1336512825 ps
CPU time 22.53 seconds
Started Jan 25 01:19:28 AM PST 24
Finished Jan 25 01:19:51 AM PST 24
Peak memory 207396 kb
Host smart-a7d29a27-7e0d-4c1e-b045-2dcf2828f222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014192114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3014192114
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1084618897
Short name T608
Test name
Test status
Simulation time 750919592 ps
CPU time 32.61 seconds
Started Jan 24 11:41:53 PM PST 24
Finished Jan 24 11:42:27 PM PST 24
Peak memory 199196 kb
Host smart-4477e8bc-ab76-406c-83df-e41a436e19fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084618897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1084618897
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3647265995
Short name T303
Test name
Test status
Simulation time 6680137083 ps
CPU time 90.52 seconds
Started Jan 24 11:31:08 PM PST 24
Finished Jan 24 11:32:42 PM PST 24
Peak memory 199228 kb
Host smart-dd7a837d-d566-4088-b47f-51a94ee80ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647265995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3647265995
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.720480811
Short name T565
Test name
Test status
Simulation time 5070843664 ps
CPU time 23.42 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:31:35 PM PST 24
Peak memory 199252 kb
Host smart-d2bc2fc6-4a3b-4299-b83f-2902db7bf835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720480811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.720480811
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3673588679
Short name T660
Test name
Test status
Simulation time 4854733927 ps
CPU time 55.71 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:32:07 PM PST 24
Peak memory 199212 kb
Host smart-5899b9b3-d2b1-4039-9881-10b51bbd0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673588679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3673588679
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3391114732
Short name T778
Test name
Test status
Simulation time 36639871 ps
CPU time 1.24 seconds
Started Jan 24 11:31:06 PM PST 24
Finished Jan 24 11:31:09 PM PST 24
Peak memory 198896 kb
Host smart-eb97fc0b-e752-47b2-809a-ad5e5f8442b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391114732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3391114732
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.318228698
Short name T357
Test name
Test status
Simulation time 128173339568 ps
CPU time 1461.87 seconds
Started Jan 25 06:14:05 AM PST 24
Finished Jan 25 06:38:42 AM PST 24
Peak memory 214760 kb
Host smart-b1e78564-fa2a-4a3a-bf62-c361e864a911
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318228698 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.318228698
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1374566673
Short name T288
Test name
Test status
Simulation time 159959142 ps
CPU time 1.01 seconds
Started Jan 24 11:31:08 PM PST 24
Finished Jan 24 11:31:12 PM PST 24
Peak memory 194744 kb
Host smart-859fea38-a38b-46dc-b876-79f74de01565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374566673 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1374566673
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2645187782
Short name T188
Test name
Test status
Simulation time 41116833168 ps
CPU time 466.62 seconds
Started Jan 24 11:31:08 PM PST 24
Finished Jan 24 11:38:58 PM PST 24
Peak memory 197916 kb
Host smart-0a397b65-c03c-4219-aa32-45b07599bfec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645187782 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2645187782
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2617325225
Short name T292
Test name
Test status
Simulation time 2254957544 ps
CPU time 22.11 seconds
Started Jan 25 02:12:00 AM PST 24
Finished Jan 25 02:12:25 AM PST 24
Peak memory 199252 kb
Host smart-5b63703e-4565-4ec7-901c-547eed79a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617325225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2617325225
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4230917501
Short name T387
Test name
Test status
Simulation time 35788009 ps
CPU time 0.57 seconds
Started Jan 24 11:31:26 PM PST 24
Finished Jan 24 11:31:27 PM PST 24
Peak memory 193556 kb
Host smart-31bd31bd-6660-4d91-ba74-3463a9a08e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230917501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4230917501
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.526412807
Short name T437
Test name
Test status
Simulation time 1440013057 ps
CPU time 12.9 seconds
Started Jan 24 11:31:29 PM PST 24
Finished Jan 24 11:31:45 PM PST 24
Peak memory 207356 kb
Host smart-a0aaa170-cd06-48bd-9592-a5189dd26365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526412807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.526412807
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2401401977
Short name T803
Test name
Test status
Simulation time 335098490 ps
CPU time 7.63 seconds
Started Jan 24 11:31:25 PM PST 24
Finished Jan 24 11:31:34 PM PST 24
Peak memory 199164 kb
Host smart-fde5f40d-e4c0-472c-92f2-f3c29ab1142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401401977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2401401977
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1641588849
Short name T385
Test name
Test status
Simulation time 3560615189 ps
CPU time 31.28 seconds
Started Jan 24 11:31:32 PM PST 24
Finished Jan 24 11:32:06 PM PST 24
Peak memory 199212 kb
Host smart-702f013e-76b1-46ab-8048-db3289b73a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641588849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1641588849
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2675378917
Short name T564
Test name
Test status
Simulation time 4423368093 ps
CPU time 71.65 seconds
Started Jan 24 11:31:26 PM PST 24
Finished Jan 24 11:32:39 PM PST 24
Peak memory 199200 kb
Host smart-d9a39e26-0b8b-437d-8013-3a74cccdd84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675378917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2675378917
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1125850172
Short name T796
Test name
Test status
Simulation time 4408063708 ps
CPU time 19 seconds
Started Jan 24 11:31:09 PM PST 24
Finished Jan 24 11:31:31 PM PST 24
Peak memory 199216 kb
Host smart-7c08e78b-1f97-4c0f-b58d-6dc8f96edf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125850172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1125850172
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.905066245
Short name T236
Test name
Test status
Simulation time 438635989 ps
CPU time 2.15 seconds
Started Jan 24 11:31:10 PM PST 24
Finished Jan 24 11:31:15 PM PST 24
Peak memory 198972 kb
Host smart-d1478ff5-00da-426a-a418-31eca806124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905066245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.905066245
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3405334048
Short name T233
Test name
Test status
Simulation time 34562631624 ps
CPU time 429.64 seconds
Started Jan 24 11:31:25 PM PST 24
Finished Jan 24 11:38:36 PM PST 24
Peak memory 199176 kb
Host smart-0a771d67-1314-4b09-8b71-44df184bb3ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405334048 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3405334048
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.2710504806
Short name T588
Test name
Test status
Simulation time 50716222068 ps
CPU time 682.57 seconds
Started Jan 24 11:31:26 PM PST 24
Finished Jan 24 11:42:49 PM PST 24
Peak memory 241680 kb
Host smart-6526a8ca-f0b2-4e4c-a222-915badc69c7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710504806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.2710504806
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1286520678
Short name T332
Test name
Test status
Simulation time 29913964 ps
CPU time 1 seconds
Started Jan 24 11:31:29 PM PST 24
Finished Jan 24 11:31:32 PM PST 24
Peak memory 197608 kb
Host smart-79b23ac9-92fb-43a7-bff7-66cc64570c24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286520678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1286520678
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3575260503
Short name T550
Test name
Test status
Simulation time 8055464225 ps
CPU time 410.2 seconds
Started Jan 24 11:31:27 PM PST 24
Finished Jan 24 11:38:18 PM PST 24
Peak memory 199144 kb
Host smart-7a8c3250-e887-4250-be03-f510620a77e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575260503 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.3575260503
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2565310205
Short name T186
Test name
Test status
Simulation time 2275721715 ps
CPU time 48.75 seconds
Started Jan 24 11:31:28 PM PST 24
Finished Jan 24 11:32:17 PM PST 24
Peak memory 199212 kb
Host smart-1fcdcd4c-1e74-443e-975d-5457af8a05cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565310205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2565310205
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1131994396
Short name T815
Test name
Test status
Simulation time 14286976 ps
CPU time 0.6 seconds
Started Jan 24 11:31:45 PM PST 24
Finished Jan 24 11:31:48 PM PST 24
Peak memory 192544 kb
Host smart-0a4710a7-7ae8-4d25-b731-76d4d5a94bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131994396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1131994396
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3120521708
Short name T369
Test name
Test status
Simulation time 1878939186 ps
CPU time 13.09 seconds
Started Jan 24 11:31:42 PM PST 24
Finished Jan 24 11:31:56 PM PST 24
Peak memory 199188 kb
Host smart-3af521fe-d312-416b-a61a-1c11cb7b25c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120521708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3120521708
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3105324392
Short name T606
Test name
Test status
Simulation time 3040742675 ps
CPU time 43.7 seconds
Started Jan 24 11:31:43 PM PST 24
Finished Jan 24 11:32:27 PM PST 24
Peak memory 199204 kb
Host smart-ca297a08-3a73-48e6-a56e-920d5039304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105324392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3105324392
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2741483119
Short name T693
Test name
Test status
Simulation time 3216160795 ps
CPU time 35.82 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:32:22 PM PST 24
Peak memory 199184 kb
Host smart-764558f4-8559-4be0-b760-31df87079a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741483119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2741483119
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1072519002
Short name T386
Test name
Test status
Simulation time 2547205926 ps
CPU time 131.23 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:33:57 PM PST 24
Peak memory 199212 kb
Host smart-9c0cc081-1a11-4ab6-8b26-c4ae51f25f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072519002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1072519002
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.5968933
Short name T105
Test name
Test status
Simulation time 2389000739 ps
CPU time 41.71 seconds
Started Jan 24 11:31:43 PM PST 24
Finished Jan 24 11:32:25 PM PST 24
Peak memory 199212 kb
Host smart-f52017eb-f9de-464c-af13-26b84a1b8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5968933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.5968933
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.853871887
Short name T38
Test name
Test status
Simulation time 271333115 ps
CPU time 3.22 seconds
Started Jan 24 11:31:26 PM PST 24
Finished Jan 24 11:31:30 PM PST 24
Peak memory 199132 kb
Host smart-d8c63208-96a8-432a-9680-9341f20a53d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853871887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.853871887
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3757181268
Short name T116
Test name
Test status
Simulation time 68446389583 ps
CPU time 699.83 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:43:26 PM PST 24
Peak memory 220628 kb
Host smart-74f12a43-6631-40a8-af30-63e332747828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757181268 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3757181268
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1721087553
Short name T627
Test name
Test status
Simulation time 53088216891 ps
CPU time 1019.63 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:48:46 PM PST 24
Peak memory 241128 kb
Host smart-260e500b-3ac7-423f-87db-3ea0947de80f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721087553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.1721087553
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4232539715
Short name T586
Test name
Test status
Simulation time 30267741 ps
CPU time 1.17 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:31:46 PM PST 24
Peak memory 197596 kb
Host smart-8e69304b-c34b-4f72-bea2-0afc594b3f41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232539715 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4232539715
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1879791524
Short name T269
Test name
Test status
Simulation time 68937354338 ps
CPU time 405.14 seconds
Started Jan 24 11:31:40 PM PST 24
Finished Jan 24 11:38:28 PM PST 24
Peak memory 199200 kb
Host smart-24b995ff-a3b8-488a-970f-5a0f3b622781
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879791524 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1879791524
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.370503987
Short name T630
Test name
Test status
Simulation time 1090024130 ps
CPU time 5.28 seconds
Started Jan 24 11:31:44 PM PST 24
Finished Jan 24 11:31:50 PM PST 24
Peak memory 199148 kb
Host smart-3989d0d4-d8ff-4b60-a9dc-d549a07eed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370503987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.370503987
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2849507999
Short name T726
Test name
Test status
Simulation time 41717756 ps
CPU time 0.57 seconds
Started Jan 24 11:31:59 PM PST 24
Finished Jan 24 11:32:02 PM PST 24
Peak memory 192596 kb
Host smart-35ba729e-708a-4aa2-8737-a58b55f9ac5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849507999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2849507999
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3854023506
Short name T790
Test name
Test status
Simulation time 90245753 ps
CPU time 1.83 seconds
Started Jan 24 11:32:03 PM PST 24
Finished Jan 24 11:32:07 PM PST 24
Peak memory 199064 kb
Host smart-11418ec8-250c-443e-940d-cd96dd8d36f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854023506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3854023506
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3185889751
Short name T425
Test name
Test status
Simulation time 1087553952 ps
CPU time 51.05 seconds
Started Jan 24 11:32:00 PM PST 24
Finished Jan 24 11:32:52 PM PST 24
Peak memory 199104 kb
Host smart-d9fc7e9a-3663-4a8d-a1f5-afa94115670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185889751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3185889751
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2590148597
Short name T505
Test name
Test status
Simulation time 1956847469 ps
CPU time 102.25 seconds
Started Jan 24 11:32:00 PM PST 24
Finished Jan 24 11:33:44 PM PST 24
Peak memory 199188 kb
Host smart-aa7816ec-fe88-424a-aebb-9044bbf6f6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590148597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2590148597
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1601071931
Short name T429
Test name
Test status
Simulation time 2164337304 ps
CPU time 34.32 seconds
Started Jan 24 11:32:01 PM PST 24
Finished Jan 24 11:32:37 PM PST 24
Peak memory 199236 kb
Host smart-c05a8403-c886-44ad-b893-81dd0e1ddb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601071931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1601071931
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1677339441
Short name T585
Test name
Test status
Simulation time 14306954519 ps
CPU time 43.27 seconds
Started Jan 24 11:32:01 PM PST 24
Finished Jan 24 11:32:46 PM PST 24
Peak memory 199164 kb
Host smart-2213ffa5-e659-4aec-8f03-53d2609f3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677339441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1677339441
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1041943303
Short name T487
Test name
Test status
Simulation time 352478716 ps
CPU time 4.15 seconds
Started Jan 24 11:31:46 PM PST 24
Finished Jan 24 11:31:51 PM PST 24
Peak memory 199180 kb
Host smart-4d5db646-a072-4a8e-9314-891b975da54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041943303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1041943303
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.698018615
Short name T478
Test name
Test status
Simulation time 95322991823 ps
CPU time 1538.22 seconds
Started Jan 24 11:31:59 PM PST 24
Finished Jan 24 11:57:39 PM PST 24
Peak memory 231036 kb
Host smart-9c4dd23b-2a8b-40b4-8807-d3f6c915cd1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698018615 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.698018615
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.3759135395
Short name T626
Test name
Test status
Simulation time 154980806707 ps
CPU time 2054.72 seconds
Started Jan 24 11:32:00 PM PST 24
Finished Jan 25 12:06:16 AM PST 24
Peak memory 256592 kb
Host smart-ee271fd3-17c4-467c-82ee-4e8a71372309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759135395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.3759135395
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3909284245
Short name T256
Test name
Test status
Simulation time 114465455 ps
CPU time 0.97 seconds
Started Jan 24 11:32:00 PM PST 24
Finished Jan 24 11:32:02 PM PST 24
Peak memory 197172 kb
Host smart-c1f3b174-632a-4df9-950b-e826b2096153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909284245 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3909284245
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3377889957
Short name T712
Test name
Test status
Simulation time 41730409924 ps
CPU time 503.55 seconds
Started Jan 24 11:31:58 PM PST 24
Finished Jan 24 11:40:24 PM PST 24
Peak memory 199212 kb
Host smart-705fe34a-4b3f-4501-89a3-a867a4c3f123
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377889957 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3377889957
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3031976857
Short name T392
Test name
Test status
Simulation time 884752432 ps
CPU time 15.08 seconds
Started Jan 24 11:32:01 PM PST 24
Finished Jan 24 11:32:18 PM PST 24
Peak memory 199104 kb
Host smart-a8ebc80f-e581-4476-ab85-61b152d2d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031976857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3031976857
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.969862558
Short name T351
Test name
Test status
Simulation time 34934186 ps
CPU time 0.58 seconds
Started Jan 24 11:26:00 PM PST 24
Finished Jan 24 11:26:06 PM PST 24
Peak memory 192564 kb
Host smart-2950ec91-3910-40f7-afd6-63c486764838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969862558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.969862558
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3629235176
Short name T298
Test name
Test status
Simulation time 452770918 ps
CPU time 12.11 seconds
Started Jan 24 11:25:54 PM PST 24
Finished Jan 24 11:26:13 PM PST 24
Peak memory 215572 kb
Host smart-a9a86481-5102-4f29-add6-9984310dd703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629235176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3629235176
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3899924170
Short name T431
Test name
Test status
Simulation time 10014809085 ps
CPU time 14.3 seconds
Started Jan 24 11:25:57 PM PST 24
Finished Jan 24 11:26:17 PM PST 24
Peak memory 199220 kb
Host smart-2d668041-4ab0-4454-8bb2-6b8e68dea514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899924170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3899924170
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3538713453
Short name T6
Test name
Test status
Simulation time 1726399735 ps
CPU time 93.15 seconds
Started Jan 24 11:25:58 PM PST 24
Finished Jan 24 11:27:36 PM PST 24
Peak memory 199148 kb
Host smart-dbf8366a-f671-4253-8878-5bae34795ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538713453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3538713453
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1561661433
Short name T558
Test name
Test status
Simulation time 17543492766 ps
CPU time 215.39 seconds
Started Jan 24 11:26:00 PM PST 24
Finished Jan 24 11:29:41 PM PST 24
Peak memory 199216 kb
Host smart-0820aa80-69f1-4a73-b0d4-b2b334af6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561661433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1561661433
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3808988167
Short name T572
Test name
Test status
Simulation time 3499700187 ps
CPU time 74.54 seconds
Started Jan 24 11:25:59 PM PST 24
Finished Jan 24 11:27:19 PM PST 24
Peak memory 199212 kb
Host smart-70a17475-72e8-4bb2-afed-e8a2397b5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808988167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3808988167
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3715070608
Short name T46
Test name
Test status
Simulation time 171974959 ps
CPU time 0.89 seconds
Started Jan 24 11:26:00 PM PST 24
Finished Jan 24 11:26:06 PM PST 24
Peak memory 216140 kb
Host smart-f0e336b5-f426-417f-8d51-32541eeaeb4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715070608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3715070608
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.192756970
Short name T809
Test name
Test status
Simulation time 159566678 ps
CPU time 3.64 seconds
Started Jan 24 11:25:53 PM PST 24
Finished Jan 24 11:26:04 PM PST 24
Peak memory 199104 kb
Host smart-3d39bd89-4cc4-40e1-82e0-51377fcfc4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192756970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.192756970
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1009402446
Short name T684
Test name
Test status
Simulation time 135559768397 ps
CPU time 1822.14 seconds
Started Jan 24 11:25:56 PM PST 24
Finished Jan 24 11:56:25 PM PST 24
Peak memory 227908 kb
Host smart-28c10785-3ff6-4bd7-9ee1-77a3b0f1421a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009402446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1009402446
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3703841550
Short name T391
Test name
Test status
Simulation time 45438392609 ps
CPU time 596.91 seconds
Started Jan 24 11:25:56 PM PST 24
Finished Jan 24 11:35:59 PM PST 24
Peak memory 240340 kb
Host smart-6cc0bea5-0eb9-4642-8501-e3e085dbcea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703841550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3703841550
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3686983804
Short name T739
Test name
Test status
Simulation time 55434629 ps
CPU time 1.19 seconds
Started Jan 24 11:25:58 PM PST 24
Finished Jan 24 11:26:04 PM PST 24
Peak memory 197640 kb
Host smart-64b14cb9-6406-488f-b975-b572fb936d26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686983804 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3686983804
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1683155677
Short name T219
Test name
Test status
Simulation time 39463410428 ps
CPU time 432.79 seconds
Started Jan 24 11:25:53 PM PST 24
Finished Jan 24 11:33:14 PM PST 24
Peak memory 199092 kb
Host smart-0eba4249-6d1c-45b7-af84-9026dde066fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683155677 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1683155677
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2840188241
Short name T350
Test name
Test status
Simulation time 1384507035 ps
CPU time 43.73 seconds
Started Jan 24 11:25:57 PM PST 24
Finished Jan 24 11:26:46 PM PST 24
Peak memory 199180 kb
Host smart-1c64ac97-fb6f-4959-a261-0bab3ea1d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840188241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2840188241
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3368535353
Short name T783
Test name
Test status
Simulation time 12147147 ps
CPU time 0.64 seconds
Started Jan 24 11:32:16 PM PST 24
Finished Jan 24 11:32:18 PM PST 24
Peak memory 192596 kb
Host smart-321c6506-21f7-4827-8aff-cc0cce9ccc95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368535353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3368535353
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1971300342
Short name T245
Test name
Test status
Simulation time 1539067653 ps
CPU time 10.94 seconds
Started Jan 24 11:32:17 PM PST 24
Finished Jan 24 11:32:29 PM PST 24
Peak memory 219476 kb
Host smart-8347e781-9170-495d-88f7-ceba7b040d7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971300342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1971300342
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.298017755
Short name T382
Test name
Test status
Simulation time 132097381 ps
CPU time 6.26 seconds
Started Jan 24 11:32:20 PM PST 24
Finished Jan 24 11:32:28 PM PST 24
Peak memory 199160 kb
Host smart-b222b2fb-883a-4e1e-95f3-45642ece8e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298017755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.298017755
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.609904048
Short name T300
Test name
Test status
Simulation time 829820002 ps
CPU time 41.54 seconds
Started Jan 24 11:32:17 PM PST 24
Finished Jan 24 11:32:59 PM PST 24
Peak memory 199160 kb
Host smart-a12e3b97-aa16-4879-b65f-98207fcc16f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609904048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.609904048
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.152198635
Short name T557
Test name
Test status
Simulation time 1562782947 ps
CPU time 80.87 seconds
Started Jan 24 11:32:20 PM PST 24
Finished Jan 24 11:33:43 PM PST 24
Peak memory 199160 kb
Host smart-d65baef8-9d0d-4e59-93c2-ea9bcb235e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152198635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.152198635
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3845583762
Short name T412
Test name
Test status
Simulation time 22169922524 ps
CPU time 85.26 seconds
Started Jan 24 11:32:15 PM PST 24
Finished Jan 24 11:33:42 PM PST 24
Peak memory 199212 kb
Host smart-49fba8d2-bf20-4cb3-bea0-0ca9dafcd331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845583762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3845583762
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3287043110
Short name T324
Test name
Test status
Simulation time 200094340 ps
CPU time 1.58 seconds
Started Jan 24 11:32:01 PM PST 24
Finished Jan 24 11:32:03 PM PST 24
Peak memory 198676 kb
Host smart-cb875aea-5fda-4ae2-9f2d-74756bc39a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287043110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3287043110
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3025758474
Short name T511
Test name
Test status
Simulation time 6656876291 ps
CPU time 165.87 seconds
Started Jan 24 11:32:18 PM PST 24
Finished Jan 24 11:35:06 PM PST 24
Peak memory 240172 kb
Host smart-27338d9b-64b1-4b33-a97e-4a5802faecd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025758474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3025758474
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.2425764001
Short name T104
Test name
Test status
Simulation time 70786807371 ps
CPU time 463.56 seconds
Started Jan 24 11:32:18 PM PST 24
Finished Jan 24 11:40:03 PM PST 24
Peak memory 215736 kb
Host smart-17576ac3-cbd3-45a1-8fe8-6d2cc3956c75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425764001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.2425764001
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2036719099
Short name T231
Test name
Test status
Simulation time 60045490 ps
CPU time 1.22 seconds
Started Jan 25 02:21:47 AM PST 24
Finished Jan 25 02:21:59 AM PST 24
Peak memory 197736 kb
Host smart-7ebe2a49-9d2e-4c7e-ba97-87b55e8c4b73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036719099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2036719099
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2930380513
Short name T594
Test name
Test status
Simulation time 8118435821 ps
CPU time 411.12 seconds
Started Jan 24 11:32:17 PM PST 24
Finished Jan 24 11:39:09 PM PST 24
Peak memory 199144 kb
Host smart-1e6ccccd-7b88-401f-9abf-4efe6b938000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930380513 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.2930380513
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.621581369
Short name T311
Test name
Test status
Simulation time 3201513345 ps
CPU time 51.01 seconds
Started Jan 24 11:32:16 PM PST 24
Finished Jan 24 11:33:08 PM PST 24
Peak memory 199244 kb
Host smart-2b7ecce8-7d31-426c-8589-a6429dd2e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621581369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.621581369
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.137685671
Short name T720
Test name
Test status
Simulation time 36937228 ps
CPU time 0.58 seconds
Started Jan 24 11:32:39 PM PST 24
Finished Jan 24 11:32:43 PM PST 24
Peak memory 192572 kb
Host smart-9c02196c-4812-4c5f-b040-b5bf16b6992f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137685671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.137685671
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1882548724
Short name T699
Test name
Test status
Simulation time 2048434448 ps
CPU time 55.83 seconds
Started Jan 25 02:24:02 AM PST 24
Finished Jan 25 02:24:58 AM PST 24
Peak memory 222756 kb
Host smart-35c4e093-1f11-49aa-aeb4-a44d7a32dabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882548724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1882548724
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3266214656
Short name T727
Test name
Test status
Simulation time 909925011 ps
CPU time 43.53 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:33:26 PM PST 24
Peak memory 199100 kb
Host smart-29612876-f977-4035-b159-3492448cb13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266214656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3266214656
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1951521482
Short name T551
Test name
Test status
Simulation time 610860907 ps
CPU time 7.52 seconds
Started Jan 24 11:32:39 PM PST 24
Finished Jan 24 11:32:50 PM PST 24
Peak memory 199140 kb
Host smart-e1499953-9a86-4542-afdd-059715b88583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951521482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1951521482
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1560106519
Short name T92
Test name
Test status
Simulation time 8986035671 ps
CPU time 56.81 seconds
Started Jan 24 11:32:42 PM PST 24
Finished Jan 24 11:33:41 PM PST 24
Peak memory 199248 kb
Host smart-2560158a-0cd6-4470-9a24-3cd859ed2035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560106519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1560106519
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3937397690
Short name T806
Test name
Test status
Simulation time 75071032602 ps
CPU time 74.61 seconds
Started Jan 24 11:32:20 PM PST 24
Finished Jan 24 11:33:36 PM PST 24
Peak memory 199224 kb
Host smart-472e1a66-44e7-4148-aae0-1c0b3cf6baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937397690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3937397690
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4044336473
Short name T371
Test name
Test status
Simulation time 180176799 ps
CPU time 2.57 seconds
Started Jan 24 11:32:17 PM PST 24
Finished Jan 24 11:32:21 PM PST 24
Peak memory 198736 kb
Host smart-7fedb699-6f57-4cb5-bd9b-1655e3d38780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044336473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4044336473
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2332808948
Short name T258
Test name
Test status
Simulation time 30122455901 ps
CPU time 437.4 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:40:00 PM PST 24
Peak memory 207432 kb
Host smart-ffddfff7-7972-48f5-bd79-7d9aa3629ca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332808948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2332808948
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2706104651
Short name T218
Test name
Test status
Simulation time 75883283640 ps
CPU time 1118.01 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:51:21 PM PST 24
Peak memory 215768 kb
Host smart-bd6c35cd-cdd5-446f-a953-c928d7265d0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706104651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.2706104651
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1365441184
Short name T211
Test name
Test status
Simulation time 53034927 ps
CPU time 0.96 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:32:43 PM PST 24
Peak memory 197180 kb
Host smart-ee9e20ef-5e18-4c53-89cc-38962ed90aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365441184 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1365441184
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4100680546
Short name T221
Test name
Test status
Simulation time 102262019652 ps
CPU time 455.94 seconds
Started Jan 24 11:32:36 PM PST 24
Finished Jan 24 11:40:15 PM PST 24
Peak memory 199176 kb
Host smart-36e926b1-517d-44d8-823b-dca4dfe8f3c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100680546 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.4100680546
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1683682542
Short name T749
Test name
Test status
Simulation time 512110538 ps
CPU time 2.17 seconds
Started Jan 24 11:32:36 PM PST 24
Finished Jan 24 11:32:41 PM PST 24
Peak memory 198692 kb
Host smart-a954d399-4dc7-4c4e-a089-dc03e995de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683682542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1683682542
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4085088755
Short name T204
Test name
Test status
Simulation time 15156560 ps
CPU time 0.64 seconds
Started Jan 24 11:33:00 PM PST 24
Finished Jan 24 11:33:04 PM PST 24
Peak memory 192596 kb
Host smart-2c046b41-6703-4f43-89d5-6392a3507e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085088755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4085088755
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1970069227
Short name T253
Test name
Test status
Simulation time 895497232 ps
CPU time 13.42 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:32:56 PM PST 24
Peak memory 199120 kb
Host smart-75483267-807e-470d-88f8-9362147f16db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970069227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1970069227
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2848203162
Short name T331
Test name
Test status
Simulation time 1928850900 ps
CPU time 36.03 seconds
Started Jan 24 11:32:36 PM PST 24
Finished Jan 24 11:33:15 PM PST 24
Peak memory 199084 kb
Host smart-e50a933f-5337-405a-856e-cc4b7ae4d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848203162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2848203162
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.431328599
Short name T824
Test name
Test status
Simulation time 3925284956 ps
CPU time 99.59 seconds
Started Jan 24 11:32:39 PM PST 24
Finished Jan 24 11:34:23 PM PST 24
Peak memory 199196 kb
Host smart-15fe6e0e-189f-484c-a812-8e11dca3d652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431328599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.431328599
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3575824421
Short name T750
Test name
Test status
Simulation time 8866403743 ps
CPU time 118.12 seconds
Started Jan 24 11:32:58 PM PST 24
Finished Jan 24 11:34:56 PM PST 24
Peak memory 199196 kb
Host smart-d6343b45-8331-4685-a447-112cd2a798b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575824421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3575824421
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.692429480
Short name T482
Test name
Test status
Simulation time 13836774510 ps
CPU time 61.85 seconds
Started Jan 24 11:32:38 PM PST 24
Finished Jan 24 11:33:44 PM PST 24
Peak memory 199248 kb
Host smart-917dc53f-99ff-43b0-b2e3-031cbae26580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692429480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.692429480
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1074699523
Short name T614
Test name
Test status
Simulation time 1020811128 ps
CPU time 3.64 seconds
Started Jan 24 11:32:37 PM PST 24
Finished Jan 24 11:32:43 PM PST 24
Peak memory 199064 kb
Host smart-a0e00c51-ac90-4000-8431-b6e509acd7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074699523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1074699523
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1080193636
Short name T424
Test name
Test status
Simulation time 10674395150 ps
CPU time 439.83 seconds
Started Jan 24 11:32:57 PM PST 24
Finished Jan 24 11:40:17 PM PST 24
Peak memory 226856 kb
Host smart-81621c16-c16d-4541-b3ae-a9f41627db26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080193636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1080193636
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.4147091011
Short name T126
Test name
Test status
Simulation time 427844406290 ps
CPU time 1595.59 seconds
Started Jan 24 11:32:57 PM PST 24
Finished Jan 24 11:59:33 PM PST 24
Peak memory 256224 kb
Host smart-40716712-863f-44ef-825e-d7d997fdb8d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147091011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.4147091011
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.71203662
Short name T287
Test name
Test status
Simulation time 104319234 ps
CPU time 1.07 seconds
Started Jan 24 11:33:01 PM PST 24
Finished Jan 24 11:33:09 PM PST 24
Peak memory 197480 kb
Host smart-94849833-f75d-45c4-ab07-96d855111c9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71203662 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_hmac_vectors.71203662
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3351085004
Short name T447
Test name
Test status
Simulation time 27358801505 ps
CPU time 449.79 seconds
Started Jan 24 11:33:00 PM PST 24
Finished Jan 24 11:40:32 PM PST 24
Peak memory 199196 kb
Host smart-49824997-315f-4175-92fe-8806899826dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351085004 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.3351085004
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1920306328
Short name T728
Test name
Test status
Simulation time 236162522 ps
CPU time 3.79 seconds
Started Jan 24 11:33:00 PM PST 24
Finished Jan 24 11:33:06 PM PST 24
Peak memory 199148 kb
Host smart-089c90b5-a1ab-43ae-92e0-e748004cd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920306328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1920306328
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.781410000
Short name T214
Test name
Test status
Simulation time 23184305 ps
CPU time 0.57 seconds
Started Jan 24 11:33:19 PM PST 24
Finished Jan 24 11:33:29 PM PST 24
Peak memory 193512 kb
Host smart-ebc79cbe-a106-48b7-bdf2-d51b23d32085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781410000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.781410000
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3713627583
Short name T212
Test name
Test status
Simulation time 8353833222 ps
CPU time 54.11 seconds
Started Jan 24 11:32:57 PM PST 24
Finished Jan 24 11:33:52 PM PST 24
Peak memory 228896 kb
Host smart-6f8a1fca-c4fb-4661-9f73-4415d09cc06b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713627583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3713627583
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3451013184
Short name T555
Test name
Test status
Simulation time 325037593 ps
CPU time 6.44 seconds
Started Jan 24 11:33:17 PM PST 24
Finished Jan 24 11:33:33 PM PST 24
Peak memory 199148 kb
Host smart-c3635198-e2aa-42c3-9f71-70e06730b68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451013184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3451013184
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.241810381
Short name T10
Test name
Test status
Simulation time 27131879532 ps
CPU time 89.23 seconds
Started Jan 24 11:33:19 PM PST 24
Finished Jan 24 11:34:57 PM PST 24
Peak memory 199204 kb
Host smart-f8d0185a-eb73-4c2a-bb46-d33f92c9ac32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241810381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.241810381
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1776568593
Short name T208
Test name
Test status
Simulation time 2273663859 ps
CPU time 38.45 seconds
Started Jan 24 11:33:21 PM PST 24
Finished Jan 24 11:34:07 PM PST 24
Peak memory 199184 kb
Host smart-e75f3ef3-4ffc-4b43-9f74-52a5fac867c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776568593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1776568593
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3413664534
Short name T456
Test name
Test status
Simulation time 37728582355 ps
CPU time 96.45 seconds
Started Jan 24 11:32:57 PM PST 24
Finished Jan 24 11:34:34 PM PST 24
Peak memory 199244 kb
Host smart-f21c6428-9cf0-458b-be70-5e91c1456840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413664534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3413664534
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2871416336
Short name T793
Test name
Test status
Simulation time 171151128 ps
CPU time 1.33 seconds
Started Jan 24 11:32:58 PM PST 24
Finished Jan 24 11:33:00 PM PST 24
Peak memory 198488 kb
Host smart-09c39aa7-24e7-496d-b7a8-93ec8d7a3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871416336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2871416336
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2858376838
Short name T488
Test name
Test status
Simulation time 177632995099 ps
CPU time 740.39 seconds
Started Jan 24 11:33:18 PM PST 24
Finished Jan 24 11:45:48 PM PST 24
Peak memory 199276 kb
Host smart-4fa0dfbc-db36-401c-b965-a3bae497ce11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858376838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2858376838
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.561594162
Short name T410
Test name
Test status
Simulation time 293312233604 ps
CPU time 1075.06 seconds
Started Jan 24 11:33:18 PM PST 24
Finished Jan 24 11:51:22 PM PST 24
Peak memory 240936 kb
Host smart-3e4bffbe-17e5-4a3b-8139-6c5b88a6d6b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561594162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.561594162
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2111099641
Short name T647
Test name
Test status
Simulation time 66388204 ps
CPU time 1.36 seconds
Started Jan 24 11:33:17 PM PST 24
Finished Jan 24 11:33:28 PM PST 24
Peak memory 197164 kb
Host smart-cb05796c-4b6d-4aac-98b8-dc9ef791705d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111099641 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2111099641
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1544197666
Short name T266
Test name
Test status
Simulation time 2106002733 ps
CPU time 26.26 seconds
Started Jan 24 11:33:19 PM PST 24
Finished Jan 24 11:33:54 PM PST 24
Peak memory 199148 kb
Host smart-a523e675-8462-49ae-97ef-f511dc8db7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544197666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1544197666
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2737671652
Short name T541
Test name
Test status
Simulation time 36413731 ps
CPU time 0.54 seconds
Started Jan 24 11:33:33 PM PST 24
Finished Jan 24 11:33:36 PM PST 24
Peak memory 193572 kb
Host smart-bf6de9bf-2bee-4831-93bc-4dc515e05ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737671652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2737671652
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3630457046
Short name T33
Test name
Test status
Simulation time 7424849055 ps
CPU time 44.49 seconds
Started Jan 24 11:33:17 PM PST 24
Finished Jan 24 11:34:11 PM PST 24
Peak memory 228912 kb
Host smart-90ae70aa-ea93-419b-a90d-75f2267ef3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630457046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3630457046
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2071935522
Short name T617
Test name
Test status
Simulation time 2760814067 ps
CPU time 32.95 seconds
Started Jan 24 11:33:17 PM PST 24
Finished Jan 24 11:33:59 PM PST 24
Peak memory 199220 kb
Host smart-9f865f49-630e-4e75-b6db-d681622f3de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071935522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2071935522
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3457563155
Short name T366
Test name
Test status
Simulation time 2321952286 ps
CPU time 64.53 seconds
Started Jan 24 11:33:19 PM PST 24
Finished Jan 24 11:34:33 PM PST 24
Peak memory 199208 kb
Host smart-1a7f4da4-5e7f-46f8-96d2-b7233253c5b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457563155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3457563155
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1490853399
Short name T400
Test name
Test status
Simulation time 5775078383 ps
CPU time 94.98 seconds
Started Jan 24 11:33:18 PM PST 24
Finished Jan 24 11:35:02 PM PST 24
Peak memory 199208 kb
Host smart-1972dd6e-c52b-42c7-841e-e5d515cb4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490853399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1490853399
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4025858503
Short name T618
Test name
Test status
Simulation time 44014711108 ps
CPU time 64.44 seconds
Started Jan 24 11:33:19 PM PST 24
Finished Jan 24 11:34:32 PM PST 24
Peak memory 199172 kb
Host smart-fca2e8ba-58ec-4258-bfee-c27180fc3186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025858503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4025858503
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3438851144
Short name T384
Test name
Test status
Simulation time 153314446 ps
CPU time 2.16 seconds
Started Jan 24 11:33:16 PM PST 24
Finished Jan 24 11:33:29 PM PST 24
Peak memory 199076 kb
Host smart-5948f8bf-ce97-4a61-948f-92501d0015cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438851144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3438851144
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2172276468
Short name T668
Test name
Test status
Simulation time 16400034876 ps
CPU time 815.89 seconds
Started Jan 24 11:33:20 PM PST 24
Finished Jan 24 11:47:04 PM PST 24
Peak memory 199232 kb
Host smart-af138884-2ecc-474c-9581-d55ad1ebe49a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172276468 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2172276468
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1729553848
Short name T276
Test name
Test status
Simulation time 57840899 ps
CPU time 1.05 seconds
Started Jan 24 11:33:21 PM PST 24
Finished Jan 24 11:33:29 PM PST 24
Peak memory 196744 kb
Host smart-eec78061-c6c6-40d5-b5c9-bf9468ce4eb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729553848 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1729553848
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.437613630
Short name T189
Test name
Test status
Simulation time 32412323101 ps
CPU time 394.85 seconds
Started Jan 24 11:33:20 PM PST 24
Finished Jan 24 11:40:03 PM PST 24
Peak memory 199140 kb
Host smart-f1f7b3d9-e0f6-4958-828c-2bec9c904bb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437613630 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.437613630
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1532253608
Short name T776
Test name
Test status
Simulation time 10980968416 ps
CPU time 64.75 seconds
Started Jan 24 11:33:17 PM PST 24
Finished Jan 24 11:34:31 PM PST 24
Peak memory 199228 kb
Host smart-b41cb575-c688-486f-9847-b5ae1d9e30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532253608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1532253608
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.325002648
Short name T43
Test name
Test status
Simulation time 34336780 ps
CPU time 0.57 seconds
Started Jan 25 05:28:16 AM PST 24
Finished Jan 25 05:28:18 AM PST 24
Peak memory 192704 kb
Host smart-394d5b5c-6e37-4283-bb31-c01b656b297a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325002648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.325002648
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.699417056
Short name T649
Test name
Test status
Simulation time 6293026703 ps
CPU time 60.95 seconds
Started Jan 24 11:33:37 PM PST 24
Finished Jan 24 11:34:39 PM PST 24
Peak memory 230996 kb
Host smart-4bb69a06-e6bd-4b90-8670-e5bf2bb06bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699417056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.699417056
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1963159637
Short name T345
Test name
Test status
Simulation time 3250701246 ps
CPU time 43.24 seconds
Started Jan 24 11:33:38 PM PST 24
Finished Jan 24 11:34:22 PM PST 24
Peak memory 199188 kb
Host smart-98441b0e-b2ea-403b-927e-f97ce781abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963159637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1963159637
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1093755226
Short name T801
Test name
Test status
Simulation time 34776353485 ps
CPU time 117.78 seconds
Started Jan 24 11:33:35 PM PST 24
Finished Jan 24 11:35:35 PM PST 24
Peak memory 199188 kb
Host smart-d678d637-f9f3-430b-81bc-5d7f35c6e954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093755226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1093755226
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3820356719
Short name T812
Test name
Test status
Simulation time 1926371071 ps
CPU time 49.84 seconds
Started Jan 24 11:33:35 PM PST 24
Finished Jan 24 11:34:26 PM PST 24
Peak memory 199096 kb
Host smart-a4cd50ca-edea-46a2-9786-85108b6aa9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820356719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3820356719
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.983946870
Short name T469
Test name
Test status
Simulation time 578222507 ps
CPU time 7.18 seconds
Started Jan 24 11:33:35 PM PST 24
Finished Jan 24 11:33:44 PM PST 24
Peak memory 198888 kb
Host smart-a43cf73c-d441-4758-a9a1-190b4d6f128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983946870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.983946870
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1797621957
Short name T194
Test name
Test status
Simulation time 131379667 ps
CPU time 0.81 seconds
Started Jan 24 11:33:36 PM PST 24
Finished Jan 24 11:33:38 PM PST 24
Peak memory 195532 kb
Host smart-3aefa976-8e05-4d3a-9c76-b6a49be6bd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797621957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1797621957
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1761427363
Short name T377
Test name
Test status
Simulation time 258625834768 ps
CPU time 1094.75 seconds
Started Jan 25 01:06:02 AM PST 24
Finished Jan 25 01:24:18 AM PST 24
Peak memory 199232 kb
Host smart-f21923ad-97d9-4247-a621-0b11d32d7f74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761427363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1761427363
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.391100515
Short name T113
Test name
Test status
Simulation time 113964011576 ps
CPU time 6042.4 seconds
Started Jan 24 11:33:51 PM PST 24
Finished Jan 25 01:14:36 AM PST 24
Peak memory 262400 kb
Host smart-0c572937-f704-4211-a888-48c83980ef99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391100515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.391100515
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2702824703
Short name T644
Test name
Test status
Simulation time 276486530 ps
CPU time 1.24 seconds
Started Jan 24 11:33:50 PM PST 24
Finished Jan 24 11:33:54 PM PST 24
Peak memory 197628 kb
Host smart-e95442e0-607e-4886-bec0-34dba5efc099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702824703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2702824703
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.765715104
Short name T209
Test name
Test status
Simulation time 118100228635 ps
CPU time 478.93 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:41:55 PM PST 24
Peak memory 199140 kb
Host smart-f8e80b91-8e70-4458-84a1-15e9f8f1359d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765715104 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_sha_vectors.765715104
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2426396750
Short name T139
Test name
Test status
Simulation time 1385197768 ps
CPU time 51.88 seconds
Started Jan 24 11:33:34 PM PST 24
Finished Jan 24 11:34:28 PM PST 24
Peak memory 199148 kb
Host smart-02e3c43e-a4c8-4162-9b1c-71914e34c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426396750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2426396750
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.133928331
Short name T544
Test name
Test status
Simulation time 17669679 ps
CPU time 0.61 seconds
Started Jan 24 11:34:08 PM PST 24
Finished Jan 24 11:34:11 PM PST 24
Peak memory 193568 kb
Host smart-91a6b288-f133-4426-96eb-71cc989a3728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133928331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.133928331
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3677967805
Short name T397
Test name
Test status
Simulation time 668436940 ps
CPU time 6.21 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:34:04 PM PST 24
Peak memory 207352 kb
Host smart-16627194-7de2-4ab3-b9fd-308f11ee94b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677967805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3677967805
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.254878226
Short name T747
Test name
Test status
Simulation time 1614600134 ps
CPU time 21.5 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:34:19 PM PST 24
Peak memory 199168 kb
Host smart-7a574c0c-b65d-46bc-bd10-000bb07a2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254878226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.254878226
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2724890483
Short name T639
Test name
Test status
Simulation time 2165674966 ps
CPU time 110.75 seconds
Started Jan 24 11:33:52 PM PST 24
Finished Jan 24 11:35:46 PM PST 24
Peak memory 199204 kb
Host smart-01222153-bcc5-473f-9a13-f084fa962c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724890483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2724890483
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1924240644
Short name T631
Test name
Test status
Simulation time 2593953938 ps
CPU time 42.87 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:34:39 PM PST 24
Peak memory 199196 kb
Host smart-1856e52f-8057-4981-a62f-0bad6919b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924240644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1924240644
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3711577141
Short name T465
Test name
Test status
Simulation time 671947730 ps
CPU time 31.29 seconds
Started Jan 24 11:33:54 PM PST 24
Finished Jan 24 11:34:30 PM PST 24
Peak memory 199128 kb
Host smart-fe317543-2f3b-44dc-9eb7-0b7e49f1389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711577141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3711577141
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3602507384
Short name T202
Test name
Test status
Simulation time 972209377 ps
CPU time 2.36 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:34:00 PM PST 24
Peak memory 199124 kb
Host smart-7728dc43-5548-45f9-82ee-eebeeac2a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602507384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3602507384
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1603203259
Short name T722
Test name
Test status
Simulation time 60216239452 ps
CPU time 892.92 seconds
Started Jan 25 02:01:17 AM PST 24
Finished Jan 25 02:16:12 AM PST 24
Peak memory 199244 kb
Host smart-bdb4eb8c-93a3-4549-ac8d-be1eaaa31ef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603203259 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1603203259
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.4100278442
Short name T515
Test name
Test status
Simulation time 683847978326 ps
CPU time 1767.57 seconds
Started Jan 24 11:34:07 PM PST 24
Finished Jan 25 12:03:38 AM PST 24
Peak memory 248548 kb
Host smart-3d730e34-9e1b-4f67-bd6c-6ca52e9683df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100278442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.4100278442
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2638947156
Short name T821
Test name
Test status
Simulation time 32581968 ps
CPU time 1.09 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:33:58 PM PST 24
Peak memory 197316 kb
Host smart-c3866a0f-5d65-4839-a293-bb5fa9405d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638947156 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2638947156
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.490940307
Short name T420
Test name
Test status
Simulation time 38264227868 ps
CPU time 405.47 seconds
Started Jan 24 11:33:53 PM PST 24
Finished Jan 24 11:40:42 PM PST 24
Peak memory 199040 kb
Host smart-09795369-9b3f-4e9d-9c22-075767e8297b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490940307 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.490940307
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2386862530
Short name T786
Test name
Test status
Simulation time 1635006216 ps
CPU time 13.05 seconds
Started Jan 24 11:33:52 PM PST 24
Finished Jan 24 11:34:07 PM PST 24
Peak memory 199152 kb
Host smart-d68804fd-b1ed-4381-8e39-3a217c9f4716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386862530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2386862530
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.736156298
Short name T498
Test name
Test status
Simulation time 13025146 ps
CPU time 0.57 seconds
Started Jan 24 11:34:32 PM PST 24
Finished Jan 24 11:34:34 PM PST 24
Peak memory 193560 kb
Host smart-f5aecc85-b685-43c0-a6f0-c20d00845907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736156298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.736156298
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.93379069
Short name T360
Test name
Test status
Simulation time 122371031 ps
CPU time 4.96 seconds
Started Jan 24 11:34:05 PM PST 24
Finished Jan 24 11:34:12 PM PST 24
Peak memory 206572 kb
Host smart-89f9bc42-657a-40d8-a8a0-24ca3d7c53a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93379069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.93379069
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2563530556
Short name T468
Test name
Test status
Simulation time 2022726303 ps
CPU time 18.46 seconds
Started Jan 24 11:34:10 PM PST 24
Finished Jan 24 11:34:30 PM PST 24
Peak memory 199120 kb
Host smart-090106b7-6418-4526-818a-cbf922918dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563530556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2563530556
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1507287955
Short name T523
Test name
Test status
Simulation time 6278555610 ps
CPU time 80.07 seconds
Started Jan 24 11:34:07 PM PST 24
Finished Jan 24 11:35:29 PM PST 24
Peak memory 199168 kb
Host smart-ea07c28a-8ff1-487c-94e0-d7c20f6aa343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507287955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1507287955
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1254226760
Short name T308
Test name
Test status
Simulation time 18364531997 ps
CPU time 51.31 seconds
Started Jan 24 11:34:32 PM PST 24
Finished Jan 24 11:35:25 PM PST 24
Peak memory 199252 kb
Host smart-fa582b4e-ba38-4bc1-bf96-3a39172c9379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254226760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1254226760
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2511702884
Short name T731
Test name
Test status
Simulation time 16858000971 ps
CPU time 58.38 seconds
Started Jan 24 11:34:07 PM PST 24
Finished Jan 24 11:35:08 PM PST 24
Peak memory 199212 kb
Host smart-bda468fb-dc9f-4c77-818d-a5229a72815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511702884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2511702884
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3287018367
Short name T567
Test name
Test status
Simulation time 79854934 ps
CPU time 1.32 seconds
Started Jan 25 01:10:43 AM PST 24
Finished Jan 25 01:10:46 AM PST 24
Peak memory 199160 kb
Host smart-014acf87-69b7-453b-9f46-96f9f8145040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287018367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3287018367
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3634501619
Short name T629
Test name
Test status
Simulation time 53345263306 ps
CPU time 622.45 seconds
Started Jan 24 11:34:33 PM PST 24
Finished Jan 24 11:44:57 PM PST 24
Peak memory 199148 kb
Host smart-fb22e431-a93f-48fc-bbcd-1f899a443f64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634501619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3634501619
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2110542687
Short name T651
Test name
Test status
Simulation time 353257373 ps
CPU time 0.94 seconds
Started Jan 24 11:34:30 PM PST 24
Finished Jan 24 11:34:33 PM PST 24
Peak memory 195988 kb
Host smart-babd945e-42a8-47fc-9797-986f10dcf09a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110542687 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2110542687
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3956292396
Short name T418
Test name
Test status
Simulation time 30858323732 ps
CPU time 423.18 seconds
Started Jan 24 11:34:31 PM PST 24
Finished Jan 24 11:41:35 PM PST 24
Peak memory 199156 kb
Host smart-fc7dcc56-891a-460e-b542-c4a3884fee38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956292396 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3956292396
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3917105736
Short name T224
Test name
Test status
Simulation time 18058754595 ps
CPU time 72.79 seconds
Started Jan 24 11:34:30 PM PST 24
Finished Jan 24 11:35:44 PM PST 24
Peak memory 199212 kb
Host smart-a299f76b-8d3d-4ee6-b65f-619e405fde04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917105736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3917105736
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2866453172
Short name T299
Test name
Test status
Simulation time 187459197 ps
CPU time 0.63 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:34:56 PM PST 24
Peak memory 192636 kb
Host smart-f95d578c-42f4-4e70-8fde-ce01dff7b4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866453172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2866453172
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2908862844
Short name T355
Test name
Test status
Simulation time 4328129514 ps
CPU time 34.81 seconds
Started Jan 24 11:34:50 PM PST 24
Finished Jan 24 11:35:27 PM PST 24
Peak memory 215340 kb
Host smart-57be3ef8-1488-4221-9d88-57091e2f526d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908862844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2908862844
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1627231284
Short name T132
Test name
Test status
Simulation time 3546443140 ps
CPU time 12.73 seconds
Started Jan 24 11:34:52 PM PST 24
Finished Jan 24 11:35:06 PM PST 24
Peak memory 199252 kb
Host smart-a87d9dd7-209b-4a49-baa7-0fb4a05c397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627231284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1627231284
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3964325272
Short name T682
Test name
Test status
Simulation time 16654208002 ps
CPU time 45.49 seconds
Started Jan 24 11:34:52 PM PST 24
Finished Jan 24 11:35:39 PM PST 24
Peak memory 199172 kb
Host smart-b915bc3c-f998-43ae-a83d-d04ad3623502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964325272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3964325272
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3093792872
Short name T448
Test name
Test status
Simulation time 1959713838 ps
CPU time 25.55 seconds
Started Jan 24 11:34:57 PM PST 24
Finished Jan 24 11:35:23 PM PST 24
Peak memory 199148 kb
Host smart-4e5b7dc6-1d74-4823-8227-f43c1842f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093792872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3093792872
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2660208496
Short name T646
Test name
Test status
Simulation time 2387024994 ps
CPU time 13.56 seconds
Started Jan 24 11:34:28 PM PST 24
Finished Jan 24 11:34:43 PM PST 24
Peak memory 199200 kb
Host smart-0305c05a-b298-41fc-b5a1-1e526bebff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660208496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2660208496
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2235498060
Short name T695
Test name
Test status
Simulation time 431527521 ps
CPU time 3.24 seconds
Started Jan 24 11:34:33 PM PST 24
Finished Jan 24 11:34:37 PM PST 24
Peak memory 198996 kb
Host smart-644dd90f-3233-4c59-8a41-2bc294bd69a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235498060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2235498060
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.895930068
Short name T756
Test name
Test status
Simulation time 246880720621 ps
CPU time 724.29 seconds
Started Jan 24 11:34:55 PM PST 24
Finished Jan 24 11:47:02 PM PST 24
Peak memory 199272 kb
Host smart-a59b566e-c4ea-45da-88c2-844127311726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895930068 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.895930068
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.2658121860
Short name T584
Test name
Test status
Simulation time 35719337453 ps
CPU time 1201.87 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:54:57 PM PST 24
Peak memory 200312 kb
Host smart-3db46460-f3fb-411d-9654-0f9686165390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658121860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.2658121860
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1350040547
Short name T243
Test name
Test status
Simulation time 183968514 ps
CPU time 0.99 seconds
Started Jan 24 11:34:55 PM PST 24
Finished Jan 24 11:34:58 PM PST 24
Peak memory 196232 kb
Host smart-643b167b-53a9-4e67-b69c-ff5fcd589f25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350040547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1350040547
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3391279737
Short name T686
Test name
Test status
Simulation time 80974312497 ps
CPU time 465.11 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:42:41 PM PST 24
Peak memory 198924 kb
Host smart-d0befb8d-4e9a-4550-8edd-7c11708b361b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391279737 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.3391279737
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1396391096
Short name T820
Test name
Test status
Simulation time 5141744911 ps
CPU time 53.51 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:35:49 PM PST 24
Peak memory 199216 kb
Host smart-29b7cfbe-b699-4ff8-94b5-fa39d9f60de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396391096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1396391096
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3099838419
Short name T403
Test name
Test status
Simulation time 12177236 ps
CPU time 0.56 seconds
Started Jan 24 11:35:11 PM PST 24
Finished Jan 24 11:35:13 PM PST 24
Peak memory 193552 kb
Host smart-2c8f939d-fb2d-4e97-a630-795c9bfd9d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099838419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3099838419
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.28497721
Short name T628
Test name
Test status
Simulation time 3023530053 ps
CPU time 35.53 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:35:32 PM PST 24
Peak memory 219864 kb
Host smart-e3dd037a-fdfb-425a-a7d0-ef4439d78377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28497721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.28497721
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3376556702
Short name T293
Test name
Test status
Simulation time 5723074067 ps
CPU time 44.93 seconds
Started Jan 24 11:34:54 PM PST 24
Finished Jan 24 11:35:40 PM PST 24
Peak memory 199172 kb
Host smart-bfd1eac0-07bb-454d-b7d3-01014836bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376556702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3376556702
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1608042838
Short name T794
Test name
Test status
Simulation time 207602116 ps
CPU time 10.86 seconds
Started Jan 24 11:34:52 PM PST 24
Finished Jan 24 11:35:04 PM PST 24
Peak memory 198960 kb
Host smart-5d342872-f9d5-4a4c-b9bd-35894d447324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608042838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1608042838
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1351406125
Short name T561
Test name
Test status
Simulation time 9745674017 ps
CPU time 126.65 seconds
Started Jan 24 11:35:18 PM PST 24
Finished Jan 24 11:37:27 PM PST 24
Peak memory 199248 kb
Host smart-c196d43d-3b34-4b90-b7e0-22d5cfbcb679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351406125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1351406125
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1341473768
Short name T342
Test name
Test status
Simulation time 263635466 ps
CPU time 13.16 seconds
Started Jan 24 11:34:53 PM PST 24
Finished Jan 24 11:35:07 PM PST 24
Peak memory 199144 kb
Host smart-37361c0a-69a6-4b05-b357-e41aa3fdc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341473768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1341473768
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1727824523
Short name T228
Test name
Test status
Simulation time 1255789783 ps
CPU time 4.21 seconds
Started Jan 24 11:34:56 PM PST 24
Finished Jan 24 11:35:02 PM PST 24
Peak memory 199132 kb
Host smart-5cf1d142-69ee-4499-b9bd-d23c5eb465b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727824523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1727824523
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4286180813
Short name T195
Test name
Test status
Simulation time 14800475488 ps
CPU time 721.89 seconds
Started Jan 24 11:35:16 PM PST 24
Finished Jan 24 11:47:19 PM PST 24
Peak memory 215656 kb
Host smart-8cd62d93-afc6-4e90-b1ad-3a75d2b66c5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286180813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4286180813
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3590103532
Short name T818
Test name
Test status
Simulation time 759981326686 ps
CPU time 1218.73 seconds
Started Jan 24 11:35:18 PM PST 24
Finished Jan 24 11:55:38 PM PST 24
Peak memory 263996 kb
Host smart-4fbe2502-bca8-4619-9a68-3c0193d57435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590103532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.3590103532
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4173857998
Short name T738
Test name
Test status
Simulation time 277096804 ps
CPU time 0.88 seconds
Started Jan 24 11:35:18 PM PST 24
Finished Jan 24 11:35:20 PM PST 24
Peak memory 196964 kb
Host smart-6ad8e48d-2f38-44fe-be76-41e2b67de5e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173857998 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.4173857998
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3556720014
Short name T596
Test name
Test status
Simulation time 6907496649 ps
CPU time 84.98 seconds
Started Jan 24 11:35:10 PM PST 24
Finished Jan 24 11:36:36 PM PST 24
Peak memory 199232 kb
Host smart-e46db19e-4594-49c3-a391-71c8ae7960a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556720014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3556720014
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3576051691
Short name T531
Test name
Test status
Simulation time 12969083 ps
CPU time 0.58 seconds
Started Jan 24 11:26:20 PM PST 24
Finished Jan 24 11:26:24 PM PST 24
Peak memory 192572 kb
Host smart-e762d76f-1f8b-4570-9e8c-efe6d1077ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576051691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3576051691
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2310499953
Short name T222
Test name
Test status
Simulation time 3902988987 ps
CPU time 28.02 seconds
Started Jan 24 11:26:17 PM PST 24
Finished Jan 24 11:26:49 PM PST 24
Peak memory 207404 kb
Host smart-9cdf0115-7c56-472a-8522-4d900a96a4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310499953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2310499953
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2695987040
Short name T240
Test name
Test status
Simulation time 3899402485 ps
CPU time 36.55 seconds
Started Jan 24 11:26:15 PM PST 24
Finished Jan 24 11:26:55 PM PST 24
Peak memory 199192 kb
Host smart-43fc385f-3304-4ee1-bbc0-f64682195227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695987040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2695987040
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.60440238
Short name T698
Test name
Test status
Simulation time 5203633537 ps
CPU time 68.34 seconds
Started Jan 24 11:26:13 PM PST 24
Finished Jan 24 11:27:23 PM PST 24
Peak memory 199204 kb
Host smart-543f5e1c-c7e1-4384-9247-4ce465f8f17f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60440238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.60440238
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.583521993
Short name T337
Test name
Test status
Simulation time 18657503692 ps
CPU time 73.82 seconds
Started Jan 24 11:26:15 PM PST 24
Finished Jan 24 11:27:31 PM PST 24
Peak memory 199256 kb
Host smart-9b480958-ce9f-47fa-aea8-ba9416d35947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583521993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.583521993
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3781933883
Short name T703
Test name
Test status
Simulation time 30627614216 ps
CPU time 76.38 seconds
Started Jan 24 11:26:16 PM PST 24
Finished Jan 24 11:27:36 PM PST 24
Peak memory 199224 kb
Host smart-104ca257-e54a-4d8d-9fd7-93f1f7f54853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781933883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3781933883
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1937870670
Short name T49
Test name
Test status
Simulation time 369433835 ps
CPU time 0.9 seconds
Started Jan 24 11:26:17 PM PST 24
Finished Jan 24 11:26:22 PM PST 24
Peak memory 215876 kb
Host smart-8675ab29-ece7-4489-abf6-8c9a916b6b42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937870670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1937870670
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1576378844
Short name T302
Test name
Test status
Simulation time 1276601103 ps
CPU time 4.48 seconds
Started Jan 24 11:26:19 PM PST 24
Finished Jan 24 11:26:27 PM PST 24
Peak memory 199108 kb
Host smart-642609a8-f70e-4a24-9b5c-c24f7c7a9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576378844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1576378844
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2658759254
Short name T508
Test name
Test status
Simulation time 388580912533 ps
CPU time 1248.94 seconds
Started Jan 24 11:26:15 PM PST 24
Finished Jan 24 11:47:05 PM PST 24
Peak memory 199272 kb
Host smart-ce4260b0-9c90-46b8-981f-81c2675e3c55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658759254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2658759254
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3742717821
Short name T121
Test name
Test status
Simulation time 91442079283 ps
CPU time 1445.87 seconds
Started Jan 24 11:26:19 PM PST 24
Finished Jan 24 11:50:28 PM PST 24
Peak memory 244792 kb
Host smart-a387be22-3d62-4257-90fd-61cd6b8e2aae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742717821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3742717821
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.597392486
Short name T725
Test name
Test status
Simulation time 162909969 ps
CPU time 1.01 seconds
Started Jan 24 11:26:15 PM PST 24
Finished Jan 24 11:26:19 PM PST 24
Peak memory 196076 kb
Host smart-82346a30-1b07-4457-ba26-b53f5beba96c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597392486 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.597392486
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1144367188
Short name T455
Test name
Test status
Simulation time 1346373797 ps
CPU time 21.01 seconds
Started Jan 24 11:26:17 PM PST 24
Finished Jan 24 11:26:41 PM PST 24
Peak memory 199104 kb
Host smart-f351c6a5-6329-4f65-99f7-eae8ed3f0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144367188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1144367188
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1055881860
Short name T692
Test name
Test status
Simulation time 81893747 ps
CPU time 0.56 seconds
Started Jan 24 11:35:36 PM PST 24
Finished Jan 24 11:35:38 PM PST 24
Peak memory 192584 kb
Host smart-9b99c279-b9e0-4dcf-8476-f6ae1d65381f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055881860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1055881860
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3440971850
Short name T206
Test name
Test status
Simulation time 1830681785 ps
CPU time 31.04 seconds
Started Jan 24 11:51:22 PM PST 24
Finished Jan 24 11:51:59 PM PST 24
Peak memory 231956 kb
Host smart-c7641141-dedf-4afa-8e18-856254b9bda4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440971850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3440971850
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.822744065
Short name T553
Test name
Test status
Simulation time 7410487609 ps
CPU time 36.11 seconds
Started Jan 25 12:58:09 AM PST 24
Finished Jan 25 12:58:46 AM PST 24
Peak memory 199212 kb
Host smart-f7a5fe33-dd3a-4926-89c2-d6f8d8e301f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822744065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.822744065
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.473714775
Short name T251
Test name
Test status
Simulation time 1964036471 ps
CPU time 49.53 seconds
Started Jan 24 11:35:16 PM PST 24
Finished Jan 24 11:36:07 PM PST 24
Peak memory 199136 kb
Host smart-37889e92-1cea-46f4-85a3-c131c2d69774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473714775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.473714775
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4079587612
Short name T193
Test name
Test status
Simulation time 505487392 ps
CPU time 13.46 seconds
Started Jan 25 12:43:38 AM PST 24
Finished Jan 25 12:43:52 AM PST 24
Peak memory 199184 kb
Host smart-22c078ce-0b81-40a2-a96c-3062d9f6ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079587612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4079587612
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2293850880
Short name T3
Test name
Test status
Simulation time 2902703040 ps
CPU time 26.44 seconds
Started Jan 24 11:35:13 PM PST 24
Finished Jan 24 11:35:40 PM PST 24
Peak memory 199220 kb
Host smart-d82a8e86-dc13-4065-a515-8410f76bf643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293850880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2293850880
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1856422860
Short name T250
Test name
Test status
Simulation time 184968784 ps
CPU time 4.22 seconds
Started Jan 24 11:35:18 PM PST 24
Finished Jan 24 11:35:24 PM PST 24
Peak memory 198604 kb
Host smart-4d64e6d2-6e04-4af7-a3c1-de1364251c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856422860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1856422860
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3809717083
Short name T129
Test name
Test status
Simulation time 49821101116 ps
CPU time 592.18 seconds
Started Jan 24 11:35:40 PM PST 24
Finished Jan 24 11:45:34 PM PST 24
Peak memory 225860 kb
Host smart-9cef050b-42b1-4e4f-b2ce-8a620cedd207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809717083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3809717083
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.1937561848
Short name T123
Test name
Test status
Simulation time 353921291083 ps
CPU time 3171.03 seconds
Started Jan 24 11:35:35 PM PST 24
Finished Jan 25 12:28:27 AM PST 24
Peak memory 256712 kb
Host smart-01bcd137-1231-450a-b6c1-1d0682a6360f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937561848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.1937561848
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1118856759
Short name T213
Test name
Test status
Simulation time 31330407 ps
CPU time 1.21 seconds
Started Jan 25 12:10:40 AM PST 24
Finished Jan 25 12:10:42 AM PST 24
Peak memory 197316 kb
Host smart-e5773404-741e-4fae-aed8-1e50a16f9c49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118856759 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1118856759
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3994630144
Short name T658
Test name
Test status
Simulation time 8997845319 ps
CPU time 435.61 seconds
Started Jan 25 04:14:44 AM PST 24
Finished Jan 25 04:22:02 AM PST 24
Peak memory 199180 kb
Host smart-de4a58e9-2e82-421c-b172-8bf95ad8eeee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994630144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.3994630144
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.137820999
Short name T273
Test name
Test status
Simulation time 2185393398 ps
CPU time 32.55 seconds
Started Jan 24 11:55:48 PM PST 24
Finished Jan 24 11:56:23 PM PST 24
Peak memory 199228 kb
Host smart-6ffd1fac-92ed-41ab-bbfa-5a906466f4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137820999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.137820999
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3220461054
Short name T284
Test name
Test status
Simulation time 35997113 ps
CPU time 0.58 seconds
Started Jan 25 02:45:10 AM PST 24
Finished Jan 25 02:45:12 AM PST 24
Peak memory 193564 kb
Host smart-d6eb66c3-7066-4d5f-94b4-c67d286b26fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220461054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3220461054
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3610567652
Short name T36
Test name
Test status
Simulation time 1654032593 ps
CPU time 17.57 seconds
Started Jan 24 11:35:37 PM PST 24
Finished Jan 24 11:35:56 PM PST 24
Peak memory 215572 kb
Host smart-60548d1a-3dc6-477d-940a-d92dd069b44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610567652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3610567652
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3828595915
Short name T791
Test name
Test status
Simulation time 591746199 ps
CPU time 6.51 seconds
Started Jan 24 11:35:37 PM PST 24
Finished Jan 24 11:35:44 PM PST 24
Peak memory 199172 kb
Host smart-98555c0f-1488-42dc-a891-9ef029b62228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828595915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3828595915
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1013205512
Short name T362
Test name
Test status
Simulation time 2331674989 ps
CPU time 119.57 seconds
Started Jan 24 11:35:37 PM PST 24
Finished Jan 24 11:37:38 PM PST 24
Peak memory 199156 kb
Host smart-69e177b6-7c75-4ee2-b2bd-97104a6eb1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013205512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1013205512
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3329055476
Short name T509
Test name
Test status
Simulation time 7999270897 ps
CPU time 134.41 seconds
Started Jan 24 11:35:34 PM PST 24
Finished Jan 24 11:37:49 PM PST 24
Peak memory 199232 kb
Host smart-873fb4ec-3703-4a3b-8067-6342d2d7cb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329055476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3329055476
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4065730820
Short name T795
Test name
Test status
Simulation time 3456724633 ps
CPU time 92.91 seconds
Started Jan 24 11:35:48 PM PST 24
Finished Jan 24 11:37:22 PM PST 24
Peak memory 199224 kb
Host smart-d434ef02-ba8a-4b6d-9a35-77e881fcccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065730820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4065730820
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2272050861
Short name T57
Test name
Test status
Simulation time 3702958047 ps
CPU time 3.08 seconds
Started Jan 24 11:35:39 PM PST 24
Finished Jan 24 11:35:44 PM PST 24
Peak memory 199188 kb
Host smart-e8909508-624c-480b-bc46-16b9b44e164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272050861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2272050861
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1420500451
Short name T390
Test name
Test status
Simulation time 11116061823 ps
CPU time 524 seconds
Started Jan 24 11:35:59 PM PST 24
Finished Jan 24 11:44:44 PM PST 24
Peak memory 199212 kb
Host smart-db3dd4fb-dc01-400d-a018-02097e8cf3d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420500451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1420500451
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.699528451
Short name T428
Test name
Test status
Simulation time 15574880279 ps
CPU time 230.45 seconds
Started Jan 24 11:36:01 PM PST 24
Finished Jan 24 11:39:52 PM PST 24
Peak memory 214972 kb
Host smart-0c3a2d74-09ae-4374-8683-2ea25e51f906
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699528451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.699528451
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.806965548
Short name T694
Test name
Test status
Simulation time 29088233 ps
CPU time 0.85 seconds
Started Jan 24 11:35:52 PM PST 24
Finished Jan 24 11:35:54 PM PST 24
Peak memory 195984 kb
Host smart-92297b32-740a-4f59-b9e3-50138326d16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806965548 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.806965548
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.253127585
Short name T752
Test name
Test status
Simulation time 41646731868 ps
CPU time 494.98 seconds
Started Jan 25 03:01:12 AM PST 24
Finished Jan 25 03:09:32 AM PST 24
Peak memory 199192 kb
Host smart-cb43c00c-1c27-4af1-bcf7-fbf16667fe11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253127585 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_sha_vectors.253127585
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3075064384
Short name T691
Test name
Test status
Simulation time 4073527704 ps
CPU time 70.52 seconds
Started Jan 24 11:35:38 PM PST 24
Finished Jan 24 11:36:49 PM PST 24
Peak memory 199268 kb
Host smart-12054e12-6a31-42a4-86ff-2af5433d6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075064384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3075064384
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2384220837
Short name T760
Test name
Test status
Simulation time 20940584 ps
CPU time 0.59 seconds
Started Jan 24 11:35:54 PM PST 24
Finished Jan 24 11:35:55 PM PST 24
Peak memory 193548 kb
Host smart-1e6770f6-83da-4f8d-8691-c516e1da878f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384220837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2384220837
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.300075612
Short name T242
Test name
Test status
Simulation time 660736086 ps
CPU time 22.43 seconds
Started Jan 25 12:20:36 AM PST 24
Finished Jan 25 12:20:59 AM PST 24
Peak memory 215588 kb
Host smart-54479ae0-d00a-4d01-988b-9b354a7ee367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300075612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.300075612
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1266563260
Short name T259
Test name
Test status
Simulation time 2385806749 ps
CPU time 15.57 seconds
Started Jan 24 11:36:02 PM PST 24
Finished Jan 24 11:36:18 PM PST 24
Peak memory 199208 kb
Host smart-d9e42f09-40b9-4b8a-a6e0-7edd8795e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266563260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1266563260
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4222987813
Short name T274
Test name
Test status
Simulation time 27306257 ps
CPU time 0.61 seconds
Started Jan 24 11:36:01 PM PST 24
Finished Jan 24 11:36:03 PM PST 24
Peak memory 194380 kb
Host smart-0761939f-bc46-40b5-a420-81157fdaa92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222987813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4222987813
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1869190783
Short name T539
Test name
Test status
Simulation time 355617432 ps
CPU time 6.39 seconds
Started Jan 24 11:36:01 PM PST 24
Finished Jan 24 11:36:08 PM PST 24
Peak memory 198396 kb
Host smart-34c37441-17d9-48df-83d1-8d14038279be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869190783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1869190783
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1817248908
Short name T358
Test name
Test status
Simulation time 3883838507 ps
CPU time 67.11 seconds
Started Jan 24 11:35:59 PM PST 24
Finished Jan 24 11:37:07 PM PST 24
Peak memory 199172 kb
Host smart-f66aafd8-ee47-4bd6-b913-d3ff67e14ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817248908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1817248908
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.45904119
Short name T826
Test name
Test status
Simulation time 1334604422 ps
CPU time 4.55 seconds
Started Jan 24 11:35:59 PM PST 24
Finished Jan 24 11:36:05 PM PST 24
Peak memory 198864 kb
Host smart-52fa9747-443f-4c21-a72c-7d57ae995be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45904119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.45904119
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1809931090
Short name T579
Test name
Test status
Simulation time 13064649880 ps
CPU time 169.95 seconds
Started Jan 25 04:26:47 AM PST 24
Finished Jan 25 04:29:45 AM PST 24
Peak memory 199268 kb
Host smart-7c6e0e89-6785-466f-8979-9e568b7d7a24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809931090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1809931090
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.970785570
Short name T789
Test name
Test status
Simulation time 226449624246 ps
CPU time 999.98 seconds
Started Jan 24 11:35:55 PM PST 24
Finished Jan 24 11:52:37 PM PST 24
Peak memory 242752 kb
Host smart-f0872a6f-bd34-46b8-be8c-f74a76e602dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970785570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.970785570
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3272395256
Short name T217
Test name
Test status
Simulation time 76525855 ps
CPU time 1.15 seconds
Started Jan 25 12:01:01 AM PST 24
Finished Jan 25 12:01:09 AM PST 24
Peak memory 196796 kb
Host smart-e83c88b4-98f2-42b1-af74-abcd66602b6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272395256 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3272395256
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2426493800
Short name T453
Test name
Test status
Simulation time 24752424611 ps
CPU time 353.16 seconds
Started Jan 24 11:35:52 PM PST 24
Finished Jan 24 11:41:46 PM PST 24
Peak memory 199180 kb
Host smart-d387df25-5473-4f8b-bf50-689a6828173c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426493800 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2426493800
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1872928781
Short name T446
Test name
Test status
Simulation time 3035723297 ps
CPU time 32.47 seconds
Started Jan 25 02:58:39 AM PST 24
Finished Jan 25 02:59:12 AM PST 24
Peak memory 199224 kb
Host smart-1f2718cb-4673-442c-883e-2af1ce141c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872928781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1872928781
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3327478660
Short name T402
Test name
Test status
Simulation time 14682412 ps
CPU time 0.6 seconds
Started Jan 25 12:02:03 AM PST 24
Finished Jan 25 12:02:04 AM PST 24
Peak memory 193584 kb
Host smart-7aa3834d-ba4b-4010-ad10-d4afe68cb4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327478660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3327478660
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1201331915
Short name T601
Test name
Test status
Simulation time 105889549 ps
CPU time 2.54 seconds
Started Jan 24 11:35:55 PM PST 24
Finished Jan 24 11:35:59 PM PST 24
Peak memory 199128 kb
Host smart-eb3cbdf7-f2ad-40cd-bcf2-6442a76f4e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201331915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1201331915
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.749446985
Short name T476
Test name
Test status
Simulation time 324126048 ps
CPU time 15.58 seconds
Started Jan 25 12:55:13 AM PST 24
Finished Jan 25 12:55:30 AM PST 24
Peak memory 199108 kb
Host smart-9c6fcc06-a0ed-40bc-a230-d7b27e1c506f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749446985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.749446985
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4011721341
Short name T621
Test name
Test status
Simulation time 1440105336 ps
CPU time 88.05 seconds
Started Jan 25 01:16:52 AM PST 24
Finished Jan 25 01:18:21 AM PST 24
Peak memory 199192 kb
Host smart-f2e36afd-f73c-4fe7-b9af-a80496853996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011721341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4011721341
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2527687006
Short name T512
Test name
Test status
Simulation time 11499515664 ps
CPU time 32.21 seconds
Started Jan 25 12:30:28 AM PST 24
Finished Jan 25 12:31:01 AM PST 24
Peak memory 199200 kb
Host smart-fc77139a-3599-44c6-afb5-4ed2b8da33a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527687006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2527687006
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1111443736
Short name T496
Test name
Test status
Simulation time 1361853948 ps
CPU time 39.58 seconds
Started Jan 25 12:58:21 AM PST 24
Finished Jan 25 12:59:01 AM PST 24
Peak memory 199180 kb
Host smart-ff2dd01f-3456-4cab-931c-7ec99010519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111443736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1111443736
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2593264420
Short name T744
Test name
Test status
Simulation time 178640475 ps
CPU time 2.63 seconds
Started Jan 24 11:35:59 PM PST 24
Finished Jan 24 11:36:03 PM PST 24
Peak memory 199080 kb
Host smart-3a4ee8a4-72fb-4703-a73b-4be8af94e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593264420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2593264420
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3000378755
Short name T534
Test name
Test status
Simulation time 95413671029 ps
CPU time 838.51 seconds
Started Jan 24 11:36:08 PM PST 24
Finished Jan 24 11:50:14 PM PST 24
Peak memory 227668 kb
Host smart-724d7680-52ac-4292-89fc-49fc7f0e7b1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000378755 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3000378755
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2225559098
Short name T527
Test name
Test status
Simulation time 150929976 ps
CPU time 1.21 seconds
Started Jan 25 02:32:11 AM PST 24
Finished Jan 25 02:32:13 AM PST 24
Peak memory 196688 kb
Host smart-fc797bc6-c378-463c-999a-5d25e4585dc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225559098 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2225559098
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.159704116
Short name T480
Test name
Test status
Simulation time 16894724700 ps
CPU time 454.85 seconds
Started Jan 24 11:36:09 PM PST 24
Finished Jan 24 11:43:50 PM PST 24
Peak memory 199176 kb
Host smart-d1e034f3-0dd7-4aa6-b258-2070060620b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159704116 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_sha_vectors.159704116
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2662780981
Short name T257
Test name
Test status
Simulation time 461985592 ps
CPU time 14.59 seconds
Started Jan 24 11:35:55 PM PST 24
Finished Jan 24 11:36:10 PM PST 24
Peak memory 199168 kb
Host smart-65a94eb8-867e-4e85-83a1-e62d3e6c5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662780981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2662780981
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3841914586
Short name T595
Test name
Test status
Simulation time 12986433 ps
CPU time 0.6 seconds
Started Jan 24 11:36:32 PM PST 24
Finished Jan 24 11:36:36 PM PST 24
Peak memory 194580 kb
Host smart-71cf63a5-5872-4cb2-8b1f-893bcf095866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841914586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3841914586
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1866696136
Short name T313
Test name
Test status
Simulation time 340160096 ps
CPU time 14.08 seconds
Started Jan 24 11:36:10 PM PST 24
Finished Jan 24 11:36:29 PM PST 24
Peak memory 220672 kb
Host smart-647567e1-c8bc-49e5-a27f-e628b91f510f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866696136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1866696136
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.630536354
Short name T354
Test name
Test status
Simulation time 2777442196 ps
CPU time 31.73 seconds
Started Jan 24 11:36:10 PM PST 24
Finished Jan 24 11:36:47 PM PST 24
Peak memory 199204 kb
Host smart-18dea7f5-3075-4c86-bec7-75583644b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630536354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.630536354
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.403499707
Short name T825
Test name
Test status
Simulation time 323558358 ps
CPU time 18.86 seconds
Started Jan 25 12:25:34 AM PST 24
Finished Jan 25 12:25:59 AM PST 24
Peak memory 199172 kb
Host smart-27754e8d-8513-466f-a88c-56f475d16aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403499707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.403499707
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3836551222
Short name T735
Test name
Test status
Simulation time 6620532611 ps
CPU time 77.72 seconds
Started Jan 24 11:36:26 PM PST 24
Finished Jan 24 11:37:45 PM PST 24
Peak memory 199188 kb
Host smart-d84e75e9-433d-4ab3-bb60-87d013c1a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836551222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3836551222
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.687633119
Short name T237
Test name
Test status
Simulation time 3650643330 ps
CPU time 64.35 seconds
Started Jan 24 11:36:10 PM PST 24
Finished Jan 24 11:37:19 PM PST 24
Peak memory 199204 kb
Host smart-6c2d3195-50a1-4957-8f78-c3c7dcbf7141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687633119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.687633119
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.257243282
Short name T309
Test name
Test status
Simulation time 519930596 ps
CPU time 3.19 seconds
Started Jan 24 11:36:09 PM PST 24
Finished Jan 24 11:36:18 PM PST 24
Peak memory 199020 kb
Host smart-6bceb3f6-f0f9-4e12-aa49-a571e4e5614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257243282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.257243282
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.810619680
Short name T37
Test name
Test status
Simulation time 4983114066 ps
CPU time 24.05 seconds
Started Jan 24 11:36:25 PM PST 24
Finished Jan 24 11:36:50 PM PST 24
Peak memory 199148 kb
Host smart-6a0abbb4-afc8-42c9-ad18-a42456ee45e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810619680 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.810619680
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.1302693931
Short name T461
Test name
Test status
Simulation time 20724129750 ps
CPU time 330.07 seconds
Started Jan 24 11:36:28 PM PST 24
Finished Jan 24 11:42:02 PM PST 24
Peak memory 215076 kb
Host smart-ff9d7a3f-2400-4bb5-9acb-b06ff8d59acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302693931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.1302693931
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1605728510
Short name T51
Test name
Test status
Simulation time 114761411 ps
CPU time 1.03 seconds
Started Jan 24 11:36:27 PM PST 24
Finished Jan 24 11:36:29 PM PST 24
Peak memory 197328 kb
Host smart-8456c01e-de76-4117-977f-6eda9840d0b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605728510 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1605728510
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1901918084
Short name T317
Test name
Test status
Simulation time 4526486206 ps
CPU time 33.32 seconds
Started Jan 24 11:36:26 PM PST 24
Finished Jan 24 11:37:00 PM PST 24
Peak memory 199172 kb
Host smart-2ff01b77-ef75-4b28-93f6-ba376d28c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901918084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1901918084
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2247339685
Short name T42
Test name
Test status
Simulation time 22865234 ps
CPU time 0.63 seconds
Started Jan 24 11:36:41 PM PST 24
Finished Jan 24 11:36:44 PM PST 24
Peak memory 192584 kb
Host smart-9d04eadf-ea21-42c7-a3d7-53aad48cf2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247339685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2247339685
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1870276834
Short name T216
Test name
Test status
Simulation time 3050177190 ps
CPU time 23.99 seconds
Started Jan 24 11:36:26 PM PST 24
Finished Jan 24 11:36:52 PM PST 24
Peak memory 214896 kb
Host smart-b7dddc77-cdc0-444b-b979-24ee59727a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870276834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1870276834
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3683377621
Short name T249
Test name
Test status
Simulation time 1411245636 ps
CPU time 30.91 seconds
Started Jan 24 11:36:26 PM PST 24
Finished Jan 24 11:36:58 PM PST 24
Peak memory 199152 kb
Host smart-01afdf07-0427-4c45-9a50-2c03bdc3cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683377621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3683377621
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3760156979
Short name T394
Test name
Test status
Simulation time 11359464953 ps
CPU time 96.08 seconds
Started Jan 25 01:21:39 AM PST 24
Finished Jan 25 01:23:15 AM PST 24
Peak memory 199196 kb
Host smart-6d9c162b-9cb0-4b94-9867-b9776fbea408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760156979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3760156979
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.685380021
Short name T199
Test name
Test status
Simulation time 10144120925 ps
CPU time 60.38 seconds
Started Jan 24 11:36:27 PM PST 24
Finished Jan 24 11:37:28 PM PST 24
Peak memory 199220 kb
Host smart-07a5eeb5-9893-4b8e-a3aa-5de3c9de9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685380021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.685380021
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3640696848
Short name T653
Test name
Test status
Simulation time 20610904291 ps
CPU time 60.94 seconds
Started Jan 24 11:36:28 PM PST 24
Finished Jan 24 11:37:33 PM PST 24
Peak memory 199212 kb
Host smart-a1d4fc55-711e-40e9-921f-e0c8ac7d429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640696848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3640696848
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3015165124
Short name T268
Test name
Test status
Simulation time 406625334 ps
CPU time 2.8 seconds
Started Jan 24 11:36:29 PM PST 24
Finished Jan 24 11:36:35 PM PST 24
Peak memory 199092 kb
Host smart-a06991a7-1ac7-4c1f-92b0-8b96153de455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015165124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3015165124
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1369778664
Short name T367
Test name
Test status
Simulation time 6080512011 ps
CPU time 291.65 seconds
Started Jan 25 05:50:22 AM PST 24
Finished Jan 25 05:55:23 AM PST 24
Peak memory 199312 kb
Host smart-7aa7bd65-8dcd-48ab-b13b-8b0ee48e04e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369778664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1369778664
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.783703128
Short name T519
Test name
Test status
Simulation time 41802600340 ps
CPU time 603.62 seconds
Started Jan 24 11:36:25 PM PST 24
Finished Jan 24 11:46:30 PM PST 24
Peak memory 247596 kb
Host smart-cabf52be-0ce6-49d2-a4bc-a004e79789e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783703128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.783703128
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1508758306
Short name T225
Test name
Test status
Simulation time 254577463 ps
CPU time 1.2 seconds
Started Jan 24 11:36:29 PM PST 24
Finished Jan 24 11:36:33 PM PST 24
Peak memory 198308 kb
Host smart-1050b2b2-7cc4-49d0-a578-40c3741b98d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508758306 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1508758306
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3088421812
Short name T746
Test name
Test status
Simulation time 98078879888 ps
CPU time 495.26 seconds
Started Jan 24 11:36:27 PM PST 24
Finished Jan 24 11:44:43 PM PST 24
Peak memory 199232 kb
Host smart-b670d84b-3af0-470c-96ef-49ac8e7c5285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088421812 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.3088421812
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2526906420
Short name T623
Test name
Test status
Simulation time 30019957180 ps
CPU time 92.79 seconds
Started Jan 24 11:36:27 PM PST 24
Finished Jan 24 11:38:01 PM PST 24
Peak memory 199212 kb
Host smart-aebfb692-a12e-46d6-a48d-d14d236a5690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526906420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2526906420
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3080932686
Short name T368
Test name
Test status
Simulation time 46262605 ps
CPU time 0.61 seconds
Started Jan 25 01:01:13 AM PST 24
Finished Jan 25 01:01:15 AM PST 24
Peak memory 194608 kb
Host smart-9c000aa6-3436-42cc-9f55-422393e9e492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080932686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3080932686
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1112575355
Short name T781
Test name
Test status
Simulation time 365427141 ps
CPU time 10.5 seconds
Started Jan 24 11:36:42 PM PST 24
Finished Jan 24 11:36:55 PM PST 24
Peak memory 199140 kb
Host smart-c0c85abc-59a8-466a-90bb-b03e786002bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112575355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1112575355
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3276220553
Short name T484
Test name
Test status
Simulation time 5251797137 ps
CPU time 59.56 seconds
Started Jan 24 11:36:41 PM PST 24
Finished Jan 24 11:37:43 PM PST 24
Peak memory 199232 kb
Host smart-64778212-91dd-4749-bacf-b82a6d8020d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276220553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3276220553
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3435592829
Short name T229
Test name
Test status
Simulation time 2033240827 ps
CPU time 52.66 seconds
Started Jan 24 11:36:43 PM PST 24
Finished Jan 24 11:37:38 PM PST 24
Peak memory 199132 kb
Host smart-0d06dedf-8fa8-4c8e-8204-ec538c9894c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435592829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3435592829
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2285788692
Short name T52
Test name
Test status
Simulation time 6648235458 ps
CPU time 108.97 seconds
Started Jan 24 11:36:44 PM PST 24
Finished Jan 24 11:38:35 PM PST 24
Peak memory 199156 kb
Host smart-b53395bb-07dc-462d-bd5a-751123c32fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285788692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2285788692
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2798047553
Short name T307
Test name
Test status
Simulation time 4378946301 ps
CPU time 59.41 seconds
Started Jan 24 11:51:07 PM PST 24
Finished Jan 24 11:52:08 PM PST 24
Peak memory 199212 kb
Host smart-89fc1a49-476a-4876-9a82-46a7bfd4f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798047553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2798047553
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.16122295
Short name T422
Test name
Test status
Simulation time 167528651 ps
CPU time 1.59 seconds
Started Jan 24 11:36:44 PM PST 24
Finished Jan 24 11:36:48 PM PST 24
Peak memory 198888 kb
Host smart-9f4ced12-a13f-407f-bfbb-976fdf000c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16122295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.16122295
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2239016438
Short name T671
Test name
Test status
Simulation time 12357013004 ps
CPU time 606.01 seconds
Started Jan 24 11:36:42 PM PST 24
Finished Jan 24 11:46:51 PM PST 24
Peak memory 239720 kb
Host smart-44b30b99-813f-43b2-84f7-f0cfd1ef6472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239016438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2239016438
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.4048369238
Short name T619
Test name
Test status
Simulation time 207133067774 ps
CPU time 2201.08 seconds
Started Jan 24 11:36:40 PM PST 24
Finished Jan 25 12:13:24 AM PST 24
Peak memory 251392 kb
Host smart-177e52a9-07ed-4023-a12d-aa749969f419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048369238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.4048369238
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.297053064
Short name T363
Test name
Test status
Simulation time 57212056 ps
CPU time 1.16 seconds
Started Jan 24 11:36:42 PM PST 24
Finished Jan 24 11:36:46 PM PST 24
Peak memory 198472 kb
Host smart-a3c8049e-b995-4a5d-9b77-b74b83c5e447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297053064 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.297053064
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2835658595
Short name T708
Test name
Test status
Simulation time 79524514230 ps
CPU time 515.68 seconds
Started Jan 24 11:36:43 PM PST 24
Finished Jan 24 11:45:21 PM PST 24
Peak memory 199168 kb
Host smart-e47319ff-070a-4262-8d0d-8f0595b17d1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835658595 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.2835658595
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.788006841
Short name T187
Test name
Test status
Simulation time 24658598761 ps
CPU time 23.08 seconds
Started Jan 24 11:36:46 PM PST 24
Finished Jan 24 11:37:12 PM PST 24
Peak memory 199184 kb
Host smart-1e7bbd86-fdd7-4eb9-a93f-0069a6201497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788006841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.788006841
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3057225760
Short name T664
Test name
Test status
Simulation time 17924837 ps
CPU time 0.55 seconds
Started Jan 24 11:36:59 PM PST 24
Finished Jan 24 11:37:07 PM PST 24
Peak memory 193512 kb
Host smart-b216b09a-abea-4c38-a3ae-acf4c324d7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057225760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3057225760
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.169398428
Short name T375
Test name
Test status
Simulation time 971550627 ps
CPU time 30.39 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:37:36 PM PST 24
Peak memory 214848 kb
Host smart-d81ce660-30fa-476f-bfc4-9db7106c53eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169398428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.169398428
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2216107944
Short name T215
Test name
Test status
Simulation time 8148713857 ps
CPU time 24.9 seconds
Started Jan 24 11:36:55 PM PST 24
Finished Jan 24 11:37:28 PM PST 24
Peak memory 199204 kb
Host smart-64f7e342-9b8f-4937-b383-d349ee7bb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216107944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2216107944
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3459559929
Short name T767
Test name
Test status
Simulation time 3538457102 ps
CPU time 31.85 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:37:38 PM PST 24
Peak memory 199184 kb
Host smart-acf8a777-e682-4bf9-8b5a-c8694e9e7648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459559929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3459559929
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2434199727
Short name T451
Test name
Test status
Simulation time 3544621234 ps
CPU time 41.6 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:37:48 PM PST 24
Peak memory 199200 kb
Host smart-21507dfa-2f61-4bf1-bd90-73a6cb48e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434199727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2434199727
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.825448918
Short name T272
Test name
Test status
Simulation time 3996451027 ps
CPU time 108.2 seconds
Started Jan 24 11:36:59 PM PST 24
Finished Jan 24 11:38:55 PM PST 24
Peak memory 199204 kb
Host smart-8ff28f63-2ac8-475b-9d85-084a60ce41db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825448918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.825448918
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.652917339
Short name T341
Test name
Test status
Simulation time 215309938 ps
CPU time 3.09 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:37:09 PM PST 24
Peak memory 198148 kb
Host smart-c3178838-7238-40ff-a439-1f8b6b23f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652917339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.652917339
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1162231920
Short name T710
Test name
Test status
Simulation time 135602725094 ps
CPU time 1570.56 seconds
Started Jan 24 11:36:59 PM PST 24
Finished Jan 25 12:03:17 AM PST 24
Peak memory 199176 kb
Host smart-fc452bed-a894-4ab9-ae70-36a38102ee46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162231920 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1162231920
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.520053695
Short name T665
Test name
Test status
Simulation time 42832794166 ps
CPU time 1101.87 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:55:28 PM PST 24
Peak memory 223976 kb
Host smart-acbee18f-4aec-44ab-8722-a0ae20db843d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520053695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.520053695
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2955487082
Short name T401
Test name
Test status
Simulation time 140871761 ps
CPU time 0.99 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:37:07 PM PST 24
Peak memory 196768 kb
Host smart-e3b82eb9-9f3f-41b3-84dd-5d6c740b20c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955487082 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2955487082
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3792650701
Short name T754
Test name
Test status
Simulation time 54240139358 ps
CPU time 353.85 seconds
Started Jan 24 11:36:58 PM PST 24
Finished Jan 24 11:43:00 PM PST 24
Peak memory 199136 kb
Host smart-840a3777-f8a6-477e-b91d-8d924a6c5a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792650701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.3792650701
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2186013321
Short name T462
Test name
Test status
Simulation time 483744242 ps
CPU time 21.99 seconds
Started Jan 25 12:55:33 AM PST 24
Finished Jan 25 12:55:55 AM PST 24
Peak memory 199196 kb
Host smart-5a60296a-79ae-44ee-93b0-19e8a7d23198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186013321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2186013321
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3014046038
Short name T244
Test name
Test status
Simulation time 13759116 ps
CPU time 0.63 seconds
Started Jan 24 11:37:30 PM PST 24
Finished Jan 24 11:37:33 PM PST 24
Peak memory 192572 kb
Host smart-7646264c-e8ba-4835-863f-ae6b61ff209c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014046038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3014046038
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1567435801
Short name T278
Test name
Test status
Simulation time 11196350100 ps
CPU time 32.34 seconds
Started Jan 24 11:37:17 PM PST 24
Finished Jan 24 11:37:54 PM PST 24
Peak memory 238304 kb
Host smart-11a05d83-5c0c-42f7-9017-5da3f90f7390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567435801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1567435801
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3579896385
Short name T506
Test name
Test status
Simulation time 4096442743 ps
CPU time 25.79 seconds
Started Jan 24 11:37:16 PM PST 24
Finished Jan 24 11:37:43 PM PST 24
Peak memory 199224 kb
Host smart-bd8bdae7-f3ba-4b61-9d2e-c7e8d3aa1bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579896385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3579896385
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3187675287
Short name T575
Test name
Test status
Simulation time 1782938981 ps
CPU time 79.28 seconds
Started Jan 24 11:37:25 PM PST 24
Finished Jan 24 11:38:49 PM PST 24
Peak memory 199088 kb
Host smart-f8abd2db-4dcc-41bb-8df6-81d3da48cf09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187675287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3187675287
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2546364516
Short name T190
Test name
Test status
Simulation time 7585496964 ps
CPU time 103.48 seconds
Started Jan 24 11:37:24 PM PST 24
Finished Jan 24 11:39:13 PM PST 24
Peak memory 199124 kb
Host smart-83386726-9409-4f0a-8964-8ea3480e9989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546364516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2546364516
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2732291677
Short name T755
Test name
Test status
Simulation time 6307179997 ps
CPU time 19.9 seconds
Started Jan 24 11:37:19 PM PST 24
Finished Jan 24 11:37:43 PM PST 24
Peak memory 199200 kb
Host smart-dcce4ded-fd62-4eea-8571-cdcf3d5c02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732291677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2732291677
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3684813237
Short name T296
Test name
Test status
Simulation time 114951799 ps
CPU time 1.07 seconds
Started Jan 24 11:37:16 PM PST 24
Finished Jan 24 11:37:18 PM PST 24
Peak memory 198224 kb
Host smart-d135fccc-cb1a-4e06-8972-29cbfe5771e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684813237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3684813237
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3810174495
Short name T800
Test name
Test status
Simulation time 93793852 ps
CPU time 0.88 seconds
Started Jan 24 11:37:17 PM PST 24
Finished Jan 24 11:37:20 PM PST 24
Peak memory 196224 kb
Host smart-adc56ddf-fa08-45e6-98ce-4d8c9ca9b5c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810174495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3810174495
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.1361235321
Short name T706
Test name
Test status
Simulation time 45281628695 ps
CPU time 2520.91 seconds
Started Jan 24 11:37:33 PM PST 24
Finished Jan 25 12:19:36 AM PST 24
Peak memory 246208 kb
Host smart-6e2a6a14-69f3-4343-8db4-cba670553ab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361235321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.1361235321
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2993215316
Short name T404
Test name
Test status
Simulation time 122812325 ps
CPU time 0.9 seconds
Started Jan 24 11:37:17 PM PST 24
Finished Jan 24 11:37:21 PM PST 24
Peak memory 196888 kb
Host smart-7c4dcea9-5ebc-43f2-9eb7-28e0549b1843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993215316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2993215316
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3016569380
Short name T9
Test name
Test status
Simulation time 25347222423 ps
CPU time 424.51 seconds
Started Jan 24 11:37:14 PM PST 24
Finished Jan 24 11:44:20 PM PST 24
Peak memory 199172 kb
Host smart-1501ec32-d2c1-4b10-b38f-a9162431d4e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016569380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.3016569380
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2038387739
Short name T359
Test name
Test status
Simulation time 1869873504 ps
CPU time 14.3 seconds
Started Jan 24 11:37:17 PM PST 24
Finished Jan 24 11:37:35 PM PST 24
Peak memory 199144 kb
Host smart-c767b2f0-980c-4835-90b7-c44e4ae778a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038387739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2038387739
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1583003220
Short name T745
Test name
Test status
Simulation time 22817423 ps
CPU time 0.66 seconds
Started Jan 25 01:54:33 AM PST 24
Finished Jan 25 01:54:36 AM PST 24
Peak memory 193592 kb
Host smart-b98fdf63-5cd8-441f-89aa-18cd2a7216b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583003220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1583003220
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2019720175
Short name T203
Test name
Test status
Simulation time 3686641701 ps
CPU time 22.99 seconds
Started Jan 24 11:37:31 PM PST 24
Finished Jan 24 11:37:57 PM PST 24
Peak memory 207368 kb
Host smart-f36cb511-87ef-4c7a-886e-bc9de550a48b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019720175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2019720175
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2135378382
Short name T663
Test name
Test status
Simulation time 1363295950 ps
CPU time 62.35 seconds
Started Jan 24 11:37:30 PM PST 24
Finished Jan 24 11:38:35 PM PST 24
Peak memory 199108 kb
Host smart-903bfc34-0911-414d-948c-5e5f48cb0488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135378382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2135378382
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3362026488
Short name T817
Test name
Test status
Simulation time 2676069434 ps
CPU time 71.45 seconds
Started Jan 24 11:37:29 PM PST 24
Finished Jan 24 11:38:43 PM PST 24
Peak memory 199220 kb
Host smart-159c5bed-a848-4f76-b287-bd61a1d574d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362026488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3362026488
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.751480121
Short name T489
Test name
Test status
Simulation time 953838940 ps
CPU time 47.79 seconds
Started Jan 24 11:37:29 PM PST 24
Finished Jan 24 11:38:20 PM PST 24
Peak memory 199152 kb
Host smart-81c6c9cd-5fe9-42d6-b6be-b3c1620e0d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751480121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.751480121
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2132907378
Short name T481
Test name
Test status
Simulation time 4580217177 ps
CPU time 45.02 seconds
Started Jan 24 11:37:27 PM PST 24
Finished Jan 24 11:38:15 PM PST 24
Peak memory 199212 kb
Host smart-cf442442-1b88-494d-af9d-b5d7cf5b7146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132907378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2132907378
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.812246781
Short name T669
Test name
Test status
Simulation time 209276355 ps
CPU time 2.02 seconds
Started Jan 24 11:37:33 PM PST 24
Finished Jan 24 11:37:37 PM PST 24
Peak memory 198920 kb
Host smart-e52296ca-b775-4679-bbd0-5ab46fe9b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812246781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.812246781
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3009779572
Short name T500
Test name
Test status
Simulation time 60280025107 ps
CPU time 756.23 seconds
Started Jan 24 11:37:55 PM PST 24
Finished Jan 24 11:50:33 PM PST 24
Peak memory 207444 kb
Host smart-928127f2-e0ef-44a0-8ca1-3b7295c03110
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009779572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3009779572
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.160995006
Short name T376
Test name
Test status
Simulation time 1105100295 ps
CPU time 1.28 seconds
Started Jan 25 01:24:43 AM PST 24
Finished Jan 25 01:24:45 AM PST 24
Peak memory 197460 kb
Host smart-385e605d-23bc-4755-bebf-e5a145c9d051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160995006 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.160995006
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.3746832913
Short name T356
Test name
Test status
Simulation time 25194353727 ps
CPU time 417.58 seconds
Started Jan 25 03:29:17 AM PST 24
Finished Jan 25 03:36:16 AM PST 24
Peak memory 199180 kb
Host smart-f32cb8db-75c3-4296-a030-e049b1afa151
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746832913 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.3746832913
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2632702434
Short name T592
Test name
Test status
Simulation time 5888452392 ps
CPU time 67.07 seconds
Started Jan 24 11:37:31 PM PST 24
Finished Jan 24 11:38:41 PM PST 24
Peak memory 199188 kb
Host smart-31224575-771a-458c-9b7f-04dab1d9136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632702434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2632702434
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3903563542
Short name T672
Test name
Test status
Simulation time 129814896 ps
CPU time 0.62 seconds
Started Jan 25 01:51:30 AM PST 24
Finished Jan 25 01:51:33 AM PST 24
Peak memory 192608 kb
Host smart-419e0b4c-8a5c-4744-a8cd-1f063b6b8ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903563542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3903563542
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.597968635
Short name T643
Test name
Test status
Simulation time 103565680 ps
CPU time 3.65 seconds
Started Jan 24 11:26:20 PM PST 24
Finished Jan 24 11:26:27 PM PST 24
Peak memory 199184 kb
Host smart-c6aac72e-30ff-4889-84dc-2449dc9b70f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597968635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.597968635
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2608929651
Short name T830
Test name
Test status
Simulation time 935905307 ps
CPU time 2.89 seconds
Started Jan 24 11:26:20 PM PST 24
Finished Jan 24 11:26:26 PM PST 24
Peak memory 199140 kb
Host smart-51e5c16c-dfb8-4df4-9c28-36d543b772de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608929651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2608929651
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.563285819
Short name T32
Test name
Test status
Simulation time 9462272560 ps
CPU time 132.99 seconds
Started Jan 24 11:26:23 PM PST 24
Finished Jan 24 11:28:39 PM PST 24
Peak memory 199228 kb
Host smart-a60f0593-2edb-49da-8a6a-8366d5693fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563285819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.563285819
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.42812404
Short name T547
Test name
Test status
Simulation time 1029218154 ps
CPU time 25.4 seconds
Started Jan 24 11:26:19 PM PST 24
Finished Jan 24 11:26:47 PM PST 24
Peak memory 199072 kb
Host smart-43dd523b-2c7b-4de0-94b1-d088e870f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42812404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.42812404
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4015444875
Short name T520
Test name
Test status
Simulation time 12542065035 ps
CPU time 87.42 seconds
Started Jan 24 11:26:20 PM PST 24
Finished Jan 24 11:27:51 PM PST 24
Peak memory 199212 kb
Host smart-431d0362-f02a-4c29-b990-486f765488d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015444875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4015444875
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3102834760
Short name T504
Test name
Test status
Simulation time 133921586 ps
CPU time 3.7 seconds
Started Jan 24 11:26:17 PM PST 24
Finished Jan 24 11:26:24 PM PST 24
Peak memory 199128 kb
Host smart-1d7993ab-2529-47b5-ad65-9d20b20241b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102834760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3102834760
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.687477140
Short name T467
Test name
Test status
Simulation time 85315417400 ps
CPU time 700.08 seconds
Started Jan 24 11:26:23 PM PST 24
Finished Jan 24 11:38:06 PM PST 24
Peak memory 207440 kb
Host smart-76ccb4f5-f1d3-4c26-88e7-264d7a68f71d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687477140 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.687477140
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3010376289
Short name T716
Test name
Test status
Simulation time 49319560470 ps
CPU time 340.86 seconds
Started Jan 24 11:26:19 PM PST 24
Finished Jan 24 11:32:04 PM PST 24
Peak memory 215760 kb
Host smart-1062c81d-606f-4c9a-803b-03c665f40ada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010376289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3010376289
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3574534865
Short name T264
Test name
Test status
Simulation time 49600851 ps
CPU time 1.02 seconds
Started Jan 24 11:26:18 PM PST 24
Finished Jan 24 11:26:22 PM PST 24
Peak memory 196472 kb
Host smart-fa19eb21-bae4-46bd-8181-cc1a6c8c62a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574534865 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3574534865
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1185701673
Short name T248
Test name
Test status
Simulation time 4948717598 ps
CPU time 27.65 seconds
Started Jan 24 11:26:20 PM PST 24
Finished Jan 24 11:26:51 PM PST 24
Peak memory 199224 kb
Host smart-72bd8151-6b3d-4286-9dae-d764a84cdf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185701673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1185701673
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.747619229
Short name T612
Test name
Test status
Simulation time 89834053108 ps
CPU time 4997.2 seconds
Started Jan 24 11:37:52 PM PST 24
Finished Jan 25 01:01:11 AM PST 24
Peak memory 248536 kb
Host smart-8c0c6935-2884-4a09-b9ff-d8c7b7d34f5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747619229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.747619229
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.3811076512
Short name T110
Test name
Test status
Simulation time 86546656661 ps
CPU time 1518.92 seconds
Started Jan 24 11:37:52 PM PST 24
Finished Jan 25 12:03:12 AM PST 24
Peak memory 256692 kb
Host smart-fde190dc-b6eb-477f-8e4c-f3bb46b8c2d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811076512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.3811076512
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.41723550
Short name T417
Test name
Test status
Simulation time 109155922086 ps
CPU time 1465.08 seconds
Started Jan 24 11:38:13 PM PST 24
Finished Jan 25 12:02:45 AM PST 24
Peak memory 239440 kb
Host smart-363c690f-a827-4895-915b-6efb495ed99e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41723550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.41723550
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.4227491863
Short name T528
Test name
Test status
Simulation time 163349198700 ps
CPU time 692.57 seconds
Started Jan 24 11:38:13 PM PST 24
Finished Jan 24 11:49:52 PM PST 24
Peak memory 242308 kb
Host smart-5a8e6e4c-c4f5-4308-ab7f-a9c9b66d682d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227491863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.4227491863
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.2005780169
Short name T597
Test name
Test status
Simulation time 19810553407 ps
CPU time 885.78 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 24 11:53:05 PM PST 24
Peak memory 240356 kb
Host smart-5c1ab6b2-2e41-4594-a254-b4d96b4a45fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005780169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.2005780169
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.1994162707
Short name T335
Test name
Test status
Simulation time 78168747939 ps
CPU time 3765.03 seconds
Started Jan 25 12:02:53 AM PST 24
Finished Jan 25 01:05:39 AM PST 24
Peak memory 264208 kb
Host smart-661fb25a-0fb5-4fc9-bb73-e8cb37c1ed9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994162707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.1994162707
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.2366091702
Short name T396
Test name
Test status
Simulation time 62775087465 ps
CPU time 3497.52 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 25 12:36:36 AM PST 24
Peak memory 253868 kb
Host smart-b804e8ae-b38b-45ca-8c49-58327f70e987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366091702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.2366091702
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.3800628348
Short name T108
Test name
Test status
Simulation time 525030901934 ps
CPU time 2573.21 seconds
Started Jan 24 11:38:14 PM PST 24
Finished Jan 25 12:21:14 AM PST 24
Peak memory 248424 kb
Host smart-d94abfd8-60ef-45a4-8fb5-a0ce5bb11f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800628348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.3800628348
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1993433427
Short name T421
Test name
Test status
Simulation time 12755598 ps
CPU time 0.58 seconds
Started Jan 24 11:26:55 PM PST 24
Finished Jan 24 11:26:57 PM PST 24
Peak memory 192604 kb
Host smart-1db95d6e-5d8e-46d8-bbb3-cd3253048655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993433427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1993433427
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3296544871
Short name T502
Test name
Test status
Simulation time 466530263 ps
CPU time 14.47 seconds
Started Jan 24 11:26:55 PM PST 24
Finished Jan 24 11:27:11 PM PST 24
Peak memory 199128 kb
Host smart-e8bf700b-0328-45c0-bfd3-27c02bdb0262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296544871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3296544871
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.280398537
Short name T290
Test name
Test status
Simulation time 465074227 ps
CPU time 19.99 seconds
Started Jan 24 11:27:03 PM PST 24
Finished Jan 24 11:27:26 PM PST 24
Peak memory 199144 kb
Host smart-8aa54304-dad8-40a3-9385-ab908a259f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280398537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.280398537
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3758078460
Short name T536
Test name
Test status
Simulation time 4475433233 ps
CPU time 60.87 seconds
Started Jan 24 11:26:57 PM PST 24
Finished Jan 24 11:27:59 PM PST 24
Peak memory 199188 kb
Host smart-db2a53eb-84d8-4f6f-be15-da3fd33091ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758078460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3758078460
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.421487453
Short name T281
Test name
Test status
Simulation time 3153432571 ps
CPU time 38.75 seconds
Started Jan 24 11:27:04 PM PST 24
Finished Jan 24 11:27:45 PM PST 24
Peak memory 199204 kb
Host smart-d194c163-560b-427a-b211-fb8bdeab2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421487453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.421487453
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.344544604
Short name T1
Test name
Test status
Simulation time 24270570720 ps
CPU time 85.26 seconds
Started Jan 24 11:26:56 PM PST 24
Finished Jan 24 11:28:23 PM PST 24
Peak memory 199228 kb
Host smart-c4d099db-c222-427e-ba62-9aca99205595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344544604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.344544604
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.959223548
Short name T294
Test name
Test status
Simulation time 95733355 ps
CPU time 2.47 seconds
Started Jan 24 11:26:57 PM PST 24
Finished Jan 24 11:27:01 PM PST 24
Peak memory 199028 kb
Host smart-c3dd73c1-4d68-4e25-b147-30624eacf168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959223548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.959223548
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2635271584
Short name T650
Test name
Test status
Simulation time 104107397631 ps
CPU time 1180.2 seconds
Started Jan 24 11:27:03 PM PST 24
Finished Jan 24 11:46:47 PM PST 24
Peak memory 199236 kb
Host smart-fcb683a6-d5a9-4df0-9c12-15c960ec9f19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635271584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2635271584
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4025753832
Short name T702
Test name
Test status
Simulation time 353905911785 ps
CPU time 1845.56 seconds
Started Jan 24 11:27:02 PM PST 24
Finished Jan 24 11:57:52 PM PST 24
Peak memory 223952 kb
Host smart-32050d81-dbe7-4e4f-9015-f983e35b4782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025753832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4025753832
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.561342530
Short name T532
Test name
Test status
Simulation time 39819916 ps
CPU time 0.96 seconds
Started Jan 24 11:26:56 PM PST 24
Finished Jan 24 11:26:58 PM PST 24
Peak memory 196820 kb
Host smart-d682ed7c-29c3-4cd5-b5ee-cca7f389f2fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561342530 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.561342530
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3059621518
Short name T495
Test name
Test status
Simulation time 138681590591 ps
CPU time 404.96 seconds
Started Jan 24 11:26:59 PM PST 24
Finished Jan 24 11:33:48 PM PST 24
Peak memory 199124 kb
Host smart-bf9c72ec-e47d-44cb-9620-65eb532c041a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059621518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3059621518
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3877996128
Short name T185
Test name
Test status
Simulation time 2277104003 ps
CPU time 33.65 seconds
Started Jan 25 05:00:40 AM PST 24
Finished Jan 25 05:01:16 AM PST 24
Peak memory 199172 kb
Host smart-63339d19-1883-4913-bae6-48027a3e5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877996128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3877996128
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.655379187
Short name T751
Test name
Test status
Simulation time 54788646755 ps
CPU time 807.81 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 24 11:51:46 PM PST 24
Peak memory 199388 kb
Host smart-b0160be0-428c-44ad-90da-8c23b4e42558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655379187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.655379187
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.163899818
Short name T399
Test name
Test status
Simulation time 348753079929 ps
CPU time 2389.47 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 25 12:18:09 AM PST 24
Peak memory 248476 kb
Host smart-b867ba38-dbf3-49fd-8e25-5b1050519ccf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163899818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.163899818
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.4026057896
Short name T740
Test name
Test status
Simulation time 128981016096 ps
CPU time 1212.1 seconds
Started Jan 25 02:29:34 AM PST 24
Finished Jan 25 02:49:48 AM PST 24
Peak memory 215752 kb
Host smart-196dffe8-5adf-4420-971d-064e6a70fe35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026057896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.4026057896
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.1583823126
Short name T183
Test name
Test status
Simulation time 56411675505 ps
CPU time 392.88 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 24 11:44:51 PM PST 24
Peak memory 199332 kb
Host smart-8f84d013-befd-465f-9412-34341347c20c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583823126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.1583823126
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.4185300598
Short name T518
Test name
Test status
Simulation time 274910325978 ps
CPU time 1227.44 seconds
Started Jan 24 11:38:12 PM PST 24
Finished Jan 24 11:58:46 PM PST 24
Peak memory 240380 kb
Host smart-e99e7cbe-d35d-4b5d-8285-76b180a87841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185300598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.4185300598
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.2631379688
Short name T443
Test name
Test status
Simulation time 478656258974 ps
CPU time 1421.67 seconds
Started Jan 24 11:38:14 PM PST 24
Finished Jan 25 12:02:03 AM PST 24
Peak memory 247824 kb
Host smart-d451d7d5-a9fb-451a-841b-920b2ece78a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631379688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.2631379688
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.296105101
Short name T569
Test name
Test status
Simulation time 232680277478 ps
CPU time 830.99 seconds
Started Jan 24 11:38:14 PM PST 24
Finished Jan 24 11:52:12 PM PST 24
Peak memory 246728 kb
Host smart-af5d9d0e-98c2-4999-810d-21cff540d1ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296105101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.296105101
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.56282597
Short name T804
Test name
Test status
Simulation time 213879811552 ps
CPU time 663.42 seconds
Started Jan 24 11:38:31 PM PST 24
Finished Jan 24 11:49:36 PM PST 24
Peak memory 225816 kb
Host smart-942cc926-8741-4201-8bc4-fcc08797c605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56282597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.56282597
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.172510314
Short name T112
Test name
Test status
Simulation time 406404331488 ps
CPU time 1941.09 seconds
Started Jan 24 11:38:32 PM PST 24
Finished Jan 25 12:10:55 AM PST 24
Peak memory 249516 kb
Host smart-41cf55e8-2558-4a2b-b179-dcaec867b4ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172510314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.172510314
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1039575067
Short name T780
Test name
Test status
Simulation time 21428989 ps
CPU time 0.58 seconds
Started Jan 24 11:26:59 PM PST 24
Finished Jan 24 11:27:04 PM PST 24
Peak memory 192544 kb
Host smart-29e5cc8b-277d-4b1e-843b-89ef0c44259e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039575067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1039575067
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3813460442
Short name T715
Test name
Test status
Simulation time 5596920378 ps
CPU time 33.98 seconds
Started Jan 24 11:26:55 PM PST 24
Finished Jan 24 11:27:31 PM PST 24
Peak memory 215304 kb
Host smart-4fb58b9a-0c3c-4a34-9ab9-2f9820154bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813460442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3813460442
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2722414093
Short name T762
Test name
Test status
Simulation time 6349286615 ps
CPU time 24.85 seconds
Started Jan 24 11:26:56 PM PST 24
Finished Jan 24 11:27:22 PM PST 24
Peak memory 199224 kb
Host smart-b2891ad0-064d-469d-8f5a-fc8cbd87f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722414093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2722414093
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1297756768
Short name T485
Test name
Test status
Simulation time 4513710992 ps
CPU time 119.1 seconds
Started Jan 24 11:27:03 PM PST 24
Finished Jan 24 11:29:06 PM PST 24
Peak memory 199188 kb
Host smart-bc50b4f5-1a6a-4fe6-8143-c5a0418cac33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297756768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1297756768
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1491348489
Short name T777
Test name
Test status
Simulation time 11385027319 ps
CPU time 89.05 seconds
Started Jan 24 11:26:56 PM PST 24
Finished Jan 24 11:28:26 PM PST 24
Peak memory 199244 kb
Host smart-571bd9e4-beef-43ae-ae97-525a7a3ef329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491348489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1491348489
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1928904616
Short name T314
Test name
Test status
Simulation time 298797433 ps
CPU time 16.18 seconds
Started Jan 24 11:26:57 PM PST 24
Finished Jan 24 11:27:14 PM PST 24
Peak memory 199140 kb
Host smart-c1d971c5-2a79-4911-8eb2-052da119f943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928904616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1928904616
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1536894966
Short name T200
Test name
Test status
Simulation time 141682766 ps
CPU time 1.2 seconds
Started Jan 24 11:26:55 PM PST 24
Finished Jan 24 11:26:58 PM PST 24
Peak memory 198444 kb
Host smart-9028cab9-155d-4d82-bf21-ca4dd64293ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536894966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1536894966
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1528144172
Short name T805
Test name
Test status
Simulation time 233487149037 ps
CPU time 1195.64 seconds
Started Jan 24 11:26:57 PM PST 24
Finished Jan 24 11:46:54 PM PST 24
Peak memory 199268 kb
Host smart-3ca9bfe4-5504-4c43-b9b6-d9c84f758a06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528144172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1528144172
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3953449998
Short name T583
Test name
Test status
Simulation time 134291232362 ps
CPU time 521.57 seconds
Started Jan 24 11:26:56 PM PST 24
Finished Jan 24 11:35:39 PM PST 24
Peak memory 256524 kb
Host smart-285bff6f-c442-4840-bb11-f822ee6e0764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953449998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3953449998
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.913329760
Short name T439
Test name
Test status
Simulation time 430491836 ps
CPU time 1.19 seconds
Started Jan 24 11:26:59 PM PST 24
Finished Jan 24 11:27:04 PM PST 24
Peak memory 196568 kb
Host smart-382395cf-2462-4b07-9b33-38e487a40194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913329760 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.913329760
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.36442880
Short name T435
Test name
Test status
Simulation time 26423650110 ps
CPU time 458.96 seconds
Started Jan 24 11:26:55 PM PST 24
Finished Jan 24 11:34:36 PM PST 24
Peak memory 199188 kb
Host smart-5dd9f3b7-8ad9-4017-b18f-5f61ee849a33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442880 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.hmac_test_sha_vectors.36442880
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.665306939
Short name T405
Test name
Test status
Simulation time 935906990 ps
CPU time 24.43 seconds
Started Jan 24 11:26:54 PM PST 24
Finished Jan 24 11:27:21 PM PST 24
Peak memory 199140 kb
Host smart-19b4a86a-c427-4d26-ae86-6c443f74a663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665306939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.665306939
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.1330997485
Short name T263
Test name
Test status
Simulation time 39226123994 ps
CPU time 2102.34 seconds
Started Jan 24 11:38:33 PM PST 24
Finished Jan 25 12:13:36 AM PST 24
Peak memory 237244 kb
Host smart-bb10e388-e9a3-4c54-80f9-b5f2a6cf5744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330997485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.1330997485
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1315734099
Short name T719
Test name
Test status
Simulation time 441642890842 ps
CPU time 3932.63 seconds
Started Jan 24 11:38:32 PM PST 24
Finished Jan 25 12:44:06 AM PST 24
Peak memory 265968 kb
Host smart-1043fd7b-e510-41e1-9802-35ac79a348c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315734099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1315734099
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.1500642075
Short name T578
Test name
Test status
Simulation time 47706637354 ps
CPU time 655.77 seconds
Started Jan 24 11:38:33 PM PST 24
Finished Jan 24 11:49:30 PM PST 24
Peak memory 218788 kb
Host smart-4e2412b6-5c02-433e-869b-ac64ecaebc79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500642075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.1500642075
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2275087942
Short name T542
Test name
Test status
Simulation time 241369358790 ps
CPU time 861.42 seconds
Started Jan 24 11:38:33 PM PST 24
Finished Jan 24 11:52:55 PM PST 24
Peak memory 223936 kb
Host smart-1945bbd5-704b-4a2f-bdd2-e4925c635f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275087942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2275087942
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3776893318
Short name T445
Test name
Test status
Simulation time 68300481439 ps
CPU time 1235.83 seconds
Started Jan 24 11:38:30 PM PST 24
Finished Jan 24 11:59:07 PM PST 24
Peak memory 239424 kb
Host smart-3391a0e7-741e-415d-87f5-00c1d3f0d1c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776893318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.3776893318
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.1305502656
Short name T543
Test name
Test status
Simulation time 139171358748 ps
CPU time 599.9 seconds
Started Jan 24 11:38:29 PM PST 24
Finished Jan 24 11:48:31 PM PST 24
Peak memory 209608 kb
Host smart-3a65f6f1-dcb3-4b99-ad96-e6b892d13a11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305502656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.1305502656
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.1234022934
Short name T816
Test name
Test status
Simulation time 52759539984 ps
CPU time 2692.57 seconds
Started Jan 24 11:38:31 PM PST 24
Finished Jan 25 12:23:26 AM PST 24
Peak memory 245344 kb
Host smart-7117474b-6c53-4bec-914c-384fce77ff53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234022934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.1234022934
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.2112104163
Short name T128
Test name
Test status
Simulation time 1979035816987 ps
CPU time 4797.12 seconds
Started Jan 24 11:38:51 PM PST 24
Finished Jan 25 12:58:51 AM PST 24
Peak memory 273100 kb
Host smart-b3cc0b21-c2d8-4bf4-8e52-047a9a963ba7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112104163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.2112104163
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1342812228
Short name T688
Test name
Test status
Simulation time 14086299 ps
CPU time 0.58 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:27:17 PM PST 24
Peak memory 193560 kb
Host smart-74d04d93-ab04-4450-93d1-a3afca42481d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342812228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1342812228
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.945401208
Short name T246
Test name
Test status
Simulation time 474168798 ps
CPU time 15.92 seconds
Started Jan 24 11:26:54 PM PST 24
Finished Jan 24 11:27:12 PM PST 24
Peak memory 222780 kb
Host smart-619b8e79-de85-47a6-b49e-c6d653e9294c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945401208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.945401208
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1400780733
Short name T321
Test name
Test status
Simulation time 9365449038 ps
CPU time 39.89 seconds
Started Jan 24 11:26:54 PM PST 24
Finished Jan 24 11:27:36 PM PST 24
Peak memory 199208 kb
Host smart-502d3b68-d7c3-42be-9add-510bfd0f9de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400780733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1400780733
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.692401538
Short name T7
Test name
Test status
Simulation time 2516807061 ps
CPU time 131.94 seconds
Started Jan 24 11:26:54 PM PST 24
Finished Jan 24 11:29:08 PM PST 24
Peak memory 199208 kb
Host smart-c5d7b83f-623d-4daa-9f53-8110885834e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692401538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.692401538
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1832275586
Short name T464
Test name
Test status
Simulation time 42768444189 ps
CPU time 121.06 seconds
Started Jan 24 11:27:03 PM PST 24
Finished Jan 24 11:29:08 PM PST 24
Peak memory 199216 kb
Host smart-96b5f368-ba97-42b0-9950-b5ead95755a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832275586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1832275586
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1235917159
Short name T326
Test name
Test status
Simulation time 1655240273 ps
CPU time 75.36 seconds
Started Jan 24 11:27:03 PM PST 24
Finished Jan 24 11:28:22 PM PST 24
Peak memory 199176 kb
Host smart-7dabab28-c061-4866-a1b1-335736ebc2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235917159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1235917159
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4030006989
Short name T577
Test name
Test status
Simulation time 136730430 ps
CPU time 1.19 seconds
Started Jan 24 11:26:59 PM PST 24
Finished Jan 24 11:27:04 PM PST 24
Peak memory 198496 kb
Host smart-9d84425c-2ac3-4d76-b807-58793fe272c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030006989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4030006989
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2774716323
Short name T103
Test name
Test status
Simulation time 32685060938 ps
CPU time 375.46 seconds
Started Jan 24 11:27:18 PM PST 24
Finished Jan 24 11:33:34 PM PST 24
Peak memory 199180 kb
Host smart-3bb42037-4f3b-46e0-97b2-adcd53c9286c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774716323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2774716323
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3752095964
Short name T730
Test name
Test status
Simulation time 27910490688 ps
CPU time 264.4 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:31:40 PM PST 24
Peak memory 215716 kb
Host smart-d78ec785-cd28-4d22-bc0e-036c47b19576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752095964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3752095964
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3469179395
Short name T255
Test name
Test status
Simulation time 36829639 ps
CPU time 0.96 seconds
Started Jan 25 01:22:20 AM PST 24
Finished Jan 25 01:22:21 AM PST 24
Peak memory 196208 kb
Host smart-7169e765-81d8-48c2-ac5c-6ff2377e8630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469179395 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3469179395
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2805464413
Short name T681
Test name
Test status
Simulation time 170500993603 ps
CPU time 449.21 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:34:44 PM PST 24
Peak memory 199156 kb
Host smart-79715636-ed3a-456d-8366-06785ab4d083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805464413 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.2805464413
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.747973201
Short name T680
Test name
Test status
Simulation time 5775338289 ps
CPU time 78.9 seconds
Started Jan 24 11:26:57 PM PST 24
Finished Jan 24 11:28:18 PM PST 24
Peak memory 199256 kb
Host smart-08fe92a4-50b1-4546-b2f5-01827ae759e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747973201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.747973201
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2516597009
Short name T548
Test name
Test status
Simulation time 1274488328396 ps
CPU time 2368.59 seconds
Started Jan 24 11:38:51 PM PST 24
Finished Jan 25 12:18:21 AM PST 24
Peak memory 248476 kb
Host smart-cc946867-ff34-4798-9499-69dec8b6c7a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516597009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2516597009
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.2148224943
Short name T265
Test name
Test status
Simulation time 143225380792 ps
CPU time 1965.16 seconds
Started Jan 24 11:38:50 PM PST 24
Finished Jan 25 12:11:37 AM PST 24
Peak memory 256644 kb
Host smart-3dcb0a70-93ff-4c57-ad70-1d36efaa182c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148224943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.2148224943
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.2811488019
Short name T353
Test name
Test status
Simulation time 150850661204 ps
CPU time 1170.93 seconds
Started Jan 24 11:38:52 PM PST 24
Finished Jan 24 11:58:24 PM PST 24
Peak memory 248512 kb
Host smart-d655e050-fd25-4b37-9550-555e4d255a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811488019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.2811488019
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2010112407
Short name T709
Test name
Test status
Simulation time 317099590588 ps
CPU time 1144.43 seconds
Started Jan 24 11:38:50 PM PST 24
Finished Jan 24 11:57:56 PM PST 24
Peak memory 224592 kb
Host smart-9fd933f5-06db-4318-bd0b-c126888a766f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010112407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.2010112407
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.880359224
Short name T325
Test name
Test status
Simulation time 60963187033 ps
CPU time 1234.19 seconds
Started Jan 24 11:38:51 PM PST 24
Finished Jan 24 11:59:27 PM PST 24
Peak memory 247804 kb
Host smart-a8354101-7624-4261-be6a-49bb61c1f5c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880359224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.880359224
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2070198881
Short name T99
Test name
Test status
Simulation time 65216054621 ps
CPU time 1166.86 seconds
Started Jan 24 11:38:54 PM PST 24
Finished Jan 24 11:58:23 PM PST 24
Peak memory 241680 kb
Host smart-18a75c0d-db6c-4ed3-9547-930b891350f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070198881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.2070198881
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.3538432758
Short name T673
Test name
Test status
Simulation time 69968610005 ps
CPU time 631.49 seconds
Started Jan 24 11:38:54 PM PST 24
Finished Jan 24 11:49:27 PM PST 24
Peak memory 232128 kb
Host smart-ddb19eb9-c521-447e-b48a-787ca41ae82f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538432758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.3538432758
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.723625177
Short name T280
Test name
Test status
Simulation time 52888892443 ps
CPU time 2633.24 seconds
Started Jan 24 11:38:49 PM PST 24
Finished Jan 25 12:22:45 AM PST 24
Peak memory 240832 kb
Host smart-7401583b-a0e7-455a-9683-4a40400802cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723625177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.723625177
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3438474953
Short name T312
Test name
Test status
Simulation time 161792066962 ps
CPU time 1578.98 seconds
Started Jan 24 11:38:50 PM PST 24
Finished Jan 25 12:05:11 AM PST 24
Peak memory 242876 kb
Host smart-4b2fa84a-b39d-4ade-b29b-439694b8123d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438474953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.3438474953
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.701527540
Short name T192
Test name
Test status
Simulation time 13795654 ps
CPU time 0.59 seconds
Started Jan 25 04:47:34 AM PST 24
Finished Jan 25 04:47:47 AM PST 24
Peak memory 193576 kb
Host smart-e8fb4fa2-78e9-468c-b4b8-388cfa9d7a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701527540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.701527540
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1498655767
Short name T599
Test name
Test status
Simulation time 826854414 ps
CPU time 28.27 seconds
Started Jan 25 01:38:00 AM PST 24
Finished Jan 25 01:38:29 AM PST 24
Peak memory 215532 kb
Host smart-5cc1e0ee-c886-467b-88a3-91f17430c5d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498655767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1498655767
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2308031189
Short name T56
Test name
Test status
Simulation time 3227751959 ps
CPU time 26.35 seconds
Started Jan 24 11:27:13 PM PST 24
Finished Jan 24 11:27:40 PM PST 24
Peak memory 199180 kb
Host smart-0d13eab0-1203-4685-a93d-ffb86e68be34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308031189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2308031189
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3266508194
Short name T634
Test name
Test status
Simulation time 2284120840 ps
CPU time 27.65 seconds
Started Jan 24 11:27:12 PM PST 24
Finished Jan 24 11:27:41 PM PST 24
Peak memory 199220 kb
Host smart-852d7a30-a226-4eb7-9847-f8b0ddfe23ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266508194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3266508194
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2206590221
Short name T654
Test name
Test status
Simulation time 11406968065 ps
CPU time 118 seconds
Started Jan 25 12:47:28 AM PST 24
Finished Jan 25 12:49:29 AM PST 24
Peak memory 199212 kb
Host smart-5481033e-bdd3-48ed-a728-aa033a62344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206590221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2206590221
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.249725673
Short name T205
Test name
Test status
Simulation time 2308029305 ps
CPU time 61.69 seconds
Started Jan 24 11:27:12 PM PST 24
Finished Jan 24 11:28:15 PM PST 24
Peak memory 199248 kb
Host smart-03e1f185-424e-4185-9003-ca84c2350555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249725673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.249725673
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.88788335
Short name T340
Test name
Test status
Simulation time 331840548 ps
CPU time 3.71 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:27:19 PM PST 24
Peak memory 199092 kb
Host smart-2bd98501-0261-4ec0-b299-da99d3b1b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88788335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.88788335
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3992700446
Short name T380
Test name
Test status
Simulation time 659764904553 ps
CPU time 2007.68 seconds
Started Jan 24 11:27:12 PM PST 24
Finished Jan 25 12:00:41 AM PST 24
Peak memory 207428 kb
Host smart-660150ff-8575-4d31-940c-6ab59a0e2b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992700446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3992700446
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.39799585
Short name T782
Test name
Test status
Simulation time 175127967340 ps
CPU time 2506.59 seconds
Started Jan 24 11:27:16 PM PST 24
Finished Jan 25 12:09:04 AM PST 24
Peak memory 241648 kb
Host smart-fccfc863-754a-46ce-ae1d-f68233e1d8ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39799585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.39799585
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1655274646
Short name T479
Test name
Test status
Simulation time 29341005 ps
CPU time 0.93 seconds
Started Jan 24 11:27:15 PM PST 24
Finished Jan 24 11:27:18 PM PST 24
Peak memory 196788 kb
Host smart-95779145-4244-44ac-83de-53b9b79826c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655274646 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1655274646
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3030003003
Short name T182
Test name
Test status
Simulation time 27106037271 ps
CPU time 454.09 seconds
Started Jan 24 11:27:12 PM PST 24
Finished Jan 24 11:34:48 PM PST 24
Peak memory 199164 kb
Host smart-d350a398-7dd5-4e48-acda-0ec0d7fe037c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030003003 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.3030003003
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2538471056
Short name T365
Test name
Test status
Simulation time 4354549245 ps
CPU time 64.31 seconds
Started Jan 24 11:27:14 PM PST 24
Finished Jan 24 11:28:20 PM PST 24
Peak memory 199204 kb
Host smart-e6c20033-7126-4217-97c0-290250e066be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538471056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2538471056
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3134851670
Short name T632
Test name
Test status
Simulation time 71078806056 ps
CPU time 603.22 seconds
Started Jan 24 11:38:52 PM PST 24
Finished Jan 24 11:48:57 PM PST 24
Peak memory 207552 kb
Host smart-c7316333-8229-4b84-882e-abfde9429d34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134851670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.3134851670
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.1996855012
Short name T822
Test name
Test status
Simulation time 48514048915 ps
CPU time 1376.43 seconds
Started Jan 24 11:38:54 PM PST 24
Finished Jan 25 12:01:52 AM PST 24
Peak memory 248064 kb
Host smart-3f7976fa-8934-42d3-ab62-97a752e4238e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996855012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.1996855012
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.4164644933
Short name T667
Test name
Test status
Simulation time 280610149034 ps
CPU time 1185.66 seconds
Started Jan 25 12:52:59 AM PST 24
Finished Jan 25 01:12:45 AM PST 24
Peak memory 214976 kb
Host smart-968c7f1a-9dae-4a7d-8a7b-40056e652db4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164644933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.4164644933
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1518536674
Short name T227
Test name
Test status
Simulation time 165800569153 ps
CPU time 595.08 seconds
Started Jan 24 11:38:51 PM PST 24
Finished Jan 24 11:48:48 PM PST 24
Peak memory 245080 kb
Host smart-aa154ae5-352b-4b81-bc5b-aac298761989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518536674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.1518536674
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.940955105
Short name T39
Test name
Test status
Simulation time 98101106430 ps
CPU time 1894.42 seconds
Started Jan 24 11:38:54 PM PST 24
Finished Jan 25 12:10:30 AM PST 24
Peak memory 248452 kb
Host smart-290e4296-e0ca-4efb-a28a-7a4aa38b74d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940955105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.940955105
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3927420818
Short name T713
Test name
Test status
Simulation time 74388574094 ps
CPU time 1113.64 seconds
Started Jan 24 11:38:54 PM PST 24
Finished Jan 24 11:57:29 PM PST 24
Peak memory 232124 kb
Host smart-d1361a48-c1ce-4b66-bbcb-ffe427a25a8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927420818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.3927420818
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3087396557
Short name T297
Test name
Test status
Simulation time 79174116562 ps
CPU time 803.16 seconds
Started Jan 25 12:44:17 AM PST 24
Finished Jan 25 12:57:41 AM PST 24
Peak memory 225712 kb
Host smart-69066564-4330-45b9-861d-031811b9ea31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087396557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.3087396557
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.1307618955
Short name T374
Test name
Test status
Simulation time 69383462625 ps
CPU time 1301.89 seconds
Started Jan 25 12:34:45 AM PST 24
Finished Jan 25 12:56:29 AM PST 24
Peak memory 244440 kb
Host smart-ac6087a7-b484-45b8-970b-eb48a8c3568d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307618955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.1307618955
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.3452972073
Short name T94
Test name
Test status
Simulation time 117417587927 ps
CPU time 1055.04 seconds
Started Jan 24 11:39:02 PM PST 24
Finished Jan 24 11:56:39 PM PST 24
Peak memory 213084 kb
Host smart-6c13bbfc-1fe3-4143-8092-57c60ad9e31d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452972073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.3452972073
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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