Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18839265

1

T1

14315

T2

18829

T3

33

auto[1]

8770023

1

T1

12197

T2

25994

T9

5136

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8786064

1

T1

9170

T2

20845

T9

6231

auto[1]

18823224

1

T1

17342

T2

23978

T3

33

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16485235

1

T1

7068

T2

23232

T6

37343

auto[1]

11124053

1

T1

19444

T2

21591

T3

33

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16124816	1			T1	23210		T2	37920		T3	11
fifo_depth[1]	1398771	1			T1	1499		T2	2491		T3	5
fifo_depth[2]	1248650	1			T1	1035		T2	1980		T3	3
fifo_depth[3]	1052202	1			T1	506		T2	947		T3	3
fifo_depth[4]	1014469	1			T1	185		T2	745		T5	1
fifo_depth[5]	861407	1			T1	62		T2	189		T3	2
fifo_depth[6]	885481	1			T1	12		T2	265		T3	2
fifo_depth[7]	754500	1			T1	3		T2	75		T3	5
fifo_depth[8]	859787	1			T2	175		T3	2		T6	526
fifo_depth[9]	520038	1			T2	14		T6	341		T9	449
fifo_depth[10]	516296	1			T2	17		T6	211		T9	291
fifo_depth[11]	310791	1			T2	4		T6	119		T9	165
fifo_depth[12]	479321	1			T2	1		T6	64		T9	78
fifo_depth[13]	223601	1			T6	26		T9	25		T12	10
fifo_depth[14]	354583	1			T6	11		T9	17		T13	30
fifo_depth[15]	200825	1			T6	4		T9	5		T12	1
fifo_depth[16]	803750	1			T6	2		T9	4		T13	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11484472

1

T1

3302

T2

6903

T3

22

auto[1]

16124816

1

T1

23210

T2

37920

T3

11

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26805538

1

T1

26512

T2

44823

T3

33

auto[1]

803750

1

T6

2

T9

4

T13

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

846214

1

T1

234

T2

579

T4

393

auto[0]

auto[0]

auto[0]

auto[1]

874959

1

T1

195

T2

798

T4

378

auto[0]

auto[0]

auto[1]

auto[0]

3217711

1

T1

220

T2

1087

T6

12439

auto[0]

auto[0]

auto[1]

auto[1]

856425

1

T1

140

T2

954

T4

233

auto[0]

auto[1]

auto[0]

auto[0]

1425976

1

T1

447

T2

612

T9

1067

auto[0]

auto[1]

auto[0]

auto[1]

1365471

1

T1

308

T2

1428

T9

3052

auto[0]

auto[1]

auto[1]

auto[0]

1477867

1

T1

884

T2

671

T3

22

auto[0]

auto[1]

auto[1]

auto[1]

1419849

1

T1

874

T2

774

T9

365

auto[1]

auto[0]

auto[0]

auto[0]

769962

1

T1

1522

T2

2639

T10

53

auto[1]

auto[0]

auto[0]

auto[1]

783492

1

T1

1560

T2

4262

T10

32

auto[1]

auto[0]

auto[1]

auto[0]

8374008

1

T1

2324

T2

7641

T6

24904

auto[1]

auto[0]

auto[1]

auto[1]

762464

1

T1

873

T2

5272

T10

29

auto[1]

auto[1]

auto[0]

auto[0]

1361426

1

T1

2905

T2

2874

T9

585

auto[1]

auto[1]

auto[0]

auto[1]

1358564

1

T1

1999

T2

7653

T9

1527

auto[1]

auto[1]

auto[1]

auto[0]

1366101

1

T1

5779

T2

2726

T3

11

auto[1]

auto[1]

auto[1]

auto[1]

1348799

1

T1

6248

T2

4853

T9

192

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1509206

1

T1

1756

T2

3218

T10

53

auto[0]

auto[0]

auto[0]

auto[1]

1556433

1

T1

1755

T2

5060

T10

32

auto[0]

auto[0]

auto[1]

auto[0]

11495642

1

T1

2544

T2

8728

T6

37341

auto[0]

auto[0]

auto[1]

auto[1]

1523272

1

T1

1013

T2

6226

T10

29

auto[0]

auto[1]

auto[0]

auto[0]

2679268

1

T1

3352

T2

3486

T9

1650

auto[0]

auto[1]

auto[0]

auto[1]

2634970

1

T1

2307

T2

9081

T9

4578

auto[0]

auto[1]

auto[1]

auto[0]

2737080

1

T1

6663

T2

3397

T3

33

auto[0]

auto[1]

auto[1]

auto[1]

2669667

1

T1

7122

T2

5627

T9

557

auto[1]

auto[0]

auto[0]

auto[0]

106970

1

T7

2884

T32

28

T35

1

auto[1]

auto[0]

auto[0]

auto[1]

102018

1

T7

1333

T8

1

T32

1729

auto[1]

auto[0]

auto[1]

auto[0]

96077

1

T6

2

T7

1693

T8

5

auto[1]

auto[0]

auto[1]

auto[1]

95617

1

T7

1272

T8

2

T32

494

auto[1]

auto[1]

auto[0]

auto[0]

108134

1

T9

2

T7

1779

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

89065

1

T9

1

T13

2

T7

2133

auto[1]

auto[1]

auto[1]

auto[0]

106888

1

T9

1

T7

1698

T8

2

auto[1]

auto[1]

auto[1]

auto[1]

98981

1

T7

2022

T8

1

T33

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	769962	1			T1	1522		T2	2639		T10	53
fifo_depth[0]	auto[0]	auto[0]	auto[1]	783492	1			T1	1560		T2	4262		T10	32
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8374008	1			T1	2324		T2	7641		T6	24904
fifo_depth[0]	auto[0]	auto[1]	auto[1]	762464	1			T1	873		T2	5272		T10	29
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1361426	1			T1	2905		T2	2874		T9	585
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1358564	1			T1	1999		T2	7653		T9	1527
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1366101	1			T1	5779		T2	2726		T3	11
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1348799	1			T1	6248		T2	4853		T9	192
fifo_depth[1]	auto[0]	auto[0]	auto[0]	69248	1			T1	104		T2	153		T4	182
fifo_depth[1]	auto[0]	auto[0]	auto[1]	71741	1			T1	83		T2	262		T4	208
fifo_depth[1]	auto[0]	auto[1]	auto[0]	594419	1			T1	111		T2	457		T6	2494
fifo_depth[1]	auto[0]	auto[1]	auto[1]	69448	1			T1	60		T2	355		T4	122
fifo_depth[1]	auto[1]	auto[0]	auto[0]	147684	1			T1	219		T2	213		T9	131
fifo_depth[1]	auto[1]	auto[0]	auto[1]	145964	1			T1	137		T2	542		T9	345
fifo_depth[1]	auto[1]	auto[1]	auto[0]	151868	1			T1	399		T2	173		T3	5
fifo_depth[1]	auto[1]	auto[1]	auto[1]	148399	1			T1	386		T2	336		T9	36
fifo_depth[2]	auto[0]	auto[0]	auto[0]	65547	1			T1	79		T2	148		T4	122
fifo_depth[2]	auto[0]	auto[0]	auto[1]	66299	1			T1	60		T2	235		T4	101
fifo_depth[2]	auto[0]	auto[1]	auto[0]	506257	1			T1	62		T2	338		T6	2380
fifo_depth[2]	auto[0]	auto[1]	auto[1]	65841	1			T1	46		T2	282		T4	60
fifo_depth[2]	auto[1]	auto[0]	auto[0]	134820	1			T1	129		T2	169		T9	119
fifo_depth[2]	auto[1]	auto[0]	auto[1]	133455	1			T1	108		T2	388		T9	323
fifo_depth[2]	auto[1]	auto[1]	auto[0]	140297	1			T1	269		T2	162		T3	3
fifo_depth[2]	auto[1]	auto[1]	auto[1]	136134	1			T1	282		T2	258		T9	40
fifo_depth[3]	auto[0]	auto[0]	auto[0]	56205	1			T1	30		T2	62		T4	34
fifo_depth[3]	auto[0]	auto[0]	auto[1]	57345	1			T1	36		T2	104		T4	42
fifo_depth[3]	auto[0]	auto[1]	auto[0]	405003	1			T1	34		T2	155		T6	1959
fifo_depth[3]	auto[0]	auto[1]	auto[1]	56132	1			T1	21		T2	144		T4	21
fifo_depth[3]	auto[1]	auto[0]	auto[0]	118165	1			T1	61		T2	79		T9	134
fifo_depth[3]	auto[1]	auto[0]	auto[1]	116631	1			T1	42		T2	229		T9	326
fifo_depth[3]	auto[1]	auto[1]	auto[0]	123182	1			T1	145		T2	65		T3	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	119539	1			T1	137		T2	109		T9	37
fifo_depth[4]	auto[0]	auto[0]	auto[0]	63880	1			T1	16		T2	84		T4	36
fifo_depth[4]	auto[0]	auto[0]	auto[1]	67736	1			T1	12		T2	107		T4	20
fifo_depth[4]	auto[0]	auto[1]	auto[0]	320053	1			T1	8		T2	82		T6	1409
fifo_depth[4]	auto[0]	auto[1]	auto[1]	65226	1			T1	5		T2	91		T4	21
fifo_depth[4]	auto[1]	auto[0]	auto[0]	124940	1			T1	24		T2	78		T9	107
fifo_depth[4]	auto[1]	auto[0]	auto[1]	118464	1			T1	12		T2	106		T9	345
fifo_depth[4]	auto[1]	auto[1]	auto[0]	129369	1			T1	53		T2	155		T5	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	124801	1			T1	55		T2	42		T9	37
fifo_depth[5]	auto[0]	auto[0]	auto[0]	52436	1			T1	5		T2	15		T4	10
fifo_depth[5]	auto[0]	auto[0]	auto[1]	54280	1			T1	2		T2	21		T4	7
fifo_depth[5]	auto[0]	auto[1]	auto[0]	263241	1			T1	4		T2	19		T6	1175
fifo_depth[5]	auto[0]	auto[1]	auto[1]	52626	1			T1	6		T2	25		T4	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	108586	1			T1	10		T2	23		T9	121
fifo_depth[5]	auto[1]	auto[0]	auto[1]	105943	1			T1	7		T2	47		T9	337
fifo_depth[5]	auto[1]	auto[1]	auto[0]	113528	1			T1	15		T2	23		T3	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	110767	1			T1	13		T2	16		T9	38
fifo_depth[6]	auto[0]	auto[0]	auto[0]	58139	1			T2	40		T4	7		T40	17
fifo_depth[6]	auto[0]	auto[0]	auto[1]	62675	1			T2	37		T40	6		T7	1376
fifo_depth[6]	auto[0]	auto[1]	auto[0]	239631	1			T1	1		T2	20		T6	956
fifo_depth[6]	auto[0]	auto[1]	auto[1]	62429	1			T1	2		T2	37		T4	4
fifo_depth[6]	auto[1]	auto[0]	auto[0]	116728	1			T1	3		T2	20		T9	121
fifo_depth[6]	auto[1]	auto[0]	auto[1]	109496	1			T1	2		T2	59		T9	303
fifo_depth[6]	auto[1]	auto[1]	auto[0]	120580	1			T1	3		T2	47		T3	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	115803	1			T1	1		T2	5		T9	37
fifo_depth[7]	auto[0]	auto[0]	auto[0]	49998	1			T2	18		T4	1		T40	3
fifo_depth[7]	auto[0]	auto[0]	auto[1]	52527	1			T1	2		T2	6		T40	6
fifo_depth[7]	auto[0]	auto[1]	auto[0]	192008	1			T2	6		T6	762		T40	6
fifo_depth[7]	auto[0]	auto[1]	auto[1]	51402	1			T2	4		T7	612		T8	243
fifo_depth[7]	auto[1]	auto[0]	auto[0]	101402	1			T1	1		T2	8		T9	112
fifo_depth[7]	auto[1]	auto[0]	auto[1]	98457	1			T2	26		T9	310		T12	75
fifo_depth[7]	auto[1]	auto[1]	auto[0]	106612	1			T2	4		T3	5		T9	261
fifo_depth[7]	auto[1]	auto[1]	auto[1]	102094	1			T2	3		T9	34		T12	13
fifo_depth[8]	auto[0]	auto[0]	auto[0]	73480	1			T2	56		T4	1		T40	13
fifo_depth[8]	auto[0]	auto[0]	auto[1]	74700	1			T2	25		T7	1736		T8	186
fifo_depth[8]	auto[0]	auto[1]	auto[0]	177739	1			T2	8		T6	526		T40	3
fifo_depth[8]	auto[0]	auto[1]	auto[1]	72313	1			T2	15		T4	1		T40	7
fifo_depth[8]	auto[1]	auto[0]	auto[0]	113998	1			T2	15		T9	85		T12	15
fifo_depth[8]	auto[1]	auto[0]	auto[1]	111699	1			T2	18		T9	275		T12	66
fifo_depth[8]	auto[1]	auto[1]	auto[0]	118375	1			T2	34		T3	2		T9	227
fifo_depth[8]	auto[1]	auto[1]	auto[1]	117483	1			T2	4		T9	38		T12	12
fifo_depth[9]	auto[0]	auto[0]	auto[0]	39756	1			T2	2		T40	2		T7	630
fifo_depth[9]	auto[0]	auto[0]	auto[1]	39977	1			T40	1		T7	1398		T8	160
fifo_depth[9]	auto[0]	auto[1]	auto[0]	108984	1			T2	1		T6	341		T40	1
fifo_depth[9]	auto[0]	auto[1]	auto[1]	40559	1			T2	1		T7	585		T8	146
fifo_depth[9]	auto[1]	auto[0]	auto[0]	73043	1			T2	6		T9	61		T12	15
fifo_depth[9]	auto[1]	auto[0]	auto[1]	69583	1			T2	3		T9	212		T12	37
fifo_depth[9]	auto[1]	auto[1]	auto[0]	75576	1			T9	149		T12	28		T13	90
fifo_depth[9]	auto[1]	auto[1]	auto[1]	72560	1			T2	1		T9	27		T12	13
fifo_depth[10]	auto[0]	auto[0]	auto[0]	45232	1			T2	1		T40	2		T7	731
fifo_depth[10]	auto[0]	auto[0]	auto[1]	47658	1			T2	1		T7	1206		T8	120
fifo_depth[10]	auto[0]	auto[1]	auto[0]	90918	1			T2	1		T6	211		T7	2145
fifo_depth[10]	auto[0]	auto[1]	auto[1]	49192	1			T7	1024		T8	89		T45	2
fifo_depth[10]	auto[1]	auto[0]	auto[0]	70483	1			T2	1		T9	38		T12	9
fifo_depth[10]	auto[1]	auto[0]	auto[1]	66807	1			T2	7		T9	131		T12	33
fifo_depth[10]	auto[1]	auto[1]	auto[0]	73713	1			T2	6		T9	101		T12	17
fifo_depth[10]	auto[1]	auto[1]	auto[1]	72293	1			T9	21		T12	7		T13	14
fifo_depth[11]	auto[0]	auto[0]	auto[0]	27982	1			T7	505		T8	27		T32	51
fifo_depth[11]	auto[0]	auto[0]	auto[1]	28958	1			T7	1014		T8	49		T32	119
fifo_depth[11]	auto[0]	auto[1]	auto[0]	53176	1			T6	119		T7	1189		T8	304
fifo_depth[11]	auto[0]	auto[1]	auto[1]	29841	1			T7	661		T8	45		T32	104
fifo_depth[11]	auto[1]	auto[0]	auto[0]	42320	1			T9	17		T12	8		T13	133
fifo_depth[11]	auto[1]	auto[0]	auto[1]	40101	1			T2	3		T9	81		T12	17
fifo_depth[11]	auto[1]	auto[1]	auto[0]	45112	1			T2	1		T9	60		T12	10
fifo_depth[11]	auto[1]	auto[1]	auto[1]	43301	1			T9	7		T12	8		T13	6
fifo_depth[12]	auto[0]	auto[0]	auto[0]	53609	1			T7	1048		T8	11		T32	32
fifo_depth[12]	auto[0]	auto[0]	auto[1]	56947	1			T7	968		T8	38		T32	107
fifo_depth[12]	auto[0]	auto[1]	auto[0]	68026	1			T6	64		T7	1080		T8	131
fifo_depth[12]	auto[0]	auto[1]	auto[1]	53264	1			T7	1051		T8	19		T32	123
fifo_depth[12]	auto[1]	auto[0]	auto[0]	59847	1			T9	9		T12	3		T13	66
fifo_depth[12]	auto[1]	auto[0]	auto[1]	59482	1			T9	43		T12	8		T13	47
fifo_depth[12]	auto[1]	auto[1]	auto[0]	66751	1			T2	1		T9	21		T12	6
fifo_depth[12]	auto[1]	auto[1]	auto[1]	61395	1			T9	5		T12	2		T13	2
fifo_depth[13]	auto[0]	auto[0]	auto[0]	22905	1			T7	314		T8	7		T32	10
fifo_depth[13]	auto[0]	auto[0]	auto[1]	24849	1			T7	798		T8	27		T32	75
fifo_depth[13]	auto[0]	auto[1]	auto[0]	31571	1			T6	26		T7	560		T8	52
fifo_depth[13]	auto[0]	auto[1]	auto[1]	26153	1			T7	614		T8	6		T32	75
fifo_depth[13]	auto[1]	auto[0]	auto[0]	30029	1			T9	5		T12	4		T13	35
fifo_depth[13]	auto[1]	auto[0]	auto[1]	28457	1			T9	13		T12	3		T13	15
fifo_depth[13]	auto[1]	auto[1]	auto[0]	31183	1			T9	5		T12	2		T13	9
fifo_depth[13]	auto[1]	auto[1]	auto[1]	28454	1			T9	2		T12	1		T13	3
fifo_depth[14]	auto[0]	auto[0]	auto[0]	39549	1			T7	630		T8	2		T32	35
fifo_depth[14]	auto[0]	auto[0]	auto[1]	43184	1			T7	689		T8	6		T32	59
fifo_depth[14]	auto[0]	auto[1]	auto[0]	45227	1			T6	11		T7	546		T8	24
fifo_depth[14]	auto[0]	auto[1]	auto[1]	42546	1			T7	786		T8	5		T32	97
fifo_depth[14]	auto[1]	auto[0]	auto[0]	47403	1			T9	4		T13	15		T7	617
fifo_depth[14]	auto[1]	auto[0]	auto[1]	44633	1			T9	5		T13	10		T7	600
fifo_depth[14]	auto[1]	auto[1]	auto[0]	48573	1			T9	4		T13	4		T7	805
fifo_depth[14]	auto[1]	auto[1]	auto[1]	43468	1			T9	4		T13	1		T7	1149
fifo_depth[15]	auto[0]	auto[0]	auto[0]	21278	1			T7	230		T8	2		T32	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	24065	1			T7	575		T8	3		T32	56
fifo_depth[15]	auto[0]	auto[1]	auto[0]	25381	1			T6	4		T7	288		T8	4
fifo_depth[15]	auto[0]	auto[1]	auto[1]	23836	1			T7	416		T8	1		T32	42
fifo_depth[15]	auto[1]	auto[0]	auto[0]	28394	1			T9	1		T13	9		T7	220
fifo_depth[15]	auto[1]	auto[0]	auto[1]	27234	1			T9	2		T13	3		T7	348
fifo_depth[15]	auto[1]	auto[1]	auto[0]	26260	1			T12	1		T13	1		T7	495
fifo_depth[15]	auto[1]	auto[1]	auto[1]	24377	1			T9	2		T7	657		T8	5
fifo_depth[16]	auto[0]	auto[0]	auto[0]	106970	1			T7	2884		T32	28		T35	1
fifo_depth[16]	auto[0]	auto[0]	auto[1]	102018	1			T7	1333		T8	1		T32	1729
fifo_depth[16]	auto[0]	auto[1]	auto[0]	96077	1			T6	2		T7	1693		T8	5
fifo_depth[16]	auto[0]	auto[1]	auto[1]	95617	1			T7	1272		T8	2		T32	494
fifo_depth[16]	auto[1]	auto[0]	auto[0]	108134	1			T9	2		T7	1779		T8	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	89065	1			T9	1		T13	2		T7	2133
fifo_depth[16]	auto[1]	auto[1]	auto[0]	106888	1			T9	1		T7	1698		T8	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	98981	1			T7	2022		T8	1		T33	3