Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.92 99.55 98.75 100.00 96.30 98.47 99.49 99.86


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.00 55.00 37.80 37.80 38.63 38.63 81.78 81.78 96.30 96.30 24.13 24.13 81.06 81.06 25.31 25.31 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.700451074
88.54 33.54 96.69 58.89 84.74 46.11 86.06 4.27 96.30 0.00 91.96 67.83 94.19 13.13 69.88 44.57 /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2029456434
92.72 4.18 98.64 1.96 92.42 7.68 98.49 12.44 96.30 0.00 94.35 2.39 94.44 0.25 74.42 4.54 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4289284838
95.32 2.60 99.10 0.45 95.43 3.01 98.74 0.25 96.30 0.00 95.43 1.09 95.71 1.26 86.52 12.10 /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.3576221938
96.93 1.61 99.32 0.23 97.82 2.39 99.50 0.75 96.30 0.00 96.74 1.30 95.96 0.25 92.85 6.33 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2827856369
97.24 0.31 99.32 0.00 97.82 0.00 99.50 0.00 96.30 0.00 96.74 0.00 97.73 1.77 93.26 0.41 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3339244018
97.47 0.24 99.32 0.00 97.82 0.00 99.50 0.00 96.30 0.00 96.74 0.00 97.73 0.00 94.91 1.65 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3442726143
97.65 0.18 99.32 0.00 98.03 0.21 100.00 0.50 96.30 0.00 96.74 0.00 97.98 0.25 95.19 0.28 /workspace/coverage/default/2.hmac_sec_cm.994239709
97.78 0.13 99.32 0.00 98.13 0.10 100.00 0.00 96.30 0.00 96.74 0.00 97.98 0.00 96.01 0.83 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.351635636
97.91 0.13 99.32 0.00 98.13 0.00 100.00 0.00 96.30 0.00 96.96 0.22 97.98 0.00 96.70 0.69 /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2202013394
98.00 0.09 99.40 0.08 98.23 0.10 100.00 0.00 96.30 0.00 97.39 0.43 97.98 0.00 96.70 0.00 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1388601443
98.08 0.08 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 97.98 0.00 97.25 0.55 /workspace/coverage/cover_reg_top/34.hmac_intr_test.444164241
98.16 0.08 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 97.98 0.00 97.80 0.55 /workspace/coverage/default/35.hmac_stress_all.2483510271
98.23 0.07 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.51 97.80 0.00 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.648378708
98.29 0.06 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 98.21 0.41 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1783429746
98.33 0.04 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 98.49 0.28 /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.4182334148
98.37 0.04 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 98.76 0.28 /workspace/coverage/default/26.hmac_stress_all.3629475161
98.41 0.04 99.40 0.00 98.23 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.04 0.28 /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2402450458
98.44 0.03 99.40 0.00 98.44 0.21 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.04 0.00 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1159675937
98.47 0.03 99.40 0.00 98.65 0.21 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.04 0.00 /workspace/coverage/default/17.hmac_alert_test.4077123044
98.48 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.17 0.14 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1325329755
98.50 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1895566304
98.52 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.1626832634
98.54 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.4264997726
98.56 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2785738654
98.58 0.02 99.40 0.00 98.65 0.00 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3272516472
98.60 0.01 99.40 0.00 98.75 0.10 100.00 0.00 96.30 0.00 97.39 0.00 98.48 0.00 99.86 0.00 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1379208859

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2641864088
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2769321355
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4195394669
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.988545849
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.1408633771
/workspace/coverage/cover_reg_top/0.hmac_intr_test.1093603615
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3157255174
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.1834635751
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.638759983
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2135405905
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2832427884
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.1391443230
/workspace/coverage/cover_reg_top/1.hmac_intr_test.846425083
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2149355761
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2394633450
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1078958910
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.13946061
/workspace/coverage/cover_reg_top/10.hmac_intr_test.1784397882
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.426396300
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.1614350497
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1265335448
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.518764368
/workspace/coverage/cover_reg_top/11.hmac_intr_test.3744750211
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3230298407
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.1771702766
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3650052863
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4181080375
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.334946431
/workspace/coverage/cover_reg_top/12.hmac_intr_test.2701888591
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.22160999
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.3986612527
/workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2354916990
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3512769833
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.3956547832
/workspace/coverage/cover_reg_top/13.hmac_intr_test.4140139509
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3574765376
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.2564217429
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3454886695
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.4293944580
/workspace/coverage/cover_reg_top/14.hmac_intr_test.1070989471
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2966088445
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.252785726
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3787730389
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.3261262254
/workspace/coverage/cover_reg_top/15.hmac_intr_test.1231477549
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3922793480
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.922976875
/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1983241636
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.827152149
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.2722095537
/workspace/coverage/cover_reg_top/16.hmac_intr_test.953642946
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4250876041
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.1403084770
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2984711264
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.722247860
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1077219077
/workspace/coverage/cover_reg_top/17.hmac_intr_test.606524525
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2867543360
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.3293033880
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.713302589
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.1952617480
/workspace/coverage/cover_reg_top/18.hmac_intr_test.1739487334
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.721256598
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.2534659031
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.448504678
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1465659461
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.3759373450
/workspace/coverage/cover_reg_top/19.hmac_intr_test.1393271419
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3884142343
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.3351298386
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.463731571
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3403117616
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3344495756
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2839756141
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1427464108
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.1453445511
/workspace/coverage/cover_reg_top/2.hmac_intr_test.598435157
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2046275133
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.130109588
/workspace/coverage/cover_reg_top/20.hmac_intr_test.908083941
/workspace/coverage/cover_reg_top/21.hmac_intr_test.1417326984
/workspace/coverage/cover_reg_top/22.hmac_intr_test.1181920453
/workspace/coverage/cover_reg_top/23.hmac_intr_test.1905072184
/workspace/coverage/cover_reg_top/24.hmac_intr_test.882417297
/workspace/coverage/cover_reg_top/25.hmac_intr_test.3031304959
/workspace/coverage/cover_reg_top/26.hmac_intr_test.2563262790
/workspace/coverage/cover_reg_top/27.hmac_intr_test.2806765286
/workspace/coverage/cover_reg_top/28.hmac_intr_test.1173417853
/workspace/coverage/cover_reg_top/29.hmac_intr_test.3672376670
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3336577516
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.379374571
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1563300794
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3464041819
/workspace/coverage/cover_reg_top/3.hmac_intr_test.1267349611
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1733894506
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.1749091553
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.544461141
/workspace/coverage/cover_reg_top/30.hmac_intr_test.1613197527
/workspace/coverage/cover_reg_top/31.hmac_intr_test.3505758122
/workspace/coverage/cover_reg_top/32.hmac_intr_test.1897051072
/workspace/coverage/cover_reg_top/33.hmac_intr_test.735757991
/workspace/coverage/cover_reg_top/35.hmac_intr_test.3493115878
/workspace/coverage/cover_reg_top/36.hmac_intr_test.2917888243
/workspace/coverage/cover_reg_top/37.hmac_intr_test.3504724497
/workspace/coverage/cover_reg_top/38.hmac_intr_test.398768138
/workspace/coverage/cover_reg_top/39.hmac_intr_test.3391128593
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.257222721
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2161345848
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3977238106
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2064433716
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.1707999393
/workspace/coverage/cover_reg_top/4.hmac_intr_test.3241995308
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1721001782
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.1396326506
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.194494051
/workspace/coverage/cover_reg_top/40.hmac_intr_test.2078299642
/workspace/coverage/cover_reg_top/41.hmac_intr_test.2516797506
/workspace/coverage/cover_reg_top/42.hmac_intr_test.1429533762
/workspace/coverage/cover_reg_top/43.hmac_intr_test.610521574
/workspace/coverage/cover_reg_top/44.hmac_intr_test.1977695130
/workspace/coverage/cover_reg_top/45.hmac_intr_test.1186614565
/workspace/coverage/cover_reg_top/46.hmac_intr_test.2934927933
/workspace/coverage/cover_reg_top/47.hmac_intr_test.1953804873
/workspace/coverage/cover_reg_top/48.hmac_intr_test.689533985
/workspace/coverage/cover_reg_top/49.hmac_intr_test.310727632
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.621447027
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.3164736354
/workspace/coverage/cover_reg_top/5.hmac_intr_test.3181220768
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1975616358
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.2944544961
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1757616591
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1593404025
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.603042478
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1373878699
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.2759828322
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.799658364
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1863977541
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.1358063810
/workspace/coverage/cover_reg_top/7.hmac_intr_test.467429846
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1324878523
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.3441491629
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.640514682
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.384223903
/workspace/coverage/cover_reg_top/8.hmac_intr_test.3646127776
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2407069472
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.2564385001
/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1289260088
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3774979453
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.1835231099
/workspace/coverage/cover_reg_top/9.hmac_intr_test.4023109517
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3248341093
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.4023377536
/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.392124571
/workspace/coverage/default/0.hmac_alert_test.751055519
/workspace/coverage/default/0.hmac_back_pressure.110173560
/workspace/coverage/default/0.hmac_burst_wr.2152766309
/workspace/coverage/default/0.hmac_datapath_stress.1519148217
/workspace/coverage/default/0.hmac_error.2982253594
/workspace/coverage/default/0.hmac_long_msg.917177807
/workspace/coverage/default/0.hmac_sec_cm.3933796011
/workspace/coverage/default/0.hmac_smoke.398131938
/workspace/coverage/default/0.hmac_stress_all.1478713037
/workspace/coverage/default/0.hmac_test_hmac_vectors.2785939995
/workspace/coverage/default/0.hmac_test_sha_vectors.532594604
/workspace/coverage/default/0.hmac_wipe_secret.3940682650
/workspace/coverage/default/1.hmac_alert_test.2168980333
/workspace/coverage/default/1.hmac_back_pressure.1976212351
/workspace/coverage/default/1.hmac_burst_wr.3125429623
/workspace/coverage/default/1.hmac_datapath_stress.3596344223
/workspace/coverage/default/1.hmac_error.492577119
/workspace/coverage/default/1.hmac_long_msg.2138892932
/workspace/coverage/default/1.hmac_sec_cm.3841255284
/workspace/coverage/default/1.hmac_smoke.3262420631
/workspace/coverage/default/1.hmac_stress_all.605280393
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1084924638
/workspace/coverage/default/1.hmac_test_hmac_vectors.630705280
/workspace/coverage/default/1.hmac_test_sha_vectors.906583860
/workspace/coverage/default/1.hmac_wipe_secret.2743050477
/workspace/coverage/default/10.hmac_alert_test.2414351880
/workspace/coverage/default/10.hmac_back_pressure.1048973598
/workspace/coverage/default/10.hmac_burst_wr.1574213451
/workspace/coverage/default/10.hmac_datapath_stress.1501622937
/workspace/coverage/default/10.hmac_error.2076477352
/workspace/coverage/default/10.hmac_long_msg.454822198
/workspace/coverage/default/10.hmac_smoke.1922242784
/workspace/coverage/default/10.hmac_stress_all.3960998706
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.43108222
/workspace/coverage/default/10.hmac_test_hmac_vectors.866457788
/workspace/coverage/default/10.hmac_test_sha_vectors.2684332549
/workspace/coverage/default/10.hmac_wipe_secret.1486216320
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1767562823
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.964516633
/workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1306971861
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1831658116
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.3557959453
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3022607917
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1953056561
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.898652498
/workspace/coverage/default/11.hmac_alert_test.1518840463
/workspace/coverage/default/11.hmac_back_pressure.4268700815
/workspace/coverage/default/11.hmac_burst_wr.2478546658
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/workspace/coverage/default/7.hmac_stress_all.1562378793
/workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2215104040
/workspace/coverage/default/7.hmac_test_hmac_vectors.2040217433
/workspace/coverage/default/7.hmac_test_sha_vectors.2585636489
/workspace/coverage/default/7.hmac_wipe_secret.1538443009
/workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2858132201
/workspace/coverage/default/71.hmac_stress_all_with_rand_reset.802973215
/workspace/coverage/default/72.hmac_stress_all_with_rand_reset.1310838073
/workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2515140724
/workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3200231589
/workspace/coverage/default/75.hmac_stress_all_with_rand_reset.4016850134
/workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3089110587
/workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1947429885
/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.4262371710
/workspace/coverage/default/8.hmac_alert_test.3933961614
/workspace/coverage/default/8.hmac_back_pressure.2095269776
/workspace/coverage/default/8.hmac_burst_wr.3192052057
/workspace/coverage/default/8.hmac_datapath_stress.974730261
/workspace/coverage/default/8.hmac_error.1906580010
/workspace/coverage/default/8.hmac_long_msg.539174834
/workspace/coverage/default/8.hmac_smoke.207917980
/workspace/coverage/default/8.hmac_stress_all.147021848
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2432344953
/workspace/coverage/default/8.hmac_test_hmac_vectors.1227737146
/workspace/coverage/default/8.hmac_test_sha_vectors.28694422
/workspace/coverage/default/8.hmac_wipe_secret.3734285852
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1041952113
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.389984806
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.845640907
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3257045399
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.2946263921
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.448675541
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.1358819920
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3291168150
/workspace/coverage/default/9.hmac_alert_test.3786875020
/workspace/coverage/default/9.hmac_back_pressure.624428836
/workspace/coverage/default/9.hmac_burst_wr.2534542893
/workspace/coverage/default/9.hmac_datapath_stress.67996280
/workspace/coverage/default/9.hmac_error.4280280150
/workspace/coverage/default/9.hmac_long_msg.1508248298
/workspace/coverage/default/9.hmac_smoke.3633757014
/workspace/coverage/default/9.hmac_stress_all.1097846269
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.4162313277
/workspace/coverage/default/9.hmac_test_hmac_vectors.1083417603
/workspace/coverage/default/9.hmac_wipe_secret.2535259979
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3683017214
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1235097479
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.595240798
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.731031671
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.2927005396
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2167880638
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1616737249
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2474398628
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1951616500



Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T14 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.700451074 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:38 PM PST 24 109870306 ps
T15 /workspace/coverage/cover_reg_top/34.hmac_intr_test.444164241 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:01 PM PST 24 11621423 ps
T16 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1173417853 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:55 PM PST 24 13676360 ps
T17 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3574765376 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:39 PM PST 24 171712918 ps
T18 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2827856369 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:41 PM PST 24 54693500 ps
T19 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3241995308 Feb 04 12:45:38 PM PST 24 Feb 04 12:45:42 PM PST 24 28215034 ps
T20 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4289284838 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 222165010 ps
T21 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.194494051 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:40 PM PST 24 113231287 ps
T22 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3922793480 Feb 04 12:45:40 PM PST 24 Feb 04 12:45:43 PM PST 24 29905517 ps
T23 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3351298386 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:57 PM PST 24 28048378 ps
T69 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3181220768 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:43 PM PST 24 16821816 ps
T72 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1613197527 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 37736767 ps
T73 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1077219077 Feb 04 12:45:59 PM PST 24 Feb 04 12:46:06 PM PST 24 36754992 ps
T74 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3339244018 Feb 04 12:45:11 PM PST 24 Feb 04 12:45:14 PM PST 24 357134018 ps
T87 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1186614565 Feb 04 12:45:56 PM PST 24 Feb 04 12:46:04 PM PST 24 15477638 ps
T66 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2394633450 Feb 04 12:45:50 PM PST 24 Feb 04 12:45:56 PM PST 24 1105308561 ps
T65 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2832427884 Feb 04 12:45:11 PM PST 24 Feb 04 12:45:12 PM PST 24 18668868 ps
T24 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3464041819 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:43 PM PST 24 15460440 ps
T81 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.648378708 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:39 PM PST 24 34508804 ps
T88 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3884142343 Feb 04 12:45:52 PM PST 24 Feb 04 12:45:56 PM PST 24 23814913 ps
T82 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4195394669 Feb 04 12:44:53 PM PST 24 Feb 04 12:44:55 PM PST 24 31710197 ps
T83 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1835231099 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 47635335 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1733894506 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:38 PM PST 24 126362918 ps
T94 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1181920453 Feb 04 12:45:52 PM PST 24 Feb 04 12:45:56 PM PST 24 22655183 ps
T70 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2046275133 Feb 04 12:45:18 PM PST 24 Feb 04 12:45:21 PM PST 24 55087373 ps
T84 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2867543360 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 86756283 ps
T25 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1396326506 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:34 PM PST 24 187072684 ps
T158 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2917888243 Feb 04 12:45:57 PM PST 24 Feb 04 12:46:06 PM PST 24 45090343 ps
T26 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1465659461 Feb 04 12:45:48 PM PST 24 Feb 04 12:45:53 PM PST 24 31293747 ps
T27 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.922976875 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:44 PM PST 24 220675358 ps
T28 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1614350497 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:38 PM PST 24 115820946 ps
T155 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.638759983 Feb 04 12:44:54 PM PST 24 Feb 04 12:44:56 PM PST 24 50379845 ps
T29 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3774979453 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:39 PM PST 24 16676241 ps
T71 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.721256598 Feb 04 12:45:52 PM PST 24 Feb 04 12:45:56 PM PST 24 154931537 ps
T159 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1897051072 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 21325068 ps
T75 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.463731571 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:03 PM PST 24 139388551 ps
T160 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3031304959 Feb 04 12:45:50 PM PST 24 Feb 04 12:45:54 PM PST 24 14921133 ps
T30 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1863977541 Feb 04 12:45:32 PM PST 24 Feb 04 12:45:36 PM PST 24 46272407 ps
T85 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.334946431 Feb 04 12:45:45 PM PST 24 Feb 04 12:45:46 PM PST 24 16244504 ps
T161 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3956547832 Feb 04 12:45:40 PM PST 24 Feb 04 12:45:43 PM PST 24 34157816 ps
T162 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.379374571 Feb 04 12:45:30 PM PST 24 Feb 04 12:45:40 PM PST 24 3116315814 ps
T31 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2759828322 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:42 PM PST 24 65871337 ps
T163 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3646127776 Feb 04 12:45:42 PM PST 24 Feb 04 12:45:45 PM PST 24 13602386 ps
T164 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.426396300 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:38 PM PST 24 34413547 ps
T76 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1771702766 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:34 PM PST 24 122337072 ps
T165 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2701888591 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:40 PM PST 24 45349576 ps
T166 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4250876041 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 240214614 ps
T167 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1417326984 Feb 04 12:45:52 PM PST 24 Feb 04 12:45:56 PM PST 24 13794613 ps
T168 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1078958910 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 101906855 ps
T77 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3650052863 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:38 PM PST 24 115269121 ps
T86 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3261262254 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:41 PM PST 24 12756920 ps
T169 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1267349611 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:36 PM PST 24 23813747 ps
T78 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2534659031 Feb 04 12:45:49 PM PST 24 Feb 04 12:45:55 PM PST 24 438384379 ps
T170 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1784397882 Feb 04 12:45:38 PM PST 24 Feb 04 12:45:42 PM PST 24 59646110 ps
T171 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1388601443 Feb 04 12:45:17 PM PST 24 Feb 04 12:45:20 PM PST 24 127156387 ps
T156 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3512769833 Feb 04 12:45:45 PM PST 24 Feb 04 12:45:48 PM PST 24 33686412 ps
T172 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1427464108 Feb 04 12:45:18 PM PST 24 Feb 04 12:45:21 PM PST 24 41238882 ps
T173 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3230298407 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 722164045 ps
T79 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1403084770 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:02 PM PST 24 90117239 ps
T174 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.384223903 Feb 04 12:45:38 PM PST 24 Feb 04 12:45:42 PM PST 24 114776573 ps
T175 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3493115878 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:02 PM PST 24 37194504 ps
T176 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.518764368 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:38 PM PST 24 36475433 ps
T177 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2722095537 Feb 04 12:45:49 PM PST 24 Feb 04 12:45:53 PM PST 24 36496736 ps
T90 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2839756141 Feb 04 12:45:18 PM PST 24 Feb 04 12:45:20 PM PST 24 28225173 ps
T102 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1231477549 Feb 04 12:45:40 PM PST 24 Feb 04 12:45:43 PM PST 24 22219188 ps
T68 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.351635636 Feb 04 12:45:48 PM PST 24 Feb 04 12:45:53 PM PST 24 219048898 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2135405905 Feb 04 12:45:08 PM PST 24 Feb 04 12:45:15 PM PST 24 360048352 ps
T80 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1749091553 Feb 04 12:45:16 PM PST 24 Feb 04 12:45:22 PM PST 24 111222007 ps
T178 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1953804873 Feb 04 12:46:03 PM PST 24 Feb 04 12:46:09 PM PST 24 46825496 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1408633771 Feb 04 12:45:02 PM PST 24 Feb 04 12:45:08 PM PST 24 28698023 ps
T179 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2161345848 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:36 PM PST 24 788360413 ps
T180 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1324878523 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:43 PM PST 24 46790056 ps
T181 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3787730389 Feb 04 12:45:59 PM PST 24 Feb 04 12:46:06 PM PST 24 37993760 ps
T182 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3672376670 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:02 PM PST 24 47859034 ps
T183 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1905072184 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:56 PM PST 24 41497692 ps
T184 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2564217429 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:41 PM PST 24 73214178 ps
T185 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1159675937 Feb 04 12:45:13 PM PST 24 Feb 04 12:45:16 PM PST 24 162753685 ps
T186 /workspace/coverage/cover_reg_top/43.hmac_intr_test.610521574 Feb 04 12:46:01 PM PST 24 Feb 04 12:46:06 PM PST 24 30151479 ps
T187 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3454886695 Feb 04 12:45:40 PM PST 24 Feb 04 12:45:44 PM PST 24 72332227 ps
T188 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2806765286 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:57 PM PST 24 86174219 ps
T189 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1393271419 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:56 PM PST 24 38823643 ps
T190 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.722247860 Feb 04 12:45:48 PM PST 24 Feb 04 12:45:52 PM PST 24 37235149 ps
T191 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.392124571 Feb 04 12:45:38 PM PST 24 Feb 04 12:45:43 PM PST 24 64873666 ps
T192 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1983241636 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:40 PM PST 24 1249857778 ps
T193 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3505758122 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:55 PM PST 24 21342244 ps
T153 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1289260088 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:44 PM PST 24 79610554 ps
T194 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2407069472 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 130997019 ps
T195 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1975616358 Feb 04 12:45:32 PM PST 24 Feb 04 12:45:37 PM PST 24 67605695 ps
T196 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2149355761 Feb 04 12:45:13 PM PST 24 Feb 04 12:45:15 PM PST 24 54676962 ps
T197 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3391128593 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 17197975 ps
T198 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3977238106 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:33 PM PST 24 21162119 ps
T147 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1325329755 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:40 PM PST 24 287146148 ps
T199 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2769321355 Feb 04 12:45:01 PM PST 24 Feb 04 12:45:16 PM PST 24 654034901 ps
T151 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2984711264 Feb 04 12:45:50 PM PST 24 Feb 04 12:45:55 PM PST 24 68308063 ps
T200 /workspace/coverage/cover_reg_top/20.hmac_intr_test.908083941 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:57 PM PST 24 48114760 ps
T157 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.827152149 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:57 PM PST 24 31378772 ps
T201 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3157255174 Feb 04 12:44:54 PM PST 24 Feb 04 12:44:55 PM PST 24 68547497 ps
T202 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2934927933 Feb 04 12:45:57 PM PST 24 Feb 04 12:46:06 PM PST 24 14473879 ps
T203 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4023109517 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:39 PM PST 24 30393173 ps
T204 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2064433716 Feb 04 12:45:40 PM PST 24 Feb 04 12:49:30 PM PST 24 35526863597 ps
T205 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2078299642 Feb 04 12:45:57 PM PST 24 Feb 04 12:46:06 PM PST 24 12546662 ps
T206 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2564385001 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:39 PM PST 24 64730168 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3336577516 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:38 PM PST 24 2132128169 ps
T207 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1757616591 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:41 PM PST 24 793026139 ps
T208 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3759373450 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 73110957 ps
T96 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1563300794 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:37 PM PST 24 17168088 ps
T209 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2516797506 Feb 04 12:45:57 PM PST 24 Feb 04 12:46:06 PM PST 24 30410910 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1707999393 Feb 04 12:45:28 PM PST 24 Feb 04 12:45:29 PM PST 24 14357826 ps
T210 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1093603615 Feb 04 12:44:53 PM PST 24 Feb 04 12:44:54 PM PST 24 12544302 ps
T211 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1834635751 Feb 04 12:45:16 PM PST 24 Feb 04 12:45:21 PM PST 24 120798313 ps
T212 /workspace/coverage/cover_reg_top/16.hmac_intr_test.953642946 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:54 PM PST 24 56583740 ps
T213 /workspace/coverage/cover_reg_top/49.hmac_intr_test.310727632 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:06 PM PST 24 12031038 ps
T1 /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1084924638 Feb 04 01:32:19 PM PST 24 Feb 04 01:40:32 PM PST 24 185308916626 ps
T2 /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2029456434 Feb 04 01:35:42 PM PST 24 Feb 04 01:45:18 PM PST 24 30830251196 ps
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