Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3922 1 T15 7 T16 7 T18 10
all_values[1] 3922 1 T15 7 T16 7 T18 10
all_values[2] 3922 1 T15 7 T16 7 T18 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5567 1 T15 13 T16 11 T18 11
auto[1] 6199 1 T15 8 T16 10 T18 19


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4427 1 T15 9 T16 10 T18 11
auto[1] 7339 1 T15 12 T16 11 T18 19


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6782 1 T15 14 T16 13 T18 15
auto[1] 4984 1 T15 7 T16 8 T18 15


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 715 1 T15 2 T16 2 T19 3
all_values[0] auto[0] auto[0] auto[1] 353 1 T15 1 T18 1 T69 1
all_values[0] auto[0] auto[1] auto[0] 844 1 T15 2 T18 3 T19 1
all_values[0] auto[0] auto[1] auto[1] 394 1 T16 2 T18 2 T19 2
all_values[0] auto[1] auto[0] auto[1] 727 1 T15 2 T16 1 T18 2
all_values[0] auto[1] auto[1] auto[1] 889 1 T16 2 T18 2 T19 4
all_values[1] auto[0] auto[0] auto[0] 698 1 T15 1 T16 1 T18 1
all_values[1] auto[0] auto[0] auto[1] 411 1 T15 1 T19 1 T69 1
all_values[1] auto[0] auto[1] auto[0] 761 1 T15 1 T16 1 T18 4
all_values[1] auto[0] auto[1] auto[1] 390 1 T15 1 T16 1 T18 1
all_values[1] auto[1] auto[0] auto[1] 808 1 T15 2 T16 2 T18 2
all_values[1] auto[1] auto[1] auto[1] 854 1 T15 1 T16 2 T18 2
all_values[2] auto[0] auto[0] auto[0] 648 1 T15 2 T16 4 T18 1
all_values[2] auto[0] auto[0] auto[1] 381 1 T15 1 T69 1 T72 2
all_values[2] auto[0] auto[1] auto[0] 761 1 T15 1 T16 2 T18 2
all_values[2] auto[0] auto[1] auto[1] 426 1 T15 1 T19 1 T69 1
all_values[2] auto[1] auto[0] auto[1] 826 1 T15 1 T16 1 T18 4
all_values[2] auto[1] auto[1] auto[1] 880 1 T15 1 T18 3 T19 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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