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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.92 99.55 98.75 100.00 96.30 98.47 99.49 99.86


Total test records in report: 912
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T763 /workspace/coverage/default/17.hmac_stress_all.271677789 Feb 04 01:33:11 PM PST 24 Feb 04 01:54:23 PM PST 24 209998662357 ps
T764 /workspace/coverage/default/13.hmac_burst_wr.2212900410 Feb 04 01:32:35 PM PST 24 Feb 04 01:33:50 PM PST 24 6931092541 ps
T765 /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.3454267072 Feb 04 01:36:18 PM PST 24 Feb 04 02:22:27 PM PST 24 680988551499 ps
T766 /workspace/coverage/default/38.hmac_burst_wr.2993918341 Feb 04 01:34:55 PM PST 24 Feb 04 01:35:21 PM PST 24 4955865332 ps
T767 /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.415497721 Feb 04 01:32:10 PM PST 24 Feb 04 02:10:55 PM PST 24 83196745179 ps
T768 /workspace/coverage/default/46.hmac_alert_test.4077923471 Feb 04 01:35:34 PM PST 24 Feb 04 01:35:43 PM PST 24 39033189 ps
T769 /workspace/coverage/default/38.hmac_test_sha_vectors.651277689 Feb 04 01:34:59 PM PST 24 Feb 04 01:42:36 PM PST 24 158227330232 ps
T770 /workspace/coverage/default/47.hmac_alert_test.4128287674 Feb 04 01:35:31 PM PST 24 Feb 04 01:35:41 PM PST 24 175242252 ps
T771 /workspace/coverage/default/20.hmac_long_msg.327472049 Feb 04 01:33:09 PM PST 24 Feb 04 01:33:57 PM PST 24 2455641273 ps
T772 /workspace/coverage/default/46.hmac_burst_wr.2695453410 Feb 04 01:35:32 PM PST 24 Feb 04 01:36:23 PM PST 24 1777410564 ps
T773 /workspace/coverage/default/13.hmac_error.4051355160 Feb 04 01:32:38 PM PST 24 Feb 04 01:34:43 PM PST 24 54939053741 ps
T774 /workspace/coverage/default/45.hmac_back_pressure.3366567583 Feb 04 01:35:22 PM PST 24 Feb 04 01:35:59 PM PST 24 942176003 ps
T775 /workspace/coverage/default/48.hmac_long_msg.1226186938 Feb 04 01:35:34 PM PST 24 Feb 04 01:35:46 PM PST 24 1371117903 ps
T776 /workspace/coverage/default/30.hmac_wipe_secret.800931792 Feb 04 01:33:59 PM PST 24 Feb 04 01:34:54 PM PST 24 19869646934 ps
T777 /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.4016850134 Feb 04 01:35:46 PM PST 24 Feb 04 01:43:09 PM PST 24 122535111483 ps
T125 /workspace/coverage/default/12.hmac_stress_all.2072118361 Feb 04 01:32:39 PM PST 24 Feb 04 01:55:52 PM PST 24 79881392492 ps
T778 /workspace/coverage/default/23.hmac_test_hmac_vectors.2203602113 Feb 04 01:33:27 PM PST 24 Feb 04 01:33:37 PM PST 24 110203184 ps
T779 /workspace/coverage/default/44.hmac_smoke.805234127 Feb 04 01:35:22 PM PST 24 Feb 04 01:35:31 PM PST 24 937076884 ps
T780 /workspace/coverage/default/8.hmac_smoke.207917980 Feb 04 01:32:19 PM PST 24 Feb 04 01:32:23 PM PST 24 180219569 ps
T781 /workspace/coverage/default/14.hmac_error.3930809839 Feb 04 01:32:54 PM PST 24 Feb 04 01:34:13 PM PST 24 1559079683 ps
T782 /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.43108222 Feb 04 01:32:23 PM PST 24 Feb 04 01:43:35 PM PST 24 58286483031 ps
T783 /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.192894728 Feb 04 01:36:18 PM PST 24 Feb 04 01:41:28 PM PST 24 71057659558 ps
T784 /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.3819971054 Feb 04 01:35:35 PM PST 24 Feb 04 02:31:52 PM PST 24 82469083905 ps
T785 /workspace/coverage/default/13.hmac_test_hmac_vectors.4072636749 Feb 04 01:32:39 PM PST 24 Feb 04 01:32:45 PM PST 24 154479071 ps
T786 /workspace/coverage/default/7.hmac_long_msg.66587048 Feb 04 01:32:07 PM PST 24 Feb 04 01:32:57 PM PST 24 7560651676 ps
T787 /workspace/coverage/default/8.hmac_long_msg.539174834 Feb 04 01:32:16 PM PST 24 Feb 04 01:32:42 PM PST 24 2000755149 ps
T788 /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.3363085667 Feb 04 01:35:33 PM PST 24 Feb 04 02:13:25 PM PST 24 304681926971 ps
T789 /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1942339301 Feb 04 01:36:18 PM PST 24 Feb 04 01:45:48 PM PST 24 58442282482 ps
T790 /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.751263916 Feb 04 01:36:00 PM PST 24 Feb 04 02:01:56 PM PST 24 495178328078 ps
T791 /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.2269863192 Feb 04 01:33:18 PM PST 24 Feb 04 01:47:16 PM PST 24 209795023910 ps
T792 /workspace/coverage/default/2.hmac_back_pressure.2422704129 Feb 04 01:32:05 PM PST 24 Feb 04 01:32:46 PM PST 24 2807866453 ps
T793 /workspace/coverage/default/21.hmac_stress_all.3564643027 Feb 04 01:33:29 PM PST 24 Feb 04 01:48:50 PM PST 24 55356983213 ps
T794 /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1767562823 Feb 04 01:35:43 PM PST 24 Feb 04 02:12:43 PM PST 24 231144386414 ps
T795 /workspace/coverage/default/46.hmac_smoke.859065083 Feb 04 01:35:23 PM PST 24 Feb 04 01:35:31 PM PST 24 49956723 ps
T796 /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.731031671 Feb 04 01:35:52 PM PST 24 Feb 04 01:57:22 PM PST 24 580312020794 ps
T797 /workspace/coverage/default/21.hmac_burst_wr.3956191882 Feb 04 01:33:27 PM PST 24 Feb 04 01:33:55 PM PST 24 1424299409 ps
T798 /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.1610490689 Feb 04 01:33:36 PM PST 24 Feb 04 01:52:27 PM PST 24 991945082710 ps
T799 /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.528594334 Feb 04 01:37:45 PM PST 24 Feb 04 01:48:35 PM PST 24 47177979393 ps
T800 /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1947429885 Feb 04 01:35:46 PM PST 24 Feb 04 02:04:19 PM PST 24 175455139331 ps
T801 /workspace/coverage/default/42.hmac_burst_wr.460177070 Feb 04 01:35:08 PM PST 24 Feb 04 01:35:29 PM PST 24 1201802484 ps
T802 /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.1514941839 Feb 04 01:36:41 PM PST 24 Feb 04 02:01:08 PM PST 24 88043349386 ps
T803 /workspace/coverage/default/18.hmac_alert_test.3260331149 Feb 04 01:33:09 PM PST 24 Feb 04 01:33:13 PM PST 24 36258399 ps
T804 /workspace/coverage/default/24.hmac_test_sha_vectors.2559922608 Feb 04 01:33:25 PM PST 24 Feb 04 01:40:18 PM PST 24 33671678091 ps
T805 /workspace/coverage/default/3.hmac_burst_wr.1345436197 Feb 04 01:32:24 PM PST 24 Feb 04 01:33:01 PM PST 24 3163798644 ps
T806 /workspace/coverage/default/36.hmac_datapath_stress.2281804712 Feb 04 01:34:26 PM PST 24 Feb 04 01:34:59 PM PST 24 656125019 ps
T807 /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3867100096 Feb 04 01:36:00 PM PST 24 Feb 04 01:56:04 PM PST 24 113961851557 ps
T808 /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.760474137 Feb 04 01:36:26 PM PST 24 Feb 04 01:41:55 PM PST 24 94258417284 ps
T809 /workspace/coverage/default/0.hmac_smoke.398131938 Feb 04 01:32:20 PM PST 24 Feb 04 01:32:23 PM PST 24 319652761 ps
T810 /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1831658116 Feb 04 01:35:45 PM PST 24 Feb 04 01:45:50 PM PST 24 74574512781 ps
T811 /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2452412463 Feb 04 01:36:16 PM PST 24 Feb 04 01:45:02 PM PST 24 32451851121 ps
T812 /workspace/coverage/default/21.hmac_back_pressure.912823618 Feb 04 01:33:21 PM PST 24 Feb 04 01:33:57 PM PST 24 3356568805 ps
T813 /workspace/coverage/default/5.hmac_smoke.1687526328 Feb 04 01:32:02 PM PST 24 Feb 04 01:32:04 PM PST 24 271085842 ps
T814 /workspace/coverage/default/48.hmac_wipe_secret.3596731549 Feb 04 01:35:38 PM PST 24 Feb 04 01:35:51 PM PST 24 557533490 ps
T815 /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2432344953 Feb 04 01:32:25 PM PST 24 Feb 04 01:42:06 PM PST 24 151615409866 ps
T816 /workspace/coverage/default/33.hmac_wipe_secret.4025150743 Feb 04 01:34:16 PM PST 24 Feb 04 01:35:15 PM PST 24 1636835213 ps
T138 /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.3503931398 Feb 04 01:37:45 PM PST 24 Feb 04 02:13:12 PM PST 24 2070472105019 ps
T817 /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.3213213929 Feb 04 01:36:00 PM PST 24 Feb 04 02:07:03 PM PST 24 401648219415 ps
T818 /workspace/coverage/default/12.hmac_burst_wr.1664367104 Feb 04 01:32:38 PM PST 24 Feb 04 01:33:23 PM PST 24 6905942786 ps
T819 /workspace/coverage/default/19.hmac_error.300274991 Feb 04 01:33:12 PM PST 24 Feb 04 01:35:46 PM PST 24 17290785269 ps
T820 /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.3091139113 Feb 04 01:36:02 PM PST 24 Feb 04 02:25:39 PM PST 24 227421733479 ps
T821 /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3787102477 Feb 04 01:36:28 PM PST 24 Feb 04 01:46:33 PM PST 24 48461558091 ps
T822 /workspace/coverage/default/11.hmac_alert_test.1518840463 Feb 04 01:32:40 PM PST 24 Feb 04 01:32:44 PM PST 24 41172097 ps
T823 /workspace/coverage/default/33.hmac_smoke.300548384 Feb 04 01:34:16 PM PST 24 Feb 04 01:34:22 PM PST 24 783582874 ps
T824 /workspace/coverage/default/33.hmac_burst_wr.2246401822 Feb 04 01:34:15 PM PST 24 Feb 04 01:34:32 PM PST 24 2698153572 ps
T825 /workspace/coverage/default/42.hmac_stress_all.3863206513 Feb 04 01:35:08 PM PST 24 Feb 04 01:51:58 PM PST 24 19818126767 ps
T826 /workspace/coverage/default/31.hmac_smoke.2920064757 Feb 04 01:34:18 PM PST 24 Feb 04 01:34:22 PM PST 24 25429234 ps
T827 /workspace/coverage/default/6.hmac_datapath_stress.4059051666 Feb 04 01:32:07 PM PST 24 Feb 04 01:34:36 PM PST 24 11594878075 ps
T828 /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3291168150 Feb 04 01:35:44 PM PST 24 Feb 04 02:41:53 PM PST 24 98258181224 ps
T829 /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.389984806 Feb 04 01:35:44 PM PST 24 Feb 04 02:05:41 PM PST 24 152178167891 ps
T830 /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.2240384392 Feb 04 01:36:45 PM PST 24 Feb 04 01:58:57 PM PST 24 630594518015 ps
T831 /workspace/coverage/default/24.hmac_stress_all.104290005 Feb 04 01:33:27 PM PST 24 Feb 04 01:39:21 PM PST 24 18351511737 ps
T832 /workspace/coverage/default/44.hmac_datapath_stress.400365968 Feb 04 01:35:26 PM PST 24 Feb 04 01:36:53 PM PST 24 7640790151 ps
T833 /workspace/coverage/default/24.hmac_back_pressure.3082463043 Feb 04 01:33:29 PM PST 24 Feb 04 01:34:33 PM PST 24 1728384670 ps
T834 /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2474398628 Feb 04 01:35:41 PM PST 24 Feb 04 01:45:11 PM PST 24 151370547763 ps
T835 /workspace/coverage/default/27.hmac_test_hmac_vectors.1301648074 Feb 04 01:33:39 PM PST 24 Feb 04 01:33:42 PM PST 24 43315838 ps
T836 /workspace/coverage/default/4.hmac_error.1325231996 Feb 04 01:31:53 PM PST 24 Feb 04 01:34:17 PM PST 24 11905323020 ps
T837 /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3257045399 Feb 04 01:35:43 PM PST 24 Feb 04 01:38:54 PM PST 24 22426073095 ps
T838 /workspace/coverage/default/41.hmac_error.1950182647 Feb 04 01:34:57 PM PST 24 Feb 04 01:36:31 PM PST 24 1772611534 ps
T839 /workspace/coverage/default/25.hmac_wipe_secret.3552598093 Feb 04 01:33:41 PM PST 24 Feb 04 01:34:46 PM PST 24 26806329905 ps
T840 /workspace/coverage/default/29.hmac_datapath_stress.3975760766 Feb 04 01:34:04 PM PST 24 Feb 04 01:35:53 PM PST 24 2434636722 ps
T841 /workspace/coverage/default/28.hmac_datapath_stress.1201966211 Feb 04 01:33:37 PM PST 24 Feb 04 01:35:11 PM PST 24 3638873261 ps
T842 /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1041952113 Feb 04 01:35:45 PM PST 24 Feb 04 01:44:30 PM PST 24 40568376279 ps
T843 /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.1491716032 Feb 04 01:35:38 PM PST 24 Feb 04 02:06:31 PM PST 24 108169116030 ps
T844 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.2196175651 Feb 04 01:36:15 PM PST 24 Feb 04 02:08:41 PM PST 24 260612015414 ps
T845 /workspace/coverage/default/15.hmac_test_hmac_vectors.1203236104 Feb 04 01:32:55 PM PST 24 Feb 04 01:32:58 PM PST 24 156402164 ps
T846 /workspace/coverage/default/13.hmac_datapath_stress.3748070640 Feb 04 01:32:37 PM PST 24 Feb 04 01:34:06 PM PST 24 6203371147 ps
T847 /workspace/coverage/default/44.hmac_error.1219897565 Feb 04 01:35:22 PM PST 24 Feb 04 01:36:07 PM PST 24 1551913318 ps
T848 /workspace/coverage/default/3.hmac_long_msg.337305702 Feb 04 01:32:24 PM PST 24 Feb 04 01:33:55 PM PST 24 5028455690 ps
T849 /workspace/coverage/default/7.hmac_wipe_secret.1538443009 Feb 04 01:32:08 PM PST 24 Feb 04 01:32:28 PM PST 24 474192067 ps
T850 /workspace/coverage/default/24.hmac_burst_wr.2177363562 Feb 04 01:33:30 PM PST 24 Feb 04 01:34:14 PM PST 24 2037639971 ps
T851 /workspace/coverage/default/4.hmac_datapath_stress.3574790473 Feb 04 01:31:54 PM PST 24 Feb 04 01:33:33 PM PST 24 1940464459 ps
T852 /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.3674481387 Feb 04 01:36:13 PM PST 24 Feb 04 02:02:20 PM PST 24 142130638478 ps
T853 /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.38077748 Feb 04 01:35:38 PM PST 24 Feb 04 01:51:39 PM PST 24 66995618192 ps
T854 /workspace/coverage/default/21.hmac_test_hmac_vectors.2520416818 Feb 04 01:33:26 PM PST 24 Feb 04 01:33:37 PM PST 24 132814750 ps
T855 /workspace/coverage/default/30.hmac_stress_all.3132395298 Feb 04 01:34:01 PM PST 24 Feb 04 01:42:52 PM PST 24 55358745320 ps
T856 /workspace/coverage/default/49.hmac_smoke.3435870374 Feb 04 01:35:33 PM PST 24 Feb 04 01:35:44 PM PST 24 134297160 ps
T857 /workspace/coverage/default/7.hmac_test_hmac_vectors.2040217433 Feb 04 01:32:18 PM PST 24 Feb 04 01:32:22 PM PST 24 106123929 ps
T858 /workspace/coverage/default/40.hmac_back_pressure.1493425857 Feb 04 01:34:59 PM PST 24 Feb 04 01:35:43 PM PST 24 5954658786 ps
T859 /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2090131485 Feb 04 01:36:29 PM PST 24 Feb 04 01:40:20 PM PST 24 60232500933 ps
T860 /workspace/coverage/default/30.hmac_smoke.4208780279 Feb 04 01:34:00 PM PST 24 Feb 04 01:34:04 PM PST 24 228611321 ps
T861 /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3610369407 Feb 04 01:33:15 PM PST 24 Feb 04 01:40:06 PM PST 24 96544714397 ps
T862 /workspace/coverage/default/21.hmac_test_sha_vectors.3961392672 Feb 04 01:33:25 PM PST 24 Feb 04 01:39:38 PM PST 24 17801769870 ps
T863 /workspace/coverage/default/41.hmac_test_sha_vectors.1727351755 Feb 04 01:35:00 PM PST 24 Feb 04 01:41:24 PM PST 24 15221778130 ps
T864 /workspace/coverage/default/18.hmac_test_sha_vectors.3957788331 Feb 04 01:33:09 PM PST 24 Feb 04 01:40:14 PM PST 24 24281366877 ps
T865 /workspace/coverage/default/28.hmac_back_pressure.278650173 Feb 04 01:33:36 PM PST 24 Feb 04 01:34:12 PM PST 24 4198605571 ps
T866 /workspace/coverage/default/34.hmac_test_sha_vectors.2013386138 Feb 04 01:34:28 PM PST 24 Feb 04 01:41:40 PM PST 24 161744158731 ps
T867 /workspace/coverage/default/17.hmac_test_sha_vectors.843344106 Feb 04 01:33:12 PM PST 24 Feb 04 01:39:34 PM PST 24 47130293007 ps
T868 /workspace/coverage/default/27.hmac_long_msg.6119488 Feb 04 01:33:33 PM PST 24 Feb 04 01:34:49 PM PST 24 2957677343 ps
T869 /workspace/coverage/default/14.hmac_wipe_secret.2103014685 Feb 04 01:33:00 PM PST 24 Feb 04 01:34:21 PM PST 24 4355465109 ps
T870 /workspace/coverage/cover_reg_top/38.hmac_intr_test.398768138 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:03 PM PST 24 43100611 ps
T154 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.130109588 Feb 04 12:45:17 PM PST 24 Feb 04 12:45:21 PM PST 24 214449613 ps
T871 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.988545849 Feb 04 12:45:06 PM PST 24 Feb 04 12:45:08 PM PST 24 16007042 ps
T872 /workspace/coverage/cover_reg_top/2.hmac_intr_test.598435157 Feb 04 12:45:21 PM PST 24 Feb 04 12:45:26 PM PST 24 20599656 ps
T873 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.640514682 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:37 PM PST 24 15103478 ps
T874 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4293944580 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:37 PM PST 24 74018389 ps
T875 /workspace/coverage/cover_reg_top/24.hmac_intr_test.882417297 Feb 04 12:45:50 PM PST 24 Feb 04 12:45:54 PM PST 24 19861832 ps
T876 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1373878699 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:41 PM PST 24 92178309 ps
T877 /workspace/coverage/cover_reg_top/17.hmac_intr_test.606524525 Feb 04 12:45:56 PM PST 24 Feb 04 12:46:04 PM PST 24 14508523 ps
T878 /workspace/coverage/cover_reg_top/33.hmac_intr_test.735757991 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:02 PM PST 24 12134977 ps
T879 /workspace/coverage/cover_reg_top/1.hmac_intr_test.846425083 Feb 04 12:45:12 PM PST 24 Feb 04 12:45:14 PM PST 24 16488760 ps
T67 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1379208859 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:41 PM PST 24 105069816 ps
T880 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1070989471 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:39 PM PST 24 19184518 ps
T881 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3164736354 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:40 PM PST 24 22666022 ps
T882 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.621447027 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:40 PM PST 24 77553076 ps
T148 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.799658364 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:37 PM PST 24 74656973 ps
T883 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3441491629 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:43 PM PST 24 198553519 ps
T884 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4023377536 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:39 PM PST 24 45752160 ps
T149 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.448504678 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:05 PM PST 24 169800106 ps
T885 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2966088445 Feb 04 12:45:45 PM PST 24 Feb 04 12:45:47 PM PST 24 202033624 ps
T886 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1265335448 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:44 PM PST 24 53852737 ps
T887 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.713302589 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:56 PM PST 24 27998725 ps
T888 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1391443230 Feb 04 12:45:14 PM PST 24 Feb 04 12:45:17 PM PST 24 46675595 ps
T889 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2944544961 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:37 PM PST 24 114733812 ps
T890 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2354916990 Feb 04 12:45:45 PM PST 24 Feb 04 12:45:48 PM PST 24 199364352 ps
T891 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3344495756 Feb 04 12:45:17 PM PST 24 Feb 04 12:45:26 PM PST 24 438017827 ps
T892 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1721001782 Feb 04 12:45:32 PM PST 24 Feb 04 12:45:36 PM PST 24 135798139 ps
T893 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.257222721 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:37 PM PST 24 60225400 ps
T150 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.544461141 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:39 PM PST 24 158411081 ps
T894 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4140139509 Feb 04 12:45:39 PM PST 24 Feb 04 12:45:43 PM PST 24 29152413 ps
T895 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4181080375 Feb 04 12:45:35 PM PST 24 Feb 04 01:08:52 PM PST 24 306642635891 ps
T896 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3744750211 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:36 PM PST 24 32682730 ps
T897 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1739487334 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:57 PM PST 24 11522454 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2641864088 Feb 04 12:44:54 PM PST 24 Feb 04 12:44:57 PM PST 24 109400220 ps
T898 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.13946061 Feb 04 12:45:34 PM PST 24 Feb 04 12:45:37 PM PST 24 29711641 ps
T98 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3403117616 Feb 04 12:45:15 PM PST 24 Feb 04 12:45:21 PM PST 24 751645637 ps
T99 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1358063810 Feb 04 12:45:32 PM PST 24 Feb 04 12:45:35 PM PST 24 46189790 ps
T899 /workspace/coverage/cover_reg_top/48.hmac_intr_test.689533985 Feb 04 12:45:59 PM PST 24 Feb 04 12:46:06 PM PST 24 84036298 ps
T152 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1783429746 Feb 04 12:45:33 PM PST 24 Feb 04 12:45:38 PM PST 24 198348714 ps
T900 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3986612527 Feb 04 12:45:35 PM PST 24 Feb 04 12:45:39 PM PST 24 496958653 ps
T901 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.22160999 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:40 PM PST 24 112488560 ps
T902 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.252785726 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:43 PM PST 24 218412063 ps
T903 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3504724497 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:06 PM PST 24 17270748 ps
T904 /workspace/coverage/cover_reg_top/7.hmac_intr_test.467429846 Feb 04 12:45:36 PM PST 24 Feb 04 12:45:39 PM PST 24 11910665 ps
T905 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3293033880 Feb 04 12:45:52 PM PST 24 Feb 04 12:45:57 PM PST 24 180455935 ps
T100 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1952617480 Feb 04 12:45:53 PM PST 24 Feb 04 12:45:56 PM PST 24 21542015 ps
T906 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3248341093 Feb 04 12:45:31 PM PST 24 Feb 04 12:45:35 PM PST 24 50557632 ps
T907 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1453445511 Feb 04 12:45:18 PM PST 24 Feb 04 12:45:20 PM PST 24 40936113 ps
T908 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1977695130 Feb 04 12:46:03 PM PST 24 Feb 04 12:46:09 PM PST 24 21019854 ps
T909 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.603042478 Feb 04 12:45:37 PM PST 24 Feb 04 12:45:41 PM PST 24 72344263 ps
T910 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2563262790 Feb 04 12:45:51 PM PST 24 Feb 04 12:45:55 PM PST 24 56342106 ps
T911 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1429533762 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:06 PM PST 24 33840842 ps
T912 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1593404025 Feb 04 12:45:34 PM PST 24 Feb 04 12:50:17 PM PST 24 84033994675 ps

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.700451074
Short name T14
Test name
Test status
Simulation time 109870306 ps
CPU time 3.19 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 198984 kb
Host smart-90576a96-c1e1-45bb-be47-16bc79350a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700451074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.700451074
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2029456434
Short name T2
Test name
Test status
Simulation time 30830251196 ps
CPU time 571.18 seconds
Started Feb 04 01:35:42 PM PST 24
Finished Feb 04 01:45:18 PM PST 24
Peak memory 207340 kb
Host smart-11909902-9c99-496e-b434-44d1265ca924
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029456434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.2029456434
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4289284838
Short name T20
Test name
Test status
Simulation time 222165010 ps
CPU time 1.2 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 198408 kb
Host smart-40b8e020-3a49-4c79-b63e-0062b7212457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289284838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4289284838
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.3576221938
Short name T7
Test name
Test status
Simulation time 71112689274 ps
CPU time 3652.61 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 02:36:48 PM PST 24
Peak memory 223808 kb
Host smart-38b7212e-1761-4d26-8354-00fd3e351fbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576221938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.3576221938
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2827856369
Short name T18
Test name
Test status
Simulation time 54693500 ps
CPU time 0.63 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 183992 kb
Host smart-6d537d8b-9b2b-4c34-a6d0-501f93cfe199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827856369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2827856369
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3339244018
Short name T74
Test name
Test status
Simulation time 357134018 ps
CPU time 1.87 seconds
Started Feb 04 12:45:11 PM PST 24
Finished Feb 04 12:45:14 PM PST 24
Peak memory 192288 kb
Host smart-5bd35b24-8ba4-47df-b569-f311679923e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339244018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3339244018
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3442726143
Short name T95
Test name
Test status
Simulation time 1418192884992 ps
CPU time 3363.96 seconds
Started Feb 04 01:37:43 PM PST 24
Finished Feb 04 02:33:48 PM PST 24
Peak memory 280260 kb
Host smart-f9ead323-65e5-4f9c-ba0d-932a94fa7eb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442726143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3442726143
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.994239709
Short name T51
Test name
Test status
Simulation time 83661998 ps
CPU time 0.92 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:19 PM PST 24
Peak memory 217236 kb
Host smart-5e8a73aa-7d9c-43f8-8c89-e597d3eb1417
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994239709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.994239709
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.351635636
Short name T68
Test name
Test status
Simulation time 219048898 ps
CPU time 2.21 seconds
Started Feb 04 12:45:48 PM PST 24
Finished Feb 04 12:45:53 PM PST 24
Peak memory 198496 kb
Host smart-9cb263bd-aa9e-4b7c-96d4-d11685de7d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351635636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.351635636
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2202013394
Short name T110
Test name
Test status
Simulation time 493777345744 ps
CPU time 1207.25 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:55:51 PM PST 24
Peak memory 231820 kb
Host smart-2a294793-685e-4c30-b801-61377549a743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202013394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.2202013394
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1388601443
Short name T171
Test name
Test status
Simulation time 127156387 ps
CPU time 0.87 seconds
Started Feb 04 12:45:17 PM PST 24
Finished Feb 04 12:45:20 PM PST 24
Peak memory 198596 kb
Host smart-abb9987f-01e5-44ad-a12a-6ceadf8b734e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388601443 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1388601443
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.444164241
Short name T15
Test name
Test status
Simulation time 11621423 ps
CPU time 0.56 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:01 PM PST 24
Peak memory 183944 kb
Host smart-3bda2ca8-26d3-418d-b492-5c9aa949f8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444164241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.444164241
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2483510271
Short name T429
Test name
Test status
Simulation time 315505143252 ps
CPU time 2074.04 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 02:09:03 PM PST 24
Peak memory 207304 kb
Host smart-da429ecd-f267-4056-901c-e666a5d48962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483510271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2483510271
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.648378708
Short name T81
Test name
Test status
Simulation time 34508804 ps
CPU time 0.61 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 194316 kb
Host smart-8bce243d-96b1-4e45-abc2-58cf22c20c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648378708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.648378708
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1783429746
Short name T152
Test name
Test status
Simulation time 198348714 ps
CPU time 2.32 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 198528 kb
Host smart-c9f7948e-0457-40ca-b9a7-f533caca74be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783429746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1783429746
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.4182334148
Short name T142
Test name
Test status
Simulation time 531957383313 ps
CPU time 2838.34 seconds
Started Feb 04 01:35:54 PM PST 24
Finished Feb 04 02:23:16 PM PST 24
Peak memory 251352 kb
Host smart-23a4e322-eab1-4129-9f7c-91e2a1b23715
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182334148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.4182334148
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3629475161
Short name T130
Test name
Test status
Simulation time 1058990561954 ps
CPU time 2742.69 seconds
Started Feb 04 01:33:35 PM PST 24
Finished Feb 04 02:19:22 PM PST 24
Peak memory 235892 kb
Host smart-f0dc0f2a-85ae-4969-a5b1-3e33c1540e22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629475161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3629475161
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2402450458
Short name T38
Test name
Test status
Simulation time 249546489944 ps
CPU time 1781.8 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 02:05:31 PM PST 24
Peak memory 248264 kb
Host smart-c496d78f-4b70-4ce8-a011-de2db2e4c48d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402450458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2402450458
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1159675937
Short name T185
Test name
Test status
Simulation time 162753685 ps
CPU time 2.83 seconds
Started Feb 04 12:45:13 PM PST 24
Finished Feb 04 12:45:16 PM PST 24
Peak memory 198740 kb
Host smart-5d70a3ac-b98b-4be5-9dc8-77f8f5b97e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159675937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1159675937
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4077123044
Short name T316
Test name
Test status
Simulation time 14496206 ps
CPU time 0.58 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:13 PM PST 24
Peak memory 193476 kb
Host smart-9681f3cb-6fbf-49c7-9915-1cbe3d6dea8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077123044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4077123044
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1325329755
Short name T147
Test name
Test status
Simulation time 287146148 ps
CPU time 2.44 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 198548 kb
Host smart-19a1adb0-fabe-4163-91bb-65c551ead69f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325329755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1325329755
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1895566304
Short name T120
Test name
Test status
Simulation time 166194441219 ps
CPU time 1716.63 seconds
Started Feb 04 01:31:58 PM PST 24
Finished Feb 04 02:00:38 PM PST 24
Peak memory 240940 kb
Host smart-61c963d7-ad67-4c10-bef0-50d47c326947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895566304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1895566304
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.1626832634
Short name T45
Test name
Test status
Simulation time 293865985727 ps
CPU time 496 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 01:44:07 PM PST 24
Peak memory 256412 kb
Host smart-aabcf2a1-e844-4805-a0ad-ec3a54d250fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626832634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.1626832634
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.4264997726
Short name T502
Test name
Test status
Simulation time 291584610582 ps
CPU time 2174.73 seconds
Started Feb 04 01:35:47 PM PST 24
Finished Feb 04 02:12:06 PM PST 24
Peak memory 264664 kb
Host smart-9de037cd-6f78-4af2-ac30-23729f725944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264997726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.4264997726
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2785738654
Short name T128
Test name
Test status
Simulation time 53861283806 ps
CPU time 781.46 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 01:49:03 PM PST 24
Peak memory 231988 kb
Host smart-93315563-f96e-4dc3-a6fc-e9ed32fa5273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785738654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2785738654
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3272516472
Short name T42
Test name
Test status
Simulation time 26373951031 ps
CPU time 992.03 seconds
Started Feb 04 01:34:35 PM PST 24
Finished Feb 04 01:51:09 PM PST 24
Peak memory 247708 kb
Host smart-f10b41a7-945e-4c08-8b3d-a2ba95bf36e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272516472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.3272516472
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1379208859
Short name T67
Test name
Test status
Simulation time 105069816 ps
CPU time 2.22 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 198560 kb
Host smart-a8ca0c69-b705-4e08-bdb3-13a396071285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379208859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1379208859
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2641864088
Short name T97
Test name
Test status
Simulation time 109400220 ps
CPU time 1.85 seconds
Started Feb 04 12:44:54 PM PST 24
Finished Feb 04 12:44:57 PM PST 24
Peak memory 183996 kb
Host smart-c35878d4-777b-4e8f-b663-eb5b36fb78a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641864088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2641864088
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2769321355
Short name T199
Test name
Test status
Simulation time 654034901 ps
CPU time 9.27 seconds
Started Feb 04 12:45:01 PM PST 24
Finished Feb 04 12:45:16 PM PST 24
Peak memory 192224 kb
Host smart-e6e4cc64-6435-4d0f-a6cb-8e5d294cec87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769321355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2769321355
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4195394669
Short name T82
Test name
Test status
Simulation time 31710197 ps
CPU time 0.62 seconds
Started Feb 04 12:44:53 PM PST 24
Finished Feb 04 12:44:55 PM PST 24
Peak memory 193820 kb
Host smart-5822c8b8-e35c-44ab-abd7-4f9d85be6999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195394669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4195394669
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.988545849
Short name T871
Test name
Test status
Simulation time 16007042 ps
CPU time 1.16 seconds
Started Feb 04 12:45:06 PM PST 24
Finished Feb 04 12:45:08 PM PST 24
Peak memory 198768 kb
Host smart-ba5b7fee-6467-449b-802f-b53156aa507d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988545849 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.988545849
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1408633771
Short name T92
Test name
Test status
Simulation time 28698023 ps
CPU time 0.74 seconds
Started Feb 04 12:45:02 PM PST 24
Finished Feb 04 12:45:08 PM PST 24
Peak memory 194816 kb
Host smart-d5362720-b065-4abb-a604-6b5785ca283a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408633771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1408633771
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1093603615
Short name T210
Test name
Test status
Simulation time 12544302 ps
CPU time 0.59 seconds
Started Feb 04 12:44:53 PM PST 24
Finished Feb 04 12:44:54 PM PST 24
Peak memory 183860 kb
Host smart-50f41be6-eadf-4562-9f5f-5e36de42ab47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093603615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1093603615
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3157255174
Short name T201
Test name
Test status
Simulation time 68547497 ps
CPU time 0.83 seconds
Started Feb 04 12:44:54 PM PST 24
Finished Feb 04 12:44:55 PM PST 24
Peak memory 192064 kb
Host smart-6e713f4e-e573-4f84-b2f8-d6f1e117c619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157255174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3157255174
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1834635751
Short name T211
Test name
Test status
Simulation time 120798313 ps
CPU time 1.9 seconds
Started Feb 04 12:45:16 PM PST 24
Finished Feb 04 12:45:21 PM PST 24
Peak memory 198700 kb
Host smart-59032f8a-9d86-4c32-873f-d9cc37422aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834635751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1834635751
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.638759983
Short name T155
Test name
Test status
Simulation time 50379845 ps
CPU time 1.14 seconds
Started Feb 04 12:44:54 PM PST 24
Finished Feb 04 12:44:56 PM PST 24
Peak memory 198184 kb
Host smart-0a2b72c4-c1ea-4a6c-a7ac-b0ff7b3ca810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638759983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.638759983
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2135405905
Short name T91
Test name
Test status
Simulation time 360048352 ps
CPU time 5.52 seconds
Started Feb 04 12:45:08 PM PST 24
Finished Feb 04 12:45:15 PM PST 24
Peak memory 196388 kb
Host smart-3b0c8c47-4ad5-45b5-aaba-b6eec3dd1d33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135405905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2135405905
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2832427884
Short name T65
Test name
Test status
Simulation time 18668868 ps
CPU time 0.69 seconds
Started Feb 04 12:45:11 PM PST 24
Finished Feb 04 12:45:12 PM PST 24
Peak memory 194464 kb
Host smart-85d7b1dd-ae95-403d-962b-9f54a54e7018
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832427884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2832427884
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1391443230
Short name T888
Test name
Test status
Simulation time 46675595 ps
CPU time 0.68 seconds
Started Feb 04 12:45:14 PM PST 24
Finished Feb 04 12:45:17 PM PST 24
Peak memory 194532 kb
Host smart-f45b5fe3-e829-4b79-ad22-4be9697bdaf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391443230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1391443230
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.846425083
Short name T879
Test name
Test status
Simulation time 16488760 ps
CPU time 0.6 seconds
Started Feb 04 12:45:12 PM PST 24
Finished Feb 04 12:45:14 PM PST 24
Peak memory 183832 kb
Host smart-656cbcc5-5f38-4ab6-a7c3-5251fee6d127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846425083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.846425083
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2149355761
Short name T196
Test name
Test status
Simulation time 54676962 ps
CPU time 1.04 seconds
Started Feb 04 12:45:13 PM PST 24
Finished Feb 04 12:45:15 PM PST 24
Peak memory 196460 kb
Host smart-c1e9d96f-bd28-4ef5-b87d-c25f7f2f5264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149355761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2149355761
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2394633450
Short name T66
Test name
Test status
Simulation time 1105308561 ps
CPU time 2.52 seconds
Started Feb 04 12:45:50 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 197868 kb
Host smart-bf544fde-294e-45a4-be4f-5ca833cbc233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394633450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2394633450
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1078958910
Short name T168
Test name
Test status
Simulation time 101906855 ps
CPU time 1.35 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 198844 kb
Host smart-cb6a01fc-aeb5-487f-adef-14e5e746d31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078958910 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1078958910
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.13946061
Short name T898
Test name
Test status
Simulation time 29711641 ps
CPU time 0.63 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 194504 kb
Host smart-c3a2545b-93a3-4ecb-926c-454540569919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13946061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.13946061
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1784397882
Short name T170
Test name
Test status
Simulation time 59646110 ps
CPU time 0.57 seconds
Started Feb 04 12:45:38 PM PST 24
Finished Feb 04 12:45:42 PM PST 24
Peak memory 183832 kb
Host smart-14387838-c4c9-46ea-b2af-157ddcfd827a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784397882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1784397882
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.426396300
Short name T164
Test name
Test status
Simulation time 34413547 ps
CPU time 0.88 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 192240 kb
Host smart-863ebf39-d24a-49d1-bb16-5144b834d328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426396300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.426396300
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1614350497
Short name T28
Test name
Test status
Simulation time 115820946 ps
CPU time 1.97 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 198796 kb
Host smart-88985188-b151-45fe-a3c4-00d7fd38dd66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614350497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1614350497
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1265335448
Short name T886
Test name
Test status
Simulation time 53852737 ps
CPU time 1.35 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:44 PM PST 24
Peak memory 198760 kb
Host smart-6792b507-82af-4873-b7c9-b62f4aa7f3d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265335448 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1265335448
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.518764368
Short name T176
Test name
Test status
Simulation time 36475433 ps
CPU time 0.65 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 194252 kb
Host smart-4b48608d-55af-48c8-b2fe-df361a7689dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518764368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.518764368
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3744750211
Short name T896
Test name
Test status
Simulation time 32682730 ps
CPU time 0.62 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:36 PM PST 24
Peak memory 183944 kb
Host smart-8c1beceb-d4ec-467a-a497-b9737f7484d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744750211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3744750211
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3230298407
Short name T173
Test name
Test status
Simulation time 722164045 ps
CPU time 1.46 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 192400 kb
Host smart-421e9b5f-7c19-4cc3-9015-46f84ed723f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230298407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3230298407
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1771702766
Short name T76
Test name
Test status
Simulation time 122337072 ps
CPU time 1.79 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:34 PM PST 24
Peak memory 198740 kb
Host smart-9da1be9d-74f2-41af-aea7-b0f9da1548df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771702766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1771702766
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3650052863
Short name T77
Test name
Test status
Simulation time 115269121 ps
CPU time 2.52 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 198492 kb
Host smart-66813f99-6d5e-44ff-9351-980dd24a1721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650052863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3650052863
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4181080375
Short name T895
Test name
Test status
Simulation time 306642635891 ps
CPU time 1394.34 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 01:08:52 PM PST 24
Peak memory 219036 kb
Host smart-ebd5ceb6-4a57-46d3-9b73-903b9d6a849e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181080375 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4181080375
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.334946431
Short name T85
Test name
Test status
Simulation time 16244504 ps
CPU time 0.63 seconds
Started Feb 04 12:45:45 PM PST 24
Finished Feb 04 12:45:46 PM PST 24
Peak memory 194364 kb
Host smart-68d605e7-38e3-4f40-ab69-04bcac061164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334946431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.334946431
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2701888591
Short name T165
Test name
Test status
Simulation time 45349576 ps
CPU time 0.59 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 183876 kb
Host smart-e5497eeb-b69b-47d9-9a73-1bddfaf18004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701888591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2701888591
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.22160999
Short name T901
Test name
Test status
Simulation time 112488560 ps
CPU time 1.08 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 196760 kb
Host smart-a9e5cdea-7e43-4f56-9638-32c528f29a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_
outstanding.22160999
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3986612527
Short name T900
Test name
Test status
Simulation time 496958653 ps
CPU time 2.76 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 198792 kb
Host smart-937a9a75-104e-48e8-b1ca-abec52b4f1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986612527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3986612527
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2354916990
Short name T890
Test name
Test status
Simulation time 199364352 ps
CPU time 2.32 seconds
Started Feb 04 12:45:45 PM PST 24
Finished Feb 04 12:45:48 PM PST 24
Peak memory 198564 kb
Host smart-e0a7f0eb-7476-44f3-9d36-0d7f0e259254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354916990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2354916990
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3512769833
Short name T156
Test name
Test status
Simulation time 33686412 ps
CPU time 2.66 seconds
Started Feb 04 12:45:45 PM PST 24
Finished Feb 04 12:45:48 PM PST 24
Peak memory 198784 kb
Host smart-21c5d961-4714-4db7-be53-9c70c9d04c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512769833 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3512769833
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3956547832
Short name T161
Test name
Test status
Simulation time 34157816 ps
CPU time 0.61 seconds
Started Feb 04 12:45:40 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 194200 kb
Host smart-7197229d-4460-4cd8-abcd-81b23d952a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956547832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3956547832
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4140139509
Short name T894
Test name
Test status
Simulation time 29152413 ps
CPU time 0.56 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 183856 kb
Host smart-037b2940-2dd5-4c5c-8f57-a5d0de4d6c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140139509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4140139509
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3574765376
Short name T17
Test name
Test status
Simulation time 171712918 ps
CPU time 1.01 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 192348 kb
Host smart-82a91840-3ce9-4863-a5b1-511383d45240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574765376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3574765376
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2564217429
Short name T184
Test name
Test status
Simulation time 73214178 ps
CPU time 3.43 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 198728 kb
Host smart-aaa2ac30-bc92-4a9f-84cf-1cf1e1b67ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564217429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2564217429
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3454886695
Short name T187
Test name
Test status
Simulation time 72332227 ps
CPU time 1.17 seconds
Started Feb 04 12:45:40 PM PST 24
Finished Feb 04 12:45:44 PM PST 24
Peak memory 198616 kb
Host smart-d0bfaaa1-149a-48fc-8266-04c1f0f3bdfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454886695 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3454886695
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4293944580
Short name T874
Test name
Test status
Simulation time 74018389 ps
CPU time 0.59 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 194356 kb
Host smart-d7b76e28-479a-4ce4-8a55-ce7ac1379229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293944580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4293944580
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1070989471
Short name T880
Test name
Test status
Simulation time 19184518 ps
CPU time 0.61 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 183880 kb
Host smart-54b19d4c-9d5c-420a-b42a-493e8b28e904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070989471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1070989471
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2966088445
Short name T885
Test name
Test status
Simulation time 202033624 ps
CPU time 1.37 seconds
Started Feb 04 12:45:45 PM PST 24
Finished Feb 04 12:45:47 PM PST 24
Peak memory 192392 kb
Host smart-57c00d95-f1c4-4b9d-8529-c7eca61a6783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966088445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2966088445
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.252785726
Short name T902
Test name
Test status
Simulation time 218412063 ps
CPU time 2.58 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 198920 kb
Host smart-e63361fe-8db6-4401-a48d-9e92c815b569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252785726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.252785726
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3787730389
Short name T181
Test name
Test status
Simulation time 37993760 ps
CPU time 1.08 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 198596 kb
Host smart-0c5450ca-48ed-4add-b8cc-e5abbd1fe8bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787730389 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3787730389
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3261262254
Short name T86
Test name
Test status
Simulation time 12756920 ps
CPU time 0.66 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 194336 kb
Host smart-ac9ee3e6-b0f8-450d-b998-d36ae3aa45df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261262254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3261262254
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1231477549
Short name T102
Test name
Test status
Simulation time 22219188 ps
CPU time 0.56 seconds
Started Feb 04 12:45:40 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 183616 kb
Host smart-4b72bf1b-97ec-4eee-95fd-42c203f52bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231477549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1231477549
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3922793480
Short name T22
Test name
Test status
Simulation time 29905517 ps
CPU time 0.8 seconds
Started Feb 04 12:45:40 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 192280 kb
Host smart-d38c0dfc-ebcf-4cf3-9a17-eda562655a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922793480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3922793480
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.922976875
Short name T27
Test name
Test status
Simulation time 220675358 ps
CPU time 3.57 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:44 PM PST 24
Peak memory 198628 kb
Host smart-76d9cdfd-4eba-47d8-ba0c-93c9bdcf0c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922976875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.922976875
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1983241636
Short name T192
Test name
Test status
Simulation time 1249857778 ps
CPU time 1.86 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 198328 kb
Host smart-2b134ee6-b252-4705-bed7-5b5c4b73edef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983241636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1983241636
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.827152149
Short name T157
Test name
Test status
Simulation time 31378772 ps
CPU time 1.11 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 198540 kb
Host smart-1ad87c9f-3dd5-4284-be6b-c070d593bd53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827152149 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.827152149
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2722095537
Short name T177
Test name
Test status
Simulation time 36496736 ps
CPU time 0.63 seconds
Started Feb 04 12:45:49 PM PST 24
Finished Feb 04 12:45:53 PM PST 24
Peak memory 194100 kb
Host smart-5d7c5dd4-c551-4e04-b6a6-5253566e09f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722095537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2722095537
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.953642946
Short name T212
Test name
Test status
Simulation time 56583740 ps
CPU time 0.57 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:54 PM PST 24
Peak memory 183884 kb
Host smart-bb343230-22dd-4ab1-8f2d-dcd26cdbc1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953642946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.953642946
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4250876041
Short name T166
Test name
Test status
Simulation time 240214614 ps
CPU time 1.13 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 196996 kb
Host smart-2ebb70b9-183c-40dc-97d3-58da58143041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250876041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4250876041
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1403084770
Short name T79
Test name
Test status
Simulation time 90117239 ps
CPU time 1.3 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:02 PM PST 24
Peak memory 198816 kb
Host smart-d1349f7d-7110-4daa-82eb-eee50e233975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403084770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1403084770
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2984711264
Short name T151
Test name
Test status
Simulation time 68308063 ps
CPU time 1.24 seconds
Started Feb 04 12:45:50 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 198016 kb
Host smart-baea4217-825a-4bcb-bb74-c90bfe1590cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984711264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2984711264
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.722247860
Short name T190
Test name
Test status
Simulation time 37235149 ps
CPU time 1.07 seconds
Started Feb 04 12:45:48 PM PST 24
Finished Feb 04 12:45:52 PM PST 24
Peak memory 198640 kb
Host smart-75cbdff1-eca3-4e27-ad7e-8da02ee30951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722247860 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.722247860
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1077219077
Short name T73
Test name
Test status
Simulation time 36754992 ps
CPU time 0.61 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194016 kb
Host smart-edd5acbb-e944-4361-aa9d-009ae3f4de5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077219077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1077219077
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.606524525
Short name T877
Test name
Test status
Simulation time 14508523 ps
CPU time 0.58 seconds
Started Feb 04 12:45:56 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 183856 kb
Host smart-e5e41327-7536-4e1b-b281-1b3aab303b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606524525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.606524525
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2867543360
Short name T84
Test name
Test status
Simulation time 86756283 ps
CPU time 1 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 192332 kb
Host smart-22312e0b-6c0c-491f-ad1d-0eb3767a68b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867543360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2867543360
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3293033880
Short name T905
Test name
Test status
Simulation time 180455935 ps
CPU time 1.99 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 198784 kb
Host smart-7a5bb5a1-5999-43ee-892f-edee6a21ba15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293033880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3293033880
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.713302589
Short name T887
Test name
Test status
Simulation time 27998725 ps
CPU time 0.88 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 198616 kb
Host smart-44cea937-426d-48b1-b29b-7e40246e69b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713302589 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.713302589
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1952617480
Short name T100
Test name
Test status
Simulation time 21542015 ps
CPU time 0.72 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 194688 kb
Host smart-e4cdd4b6-ecc5-420b-9660-9c00083cecf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952617480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1952617480
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1739487334
Short name T897
Test name
Test status
Simulation time 11522454 ps
CPU time 0.53 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 183908 kb
Host smart-dd973039-45a1-4e10-b297-3b6b590b2918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739487334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1739487334
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.721256598
Short name T71
Test name
Test status
Simulation time 154931537 ps
CPU time 1.33 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 192384 kb
Host smart-ad3d56a4-4f64-4428-b322-5c6c0b108687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721256598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.721256598
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2534659031
Short name T78
Test name
Test status
Simulation time 438384379 ps
CPU time 2.84 seconds
Started Feb 04 12:45:49 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 198848 kb
Host smart-d4829b8d-cf64-450c-9dc0-b3520ad616e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534659031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2534659031
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.448504678
Short name T149
Test name
Test status
Simulation time 169800106 ps
CPU time 2.44 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:05 PM PST 24
Peak memory 198524 kb
Host smart-e6311125-79f5-43ba-b28f-54cb864e10a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448504678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.448504678
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1465659461
Short name T26
Test name
Test status
Simulation time 31293747 ps
CPU time 2.38 seconds
Started Feb 04 12:45:48 PM PST 24
Finished Feb 04 12:45:53 PM PST 24
Peak memory 198744 kb
Host smart-f1bad288-c13a-4c64-a7f9-e00fbe1b16e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465659461 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1465659461
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3759373450
Short name T208
Test name
Test status
Simulation time 73110957 ps
CPU time 0.71 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 194488 kb
Host smart-146adbfe-b2a8-437d-8adc-bacdbf610b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759373450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3759373450
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1393271419
Short name T189
Test name
Test status
Simulation time 38823643 ps
CPU time 0.58 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 183856 kb
Host smart-b68e0579-bd08-4a69-930e-88932baee839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393271419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1393271419
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3884142343
Short name T88
Test name
Test status
Simulation time 23814913 ps
CPU time 1 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 197084 kb
Host smart-c9a0ee08-3e58-4d8c-b2f9-3c35210b7c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884142343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3884142343
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3351298386
Short name T23
Test name
Test status
Simulation time 28048378 ps
CPU time 1.4 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 198792 kb
Host smart-309a5f79-05ce-4fa6-9598-254715e87d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351298386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3351298386
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.463731571
Short name T75
Test name
Test status
Simulation time 139388551 ps
CPU time 1.82 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:03 PM PST 24
Peak memory 198392 kb
Host smart-a0d1759c-217b-4f81-b82d-f33bb3ba1273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463731571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.463731571
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3403117616
Short name T98
Test name
Test status
Simulation time 751645637 ps
CPU time 2.52 seconds
Started Feb 04 12:45:15 PM PST 24
Finished Feb 04 12:45:21 PM PST 24
Peak memory 192352 kb
Host smart-ae93c280-e9af-488c-9898-cdb23dfb9162
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403117616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3403117616
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3344495756
Short name T891
Test name
Test status
Simulation time 438017827 ps
CPU time 6.52 seconds
Started Feb 04 12:45:17 PM PST 24
Finished Feb 04 12:45:26 PM PST 24
Peak memory 192324 kb
Host smart-3c1affd8-7070-486d-a239-a8bb3b741982
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344495756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3344495756
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2839756141
Short name T90
Test name
Test status
Simulation time 28225173 ps
CPU time 0.74 seconds
Started Feb 04 12:45:18 PM PST 24
Finished Feb 04 12:45:20 PM PST 24
Peak memory 194640 kb
Host smart-24bd41b1-084d-44aa-8a70-7fc62567e34f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839756141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2839756141
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1427464108
Short name T172
Test name
Test status
Simulation time 41238882 ps
CPU time 1.79 seconds
Started Feb 04 12:45:18 PM PST 24
Finished Feb 04 12:45:21 PM PST 24
Peak memory 198784 kb
Host smart-15d94321-f27c-4ca3-bf9c-9257c3d4e77d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427464108 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1427464108
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1453445511
Short name T907
Test name
Test status
Simulation time 40936113 ps
CPU time 0.76 seconds
Started Feb 04 12:45:18 PM PST 24
Finished Feb 04 12:45:20 PM PST 24
Peak memory 194816 kb
Host smart-d2998455-aa6f-4cf2-a83c-3cc8a5d58d8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453445511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1453445511
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.598435157
Short name T872
Test name
Test status
Simulation time 20599656 ps
CPU time 0.57 seconds
Started Feb 04 12:45:21 PM PST 24
Finished Feb 04 12:45:26 PM PST 24
Peak memory 183920 kb
Host smart-30dd7936-0b0a-457f-9818-19e48b5f4834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598435157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.598435157
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2046275133
Short name T70
Test name
Test status
Simulation time 55087373 ps
CPU time 1.06 seconds
Started Feb 04 12:45:18 PM PST 24
Finished Feb 04 12:45:21 PM PST 24
Peak memory 196796 kb
Host smart-f36a27f1-d762-444f-a6e8-5b4d26ab66b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046275133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2046275133
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.130109588
Short name T154
Test name
Test status
Simulation time 214449613 ps
CPU time 1.82 seconds
Started Feb 04 12:45:17 PM PST 24
Finished Feb 04 12:45:21 PM PST 24
Peak memory 198396 kb
Host smart-bf7a8c1e-44ff-4584-b8b5-6d1ad7c1efef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130109588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.130109588
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.908083941
Short name T200
Test name
Test status
Simulation time 48114760 ps
CPU time 0.59 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 183816 kb
Host smart-d17ddf7c-1d9b-49a2-8a94-4de9961e1942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908083941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.908083941
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1417326984
Short name T167
Test name
Test status
Simulation time 13794613 ps
CPU time 0.61 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 183888 kb
Host smart-9919c2da-5153-420d-be3a-80a73d86bb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417326984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1417326984
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1181920453
Short name T94
Test name
Test status
Simulation time 22655183 ps
CPU time 0.55 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 183904 kb
Host smart-f86ef963-d89a-4acd-8716-24de1a0e77ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181920453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1181920453
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1905072184
Short name T183
Test name
Test status
Simulation time 41497692 ps
CPU time 0.56 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 183816 kb
Host smart-72b94898-4554-4fb6-b534-e125f85600d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905072184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1905072184
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.882417297
Short name T875
Test name
Test status
Simulation time 19861832 ps
CPU time 0.62 seconds
Started Feb 04 12:45:50 PM PST 24
Finished Feb 04 12:45:54 PM PST 24
Peak memory 183880 kb
Host smart-51522401-5c6e-44b4-acc4-2c5502f3aafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882417297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.882417297
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3031304959
Short name T160
Test name
Test status
Simulation time 14921133 ps
CPU time 0.58 seconds
Started Feb 04 12:45:50 PM PST 24
Finished Feb 04 12:45:54 PM PST 24
Peak memory 183888 kb
Host smart-6d91c5d5-6d45-43bc-90c4-744cb68e5121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031304959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3031304959
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2563262790
Short name T910
Test name
Test status
Simulation time 56342106 ps
CPU time 0.61 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 183880 kb
Host smart-14378e20-b109-41ab-bbc8-45f0fdd818f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563262790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2563262790
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2806765286
Short name T188
Test name
Test status
Simulation time 86174219 ps
CPU time 0.65 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 183944 kb
Host smart-2763a9ad-4f6a-463e-ba8d-2b0ffbc9edc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806765286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2806765286
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1173417853
Short name T16
Test name
Test status
Simulation time 13676360 ps
CPU time 0.6 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 183888 kb
Host smart-8c0e80a2-bef7-47e6-a952-f38d92f3e3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173417853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1173417853
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3672376670
Short name T182
Test name
Test status
Simulation time 47859034 ps
CPU time 0.6 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:02 PM PST 24
Peak memory 183944 kb
Host smart-86da24db-a640-4f20-b363-2685597d3d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672376670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3672376670
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3336577516
Short name T93
Test name
Test status
Simulation time 2132128169 ps
CPU time 2.8 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 192368 kb
Host smart-92348f76-9800-42ed-b1f5-98d81e758b1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336577516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3336577516
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.379374571
Short name T162
Test name
Test status
Simulation time 3116315814 ps
CPU time 8.85 seconds
Started Feb 04 12:45:30 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 192492 kb
Host smart-e2943e4d-99f8-4061-ad58-e7526aac94d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379374571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.379374571
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1563300794
Short name T96
Test name
Test status
Simulation time 17168088 ps
CPU time 0.63 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 194060 kb
Host smart-64fff791-8e94-446a-84ef-d168b199f995
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563300794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1563300794
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3464041819
Short name T24
Test name
Test status
Simulation time 15460440 ps
CPU time 0.91 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 198580 kb
Host smart-10887c46-26b3-474f-9976-fc89775efa6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464041819 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3464041819
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1267349611
Short name T169
Test name
Test status
Simulation time 23813747 ps
CPU time 0.56 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:36 PM PST 24
Peak memory 183896 kb
Host smart-52c74706-b562-46a6-8f6a-460351279d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267349611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1267349611
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1733894506
Short name T89
Test name
Test status
Simulation time 126362918 ps
CPU time 0.83 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:38 PM PST 24
Peak memory 192168 kb
Host smart-d5afef0b-076c-41d5-9bf9-8d810faaf98a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733894506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1733894506
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1749091553
Short name T80
Test name
Test status
Simulation time 111222007 ps
CPU time 2.91 seconds
Started Feb 04 12:45:16 PM PST 24
Finished Feb 04 12:45:22 PM PST 24
Peak memory 198780 kb
Host smart-ecf80c94-858d-498d-b6fa-cb1b6a2fc5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749091553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1749091553
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.544461141
Short name T150
Test name
Test status
Simulation time 158411081 ps
CPU time 2.38 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 198580 kb
Host smart-97c71532-698e-418b-9311-52a00a69484f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544461141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.544461141
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1613197527
Short name T72
Test name
Test status
Simulation time 37736767 ps
CPU time 0.61 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 183884 kb
Host smart-0b7a5686-ad91-424f-9a19-6c5ab5ef0d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613197527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1613197527
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3505758122
Short name T193
Test name
Test status
Simulation time 21342244 ps
CPU time 0.57 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 183856 kb
Host smart-65f7f0e4-429b-402a-9e8e-e5088fda4a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505758122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3505758122
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1897051072
Short name T159
Test name
Test status
Simulation time 21325068 ps
CPU time 0.6 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 183892 kb
Host smart-5c8d5d9d-5dbc-4b3e-bd1b-efc59d7f974e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897051072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1897051072
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.735757991
Short name T878
Test name
Test status
Simulation time 12134977 ps
CPU time 0.59 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:02 PM PST 24
Peak memory 183944 kb
Host smart-9969197d-6d39-41b5-bc5b-4a910790976a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735757991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.735757991
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3493115878
Short name T175
Test name
Test status
Simulation time 37194504 ps
CPU time 0.65 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:02 PM PST 24
Peak memory 183832 kb
Host smart-bc2a9d26-76d8-4993-8db8-3b24f5d6d548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493115878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3493115878
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2917888243
Short name T158
Test name
Test status
Simulation time 45090343 ps
CPU time 0.62 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183808 kb
Host smart-8a941067-9cdc-4211-b002-e307a266128b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917888243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2917888243
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3504724497
Short name T903
Test name
Test status
Simulation time 17270748 ps
CPU time 0.63 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183880 kb
Host smart-6a02a17a-eb52-4a14-9661-49d871c6f011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504724497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3504724497
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.398768138
Short name T870
Test name
Test status
Simulation time 43100611 ps
CPU time 0.59 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:03 PM PST 24
Peak memory 183944 kb
Host smart-aae016d0-5bdf-4950-aea5-46199a763105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398768138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.398768138
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3391128593
Short name T197
Test name
Test status
Simulation time 17197975 ps
CPU time 0.61 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 183804 kb
Host smart-0e596c43-faae-46ba-b885-624541f740ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391128593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3391128593
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.257222721
Short name T893
Test name
Test status
Simulation time 60225400 ps
CPU time 1.27 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 184068 kb
Host smart-8dbdc8a4-cc41-4eb5-b6f0-ffc242f44ae0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257222721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.257222721
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2161345848
Short name T179
Test name
Test status
Simulation time 788360413 ps
CPU time 3.29 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:36 PM PST 24
Peak memory 192360 kb
Host smart-0442fa5e-8efe-4aa7-adc3-ce7ec79a7247
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161345848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2161345848
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3977238106
Short name T198
Test name
Test status
Simulation time 21162119 ps
CPU time 0.7 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:33 PM PST 24
Peak memory 194592 kb
Host smart-f04ed066-3816-400e-9736-58fbec246474
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977238106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3977238106
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2064433716
Short name T204
Test name
Test status
Simulation time 35526863597 ps
CPU time 227.07 seconds
Started Feb 04 12:45:40 PM PST 24
Finished Feb 04 12:49:30 PM PST 24
Peak memory 198948 kb
Host smart-bad3c954-b856-42bd-b0e7-611f54a2e663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064433716 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2064433716
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1707999393
Short name T101
Test name
Test status
Simulation time 14357826 ps
CPU time 0.65 seconds
Started Feb 04 12:45:28 PM PST 24
Finished Feb 04 12:45:29 PM PST 24
Peak memory 194356 kb
Host smart-8b5c1bf5-6f30-46ad-ad3e-77075a006e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707999393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1707999393
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3241995308
Short name T19
Test name
Test status
Simulation time 28215034 ps
CPU time 0.61 seconds
Started Feb 04 12:45:38 PM PST 24
Finished Feb 04 12:45:42 PM PST 24
Peak memory 183872 kb
Host smart-0eae4dce-a803-4a74-bd87-17619d6773a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241995308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3241995308
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1721001782
Short name T892
Test name
Test status
Simulation time 135798139 ps
CPU time 1.23 seconds
Started Feb 04 12:45:32 PM PST 24
Finished Feb 04 12:45:36 PM PST 24
Peak memory 197072 kb
Host smart-920383dc-63d3-485c-8611-b222ca03d4a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721001782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1721001782
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1396326506
Short name T25
Test name
Test status
Simulation time 187072684 ps
CPU time 2.75 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:34 PM PST 24
Peak memory 198732 kb
Host smart-ffadde8d-f337-47f7-8610-2fb211231a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396326506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1396326506
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.194494051
Short name T21
Test name
Test status
Simulation time 113231287 ps
CPU time 1.91 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 198776 kb
Host smart-528954d7-9a1b-46bc-952e-c9f7adf2256d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194494051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.194494051
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2078299642
Short name T205
Test name
Test status
Simulation time 12546662 ps
CPU time 0.59 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183848 kb
Host smart-0929238b-2a2b-4db2-b27f-e931835011d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078299642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2078299642
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2516797506
Short name T209
Test name
Test status
Simulation time 30410910 ps
CPU time 0.66 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183724 kb
Host smart-428c521b-d218-41bb-b33a-bac18cb34cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516797506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2516797506
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1429533762
Short name T911
Test name
Test status
Simulation time 33840842 ps
CPU time 0.58 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183872 kb
Host smart-b2d3ef4f-f2fe-4441-94d9-89d59c87b524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429533762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1429533762
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.610521574
Short name T186
Test name
Test status
Simulation time 30151479 ps
CPU time 0.58 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183856 kb
Host smart-0bd14ee9-4b9c-465c-899a-f77b25404828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610521574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.610521574
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1977695130
Short name T908
Test name
Test status
Simulation time 21019854 ps
CPU time 0.62 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 183764 kb
Host smart-39ccc3ae-b89e-4bf4-9ec8-8a82283d63a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977695130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1977695130
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1186614565
Short name T87
Test name
Test status
Simulation time 15477638 ps
CPU time 0.57 seconds
Started Feb 04 12:45:56 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 183880 kb
Host smart-5b23cb8e-d347-433d-9b37-2603b31a82eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186614565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1186614565
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2934927933
Short name T202
Test name
Test status
Simulation time 14473879 ps
CPU time 0.62 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183672 kb
Host smart-c95d52b5-31bb-4bc8-b23a-9d482a6a2dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934927933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2934927933
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1953804873
Short name T178
Test name
Test status
Simulation time 46825496 ps
CPU time 0.57 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 183836 kb
Host smart-2c16925b-9981-431e-9476-8b3cc0acab8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953804873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1953804873
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.689533985
Short name T899
Test name
Test status
Simulation time 84036298 ps
CPU time 0.55 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183872 kb
Host smart-d2406b71-5ea3-48f9-b357-b5cf687fc303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689533985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.689533985
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.310727632
Short name T213
Test name
Test status
Simulation time 12031038 ps
CPU time 0.56 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 183856 kb
Host smart-eecf9b78-16dd-4e0e-b556-18718aaa68b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310727632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.310727632
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.621447027
Short name T882
Test name
Test status
Simulation time 77553076 ps
CPU time 1.99 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 198788 kb
Host smart-7d1a8525-2003-46c1-9dde-126cc88cd192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621447027 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.621447027
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3164736354
Short name T881
Test name
Test status
Simulation time 22666022 ps
CPU time 0.76 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:40 PM PST 24
Peak memory 194812 kb
Host smart-66abac06-c3f4-438f-8c59-bec5b19c24b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164736354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3164736354
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3181220768
Short name T69
Test name
Test status
Simulation time 16821816 ps
CPU time 0.6 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 183848 kb
Host smart-1f7946d7-6c84-4b98-9b4a-3d74dc24c036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181220768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3181220768
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1975616358
Short name T195
Test name
Test status
Simulation time 67605695 ps
CPU time 1.45 seconds
Started Feb 04 12:45:32 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 192372 kb
Host smart-9cc44476-de97-4c1f-a193-45137a93deb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975616358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1975616358
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2944544961
Short name T889
Test name
Test status
Simulation time 114733812 ps
CPU time 1.75 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 198812 kb
Host smart-344ee307-dec2-4004-886f-2ead588031f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944544961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2944544961
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1757616591
Short name T207
Test name
Test status
Simulation time 793026139 ps
CPU time 1.25 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 198288 kb
Host smart-c549a639-eaf2-437c-b7c2-e39ae7499794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757616591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1757616591
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1593404025
Short name T912
Test name
Test status
Simulation time 84033994675 ps
CPU time 281.49 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:50:17 PM PST 24
Peak memory 201456 kb
Host smart-0974a9af-3ddd-476c-ac88-cd7f88944713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593404025 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1593404025
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.603042478
Short name T909
Test name
Test status
Simulation time 72344263 ps
CPU time 0.63 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 194080 kb
Host smart-90bde0e2-1652-4a67-8d14-a10d6481e3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603042478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.603042478
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1373878699
Short name T876
Test name
Test status
Simulation time 92178309 ps
CPU time 0.78 seconds
Started Feb 04 12:45:37 PM PST 24
Finished Feb 04 12:45:41 PM PST 24
Peak memory 192260 kb
Host smart-cd16cb3b-63f8-4878-9d54-da9ac2b0a51b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373878699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1373878699
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2759828322
Short name T31
Test name
Test status
Simulation time 65871337 ps
CPU time 3.69 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:42 PM PST 24
Peak memory 198776 kb
Host smart-11ab0cb9-ead8-4d60-8215-9e45214a4e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759828322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2759828322
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.799658364
Short name T148
Test name
Test status
Simulation time 74656973 ps
CPU time 1.8 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 198484 kb
Host smart-c78cffad-210c-40b3-a007-ae1bba0fe27e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799658364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.799658364
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1863977541
Short name T30
Test name
Test status
Simulation time 46272407 ps
CPU time 1.03 seconds
Started Feb 04 12:45:32 PM PST 24
Finished Feb 04 12:45:36 PM PST 24
Peak memory 198592 kb
Host smart-1c82ac95-f722-49ab-80a9-2b366f7e80cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863977541 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1863977541
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1358063810
Short name T99
Test name
Test status
Simulation time 46189790 ps
CPU time 0.68 seconds
Started Feb 04 12:45:32 PM PST 24
Finished Feb 04 12:45:35 PM PST 24
Peak memory 194420 kb
Host smart-d5c72a6b-92b9-4718-bce3-7ab362d4dd8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358063810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1358063810
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.467429846
Short name T904
Test name
Test status
Simulation time 11910665 ps
CPU time 0.63 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 183888 kb
Host smart-d3732436-1d8e-407b-a3cb-29b5fade4619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467429846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.467429846
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1324878523
Short name T180
Test name
Test status
Simulation time 46790056 ps
CPU time 1.14 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 196464 kb
Host smart-9cbd478f-da81-4346-be6a-cf11e7649dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324878523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1324878523
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3441491629
Short name T883
Test name
Test status
Simulation time 198553519 ps
CPU time 3.8 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 198984 kb
Host smart-875edcc2-f412-46a2-8ea8-549c4c74419f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441491629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3441491629
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.640514682
Short name T873
Test name
Test status
Simulation time 15103478 ps
CPU time 0.91 seconds
Started Feb 04 12:45:33 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 198616 kb
Host smart-cc77da08-eabd-44ef-9ed6-930321f9508c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640514682 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.640514682
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.384223903
Short name T174
Test name
Test status
Simulation time 114776573 ps
CPU time 0.72 seconds
Started Feb 04 12:45:38 PM PST 24
Finished Feb 04 12:45:42 PM PST 24
Peak memory 194252 kb
Host smart-c83e8281-a521-458f-9cf2-e9b8ea15de2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384223903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.384223903
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3646127776
Short name T163
Test name
Test status
Simulation time 13602386 ps
CPU time 0.61 seconds
Started Feb 04 12:45:42 PM PST 24
Finished Feb 04 12:45:45 PM PST 24
Peak memory 183828 kb
Host smart-643f4889-4691-48e1-a069-e974ba20a550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646127776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3646127776
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2407069472
Short name T194
Test name
Test status
Simulation time 130997019 ps
CPU time 0.86 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 192236 kb
Host smart-f8108319-a44b-432b-b5c0-154d7413436a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407069472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2407069472
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2564385001
Short name T206
Test name
Test status
Simulation time 64730168 ps
CPU time 2.81 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 198848 kb
Host smart-c0c165ac-d0fe-4c2e-be2f-a871005cf544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564385001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2564385001
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1289260088
Short name T153
Test name
Test status
Simulation time 79610554 ps
CPU time 1.68 seconds
Started Feb 04 12:45:39 PM PST 24
Finished Feb 04 12:45:44 PM PST 24
Peak memory 198288 kb
Host smart-4bd7a25c-03cd-494a-b8b0-c96698cf7595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289260088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1289260088
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3774979453
Short name T29
Test name
Test status
Simulation time 16676241 ps
CPU time 0.91 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 198672 kb
Host smart-95741e72-7338-4465-b22c-1ac8a5833615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774979453 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3774979453
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1835231099
Short name T83
Test name
Test status
Simulation time 47635335 ps
CPU time 0.7 seconds
Started Feb 04 12:45:34 PM PST 24
Finished Feb 04 12:45:37 PM PST 24
Peak memory 194456 kb
Host smart-2e4bf3a2-1b36-498e-8245-b2b62f0386b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835231099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1835231099
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4023109517
Short name T203
Test name
Test status
Simulation time 30393173 ps
CPU time 0.63 seconds
Started Feb 04 12:45:36 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 183888 kb
Host smart-22bc916b-06de-4198-a66f-5c793bbf4b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023109517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4023109517
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3248341093
Short name T906
Test name
Test status
Simulation time 50557632 ps
CPU time 1 seconds
Started Feb 04 12:45:31 PM PST 24
Finished Feb 04 12:45:35 PM PST 24
Peak memory 192388 kb
Host smart-1493c991-13e6-4ae2-9f8f-914e0e4dd1e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248341093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3248341093
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4023377536
Short name T884
Test name
Test status
Simulation time 45752160 ps
CPU time 2.37 seconds
Started Feb 04 12:45:35 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 198848 kb
Host smart-3cfb3261-06f9-4eb7-90f3-61a61eb0361e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023377536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4023377536
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.392124571
Short name T191
Test name
Test status
Simulation time 64873666 ps
CPU time 1.27 seconds
Started Feb 04 12:45:38 PM PST 24
Finished Feb 04 12:45:43 PM PST 24
Peak memory 197440 kb
Host smart-0e8494f5-3c04-4d34-bee0-d703c90d9950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392124571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.392124571
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.751055519
Short name T551
Test name
Test status
Simulation time 17048742 ps
CPU time 0.59 seconds
Started Feb 04 01:31:57 PM PST 24
Finished Feb 04 01:32:01 PM PST 24
Peak memory 194492 kb
Host smart-ca448633-9202-4ede-b1c8-d29b9aba4bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751055519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.751055519
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.110173560
Short name T297
Test name
Test status
Simulation time 7743844896 ps
CPU time 40.95 seconds
Started Feb 04 01:32:11 PM PST 24
Finished Feb 04 01:32:53 PM PST 24
Peak memory 231752 kb
Host smart-5c14d38f-c168-4b60-ada4-c48991ed7c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110173560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.110173560
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2152766309
Short name T364
Test name
Test status
Simulation time 572854276 ps
CPU time 29.52 seconds
Started Feb 04 01:31:56 PM PST 24
Finished Feb 04 01:32:29 PM PST 24
Peak memory 199024 kb
Host smart-33e7b1fe-631a-4282-bdc5-279ff13ba4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152766309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2152766309
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1519148217
Short name T540
Test name
Test status
Simulation time 770043571 ps
CPU time 19.97 seconds
Started Feb 04 01:31:53 PM PST 24
Finished Feb 04 01:32:20 PM PST 24
Peak memory 199068 kb
Host smart-856fe05f-47c6-4e30-af5a-37e59ad23dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519148217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1519148217
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2982253594
Short name T353
Test name
Test status
Simulation time 57695933320 ps
CPU time 181.19 seconds
Started Feb 04 01:31:58 PM PST 24
Finished Feb 04 01:35:02 PM PST 24
Peak memory 199088 kb
Host smart-078dad26-c3fa-4ad8-b590-edd78e62a390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982253594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2982253594
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.917177807
Short name T395
Test name
Test status
Simulation time 15966261598 ps
CPU time 84 seconds
Started Feb 04 01:31:55 PM PST 24
Finished Feb 04 01:33:24 PM PST 24
Peak memory 199052 kb
Host smart-5bb385c6-409d-41f9-9e06-1434be12604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917177807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.917177807
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3933796011
Short name T53
Test name
Test status
Simulation time 104726764 ps
CPU time 0.97 seconds
Started Feb 04 01:31:59 PM PST 24
Finished Feb 04 01:32:02 PM PST 24
Peak memory 217288 kb
Host smart-2b267556-310a-4ed3-b455-4409e2a622c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933796011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3933796011
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.398131938
Short name T809
Test name
Test status
Simulation time 319652761 ps
CPU time 1.6 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 198988 kb
Host smart-aaedc7d2-267d-4c9b-b18a-07dd47781de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398131938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.398131938
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1478713037
Short name T398
Test name
Test status
Simulation time 51477602363 ps
CPU time 712.81 seconds
Started Feb 04 01:31:54 PM PST 24
Finished Feb 04 01:43:53 PM PST 24
Peak memory 240108 kb
Host smart-aa68c731-681b-4a72-8f60-9ac449d86a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478713037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1478713037
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2785939995
Short name T383
Test name
Test status
Simulation time 93065347 ps
CPU time 0.95 seconds
Started Feb 04 01:31:59 PM PST 24
Finished Feb 04 01:32:02 PM PST 24
Peak memory 196816 kb
Host smart-78157bda-f227-4fed-8cb3-0afc2d365f30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785939995 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2785939995
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.532594604
Short name T56
Test name
Test status
Simulation time 90532268245 ps
CPU time 494.79 seconds
Started Feb 04 01:31:55 PM PST 24
Finished Feb 04 01:40:15 PM PST 24
Peak memory 199132 kb
Host smart-e57e152e-357d-4b73-9a58-7dd9506f1695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532594604 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.hmac_test_sha_vectors.532594604
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3940682650
Short name T440
Test name
Test status
Simulation time 4349492845 ps
CPU time 57.23 seconds
Started Feb 04 01:32:01 PM PST 24
Finished Feb 04 01:33:00 PM PST 24
Peak memory 199140 kb
Host smart-5c8c6d51-3c76-4dd9-a9ce-748a4798b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940682650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3940682650
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2168980333
Short name T580
Test name
Test status
Simulation time 45123486 ps
CPU time 0.56 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:31 PM PST 24
Peak memory 193316 kb
Host smart-42c52c88-98c1-459a-960e-91d4d652e10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168980333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2168980333
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1976212351
Short name T711
Test name
Test status
Simulation time 671155245 ps
CPU time 16.04 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:32:24 PM PST 24
Peak memory 199056 kb
Host smart-9279fd7e-8eab-42d4-b9f9-f4f2e279a14d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976212351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1976212351
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3125429623
Short name T270
Test name
Test status
Simulation time 1487174040 ps
CPU time 10.1 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:32:31 PM PST 24
Peak memory 199056 kb
Host smart-637e024c-2d2d-4275-9e80-c342c1230a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125429623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3125429623
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3596344223
Short name T303
Test name
Test status
Simulation time 985657295 ps
CPU time 50.22 seconds
Started Feb 04 01:32:06 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 199032 kb
Host smart-485c2d7f-6536-4842-8e94-7b40b0e8e349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596344223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3596344223
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.492577119
Short name T508
Test name
Test status
Simulation time 10298781757 ps
CPU time 85.24 seconds
Started Feb 04 01:32:15 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 199096 kb
Host smart-fa3d35b8-de7e-45d1-9a10-f80573c3501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492577119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.492577119
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2138892932
Short name T724
Test name
Test status
Simulation time 14919285901 ps
CPU time 31.44 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:42 PM PST 24
Peak memory 199080 kb
Host smart-f4265eae-0b20-4731-8889-126b0ae80496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138892932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2138892932
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3841255284
Short name T55
Test name
Test status
Simulation time 88762664 ps
CPU time 0.95 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:30 PM PST 24
Peak memory 217396 kb
Host smart-0b610a1a-0b8f-4ce8-a9f6-744e141ca721
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841255284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3841255284
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3262420631
Short name T650
Test name
Test status
Simulation time 370402752 ps
CPU time 2.6 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:32:24 PM PST 24
Peak memory 198476 kb
Host smart-1efecd57-e20e-4abd-bb9b-2282ac7e33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262420631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3262420631
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.605280393
Short name T480
Test name
Test status
Simulation time 10730160219 ps
CPU time 125.78 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:34:14 PM PST 24
Peak memory 199144 kb
Host smart-90a0c6c5-c0d2-488f-bf24-e86fb21e6b6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605280393 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.605280393
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1084924638
Short name T1
Test name
Test status
Simulation time 185308916626 ps
CPU time 490.72 seconds
Started Feb 04 01:32:19 PM PST 24
Finished Feb 04 01:40:32 PM PST 24
Peak memory 215444 kb
Host smart-dcb9c74c-c8b0-4f24-8252-e68cfc6aa231
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084924638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1084924638
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.630705280
Short name T655
Test name
Test status
Simulation time 106616028 ps
CPU time 1.08 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 197636 kb
Host smart-f7a4e263-6bca-4374-965c-b623231e0676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630705280 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.630705280
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.906583860
Short name T524
Test name
Test status
Simulation time 90324805711 ps
CPU time 468.01 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:39:58 PM PST 24
Peak memory 199140 kb
Host smart-153fa96f-cf37-4854-acab-d8d1d08f8d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906583860 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_sha_vectors.906583860
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2743050477
Short name T388
Test name
Test status
Simulation time 2149465360 ps
CPU time 26.5 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:32:35 PM PST 24
Peak memory 199072 kb
Host smart-c666a0b1-3a36-4949-881e-f843ef61217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743050477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2743050477
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2414351880
Short name T486
Test name
Test status
Simulation time 44809713 ps
CPU time 0.57 seconds
Started Feb 04 01:32:26 PM PST 24
Finished Feb 04 01:32:32 PM PST 24
Peak memory 193352 kb
Host smart-e9dcf0bd-66d1-4dcb-a2e2-037b1dd77ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414351880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2414351880
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1048973598
Short name T738
Test name
Test status
Simulation time 624670088 ps
CPU time 21.65 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:32:53 PM PST 24
Peak memory 231688 kb
Host smart-829c1f82-8400-410e-ba8c-0300764b0371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048973598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1048973598
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1574213451
Short name T351
Test name
Test status
Simulation time 40916399512 ps
CPU time 44.93 seconds
Started Feb 04 01:32:26 PM PST 24
Finished Feb 04 01:33:17 PM PST 24
Peak memory 198964 kb
Host smart-a1f1f5ce-9103-4172-bcc4-7e7509eff02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574213451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1574213451
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1501622937
Short name T63
Test name
Test status
Simulation time 3433009834 ps
CPU time 155.37 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:35:07 PM PST 24
Peak memory 199056 kb
Host smart-27c1dfd9-bded-4acc-958d-d8ceb29d5ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501622937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1501622937
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2076477352
Short name T222
Test name
Test status
Simulation time 4811241140 ps
CPU time 81.19 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:53 PM PST 24
Peak memory 199064 kb
Host smart-2781ca07-efe8-41e5-82f1-1bffcbaf9466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076477352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2076477352
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.454822198
Short name T214
Test name
Test status
Simulation time 7719809699 ps
CPU time 66.54 seconds
Started Feb 04 01:32:27 PM PST 24
Finished Feb 04 01:33:38 PM PST 24
Peak memory 198952 kb
Host smart-9fddbd5f-bd19-4d00-b952-9d69e75590ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454822198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.454822198
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1922242784
Short name T386
Test name
Test status
Simulation time 1178530934 ps
CPU time 2.27 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:34 PM PST 24
Peak memory 199032 kb
Host smart-204c123f-3f2f-4ad6-9785-416b0e822af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922242784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1922242784
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3960998706
Short name T141
Test name
Test status
Simulation time 38053270795 ps
CPU time 858.57 seconds
Started Feb 04 01:32:26 PM PST 24
Finished Feb 04 01:46:50 PM PST 24
Peak memory 215092 kb
Host smart-d66993ec-47a5-4e54-a455-34935dc315a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960998706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3960998706
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.43108222
Short name T782
Test name
Test status
Simulation time 58286483031 ps
CPU time 663 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:43:35 PM PST 24
Peak memory 237948 kb
Host smart-dd440e79-81d7-440a-9110-6505341671df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43108222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.43108222
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.866457788
Short name T734
Test name
Test status
Simulation time 279869066 ps
CPU time 1.18 seconds
Started Feb 04 01:32:14 PM PST 24
Finished Feb 04 01:32:16 PM PST 24
Peak memory 197224 kb
Host smart-726de0dc-3897-493b-8af8-dcfac15e285b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866457788 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.866457788
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2684332549
Short name T282
Test name
Test status
Simulation time 14865446502 ps
CPU time 360.68 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:38:32 PM PST 24
Peak memory 199084 kb
Host smart-6a7311de-b4ca-4458-845f-a3f97088cdc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684332549 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.2684332549
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1486216320
Short name T680
Test name
Test status
Simulation time 1392593264 ps
CPU time 18.43 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:32:39 PM PST 24
Peak memory 199004 kb
Host smart-6686e14a-acd4-4a9b-bbad-dedb00f9ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486216320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1486216320
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1767562823
Short name T794
Test name
Test status
Simulation time 231144386414 ps
CPU time 2215.77 seconds
Started Feb 04 01:35:43 PM PST 24
Finished Feb 04 02:12:43 PM PST 24
Peak memory 248180 kb
Host smart-1d9ca425-5864-4fc7-ae0d-2d0647c45cb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767562823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.1767562823
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.964516633
Short name T104
Test name
Test status
Simulation time 126091761195 ps
CPU time 1734.54 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 02:04:50 PM PST 24
Peak memory 261720 kb
Host smart-5b4ebebb-afc5-47e3-8b93-a0c26d531e67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964516633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.964516633
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.1306971861
Short name T475
Test name
Test status
Simulation time 35001744640 ps
CPU time 1680.36 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 02:03:50 PM PST 24
Peak memory 235908 kb
Host smart-bb162afe-7954-4e18-8891-e726a111a86e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306971861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.1306971861
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1831658116
Short name T810
Test name
Test status
Simulation time 74574512781 ps
CPU time 599.73 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 01:45:50 PM PST 24
Peak memory 226880 kb
Host smart-330c692f-bce0-4d1d-aeda-58e255da56ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831658116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.1831658116
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.3557959453
Short name T119
Test name
Test status
Simulation time 372018152189 ps
CPU time 2736.48 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 02:21:27 PM PST 24
Peak memory 248380 kb
Host smart-5051709c-f791-42f6-b81d-e01a86573c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557959453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.3557959453
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3022607917
Short name T32
Test name
Test status
Simulation time 27846264896 ps
CPU time 1413.38 seconds
Started Feb 04 01:35:49 PM PST 24
Finished Feb 04 01:59:26 PM PST 24
Peak memory 248328 kb
Host smart-d239dad3-b749-4423-9269-3811f8fabeb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022607917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3022607917
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.1953056561
Short name T675
Test name
Test status
Simulation time 227487308223 ps
CPU time 2781.32 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 02:22:12 PM PST 24
Peak memory 247724 kb
Host smart-7391e7d0-6797-4859-b254-515eb1c43576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953056561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.1953056561
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.898652498
Short name T378
Test name
Test status
Simulation time 322373083950 ps
CPU time 2645.19 seconds
Started Feb 04 01:35:43 PM PST 24
Finished Feb 04 02:19:53 PM PST 24
Peak memory 257540 kb
Host smart-98e00cc8-3b40-43b9-b260-0e46880cc524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898652498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.898652498
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1518840463
Short name T822
Test name
Test status
Simulation time 41172097 ps
CPU time 0.58 seconds
Started Feb 04 01:32:40 PM PST 24
Finished Feb 04 01:32:44 PM PST 24
Peak memory 193496 kb
Host smart-9f7dd823-5895-46a6-b038-9d57d4f3f385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518840463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1518840463
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4268700815
Short name T392
Test name
Test status
Simulation time 5034500724 ps
CPU time 40.3 seconds
Started Feb 04 01:32:40 PM PST 24
Finished Feb 04 01:33:24 PM PST 24
Peak memory 214972 kb
Host smart-df713396-ef0f-4032-8b36-65c6f30e2b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268700815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4268700815
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2478546658
Short name T459
Test name
Test status
Simulation time 2946826080 ps
CPU time 38.72 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:33:22 PM PST 24
Peak memory 199096 kb
Host smart-c4e26f22-6985-4335-a09e-102b6071fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478546658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2478546658
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1204987698
Short name T37
Test name
Test status
Simulation time 7019553420 ps
CPU time 95.07 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:34:12 PM PST 24
Peak memory 199100 kb
Host smart-8a535a44-c653-493f-92fd-f8eca7808471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204987698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1204987698
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2400583382
Short name T258
Test name
Test status
Simulation time 117970497600 ps
CPU time 64.04 seconds
Started Feb 04 01:32:36 PM PST 24
Finished Feb 04 01:33:46 PM PST 24
Peak memory 199116 kb
Host smart-2ba5f33c-1b6b-4528-a702-839f44965d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400583382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2400583382
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1378697081
Short name T299
Test name
Test status
Simulation time 1869006498 ps
CPU time 23.23 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:52 PM PST 24
Peak memory 199152 kb
Host smart-8a8d7b71-3dd6-4e9b-8158-46bef7ffa186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378697081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1378697081
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3131002369
Short name T453
Test name
Test status
Simulation time 397791552 ps
CPU time 2.68 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:33 PM PST 24
Peak memory 198764 kb
Host smart-1dd84780-0fe8-47c0-b1d7-768dca9ff1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131002369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3131002369
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4000257124
Short name T709
Test name
Test status
Simulation time 174945406781 ps
CPU time 184.01 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 216532 kb
Host smart-037cdb8e-7359-4751-a1f0-09fc633e008c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000257124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4000257124
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.1620099754
Short name T414
Test name
Test status
Simulation time 68112166010 ps
CPU time 639.59 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:43:17 PM PST 24
Peak memory 243248 kb
Host smart-1deb4f02-7197-475a-bc57-33673772cc34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620099754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.1620099754
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3953597704
Short name T361
Test name
Test status
Simulation time 169609156 ps
CPU time 0.95 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:32:38 PM PST 24
Peak memory 197324 kb
Host smart-04a66799-5d8e-43dc-98dc-af7eed42297a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953597704 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3953597704
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3311184654
Short name T735
Test name
Test status
Simulation time 8763515073 ps
CPU time 454.45 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:40:18 PM PST 24
Peak memory 199076 kb
Host smart-086d4766-0917-4f26-bba1-1810d9dee13f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311184654 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.3311184654
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2977650733
Short name T641
Test name
Test status
Simulation time 5827975170 ps
CPU time 66.18 seconds
Started Feb 04 01:32:38 PM PST 24
Finished Feb 04 01:33:50 PM PST 24
Peak memory 199060 kb
Host smart-f9132812-5240-4a1a-a019-3f047fcd065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977650733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2977650733
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.3213213929
Short name T817
Test name
Test status
Simulation time 401648219415 ps
CPU time 1861.95 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 02:07:03 PM PST 24
Peak memory 244456 kb
Host smart-794e8e38-21d6-47b2-84c1-94395ab9094d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213213929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.3213213929
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1627159391
Short name T228
Test name
Test status
Simulation time 196583327566 ps
CPU time 515.67 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:44:40 PM PST 24
Peak memory 240172 kb
Host smart-99c0901b-9b6b-4e54-9ce6-7549e9ec6f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627159391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.1627159391
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.4150617124
Short name T656
Test name
Test status
Simulation time 117906249331 ps
CPU time 5330.63 seconds
Started Feb 04 01:36:01 PM PST 24
Finished Feb 04 03:04:53 PM PST 24
Peak memory 243256 kb
Host smart-ca22b5a0-56c8-42f7-b649-603f7d74a9ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150617124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.4150617124
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.1837734889
Short name T591
Test name
Test status
Simulation time 280179821353 ps
CPU time 824.99 seconds
Started Feb 04 01:36:04 PM PST 24
Finished Feb 04 01:49:50 PM PST 24
Peak memory 229668 kb
Host smart-7b1a083e-32b2-492a-bb94-d02a336f26b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837734889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.1837734889
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.2813997220
Short name T604
Test name
Test status
Simulation time 118552659311 ps
CPU time 1088.95 seconds
Started Feb 04 01:35:54 PM PST 24
Finished Feb 04 01:54:07 PM PST 24
Peak memory 244072 kb
Host smart-c28be746-9bba-41bb-9909-bf3d3ccd6f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813997220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.2813997220
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.4018595445
Short name T285
Test name
Test status
Simulation time 138428516422 ps
CPU time 1363.87 seconds
Started Feb 04 01:36:02 PM PST 24
Finished Feb 04 01:58:48 PM PST 24
Peak memory 224720 kb
Host smart-0faf0c5a-6f16-4fef-ab7b-cd2330b99461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018595445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.4018595445
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.283377072
Short name T704
Test name
Test status
Simulation time 33123878188 ps
CPU time 1619.62 seconds
Started Feb 04 01:36:01 PM PST 24
Finished Feb 04 02:03:02 PM PST 24
Peak memory 215540 kb
Host smart-b29c90d7-5169-418f-a3d0-f00bf91b7ce0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283377072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.283377072
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.3902406695
Short name T481
Test name
Test status
Simulation time 152454050461 ps
CPU time 3853.51 seconds
Started Feb 04 01:36:01 PM PST 24
Finished Feb 04 02:40:16 PM PST 24
Peak memory 256552 kb
Host smart-21724c48-a0ab-4f98-b56a-7160d6430371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902406695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.3902406695
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.4012334119
Short name T307
Test name
Test status
Simulation time 232985220174 ps
CPU time 1485.27 seconds
Started Feb 04 01:36:12 PM PST 24
Finished Feb 04 02:01:01 PM PST 24
Peak memory 215016 kb
Host smart-30e19af1-5c6f-4d10-9de9-2d67408fda97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012334119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.4012334119
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.2612553948
Short name T253
Test name
Test status
Simulation time 352401631567 ps
CPU time 477.46 seconds
Started Feb 04 01:36:11 PM PST 24
Finished Feb 04 01:44:11 PM PST 24
Peak memory 215456 kb
Host smart-fed4ffe8-af30-4401-95a7-6b6aa9109297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612553948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.2612553948
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1551735022
Short name T527
Test name
Test status
Simulation time 23795917 ps
CPU time 0.57 seconds
Started Feb 04 01:32:52 PM PST 24
Finished Feb 04 01:32:55 PM PST 24
Peak memory 193444 kb
Host smart-d96038a8-905f-4ffb-ae33-48c30f3f16aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551735022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1551735022
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4211397052
Short name T608
Test name
Test status
Simulation time 804043443 ps
CPU time 24.61 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:33:07 PM PST 24
Peak memory 214952 kb
Host smart-1622d2e8-df7e-4d74-83d6-60345f588e5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211397052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4211397052
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1664367104
Short name T818
Test name
Test status
Simulation time 6905942786 ps
CPU time 39.13 seconds
Started Feb 04 01:32:38 PM PST 24
Finished Feb 04 01:33:23 PM PST 24
Peak memory 199092 kb
Host smart-33eba50a-031c-4b8e-b009-0b2fed0391bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664367104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1664367104
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3676760287
Short name T34
Test name
Test status
Simulation time 7589403630 ps
CPU time 100.23 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:34:23 PM PST 24
Peak memory 199076 kb
Host smart-a10d2de6-8a06-4cba-bbd0-486116e99283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676760287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3676760287
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2411191158
Short name T489
Test name
Test status
Simulation time 17497401986 ps
CPU time 95.35 seconds
Started Feb 04 01:32:36 PM PST 24
Finished Feb 04 01:34:17 PM PST 24
Peak memory 199132 kb
Host smart-d4ee1857-6c30-4997-bc12-9ba59ac55dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411191158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2411191158
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2888848285
Short name T333
Test name
Test status
Simulation time 1305139327 ps
CPU time 17.68 seconds
Started Feb 04 01:32:42 PM PST 24
Finished Feb 04 01:33:02 PM PST 24
Peak memory 198920 kb
Host smart-93a03a45-d250-442e-bce1-90908dae468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888848285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2888848285
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3180512520
Short name T245
Test name
Test status
Simulation time 321887364 ps
CPU time 3.2 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:32:41 PM PST 24
Peak memory 198848 kb
Host smart-c4fb7e8d-3b28-4913-9d9c-af74d830907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180512520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3180512520
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2072118361
Short name T125
Test name
Test status
Simulation time 79881392492 ps
CPU time 1388.33 seconds
Started Feb 04 01:32:39 PM PST 24
Finished Feb 04 01:55:52 PM PST 24
Peak memory 213040 kb
Host smart-201fee99-ccce-496b-9fd1-fa028dd93df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072118361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2072118361
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1661207501
Short name T652
Test name
Test status
Simulation time 442064944655 ps
CPU time 3667.22 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 02:33:48 PM PST 24
Peak memory 245404 kb
Host smart-326483f6-f384-4456-bfbb-145dc6ca7460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661207501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.1661207501
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1969691633
Short name T482
Test name
Test status
Simulation time 57186400 ps
CPU time 1.09 seconds
Started Feb 04 01:32:36 PM PST 24
Finished Feb 04 01:32:43 PM PST 24
Peak memory 197684 kb
Host smart-89fba6ef-2101-4d70-a4bf-fb7c1bdc85e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969691633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1969691633
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3458162033
Short name T400
Test name
Test status
Simulation time 33122379223 ps
CPU time 361.93 seconds
Started Feb 04 01:32:48 PM PST 24
Finished Feb 04 01:38:51 PM PST 24
Peak memory 199024 kb
Host smart-1016af0f-7e07-449b-bb93-799704d44d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458162033 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3458162033
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1697475826
Short name T347
Test name
Test status
Simulation time 1194535537 ps
CPU time 50.12 seconds
Started Feb 04 01:32:39 PM PST 24
Finished Feb 04 01:33:34 PM PST 24
Peak memory 199028 kb
Host smart-5853bbb8-2af4-4046-9b4f-7821ef8633af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697475826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1697475826
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.4198859344
Short name T105
Test name
Test status
Simulation time 45678155253 ps
CPU time 1768.49 seconds
Started Feb 04 01:35:55 PM PST 24
Finished Feb 04 02:05:26 PM PST 24
Peak memory 241100 kb
Host smart-d3c96ffa-ea41-4af8-8556-b8b3b87dd22f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198859344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.4198859344
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.755811967
Short name T717
Test name
Test status
Simulation time 46279575933 ps
CPU time 194.65 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 01:39:10 PM PST 24
Peak memory 231920 kb
Host smart-e9247b2d-28b8-4b24-af0b-d8a7baae2b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755811967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.755811967
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.3473007243
Short name T474
Test name
Test status
Simulation time 14883818501 ps
CPU time 737.5 seconds
Started Feb 04 01:36:12 PM PST 24
Finished Feb 04 01:48:34 PM PST 24
Peak memory 243416 kb
Host smart-d96522e9-34d1-471b-97f8-4bee414a09c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473007243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.3473007243
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.3657939497
Short name T659
Test name
Test status
Simulation time 99962654821 ps
CPU time 1485.4 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 02:00:51 PM PST 24
Peak memory 247472 kb
Host smart-8055bdca-fcbd-4401-9fec-d71182d67b8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657939497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.3657939497
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.3091139113
Short name T820
Test name
Test status
Simulation time 227421733479 ps
CPU time 2975.16 seconds
Started Feb 04 01:36:02 PM PST 24
Finished Feb 04 02:25:39 PM PST 24
Peak memory 256488 kb
Host smart-f00fae73-e255-4719-98b9-b647225d818a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091139113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.3091139113
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.2632533059
Short name T129
Test name
Test status
Simulation time 168550361922 ps
CPU time 1553.39 seconds
Started Feb 04 01:35:55 PM PST 24
Finished Feb 04 02:01:51 PM PST 24
Peak memory 250356 kb
Host smart-51fa868a-f018-4120-8da2-957b251ce368
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632533059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.2632533059
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.2144091137
Short name T544
Test name
Test status
Simulation time 327669299954 ps
CPU time 4176.07 seconds
Started Feb 04 01:36:02 PM PST 24
Finished Feb 04 02:45:39 PM PST 24
Peak memory 272812 kb
Host smart-e007b310-3119-48db-873f-374b7e6c6bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144091137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.2144091137
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1158940284
Short name T567
Test name
Test status
Simulation time 41686084 ps
CPU time 0.57 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 193468 kb
Host smart-d35f44bc-7a71-4cd9-948f-ba24c1e2fcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158940284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1158940284
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.922689048
Short name T396
Test name
Test status
Simulation time 3339932948 ps
CPU time 66.22 seconds
Started Feb 04 01:32:34 PM PST 24
Finished Feb 04 01:33:43 PM PST 24
Peak memory 240084 kb
Host smart-163f1edf-7d50-4ab5-9bee-bda50c0124ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922689048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.922689048
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2212900410
Short name T764
Test name
Test status
Simulation time 6931092541 ps
CPU time 72.44 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:33:50 PM PST 24
Peak memory 199128 kb
Host smart-78c842d2-0bfd-4dc7-921f-a1789dd3e21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212900410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2212900410
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3748070640
Short name T846
Test name
Test status
Simulation time 6203371147 ps
CPU time 82.09 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:34:06 PM PST 24
Peak memory 199044 kb
Host smart-1abd722e-a558-4b7d-8c7f-b7cafc2592c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748070640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3748070640
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.4051355160
Short name T773
Test name
Test status
Simulation time 54939053741 ps
CPU time 119.46 seconds
Started Feb 04 01:32:38 PM PST 24
Finished Feb 04 01:34:43 PM PST 24
Peak memory 199140 kb
Host smart-3c93c21d-516b-4171-8081-cc04b76cd5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051355160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4051355160
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.320959836
Short name T550
Test name
Test status
Simulation time 1965699247 ps
CPU time 102.48 seconds
Started Feb 04 01:32:41 PM PST 24
Finished Feb 04 01:34:26 PM PST 24
Peak memory 199052 kb
Host smart-aaf1c462-ac6b-4066-b2f2-751c5611d425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320959836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.320959836
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.605522478
Short name T254
Test name
Test status
Simulation time 51083986 ps
CPU time 1.57 seconds
Started Feb 04 01:32:37 PM PST 24
Finished Feb 04 01:32:44 PM PST 24
Peak memory 198892 kb
Host smart-b2317733-65f9-4e93-8e32-9df42e14b5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605522478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.605522478
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.280595363
Short name T415
Test name
Test status
Simulation time 27316197719 ps
CPU time 418.3 seconds
Started Feb 04 01:32:38 PM PST 24
Finished Feb 04 01:39:42 PM PST 24
Peak memory 199148 kb
Host smart-27ad14c8-4c02-4cc4-a34f-ca81f9da5678
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280595363 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.280595363
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.3016422226
Short name T335
Test name
Test status
Simulation time 140109326570 ps
CPU time 1776.22 seconds
Started Feb 04 01:32:59 PM PST 24
Finished Feb 04 02:02:38 PM PST 24
Peak memory 247896 kb
Host smart-0f6dd455-2d6b-4b32-b017-3cf564d20285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016422226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.3016422226
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.4072636749
Short name T785
Test name
Test status
Simulation time 154479071 ps
CPU time 1 seconds
Started Feb 04 01:32:39 PM PST 24
Finished Feb 04 01:32:45 PM PST 24
Peak memory 195948 kb
Host smart-2a118bc7-c339-426d-9fcb-92adef1160c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072636749 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.4072636749
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.278653769
Short name T226
Test name
Test status
Simulation time 57813029642 ps
CPU time 451.34 seconds
Started Feb 04 01:32:35 PM PST 24
Finished Feb 04 01:40:09 PM PST 24
Peak memory 199104 kb
Host smart-4f384f3c-ddd2-4dfd-b1d8-0af20248dc76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278653769 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_test_sha_vectors.278653769
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.411794451
Short name T661
Test name
Test status
Simulation time 403191604 ps
CPU time 16.68 seconds
Started Feb 04 01:32:34 PM PST 24
Finished Feb 04 01:32:54 PM PST 24
Peak memory 199052 kb
Host smart-6793f571-1d81-4a8f-976f-f3eee119b868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411794451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.411794451
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1988428597
Short name T460
Test name
Test status
Simulation time 100728512394 ps
CPU time 344.54 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 01:41:40 PM PST 24
Peak memory 207812 kb
Host smart-e308cfbd-5e6a-4067-b0be-a58b152680ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988428597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1988428597
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.1788131938
Short name T8
Test name
Test status
Simulation time 192880798301 ps
CPU time 1002.08 seconds
Started Feb 04 01:36:02 PM PST 24
Finished Feb 04 01:52:45 PM PST 24
Peak memory 215400 kb
Host smart-0a622630-e9fb-405d-8955-05154ced0570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788131938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.1788131938
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.3150559053
Short name T127
Test name
Test status
Simulation time 513537328276 ps
CPU time 2055.38 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 02:10:17 PM PST 24
Peak memory 243216 kb
Host smart-22077c80-5e91-44ae-a6f9-6e3391d0e0bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150559053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.3150559053
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.2629453767
Short name T57
Test name
Test status
Simulation time 140877330495 ps
CPU time 532.95 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:44:57 PM PST 24
Peak memory 208480 kb
Host smart-d9732093-7323-4aea-8a6e-4af08d555e5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629453767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.2629453767
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.4111097287
Short name T256
Test name
Test status
Simulation time 88555441523 ps
CPU time 278.04 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 01:40:40 PM PST 24
Peak memory 215388 kb
Host smart-dcdeadde-4789-40e9-9550-28f5ef02ed8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111097287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.4111097287
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.2364258060
Short name T593
Test name
Test status
Simulation time 210605260126 ps
CPU time 528.11 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:44:53 PM PST 24
Peak memory 223804 kb
Host smart-c9a1aba4-897a-41ff-a78b-03296400e6f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364258060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.2364258060
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.963497462
Short name T126
Test name
Test status
Simulation time 37528756563 ps
CPU time 980.68 seconds
Started Feb 04 01:36:11 PM PST 24
Finished Feb 04 01:52:34 PM PST 24
Peak memory 207252 kb
Host smart-1a7232d7-903d-414d-ac9d-957c2a93787a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963497462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.963497462
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3867100096
Short name T807
Test name
Test status
Simulation time 113961851557 ps
CPU time 1201.68 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 01:56:04 PM PST 24
Peak memory 223768 kb
Host smart-3a448ed8-885a-4754-bd12-a7445d510da6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867100096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3867100096
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.4044243451
Short name T342
Test name
Test status
Simulation time 68104840344 ps
CPU time 198.23 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:39:23 PM PST 24
Peak memory 207396 kb
Host smart-62878ab3-ed2f-4157-9cd0-a4b5ebdafaf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044243451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.4044243451
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.1971981355
Short name T321
Test name
Test status
Simulation time 22137434744 ps
CPU time 568.72 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:45:33 PM PST 24
Peak memory 215368 kb
Host smart-35f1f699-f7c8-46ee-9783-eccb416540c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971981355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.1971981355
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2299013306
Short name T326
Test name
Test status
Simulation time 18951602 ps
CPU time 0.57 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 193476 kb
Host smart-4045e75e-c3c2-4a02-ad3f-530b612dd190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299013306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2299013306
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2901770339
Short name T651
Test name
Test status
Simulation time 1341800551 ps
CPU time 43.78 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 231268 kb
Host smart-4818d26a-a2dc-4cc5-9635-2ce830ba5b5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901770339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2901770339
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2140212805
Short name T412
Test name
Test status
Simulation time 38276551991 ps
CPU time 35.12 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:33:33 PM PST 24
Peak memory 199132 kb
Host smart-0cb903a5-7ef4-4d7d-8c31-cb3834b2d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140212805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2140212805
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4204237878
Short name T517
Test name
Test status
Simulation time 7384103455 ps
CPU time 82.99 seconds
Started Feb 04 01:32:57 PM PST 24
Finished Feb 04 01:34:23 PM PST 24
Peak memory 199112 kb
Host smart-ce536919-1d1e-4cbb-890b-fba996276040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204237878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4204237878
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3930809839
Short name T781
Test name
Test status
Simulation time 1559079683 ps
CPU time 77.31 seconds
Started Feb 04 01:32:54 PM PST 24
Finished Feb 04 01:34:13 PM PST 24
Peak memory 199056 kb
Host smart-4a0c28e2-a49e-401f-8eb8-7e0ce39baea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930809839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3930809839
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3529802203
Short name T341
Test name
Test status
Simulation time 13501927805 ps
CPU time 48.78 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:33:47 PM PST 24
Peak memory 199100 kb
Host smart-70a40655-1879-4258-abf5-b9617d3cf1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529802203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3529802203
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1418221885
Short name T484
Test name
Test status
Simulation time 157910582 ps
CPU time 2.14 seconds
Started Feb 04 01:32:54 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 199012 kb
Host smart-9d5a821d-5315-414b-b350-ef4bc7f5ef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418221885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1418221885
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3484960726
Short name T109
Test name
Test status
Simulation time 70226401388 ps
CPU time 928.27 seconds
Started Feb 04 01:33:04 PM PST 24
Finished Feb 04 01:48:34 PM PST 24
Peak memory 231848 kb
Host smart-d56429f8-643a-4361-ae74-203b5099665c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484960726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3484960726
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.3724169655
Short name T124
Test name
Test status
Simulation time 204793966447 ps
CPU time 2857.32 seconds
Started Feb 04 01:32:54 PM PST 24
Finished Feb 04 02:20:34 PM PST 24
Peak memory 264328 kb
Host smart-8982cc6f-0cbe-4acc-a51e-f6bfbcd8a040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724169655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.3724169655
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.193306883
Short name T726
Test name
Test status
Simulation time 44128042 ps
CPU time 0.95 seconds
Started Feb 04 01:32:58 PM PST 24
Finished Feb 04 01:33:01 PM PST 24
Peak memory 196868 kb
Host smart-0dea9bc8-ea05-489f-96db-341e2d254911
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193306883 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.193306883
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2036109665
Short name T312
Test name
Test status
Simulation time 42794027875 ps
CPU time 470.78 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:40:48 PM PST 24
Peak memory 199144 kb
Host smart-344105cb-fa2f-4b3c-bef0-db8ce552a91e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036109665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.2036109665
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2103014685
Short name T869
Test name
Test status
Simulation time 4355465109 ps
CPU time 79.28 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:34:21 PM PST 24
Peak memory 199104 kb
Host smart-6165fb5e-d2a8-45ad-aeca-38b0c6f8e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103014685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2103014685
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.2310144476
Short name T751
Test name
Test status
Simulation time 78318811318 ps
CPU time 1170.25 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 01:55:32 PM PST 24
Peak memory 240140 kb
Host smart-cfe54841-9c81-4a50-8814-659eed0375c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310144476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.2310144476
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.1463045706
Short name T654
Test name
Test status
Simulation time 272641011039 ps
CPU time 566.65 seconds
Started Feb 04 01:36:03 PM PST 24
Finished Feb 04 01:45:31 PM PST 24
Peak memory 248340 kb
Host smart-c850fac2-6005-4e1e-87b2-894003f41962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463045706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.1463045706
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.751263916
Short name T790
Test name
Test status
Simulation time 495178328078 ps
CPU time 1554.44 seconds
Started Feb 04 01:36:00 PM PST 24
Finished Feb 04 02:01:56 PM PST 24
Peak memory 227308 kb
Host smart-a4209886-9950-47f0-9495-c4418ffc1696
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751263916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.751263916
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.2247137317
Short name T566
Test name
Test status
Simulation time 152926054621 ps
CPU time 1327.12 seconds
Started Feb 04 01:36:04 PM PST 24
Finished Feb 04 01:58:13 PM PST 24
Peak memory 248312 kb
Host smart-6ac5e72c-8def-4e83-a801-aa8116de77f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247137317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.2247137317
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.2463176681
Short name T317
Test name
Test status
Simulation time 164518783180 ps
CPU time 2701.49 seconds
Started Feb 04 01:36:12 PM PST 24
Finished Feb 04 02:21:17 PM PST 24
Peak memory 256540 kb
Host smart-d2d4fa98-37ab-409d-b587-6e7d37e7abd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463176681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.2463176681
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.1161435829
Short name T762
Test name
Test status
Simulation time 84877244178 ps
CPU time 383.61 seconds
Started Feb 04 01:36:02 PM PST 24
Finished Feb 04 01:42:27 PM PST 24
Peak memory 214580 kb
Host smart-8db04129-20da-409a-a8c7-5c8a7ff8e36c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161435829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.1161435829
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.2196175651
Short name T844
Test name
Test status
Simulation time 260612015414 ps
CPU time 1943.22 seconds
Started Feb 04 01:36:15 PM PST 24
Finished Feb 04 02:08:41 PM PST 24
Peak memory 248384 kb
Host smart-c3ab521b-8425-47c3-b00b-ccb3e40420ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196175651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.2196175651
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.1454863164
Short name T117
Test name
Test status
Simulation time 262055331493 ps
CPU time 1040.5 seconds
Started Feb 04 01:36:11 PM PST 24
Finished Feb 04 01:53:35 PM PST 24
Peak memory 240464 kb
Host smart-4e1a2517-5570-4ddb-89dc-3603ea77ccf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454863164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.1454863164
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.573975303
Short name T389
Test name
Test status
Simulation time 13060988927 ps
CPU time 192.45 seconds
Started Feb 04 01:36:13 PM PST 24
Finished Feb 04 01:39:30 PM PST 24
Peak memory 199184 kb
Host smart-e686a7fa-e3ac-40a4-b635-5e31eb2fd8b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573975303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.573975303
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.2423428865
Short name T407
Test name
Test status
Simulation time 474983038997 ps
CPU time 754.12 seconds
Started Feb 04 01:36:14 PM PST 24
Finished Feb 04 01:48:52 PM PST 24
Peak memory 223828 kb
Host smart-84f38196-cd72-4276-9844-3add2ac5f282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423428865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.2423428865
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3963109290
Short name T741
Test name
Test status
Simulation time 15310067 ps
CPU time 0.59 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 193576 kb
Host smart-07e9630f-4123-4653-8416-b11530f3b6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963109290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3963109290
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4219919515
Short name T522
Test name
Test status
Simulation time 4628199445 ps
CPU time 53.39 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:33:50 PM PST 24
Peak memory 223704 kb
Host smart-b33c0aed-7d0d-434f-a11f-98f5f81053fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219919515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4219919515
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3425137791
Short name T441
Test name
Test status
Simulation time 5862372842 ps
CPU time 18.53 seconds
Started Feb 04 01:32:52 PM PST 24
Finished Feb 04 01:33:13 PM PST 24
Peak memory 199136 kb
Host smart-df0a9680-3de3-49e3-8db8-c7052acfea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425137791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3425137791
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1476058022
Short name T495
Test name
Test status
Simulation time 373703261 ps
CPU time 19.98 seconds
Started Feb 04 01:33:04 PM PST 24
Finished Feb 04 01:33:26 PM PST 24
Peak memory 199032 kb
Host smart-c9463537-3187-4c1b-9459-afb6cb3081f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476058022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1476058022
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2385392796
Short name T515
Test name
Test status
Simulation time 3573487932 ps
CPU time 181.67 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:35:59 PM PST 24
Peak memory 199116 kb
Host smart-128a6fe6-da61-49d3-9ffb-e1cd18257a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385392796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2385392796
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3522070516
Short name T215
Test name
Test status
Simulation time 7993450383 ps
CPU time 39.16 seconds
Started Feb 04 01:33:05 PM PST 24
Finished Feb 04 01:33:45 PM PST 24
Peak memory 199116 kb
Host smart-f7417c9c-3f3e-4e27-9772-b3107051ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522070516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3522070516
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1505216428
Short name T755
Test name
Test status
Simulation time 560464408 ps
CPU time 3.34 seconds
Started Feb 04 01:32:59 PM PST 24
Finished Feb 04 01:33:05 PM PST 24
Peak memory 198708 kb
Host smart-1c881ce7-9dc4-4a0c-8b4c-53f635264303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505216428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1505216428
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1606299708
Short name T504
Test name
Test status
Simulation time 235625263996 ps
CPU time 995.76 seconds
Started Feb 04 01:32:58 PM PST 24
Finished Feb 04 01:49:36 PM PST 24
Peak memory 240068 kb
Host smart-c55e24e3-de0c-4ba1-9c66-0577f6c3e4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606299708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1606299708
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1158333464
Short name T233
Test name
Test status
Simulation time 117545602713 ps
CPU time 225.69 seconds
Started Feb 04 01:32:57 PM PST 24
Finished Feb 04 01:36:46 PM PST 24
Peak memory 214928 kb
Host smart-25edf0ec-cce9-4a18-87d4-c6a20aeec2bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158333464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.1158333464
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1203236104
Short name T845
Test name
Test status
Simulation time 156402164 ps
CPU time 0.97 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:32:58 PM PST 24
Peak memory 196648 kb
Host smart-84abd7f9-42dc-40de-93b7-e81cdab3ade4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203236104 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1203236104
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.4123812441
Short name T284
Test name
Test status
Simulation time 28853630171 ps
CPU time 480.11 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:40:58 PM PST 24
Peak memory 199000 kb
Host smart-af4829fb-e970-4ddd-90e7-ea3b75d32bda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123812441 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.4123812441
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1268638671
Short name T715
Test name
Test status
Simulation time 1708807479 ps
CPU time 25.48 seconds
Started Feb 04 01:32:54 PM PST 24
Finished Feb 04 01:33:22 PM PST 24
Peak memory 199036 kb
Host smart-85e62f7f-14c0-4ea8-8709-2be8da892fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268638671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1268638671
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.3674481387
Short name T852
Test name
Test status
Simulation time 142130638478 ps
CPU time 1562.17 seconds
Started Feb 04 01:36:13 PM PST 24
Finished Feb 04 02:02:20 PM PST 24
Peak memory 244144 kb
Host smart-ac141dca-26be-453c-8f13-fb6e47c376f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674481387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.3674481387
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1978793564
Short name T555
Test name
Test status
Simulation time 15845105301 ps
CPU time 221.26 seconds
Started Feb 04 01:36:11 PM PST 24
Finished Feb 04 01:39:56 PM PST 24
Peak memory 215576 kb
Host smart-49f9f064-bad8-4cea-9c2f-6f7b9da3fd60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978793564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.1978793564
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.1257221325
Short name T114
Test name
Test status
Simulation time 234573510921 ps
CPU time 409.57 seconds
Started Feb 04 01:36:14 PM PST 24
Finished Feb 04 01:43:08 PM PST 24
Peak memory 247648 kb
Host smart-620f7a7f-f54d-4532-9df2-ef96a33e9779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257221325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.1257221325
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1942339301
Short name T789
Test name
Test status
Simulation time 58442282482 ps
CPU time 562.77 seconds
Started Feb 04 01:36:18 PM PST 24
Finished Feb 04 01:45:48 PM PST 24
Peak memory 213856 kb
Host smart-a046687b-7a7b-46ed-9aa2-9d996b0bf002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942339301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.1942339301
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2413867393
Short name T133
Test name
Test status
Simulation time 34702365385 ps
CPU time 695.34 seconds
Started Feb 04 01:36:16 PM PST 24
Finished Feb 04 01:47:54 PM PST 24
Peak memory 212836 kb
Host smart-b0c14f1a-03a9-48f7-9720-3408bf80b219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413867393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2413867393
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2452412463
Short name T811
Test name
Test status
Simulation time 32451851121 ps
CPU time 523.31 seconds
Started Feb 04 01:36:16 PM PST 24
Finished Feb 04 01:45:02 PM PST 24
Peak memory 247924 kb
Host smart-81ffd3b1-523e-428e-86a6-363145db4b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452412463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.2452412463
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.385229583
Short name T499
Test name
Test status
Simulation time 146086434144 ps
CPU time 2897.29 seconds
Started Feb 04 01:36:17 PM PST 24
Finished Feb 04 02:24:41 PM PST 24
Peak memory 259388 kb
Host smart-4e17a09a-6786-408e-bb4d-fd09fc034ce5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385229583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.385229583
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.192894728
Short name T783
Test name
Test status
Simulation time 71057659558 ps
CPU time 303.33 seconds
Started Feb 04 01:36:18 PM PST 24
Finished Feb 04 01:41:28 PM PST 24
Peak memory 233936 kb
Host smart-f1a88860-dda6-41a2-ab68-2b145e44f74a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192894728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.192894728
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.2247337287
Short name T265
Test name
Test status
Simulation time 109907897242 ps
CPU time 877.51 seconds
Started Feb 04 01:36:14 PM PST 24
Finished Feb 04 01:50:56 PM PST 24
Peak memory 246596 kb
Host smart-fbee4f49-34c6-4d88-a366-3cda6b628932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247337287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.2247337287
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.1668335899
Short name T308
Test name
Test status
Simulation time 331654394339 ps
CPU time 1265.4 seconds
Started Feb 04 01:36:16 PM PST 24
Finished Feb 04 01:57:24 PM PST 24
Peak memory 234124 kb
Host smart-c8abc04c-e0a4-4443-892a-235a48a1c9ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668335899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.1668335899
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3432167765
Short name T668
Test name
Test status
Simulation time 52469209 ps
CPU time 0.61 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:33:03 PM PST 24
Peak memory 193396 kb
Host smart-62016b83-ac11-4288-97b1-5cd7183ce9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432167765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3432167765
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1380357017
Short name T44
Test name
Test status
Simulation time 886634808 ps
CPU time 29.9 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:33:27 PM PST 24
Peak memory 227576 kb
Host smart-a71560d9-9301-4a6e-8857-07888fc3e6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380357017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1380357017
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3665325794
Short name T549
Test name
Test status
Simulation time 9384279775 ps
CPU time 42.04 seconds
Started Feb 04 01:33:04 PM PST 24
Finished Feb 04 01:33:48 PM PST 24
Peak memory 199116 kb
Host smart-67019128-6f1e-4be4-a3ec-e64d70d96194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665325794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3665325794
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3910204469
Short name T565
Test name
Test status
Simulation time 1676974271 ps
CPU time 58.38 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:33:55 PM PST 24
Peak memory 199124 kb
Host smart-9be4e1d5-6dea-4631-b248-0c75509e2479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910204469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3910204469
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1543053596
Short name T748
Test name
Test status
Simulation time 2929393263 ps
CPU time 36.99 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:33:34 PM PST 24
Peak memory 199052 kb
Host smart-403e59ec-7b54-4970-8716-4f21903ff728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543053596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1543053596
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4047001315
Short name T556
Test name
Test status
Simulation time 3873127992 ps
CPU time 77.74 seconds
Started Feb 04 01:32:56 PM PST 24
Finished Feb 04 01:34:16 PM PST 24
Peak memory 198836 kb
Host smart-0a34ac72-7b55-4ade-882f-f0ba931333a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047001315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4047001315
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.280551736
Short name T520
Test name
Test status
Simulation time 1872444295 ps
CPU time 3.66 seconds
Started Feb 04 01:32:59 PM PST 24
Finished Feb 04 01:33:05 PM PST 24
Peak memory 198668 kb
Host smart-31eaa7fa-0832-435b-8621-58357d6d0b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280551736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.280551736
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3929637312
Short name T143
Test name
Test status
Simulation time 183473810658 ps
CPU time 1582.47 seconds
Started Feb 04 01:32:59 PM PST 24
Finished Feb 04 01:59:24 PM PST 24
Peak memory 199088 kb
Host smart-fec7c8d3-1da9-41dd-a4be-a1c6c9a93ab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929637312 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3929637312
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.3315776910
Short name T479
Test name
Test status
Simulation time 38343844377 ps
CPU time 359.59 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:38:57 PM PST 24
Peak memory 231552 kb
Host smart-8b9ac51a-b528-48ea-b747-2cb876d8bd31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315776910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.3315776910
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.951844338
Short name T660
Test name
Test status
Simulation time 49516885 ps
CPU time 0.96 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:33:02 PM PST 24
Peak memory 196160 kb
Host smart-1156eaf3-3841-47c8-b393-30d255ddce88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951844338 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.951844338
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2620664055
Short name T290
Test name
Test status
Simulation time 37622142997 ps
CPU time 439.43 seconds
Started Feb 04 01:32:58 PM PST 24
Finished Feb 04 01:40:20 PM PST 24
Peak memory 199068 kb
Host smart-b5eaea53-e2dd-46a3-a2b4-dfd43e3001ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620664055 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.2620664055
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1036101848
Short name T340
Test name
Test status
Simulation time 2851454841 ps
CPU time 37.39 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:33:39 PM PST 24
Peak memory 199044 kb
Host smart-c4878005-da49-4c78-b708-084f75cdc0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036101848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1036101848
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.2420446103
Short name T525
Test name
Test status
Simulation time 44489684650 ps
CPU time 628.28 seconds
Started Feb 04 01:37:29 PM PST 24
Finished Feb 04 01:47:59 PM PST 24
Peak memory 228948 kb
Host smart-1f1b09e1-9ae6-4194-a8b3-a958bc05f032
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420446103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.2420446103
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1483312916
Short name T439
Test name
Test status
Simulation time 37281588932 ps
CPU time 1039.52 seconds
Started Feb 04 01:36:18 PM PST 24
Finished Feb 04 01:53:44 PM PST 24
Peak memory 215532 kb
Host smart-2a1526c9-8395-4bd4-8e2e-0a7003e83d80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483312916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.1483312916
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.2530138229
Short name T472
Test name
Test status
Simulation time 65246352558 ps
CPU time 1275.72 seconds
Started Feb 04 01:36:19 PM PST 24
Finished Feb 04 01:57:41 PM PST 24
Peak memory 248396 kb
Host smart-fa1e43df-5d66-4b46-abd1-9d0e82329d79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530138229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.2530138229
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.3454267072
Short name T765
Test name
Test status
Simulation time 680988551499 ps
CPU time 2762.69 seconds
Started Feb 04 01:36:18 PM PST 24
Finished Feb 04 02:22:27 PM PST 24
Peak memory 256536 kb
Host smart-90dd921f-25bd-4440-bf88-e5ac0edc7bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454267072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.3454267072
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.3503931398
Short name T138
Test name
Test status
Simulation time 2070472105019 ps
CPU time 2124.91 seconds
Started Feb 04 01:37:45 PM PST 24
Finished Feb 04 02:13:12 PM PST 24
Peak memory 256916 kb
Host smart-83404646-892b-4047-a991-ed40bf474486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503931398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.3503931398
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.3819725146
Short name T249
Test name
Test status
Simulation time 48300957647 ps
CPU time 1451.3 seconds
Started Feb 04 01:36:16 PM PST 24
Finished Feb 04 02:00:30 PM PST 24
Peak memory 244304 kb
Host smart-9ee829f8-51b0-45d8-8af4-d707c2865d6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819725146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.3819725146
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.34428105
Short name T702
Test name
Test status
Simulation time 50461562404 ps
CPU time 2548.59 seconds
Started Feb 04 01:36:16 PM PST 24
Finished Feb 04 02:18:47 PM PST 24
Peak memory 247540 kb
Host smart-c9b284bf-8ff9-4815-898d-a3b22fbb4e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34428105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.34428105
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.688353526
Short name T606
Test name
Test status
Simulation time 44216961485 ps
CPU time 405 seconds
Started Feb 04 01:36:17 PM PST 24
Finished Feb 04 01:43:04 PM PST 24
Peak memory 199140 kb
Host smart-76d2cb04-3e21-4adf-bf24-4d9c35e3821e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688353526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.688353526
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.3673535126
Short name T346
Test name
Test status
Simulation time 11791104364 ps
CPU time 223.77 seconds
Started Feb 04 01:36:17 PM PST 24
Finished Feb 04 01:40:07 PM PST 24
Peak memory 215572 kb
Host smart-7ae5b7f5-4049-4ecc-b5b4-973bea3a2905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673535126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.3673535126
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.1151407400
Short name T528
Test name
Test status
Simulation time 20225755293 ps
CPU time 403.81 seconds
Started Feb 04 01:36:34 PM PST 24
Finished Feb 04 01:43:19 PM PST 24
Peak memory 247292 kb
Host smart-4cc00c46-c7ff-41ea-b1ed-7d0ae2af7d12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151407400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.1151407400
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3539015526
Short name T134
Test name
Test status
Simulation time 2252620692 ps
CPU time 37.74 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:33:39 PM PST 24
Peak memory 222552 kb
Host smart-1db3512b-80bf-4a7c-a5b5-59a3374fd595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539015526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3539015526
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3129786589
Short name T145
Test name
Test status
Simulation time 1112063722 ps
CPU time 14.9 seconds
Started Feb 04 01:33:00 PM PST 24
Finished Feb 04 01:33:16 PM PST 24
Peak memory 199008 kb
Host smart-ad6b79a8-41c7-4d7e-b763-95c9e442277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129786589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3129786589
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2238859160
Short name T718
Test name
Test status
Simulation time 2422770126 ps
CPU time 67.07 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:34:04 PM PST 24
Peak memory 199072 kb
Host smart-d73464f8-8cfa-4e10-92b0-11bdd9c8adef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238859160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2238859160
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4131923354
Short name T564
Test name
Test status
Simulation time 8837703352 ps
CPU time 81.86 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:34:33 PM PST 24
Peak memory 199188 kb
Host smart-8eca01f5-d9f0-42a9-a7fe-62fdbac87f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131923354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4131923354
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.115877805
Short name T600
Test name
Test status
Simulation time 20952998955 ps
CPU time 81.53 seconds
Started Feb 04 01:32:57 PM PST 24
Finished Feb 04 01:34:21 PM PST 24
Peak memory 199108 kb
Host smart-f9625003-13b6-4230-a4c9-7a1975d750c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115877805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.115877805
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.451631790
Short name T369
Test name
Test status
Simulation time 1296926025 ps
CPU time 4.22 seconds
Started Feb 04 01:32:55 PM PST 24
Finished Feb 04 01:33:01 PM PST 24
Peak memory 199036 kb
Host smart-8959d067-a2e2-4c47-8113-1e83c6684fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451631790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.451631790
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.271677789
Short name T763
Test name
Test status
Simulation time 209998662357 ps
CPU time 1264.92 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:54:23 PM PST 24
Peak memory 199020 kb
Host smart-9eee36fd-fcf3-467c-849f-b34d61791ee1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271677789 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.271677789
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.751797703
Short name T473
Test name
Test status
Simulation time 644964676938 ps
CPU time 2706.36 seconds
Started Feb 04 01:33:14 PM PST 24
Finished Feb 04 02:18:29 PM PST 24
Peak memory 243540 kb
Host smart-ca33f688-0a40-4802-b358-1b94d25bfc07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751797703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.751797703
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2296123715
Short name T47
Test name
Test status
Simulation time 47128868 ps
CPU time 1 seconds
Started Feb 04 01:33:13 PM PST 24
Finished Feb 04 01:33:22 PM PST 24
Peak memory 197216 kb
Host smart-07f932fa-6d97-4018-bbe7-1f431042f0b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296123715 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2296123715
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.843344106
Short name T867
Test name
Test status
Simulation time 47130293007 ps
CPU time 374.41 seconds
Started Feb 04 01:33:12 PM PST 24
Finished Feb 04 01:39:34 PM PST 24
Peak memory 199132 kb
Host smart-d74f2393-4c93-4b5e-be55-2b8d08343fdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843344106 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_sha_vectors.843344106
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3385573701
Short name T227
Test name
Test status
Simulation time 2108126444 ps
CPU time 35.26 seconds
Started Feb 04 01:33:07 PM PST 24
Finished Feb 04 01:33:46 PM PST 24
Peak memory 199044 kb
Host smart-f0970d74-9d2a-4992-a48f-35d43b031a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385573701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3385573701
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.760474137
Short name T808
Test name
Test status
Simulation time 94258417284 ps
CPU time 327.74 seconds
Started Feb 04 01:36:26 PM PST 24
Finished Feb 04 01:41:55 PM PST 24
Peak memory 223724 kb
Host smart-3af3a4f9-2cc9-4cc8-964f-4e3efef97a2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760474137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.760474137
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.232290847
Short name T498
Test name
Test status
Simulation time 51018248589 ps
CPU time 741.11 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 01:48:50 PM PST 24
Peak memory 248276 kb
Host smart-7d1d2293-709b-428c-83c0-967ebfa2d8d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232290847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.232290847
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.1043819807
Short name T433
Test name
Test status
Simulation time 110932839180 ps
CPU time 845.32 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 01:50:34 PM PST 24
Peak memory 246808 kb
Host smart-067a559b-3685-4a92-9812-c091bb5bfdc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043819807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.1043819807
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3787102477
Short name T821
Test name
Test status
Simulation time 48461558091 ps
CPU time 603.83 seconds
Started Feb 04 01:36:28 PM PST 24
Finished Feb 04 01:46:33 PM PST 24
Peak memory 245272 kb
Host smart-5eb061b4-51e9-4660-af92-7e6eabc0ac8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787102477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.3787102477
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3292166846
Short name T292
Test name
Test status
Simulation time 76688716506 ps
CPU time 1482.7 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 02:01:11 PM PST 24
Peak memory 246300 kb
Host smart-6eb35277-a256-4ce8-8e72-64cf33fbf18e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292166846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.3292166846
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.2738439843
Short name T371
Test name
Test status
Simulation time 56565652664 ps
CPU time 1637.41 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 02:03:46 PM PST 24
Peak memory 241756 kb
Host smart-e4b319fb-7740-4d08-a704-36db0781ee50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738439843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.2738439843
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.1092853125
Short name T557
Test name
Test status
Simulation time 78711666821 ps
CPU time 1021.16 seconds
Started Feb 04 01:37:44 PM PST 24
Finished Feb 04 01:54:47 PM PST 24
Peak memory 256100 kb
Host smart-89154924-e078-4051-bd55-acc686f0666e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092853125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.1092853125
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.4147785133
Short name T311
Test name
Test status
Simulation time 419211463026 ps
CPU time 1490.64 seconds
Started Feb 04 01:36:26 PM PST 24
Finished Feb 04 02:01:18 PM PST 24
Peak memory 231992 kb
Host smart-124d36e5-2ddb-4bc1-81e5-5a92fe4b4f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147785133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.4147785133
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.3088816476
Short name T355
Test name
Test status
Simulation time 109880752703 ps
CPU time 1873.09 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 02:07:42 PM PST 24
Peak memory 256528 kb
Host smart-fcfd9832-3c9f-4ef3-a0cf-ba75115e3d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088816476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.3088816476
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3260331149
Short name T803
Test name
Test status
Simulation time 36258399 ps
CPU time 0.56 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:13 PM PST 24
Peak memory 193460 kb
Host smart-93021d26-3556-45d7-94a1-edce876754d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260331149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3260331149
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2228661060
Short name T359
Test name
Test status
Simulation time 1880803242 ps
CPU time 40.5 seconds
Started Feb 04 01:33:07 PM PST 24
Finished Feb 04 01:33:52 PM PST 24
Peak memory 225284 kb
Host smart-5afb4b7e-6eb0-43a5-9cc2-acf8a3549909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228661060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2228661060
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1462976257
Short name T366
Test name
Test status
Simulation time 531440574 ps
CPU time 8.11 seconds
Started Feb 04 01:33:06 PM PST 24
Finished Feb 04 01:33:15 PM PST 24
Peak memory 199036 kb
Host smart-95a9a381-78c7-48f9-8b6d-19ade4c7e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462976257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1462976257
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3681729189
Short name T315
Test name
Test status
Simulation time 275604951 ps
CPU time 13.94 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:27 PM PST 24
Peak memory 198988 kb
Host smart-6d7869a2-2843-4a17-b5d2-f49387d98a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681729189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3681729189
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2881890818
Short name T272
Test name
Test status
Simulation time 46925275480 ps
CPU time 122.36 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:35:17 PM PST 24
Peak memory 199072 kb
Host smart-5722b863-c7bd-462d-b7ac-4a258214a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881890818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2881890818
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2561056359
Short name T376
Test name
Test status
Simulation time 6412106144 ps
CPU time 41.31 seconds
Started Feb 04 01:33:12 PM PST 24
Finished Feb 04 01:34:01 PM PST 24
Peak memory 199072 kb
Host smart-3358306c-8fb7-4cde-97d2-b7ff7b57a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561056359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2561056359
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1330052640
Short name T327
Test name
Test status
Simulation time 1189316171 ps
CPU time 3.8 seconds
Started Feb 04 01:33:12 PM PST 24
Finished Feb 04 01:33:23 PM PST 24
Peak memory 199020 kb
Host smart-70a2a019-641a-4099-b9a4-4fd76963df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330052640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1330052640
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2664769783
Short name T391
Test name
Test status
Simulation time 19103561356 ps
CPU time 888.95 seconds
Started Feb 04 01:33:07 PM PST 24
Finished Feb 04 01:48:00 PM PST 24
Peak memory 199148 kb
Host smart-d177e8d0-c07c-49aa-980d-db3ff8f6ef57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664769783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2664769783
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.1578558682
Short name T43
Test name
Test status
Simulation time 139026547659 ps
CPU time 755.07 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:45:50 PM PST 24
Peak memory 240072 kb
Host smart-47a6d06a-92ea-4cb1-997f-60e0b62aa96d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578558682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.1578558682
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.310842927
Short name T523
Test name
Test status
Simulation time 35734674 ps
CPU time 0.86 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:33:18 PM PST 24
Peak memory 196104 kb
Host smart-35e4c9a4-98d5-4308-b4d0-db35ef0325a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310842927 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.310842927
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3957788331
Short name T864
Test name
Test status
Simulation time 24281366877 ps
CPU time 421.23 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:40:14 PM PST 24
Peak memory 199064 kb
Host smart-3a3c8f68-cfd4-4b86-8760-79e3da7f1583
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957788331 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.3957788331
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1660114842
Short name T410
Test name
Test status
Simulation time 17350443402 ps
CPU time 50.69 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:34:03 PM PST 24
Peak memory 199140 kb
Host smart-74cb6e60-2ff4-4a89-ac67-bd16ed557b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660114842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1660114842
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.1947440605
Short name T505
Test name
Test status
Simulation time 55630431035 ps
CPU time 2443.41 seconds
Started Feb 04 01:36:27 PM PST 24
Finished Feb 04 02:17:12 PM PST 24
Peak memory 264516 kb
Host smart-db2092a8-3802-4d40-8a94-d0ece92f32db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947440605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.1947440605
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.1284719258
Short name T300
Test name
Test status
Simulation time 83839572539 ps
CPU time 394.54 seconds
Started Feb 04 01:36:26 PM PST 24
Finished Feb 04 01:43:01 PM PST 24
Peak memory 239432 kb
Host smart-55fee45c-2a56-4d04-a064-1e0d80ed2b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284719258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.1284719258
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.528594334
Short name T799
Test name
Test status
Simulation time 47177979393 ps
CPU time 649.56 seconds
Started Feb 04 01:37:45 PM PST 24
Finished Feb 04 01:48:35 PM PST 24
Peak memory 217904 kb
Host smart-dcf362bb-2cfd-4db9-8316-f935f1da01e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528594334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.528594334
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.2888481985
Short name T716
Test name
Test status
Simulation time 30692197932 ps
CPU time 1649.22 seconds
Started Feb 04 01:36:28 PM PST 24
Finished Feb 04 02:03:59 PM PST 24
Peak memory 226428 kb
Host smart-9b5f4a4c-cb27-4e4c-a69b-5c1ea1827844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888481985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.2888481985
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.2000522012
Short name T653
Test name
Test status
Simulation time 71705143602 ps
CPU time 2779.01 seconds
Started Feb 04 01:36:26 PM PST 24
Finished Feb 04 02:22:46 PM PST 24
Peak memory 231932 kb
Host smart-3a2dc443-204b-4706-8a06-35bf78bc6a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000522012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.2000522012
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2090131485
Short name T859
Test name
Test status
Simulation time 60232500933 ps
CPU time 230.43 seconds
Started Feb 04 01:36:29 PM PST 24
Finished Feb 04 01:40:20 PM PST 24
Peak memory 246492 kb
Host smart-431aff3f-647c-458b-84d2-c11897155faf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090131485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.2090131485
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.2392224312
Short name T136
Test name
Test status
Simulation time 303983902817 ps
CPU time 3173.78 seconds
Started Feb 04 01:36:42 PM PST 24
Finished Feb 04 02:29:39 PM PST 24
Peak memory 227220 kb
Host smart-099ad0ee-d0b0-4cf4-a168-65f6804f39c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392224312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.2392224312
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.853692889
Short name T103
Test name
Test status
Simulation time 120627067202 ps
CPU time 2402.72 seconds
Started Feb 04 01:36:42 PM PST 24
Finished Feb 04 02:16:48 PM PST 24
Peak memory 264180 kb
Host smart-1959e76b-4278-46d2-9421-42e8d8000f12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853692889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.853692889
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.941737914
Short name T116
Test name
Test status
Simulation time 224100578149 ps
CPU time 842.14 seconds
Started Feb 04 01:36:41 PM PST 24
Finished Feb 04 01:50:46 PM PST 24
Peak memory 240136 kb
Host smart-248fab64-7b3f-4293-9383-ce5e6f7277d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941737914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.941737914
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.1514941839
Short name T802
Test name
Test status
Simulation time 88043349386 ps
CPU time 1464.29 seconds
Started Feb 04 01:36:41 PM PST 24
Finished Feb 04 02:01:08 PM PST 24
Peak memory 215004 kb
Host smart-cf54f18a-f8b8-4bd3-9424-7bc170d239c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514941839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.1514941839
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.940492758
Short name T559
Test name
Test status
Simulation time 27912220 ps
CPU time 0.57 seconds
Started Feb 04 01:33:08 PM PST 24
Finished Feb 04 01:33:12 PM PST 24
Peak memory 193328 kb
Host smart-8c1e4455-0b0c-4fcb-93f5-881597f45ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940492758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.940492758
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4222708927
Short name T344
Test name
Test status
Simulation time 3142698581 ps
CPU time 46.13 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:59 PM PST 24
Peak memory 214460 kb
Host smart-82c41c5d-0488-4f8e-801b-a827e25cd291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222708927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4222708927
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2106852620
Short name T59
Test name
Test status
Simulation time 22044516757 ps
CPU time 52.53 seconds
Started Feb 04 01:33:10 PM PST 24
Finished Feb 04 01:34:06 PM PST 24
Peak memory 199140 kb
Host smart-b98392ba-af6b-4c42-9ff0-294a767863d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106852620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2106852620
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2360774863
Short name T263
Test name
Test status
Simulation time 5877105494 ps
CPU time 69.98 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:34:23 PM PST 24
Peak memory 199036 kb
Host smart-0f396ceb-1411-435e-8fc4-1e6acf5e9078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360774863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2360774863
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.300274991
Short name T819
Test name
Test status
Simulation time 17290785269 ps
CPU time 146.2 seconds
Started Feb 04 01:33:12 PM PST 24
Finished Feb 04 01:35:46 PM PST 24
Peak memory 199096 kb
Host smart-79f8cdcf-cf5d-4184-8548-10cfca87341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300274991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.300274991
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.625165599
Short name T242
Test name
Test status
Simulation time 3365920192 ps
CPU time 43.42 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:56 PM PST 24
Peak memory 199036 kb
Host smart-9d002a12-8d45-473a-bc4c-b651b84ef4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625165599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.625165599
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1877137100
Short name T373
Test name
Test status
Simulation time 1018633047 ps
CPU time 3.41 seconds
Started Feb 04 01:33:13 PM PST 24
Finished Feb 04 01:33:24 PM PST 24
Peak memory 199036 kb
Host smart-0dceca70-293c-45d9-a4ea-10088d64c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877137100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1877137100
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.350855106
Short name T625
Test name
Test status
Simulation time 60159691286 ps
CPU time 823.84 seconds
Started Feb 04 01:33:07 PM PST 24
Finished Feb 04 01:46:54 PM PST 24
Peak memory 214344 kb
Host smart-085d4bbd-55fc-487a-9e2f-6ce2ee84b3d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350855106 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.350855106
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.3145203296
Short name T343
Test name
Test status
Simulation time 284959739244 ps
CPU time 1149.44 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:52:22 PM PST 24
Peak memory 253468 kb
Host smart-fc5679c5-9931-456e-ae92-ccd6db0f23a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145203296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.3145203296
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.4009565203
Short name T585
Test name
Test status
Simulation time 92354072 ps
CPU time 1.09 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:33:15 PM PST 24
Peak memory 197412 kb
Host smart-6b39e3d9-7464-4877-bbc8-686ea1571082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009565203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.4009565203
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.591199674
Short name T597
Test name
Test status
Simulation time 6735880842 ps
CPU time 50.22 seconds
Started Feb 04 01:33:10 PM PST 24
Finished Feb 04 01:34:03 PM PST 24
Peak memory 199180 kb
Host smart-a22ec76f-63d3-4330-adb0-0ebf55a2aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591199674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.591199674
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.2676232578
Short name T137
Test name
Test status
Simulation time 242757175043 ps
CPU time 2547.66 seconds
Started Feb 04 01:36:43 PM PST 24
Finished Feb 04 02:19:13 PM PST 24
Peak memory 237632 kb
Host smart-5103f7af-3d16-482a-86bf-2f6318925efd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676232578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.2676232578
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.4020786790
Short name T611
Test name
Test status
Simulation time 260751921290 ps
CPU time 1236.7 seconds
Started Feb 04 01:36:42 PM PST 24
Finished Feb 04 01:57:21 PM PST 24
Peak memory 231156 kb
Host smart-260b6cee-0dd9-4dcd-bdc8-7c3134ba5d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020786790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.4020786790
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.2916933468
Short name T111
Test name
Test status
Simulation time 41597939017 ps
CPU time 268.2 seconds
Started Feb 04 01:36:43 PM PST 24
Finished Feb 04 01:41:13 PM PST 24
Peak memory 215564 kb
Host smart-eeb9dede-38f2-416d-b676-d4aefecfd268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916933468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.2916933468
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.996344468
Short name T277
Test name
Test status
Simulation time 38863547441 ps
CPU time 669.1 seconds
Started Feb 04 01:36:43 PM PST 24
Finished Feb 04 01:47:55 PM PST 24
Peak memory 225724 kb
Host smart-ef3f0ac5-b902-4ce5-ad64-5a821b909e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996344468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.996344468
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.123902257
Short name T541
Test name
Test status
Simulation time 48604500181 ps
CPU time 874.74 seconds
Started Feb 04 01:36:46 PM PST 24
Finished Feb 04 01:51:22 PM PST 24
Peak memory 215764 kb
Host smart-ecd247d4-f3c0-4030-9c9f-3e0899103b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123902257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.123902257
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.1859022660
Short name T538
Test name
Test status
Simulation time 102088516925 ps
CPU time 2116.48 seconds
Started Feb 04 01:36:42 PM PST 24
Finished Feb 04 02:12:01 PM PST 24
Peak memory 226380 kb
Host smart-c7da81ff-87c0-4749-b50d-38f7b3c9bc23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859022660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.1859022660
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.1637304320
Short name T695
Test name
Test status
Simulation time 839881089125 ps
CPU time 1084.94 seconds
Started Feb 04 01:36:41 PM PST 24
Finished Feb 04 01:54:49 PM PST 24
Peak memory 214316 kb
Host smart-b7402d87-0b80-4ef5-9aac-4553ecdfb60a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637304320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.1637304320
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.2582766532
Short name T106
Test name
Test status
Simulation time 16084995334 ps
CPU time 317.69 seconds
Started Feb 04 01:36:42 PM PST 24
Finished Feb 04 01:42:02 PM PST 24
Peak memory 215488 kb
Host smart-2afc9ac9-d89b-4f08-9525-207283c2e9b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582766532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.2582766532
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3952806166
Short name T752
Test name
Test status
Simulation time 78741166582 ps
CPU time 311.53 seconds
Started Feb 04 01:36:41 PM PST 24
Finished Feb 04 01:41:56 PM PST 24
Peak memory 248092 kb
Host smart-b3f1efd7-19cb-448b-a92f-f71511a735d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952806166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3952806166
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.2240384392
Short name T830
Test name
Test status
Simulation time 630594518015 ps
CPU time 1330.11 seconds
Started Feb 04 01:36:45 PM PST 24
Finished Feb 04 01:58:57 PM PST 24
Peak memory 240128 kb
Host smart-12b3707f-e79c-4e30-9b19-2d044518b81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240384392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.2240384392
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.447672158
Short name T610
Test name
Test status
Simulation time 40481813 ps
CPU time 0.58 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:32 PM PST 24
Peak memory 193528 kb
Host smart-93b923dc-48a5-4144-937a-fcea8f251284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447672158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.447672158
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2422704129
Short name T792
Test name
Test status
Simulation time 2807866453 ps
CPU time 39.55 seconds
Started Feb 04 01:32:05 PM PST 24
Finished Feb 04 01:32:46 PM PST 24
Peak memory 228340 kb
Host smart-d22eb00e-b132-4c1a-b96e-7062b465c62f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422704129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2422704129
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2085054012
Short name T61
Test name
Test status
Simulation time 714041643 ps
CPU time 6.62 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:32:43 PM PST 24
Peak memory 198904 kb
Host smart-5fb02804-4f53-43f0-b058-c41ee1075f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085054012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2085054012
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3783783761
Short name T33
Test name
Test status
Simulation time 34320397639 ps
CPU time 90.58 seconds
Started Feb 04 01:32:21 PM PST 24
Finished Feb 04 01:33:57 PM PST 24
Peak memory 199188 kb
Host smart-ada22dfc-3f21-4333-a185-df2ad78e5de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783783761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3783783761
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4290472312
Short name T714
Test name
Test status
Simulation time 881649173 ps
CPU time 44.94 seconds
Started Feb 04 01:32:25 PM PST 24
Finished Feb 04 01:33:17 PM PST 24
Peak memory 198928 kb
Host smart-5c66ab5d-b47f-4226-b7d8-7db7733f7bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290472312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4290472312
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2297932756
Short name T570
Test name
Test status
Simulation time 607526858 ps
CPU time 2.4 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:32:34 PM PST 24
Peak memory 197940 kb
Host smart-d1f3abaa-701e-40a7-b3b9-f572c01493b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297932756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2297932756
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.4148007572
Short name T690
Test name
Test status
Simulation time 120481108 ps
CPU time 2.8 seconds
Started Feb 04 01:32:24 PM PST 24
Finished Feb 04 01:32:34 PM PST 24
Peak memory 198940 kb
Host smart-026618f8-ae24-45c8-b419-bda3eb2960a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148007572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4148007572
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1889854345
Short name T483
Test name
Test status
Simulation time 29192463271 ps
CPU time 94.82 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:33:56 PM PST 24
Peak memory 239480 kb
Host smart-0deb93e5-173f-4dba-89fb-1a06f51d7b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889854345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1889854345
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2358859950
Short name T462
Test name
Test status
Simulation time 40615434546 ps
CPU time 1996.33 seconds
Started Feb 04 01:32:17 PM PST 24
Finished Feb 04 02:05:37 PM PST 24
Peak memory 240144 kb
Host smart-c4a0a3e5-544a-41e3-b1a8-60335a5188b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358859950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2358859950
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2115251334
Short name T288
Test name
Test status
Simulation time 49790554 ps
CPU time 0.97 seconds
Started Feb 04 01:32:25 PM PST 24
Finished Feb 04 01:32:33 PM PST 24
Peak memory 196136 kb
Host smart-356955f2-17ee-4f69-9ce7-3beb230b7b1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115251334 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2115251334
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.294074465
Short name T497
Test name
Test status
Simulation time 2827493354 ps
CPU time 34.4 seconds
Started Feb 04 01:32:25 PM PST 24
Finished Feb 04 01:33:06 PM PST 24
Peak memory 199156 kb
Host smart-29a5d4bb-1693-4b7a-8fc8-d2f93f23cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294074465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.294074465
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1807597812
Short name T665
Test name
Test status
Simulation time 41757639 ps
CPU time 0.59 seconds
Started Feb 04 01:33:14 PM PST 24
Finished Feb 04 01:33:23 PM PST 24
Peak memory 193516 kb
Host smart-7655bc0c-5563-4f52-9a84-693106c4c010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807597812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1807597812
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1610419104
Short name T640
Test name
Test status
Simulation time 216613513 ps
CPU time 6.7 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:19 PM PST 24
Peak memory 199004 kb
Host smart-714935d8-b843-43ec-9e85-017b2ef7158a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610419104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1610419104
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3546881298
Short name T720
Test name
Test status
Simulation time 6382745772 ps
CPU time 29.88 seconds
Started Feb 04 01:33:08 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 199112 kb
Host smart-7a8d0979-3243-44dc-8933-ceafdbb039ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546881298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3546881298
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.522389665
Short name T13
Test name
Test status
Simulation time 7167689164 ps
CPU time 91.06 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:34:46 PM PST 24
Peak memory 199040 kb
Host smart-85459514-3af2-4430-89db-fbacb36f6367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522389665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.522389665
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2147041987
Short name T408
Test name
Test status
Simulation time 59901288844 ps
CPU time 199.88 seconds
Started Feb 04 01:33:13 PM PST 24
Finished Feb 04 01:36:40 PM PST 24
Peak memory 199092 kb
Host smart-7727d172-8104-4a3d-b637-891f9ccf20b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147041987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2147041987
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.327472049
Short name T771
Test name
Test status
Simulation time 2455641273 ps
CPU time 44.39 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:57 PM PST 24
Peak memory 199068 kb
Host smart-4ca1c4c9-93ad-465c-a246-3b4948899122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327472049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.327472049
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2607809154
Short name T537
Test name
Test status
Simulation time 554040431 ps
CPU time 2.21 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:15 PM PST 24
Peak memory 199040 kb
Host smart-e24a83a1-9c25-4c9b-aedf-bae0c6656056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607809154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2607809154
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1730793766
Short name T681
Test name
Test status
Simulation time 15878693572 ps
CPU time 276.3 seconds
Started Feb 04 01:33:15 PM PST 24
Finished Feb 04 01:37:59 PM PST 24
Peak memory 199108 kb
Host smart-88f447cb-86e2-4d21-873a-8ce16039fa98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730793766 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1730793766
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3610369407
Short name T861
Test name
Test status
Simulation time 96544714397 ps
CPU time 402.24 seconds
Started Feb 04 01:33:15 PM PST 24
Finished Feb 04 01:40:06 PM PST 24
Peak memory 215548 kb
Host smart-f75a100a-0fb9-46f4-8759-d41f0acb1c0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610369407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.3610369407
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3954455777
Short name T416
Test name
Test status
Simulation time 268073070 ps
CPU time 1.19 seconds
Started Feb 04 01:33:09 PM PST 24
Finished Feb 04 01:33:14 PM PST 24
Peak memory 198200 kb
Host smart-79fcd4b5-286a-4715-97e5-7e7c3d6e51a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954455777 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3954455777
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.997572223
Short name T622
Test name
Test status
Simulation time 27383070098 ps
CPU time 332.35 seconds
Started Feb 04 01:33:11 PM PST 24
Finished Feb 04 01:38:49 PM PST 24
Peak memory 199120 kb
Host smart-589bba2d-b694-48dd-9f03-d83b6be373a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997572223 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.hmac_test_sha_vectors.997572223
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4095329137
Short name T632
Test name
Test status
Simulation time 846126016 ps
CPU time 32.08 seconds
Started Feb 04 01:33:13 PM PST 24
Finished Feb 04 01:33:52 PM PST 24
Peak memory 199020 kb
Host smart-412298bf-1d7a-4197-adfd-450701843661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095329137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4095329137
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1012210543
Short name T723
Test name
Test status
Simulation time 39699117 ps
CPU time 0.58 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:33:36 PM PST 24
Peak memory 193428 kb
Host smart-2f65f941-d16e-413e-b071-da71fae08c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012210543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1012210543
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.912823618
Short name T812
Test name
Test status
Simulation time 3356568805 ps
CPU time 28.74 seconds
Started Feb 04 01:33:21 PM PST 24
Finished Feb 04 01:33:57 PM PST 24
Peak memory 225508 kb
Host smart-7cac3495-ff6e-4e8b-a228-24e974cc05e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912823618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.912823618
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3956191882
Short name T797
Test name
Test status
Simulation time 1424299409 ps
CPU time 18.42 seconds
Started Feb 04 01:33:27 PM PST 24
Finished Feb 04 01:33:55 PM PST 24
Peak memory 199052 kb
Host smart-15f66189-3b2e-4fce-9d12-9c337edc3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956191882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3956191882
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3302766622
Short name T705
Test name
Test status
Simulation time 2986920464 ps
CPU time 155.87 seconds
Started Feb 04 01:33:31 PM PST 24
Finished Feb 04 01:36:12 PM PST 24
Peak memory 199096 kb
Host smart-a2c24170-d0da-421e-bf2b-b77ed749cdd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302766622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3302766622
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3265092779
Short name T488
Test name
Test status
Simulation time 13229604952 ps
CPU time 103.19 seconds
Started Feb 04 01:33:17 PM PST 24
Finished Feb 04 01:35:07 PM PST 24
Peak memory 199000 kb
Host smart-a9e17f4a-0a57-4d44-97b3-d8ae5ba38b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265092779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3265092779
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4187352533
Short name T283
Test name
Test status
Simulation time 3794834292 ps
CPU time 48.93 seconds
Started Feb 04 01:33:19 PM PST 24
Finished Feb 04 01:34:14 PM PST 24
Peak memory 199092 kb
Host smart-fe9f7838-6cd7-4365-ba43-265bae5fe7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187352533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4187352533
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1173860871
Short name T742
Test name
Test status
Simulation time 332178474 ps
CPU time 1.8 seconds
Started Feb 04 01:33:12 PM PST 24
Finished Feb 04 01:33:22 PM PST 24
Peak memory 198824 kb
Host smart-4b4c31ce-731c-40e9-9741-1ee39b1dcc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173860871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1173860871
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3564643027
Short name T793
Test name
Test status
Simulation time 55356983213 ps
CPU time 912.99 seconds
Started Feb 04 01:33:29 PM PST 24
Finished Feb 04 01:48:50 PM PST 24
Peak memory 199152 kb
Host smart-3f7e9549-82e4-4462-bfba-912836791d5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564643027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3564643027
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.3199693107
Short name T449
Test name
Test status
Simulation time 15701549250 ps
CPU time 175.23 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:36:31 PM PST 24
Peak memory 199200 kb
Host smart-a5085e54-52e7-46a6-8b9a-854b6e7e1ee6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199693107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.3199693107
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2520416818
Short name T854
Test name
Test status
Simulation time 132814750 ps
CPU time 0.98 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:33:37 PM PST 24
Peak memory 196108 kb
Host smart-1d31dfd4-2e48-4a03-8bb5-2316aef862f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520416818 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2520416818
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3961392672
Short name T862
Test name
Test status
Simulation time 17801769870 ps
CPU time 362 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:39:38 PM PST 24
Peak memory 199120 kb
Host smart-dae44b7d-2d72-4513-90f7-a063fafc38ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961392672 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3961392672
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4094394786
Short name T406
Test name
Test status
Simulation time 5485272642 ps
CPU time 60.04 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:34:36 PM PST 24
Peak memory 199080 kb
Host smart-ace16564-41bc-475d-9357-b92aac37967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094394786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4094394786
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3054901489
Short name T691
Test name
Test status
Simulation time 38055674 ps
CPU time 0.58 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:33:37 PM PST 24
Peak memory 194456 kb
Host smart-6e420870-8d48-4b57-a088-4928ea1ff860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054901489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3054901489
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2160988518
Short name T753
Test name
Test status
Simulation time 1656816313 ps
CPU time 53.45 seconds
Started Feb 04 01:33:28 PM PST 24
Finished Feb 04 01:34:30 PM PST 24
Peak memory 222576 kb
Host smart-bd81532e-73ac-4e80-9464-29a5217dbe3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160988518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2160988518
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1486600329
Short name T423
Test name
Test status
Simulation time 242019039 ps
CPU time 4.14 seconds
Started Feb 04 01:33:29 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 198964 kb
Host smart-5c8c4cb7-0887-4360-b7aa-695b27dc5b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486600329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1486600329
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1653654189
Short name T689
Test name
Test status
Simulation time 4551336738 ps
CPU time 39.74 seconds
Started Feb 04 01:33:22 PM PST 24
Finished Feb 04 01:34:10 PM PST 24
Peak memory 199128 kb
Host smart-7f500015-0745-4866-a3b9-864f65e82f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653654189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1653654189
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3067321060
Short name T390
Test name
Test status
Simulation time 2791767013 ps
CPU time 69.46 seconds
Started Feb 04 01:33:24 PM PST 24
Finished Feb 04 01:34:41 PM PST 24
Peak memory 199044 kb
Host smart-65b428e6-322b-48b6-8562-406fab942b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067321060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3067321060
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3104763864
Short name T530
Test name
Test status
Simulation time 327965479 ps
CPU time 17.35 seconds
Started Feb 04 01:33:23 PM PST 24
Finished Feb 04 01:33:49 PM PST 24
Peak memory 199024 kb
Host smart-3908e957-5182-49d4-90c6-1d49f31fa97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104763864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3104763864
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1605233730
Short name T39
Test name
Test status
Simulation time 951031160 ps
CPU time 4.14 seconds
Started Feb 04 01:33:20 PM PST 24
Finished Feb 04 01:33:29 PM PST 24
Peak memory 198988 kb
Host smart-1bc4f221-1efb-4d0d-8e56-a6d82e6c68f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605233730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1605233730
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4085998225
Short name T334
Test name
Test status
Simulation time 8517031724 ps
CPU time 422.99 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:40:39 PM PST 24
Peak memory 199100 kb
Host smart-442e330c-90d9-4315-b1c2-b5cf0b618972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085998225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4085998225
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.302123580
Short name T325
Test name
Test status
Simulation time 307330509981 ps
CPU time 1384.43 seconds
Started Feb 04 01:33:24 PM PST 24
Finished Feb 04 01:56:37 PM PST 24
Peak memory 258572 kb
Host smart-ae89d28a-5fcd-4254-97ee-06ea8b57b5b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302123580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.302123580
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1626139187
Short name T708
Test name
Test status
Simulation time 95941946 ps
CPU time 0.96 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:33:37 PM PST 24
Peak memory 195992 kb
Host smart-f0df8ae4-b1d0-4e9d-a68b-1de23e08e4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626139187 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1626139187
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1391903982
Short name T614
Test name
Test status
Simulation time 83638959587 ps
CPU time 476.24 seconds
Started Feb 04 01:33:24 PM PST 24
Finished Feb 04 01:41:28 PM PST 24
Peak memory 199068 kb
Host smart-51fdd62a-23c3-4860-9e57-5f0a178e2e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391903982 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.1391903982
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2806306275
Short name T122
Test name
Test status
Simulation time 3073837936 ps
CPU time 31.95 seconds
Started Feb 04 01:33:19 PM PST 24
Finished Feb 04 01:33:57 PM PST 24
Peak memory 199144 kb
Host smart-dac455de-f5c1-4397-93f1-35db9b4ca63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806306275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2806306275
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.562411088
Short name T746
Test name
Test status
Simulation time 15073637 ps
CPU time 0.55 seconds
Started Feb 04 01:33:27 PM PST 24
Finished Feb 04 01:33:37 PM PST 24
Peak memory 193464 kb
Host smart-c6c68c13-82de-42e7-b1d6-2455dd73715a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562411088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.562411088
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2820044353
Short name T247
Test name
Test status
Simulation time 3920343360 ps
CPU time 28.4 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:34:05 PM PST 24
Peak memory 207276 kb
Host smart-cd6f9c71-d366-40a2-a836-17b470a432c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820044353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2820044353
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1053461432
Short name T356
Test name
Test status
Simulation time 1342286712 ps
CPU time 63.28 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:34:40 PM PST 24
Peak memory 199052 kb
Host smart-04b28bc7-0804-4f6c-b609-f3681e82d851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053461432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1053461432
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3872940212
Short name T674
Test name
Test status
Simulation time 3773757200 ps
CPU time 52.76 seconds
Started Feb 04 01:33:19 PM PST 24
Finished Feb 04 01:34:17 PM PST 24
Peak memory 199128 kb
Host smart-be183ead-b17b-4ba0-a13e-8bf040be01a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872940212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3872940212
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3943419902
Short name T583
Test name
Test status
Simulation time 39160296664 ps
CPU time 36.28 seconds
Started Feb 04 01:33:19 PM PST 24
Finished Feb 04 01:34:01 PM PST 24
Peak memory 199064 kb
Host smart-27bf3367-757a-43c6-9842-c3154154a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943419902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3943419902
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1926331788
Short name T616
Test name
Test status
Simulation time 14855495251 ps
CPU time 67.51 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:34:44 PM PST 24
Peak memory 199064 kb
Host smart-a72d3896-d9f1-403f-a0ea-caa4ec2978c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926331788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1926331788
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2141048229
Short name T379
Test name
Test status
Simulation time 341422604 ps
CPU time 1.55 seconds
Started Feb 04 01:33:17 PM PST 24
Finished Feb 04 01:33:26 PM PST 24
Peak memory 198660 kb
Host smart-3a999e64-e7ce-4bc2-8461-88bdee9ccc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141048229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2141048229
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.719420020
Short name T576
Test name
Test status
Simulation time 33958030353 ps
CPU time 280.37 seconds
Started Feb 04 01:33:18 PM PST 24
Finished Feb 04 01:38:05 PM PST 24
Peak memory 223724 kb
Host smart-261f2b5d-a7b6-44e0-8f31-5ffd5c3da61c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719420020 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.719420020
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.2269863192
Short name T791
Test name
Test status
Simulation time 209795023910 ps
CPU time 831.09 seconds
Started Feb 04 01:33:18 PM PST 24
Finished Feb 04 01:47:16 PM PST 24
Peak memory 244916 kb
Host smart-ddd2b717-27fe-46ff-8ae4-a28045547fba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269863192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.2269863192
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2203602113
Short name T778
Test name
Test status
Simulation time 110203184 ps
CPU time 1.13 seconds
Started Feb 04 01:33:27 PM PST 24
Finished Feb 04 01:33:37 PM PST 24
Peak memory 197500 kb
Host smart-20bf7c74-bbf2-41ed-a751-36d38678bd1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203602113 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2203602113
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2550194314
Short name T435
Test name
Test status
Simulation time 38221886951 ps
CPU time 423.16 seconds
Started Feb 04 01:33:21 PM PST 24
Finished Feb 04 01:40:32 PM PST 24
Peak memory 198992 kb
Host smart-5bec6701-1976-438c-a77a-605cefbee8e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550194314 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.2550194314
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3531876606
Short name T730
Test name
Test status
Simulation time 9666177212 ps
CPU time 25.18 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:34:01 PM PST 24
Peak memory 199088 kb
Host smart-0b58d5e8-08b9-4b9e-a948-0cbe9ca5655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531876606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3531876606
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3296240389
Short name T476
Test name
Test status
Simulation time 39019360 ps
CPU time 0.58 seconds
Started Feb 04 01:33:35 PM PST 24
Finished Feb 04 01:33:39 PM PST 24
Peak memory 193444 kb
Host smart-570fb611-a94e-4f54-9e78-0756a5c3fd88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296240389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3296240389
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3082463043
Short name T833
Test name
Test status
Simulation time 1728384670 ps
CPU time 57.01 seconds
Started Feb 04 01:33:29 PM PST 24
Finished Feb 04 01:34:33 PM PST 24
Peak memory 225052 kb
Host smart-9030d3ff-52c9-4623-8aff-28d66be42fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082463043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3082463043
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2177363562
Short name T850
Test name
Test status
Simulation time 2037639971 ps
CPU time 37.68 seconds
Started Feb 04 01:33:30 PM PST 24
Finished Feb 04 01:34:14 PM PST 24
Peak memory 199036 kb
Host smart-5ec3dba6-39df-44c9-b1e6-0fac12bcd2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177363562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2177363562
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.102899210
Short name T9
Test name
Test status
Simulation time 1224610546 ps
CPU time 59.49 seconds
Started Feb 04 01:33:24 PM PST 24
Finished Feb 04 01:34:31 PM PST 24
Peak memory 199060 kb
Host smart-cf57b5f5-6c1e-4b4d-84ad-8716bb81d028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102899210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.102899210
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1877919095
Short name T601
Test name
Test status
Simulation time 24399742556 ps
CPU time 72.8 seconds
Started Feb 04 01:33:23 PM PST 24
Finished Feb 04 01:34:44 PM PST 24
Peak memory 199084 kb
Host smart-0a0017a1-53c7-48f2-b0da-7c10b8aac33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877919095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1877919095
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.361092841
Short name T532
Test name
Test status
Simulation time 2081416797 ps
CPU time 26.87 seconds
Started Feb 04 01:33:29 PM PST 24
Finished Feb 04 01:34:03 PM PST 24
Peak memory 198816 kb
Host smart-945546ac-307c-45e9-a3d0-5e1b6e1cb061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361092841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.361092841
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2832281234
Short name T235
Test name
Test status
Simulation time 135410451 ps
CPU time 1.83 seconds
Started Feb 04 01:33:17 PM PST 24
Finished Feb 04 01:33:26 PM PST 24
Peak memory 198980 kb
Host smart-708fea53-ab41-4df4-bfef-1072e3f08300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832281234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2832281234
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.104290005
Short name T831
Test name
Test status
Simulation time 18351511737 ps
CPU time 344.28 seconds
Started Feb 04 01:33:27 PM PST 24
Finished Feb 04 01:39:21 PM PST 24
Peak memory 230964 kb
Host smart-73d40db7-9d4e-49c3-9903-30c0291fbb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104290005 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.104290005
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.3382260931
Short name T424
Test name
Test status
Simulation time 37886315669 ps
CPU time 813.83 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:47:14 PM PST 24
Peak memory 232036 kb
Host smart-b58f538a-8e53-4ca3-9ade-e97b3fe66e6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382260931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.3382260931
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1610850063
Short name T221
Test name
Test status
Simulation time 54407603 ps
CPU time 1.04 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:33:35 PM PST 24
Peak memory 197104 kb
Host smart-9f6e1d88-171c-48d0-b241-908fd36849ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610850063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1610850063
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2559922608
Short name T804
Test name
Test status
Simulation time 33671678091 ps
CPU time 401.72 seconds
Started Feb 04 01:33:25 PM PST 24
Finished Feb 04 01:40:18 PM PST 24
Peak memory 198960 kb
Host smart-c9777467-f086-46b0-a036-eab7d395db30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559922608 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2559922608
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1601687100
Short name T539
Test name
Test status
Simulation time 12102239653 ps
CPU time 75.21 seconds
Started Feb 04 01:33:26 PM PST 24
Finished Feb 04 01:34:51 PM PST 24
Peak memory 199108 kb
Host smart-fbca1038-5333-4463-83b4-bfb2cce2bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601687100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1601687100
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3198614176
Short name T521
Test name
Test status
Simulation time 21063489 ps
CPU time 0.53 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:33:39 PM PST 24
Peak memory 193468 kb
Host smart-98a23fc3-4656-4edf-a9c5-f9025370d708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198614176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3198614176
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.659958325
Short name T434
Test name
Test status
Simulation time 3875284056 ps
CPU time 18.34 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:33:57 PM PST 24
Peak memory 215124 kb
Host smart-423fe934-c5f2-4df9-a0bf-15fca041724f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659958325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.659958325
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4106970689
Short name T358
Test name
Test status
Simulation time 19053577880 ps
CPU time 42.69 seconds
Started Feb 04 01:33:38 PM PST 24
Finished Feb 04 01:34:23 PM PST 24
Peak memory 199104 kb
Host smart-e0581f81-ed12-4f3d-bfb2-f51b8be0232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106970689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4106970689
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3368889809
Short name T324
Test name
Test status
Simulation time 3215520833 ps
CPU time 146.41 seconds
Started Feb 04 01:33:32 PM PST 24
Finished Feb 04 01:36:05 PM PST 24
Peak memory 199060 kb
Host smart-280f39e8-1f18-4d61-b8c4-6ad55b804585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368889809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3368889809
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2400752406
Short name T554
Test name
Test status
Simulation time 13072050890 ps
CPU time 151.07 seconds
Started Feb 04 01:33:37 PM PST 24
Finished Feb 04 01:36:12 PM PST 24
Peak memory 199220 kb
Host smart-4f98a1cb-2aaa-4d30-b002-30209a770bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400752406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2400752406
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4104348232
Short name T275
Test name
Test status
Simulation time 4560442176 ps
CPU time 59.82 seconds
Started Feb 04 01:33:37 PM PST 24
Finished Feb 04 01:34:40 PM PST 24
Peak memory 198952 kb
Host smart-663cb5f4-a645-4009-8005-be06c9df2338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104348232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4104348232
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3291359737
Short name T393
Test name
Test status
Simulation time 791159321 ps
CPU time 2.5 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 198704 kb
Host smart-7ac3d999-f3e7-4937-a2a8-55435508fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291359737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3291359737
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3961043968
Short name T144
Test name
Test status
Simulation time 73674050874 ps
CPU time 1126.32 seconds
Started Feb 04 01:33:48 PM PST 24
Finished Feb 04 01:52:37 PM PST 24
Peak memory 230460 kb
Host smart-a932f2ca-9202-412f-945d-760e321a770e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961043968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3961043968
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.1610490689
Short name T798
Test name
Test status
Simulation time 991945082710 ps
CPU time 1127.23 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:52:27 PM PST 24
Peak memory 241096 kb
Host smart-9f4f154c-a60d-42fd-ad70-5fb369a8212b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610490689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.1610490689
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1373464810
Short name T291
Test name
Test status
Simulation time 72833254 ps
CPU time 1.15 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:33:40 PM PST 24
Peak memory 198076 kb
Host smart-72039c19-0cb9-45e9-b44d-f75545c22745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373464810 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1373464810
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2650299161
Short name T633
Test name
Test status
Simulation time 13710382653 ps
CPU time 335.88 seconds
Started Feb 04 01:33:38 PM PST 24
Finished Feb 04 01:39:17 PM PST 24
Peak memory 199008 kb
Host smart-66af36ef-1ce6-4e4e-bffe-8c82d04c29d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650299161 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.2650299161
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3552598093
Short name T839
Test name
Test status
Simulation time 26806329905 ps
CPU time 63.47 seconds
Started Feb 04 01:33:41 PM PST 24
Finished Feb 04 01:34:46 PM PST 24
Peak memory 198920 kb
Host smart-ba0f7939-1558-4578-9440-c6e1bd87057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552598093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3552598093
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2552836632
Short name T547
Test name
Test status
Simulation time 31203782 ps
CPU time 0.59 seconds
Started Feb 04 01:33:35 PM PST 24
Finished Feb 04 01:33:40 PM PST 24
Peak memory 193440 kb
Host smart-7dda1b7b-5f2e-4f85-9ae6-7a3a56f84a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552836632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2552836632
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3955541520
Short name T385
Test name
Test status
Simulation time 191742792 ps
CPU time 6.29 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:33:45 PM PST 24
Peak memory 198988 kb
Host smart-c6c71171-2099-478e-ad87-b7f8a5eeae10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955541520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3955541520
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.348049864
Short name T688
Test name
Test status
Simulation time 18075829792 ps
CPU time 31.54 seconds
Started Feb 04 01:33:34 PM PST 24
Finished Feb 04 01:34:10 PM PST 24
Peak memory 199012 kb
Host smart-82af6716-f0f4-4450-a23c-4d8d512c6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348049864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.348049864
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2689261833
Short name T646
Test name
Test status
Simulation time 19088424733 ps
CPU time 151.22 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:36:11 PM PST 24
Peak memory 198972 kb
Host smart-00fddbef-2188-42e9-80e6-ef645b251e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689261833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2689261833
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3415098143
Short name T339
Test name
Test status
Simulation time 100242028821 ps
CPU time 81.94 seconds
Started Feb 04 01:33:32 PM PST 24
Finished Feb 04 01:35:00 PM PST 24
Peak memory 199080 kb
Host smart-a3cfa4ee-fdeb-47b1-ac61-07b0f48018b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415098143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3415098143
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1749312641
Short name T425
Test name
Test status
Simulation time 2550849523 ps
CPU time 35.54 seconds
Started Feb 04 01:33:35 PM PST 24
Finished Feb 04 01:34:15 PM PST 24
Peak memory 199168 kb
Host smart-c8be367c-e20e-4e4b-af90-8ac6818fe6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749312641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1749312641
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2684299013
Short name T492
Test name
Test status
Simulation time 1257973316 ps
CPU time 4.22 seconds
Started Feb 04 01:33:38 PM PST 24
Finished Feb 04 01:33:45 PM PST 24
Peak memory 198656 kb
Host smart-7039b47a-b5ce-4872-b386-7e8ea4d27cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684299013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2684299013
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3456945479
Short name T684
Test name
Test status
Simulation time 99835716815 ps
CPU time 3903.17 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 02:38:43 PM PST 24
Peak memory 264064 kb
Host smart-2cf19d31-d327-45ff-bcfc-3f54fee0f6b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456945479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3456945479
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.895103617
Short name T372
Test name
Test status
Simulation time 48035595 ps
CPU time 0.95 seconds
Started Feb 04 01:33:40 PM PST 24
Finished Feb 04 01:33:43 PM PST 24
Peak memory 196640 kb
Host smart-07623cd6-7cbd-4f06-b86f-d42e0fcd378c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895103617 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.895103617
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.127081692
Short name T302
Test name
Test status
Simulation time 72793522775 ps
CPU time 466.13 seconds
Started Feb 04 01:33:38 PM PST 24
Finished Feb 04 01:41:27 PM PST 24
Peak memory 199128 kb
Host smart-35ed3552-d26c-46c4-97fc-ae5ccc04f75c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127081692 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_sha_vectors.127081692
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1279315045
Short name T216
Test name
Test status
Simulation time 747685435 ps
CPU time 14.49 seconds
Started Feb 04 01:33:48 PM PST 24
Finished Feb 04 01:34:06 PM PST 24
Peak memory 198896 kb
Host smart-ff4b0535-e024-47e3-bc26-89962e272be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279315045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1279315045
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1705839681
Short name T46
Test name
Test status
Simulation time 91846694 ps
CPU time 0.55 seconds
Started Feb 04 01:33:39 PM PST 24
Finished Feb 04 01:33:42 PM PST 24
Peak memory 193356 kb
Host smart-b27d320e-d688-4894-bb34-9879f3a5e418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705839681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1705839681
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3208505921
Short name T413
Test name
Test status
Simulation time 5958183976 ps
CPU time 38.27 seconds
Started Feb 04 01:33:33 PM PST 24
Finished Feb 04 01:34:17 PM PST 24
Peak memory 231824 kb
Host smart-903e63d7-d5fd-4a5a-9f05-c92fef26d0f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208505921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3208505921
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2847437875
Short name T743
Test name
Test status
Simulation time 2024930582 ps
CPU time 22.09 seconds
Started Feb 04 01:33:33 PM PST 24
Finished Feb 04 01:34:01 PM PST 24
Peak memory 199028 kb
Host smart-6099f1c9-f0fc-4759-a777-c8d102221b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847437875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2847437875
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.127127006
Short name T271
Test name
Test status
Simulation time 1329587512 ps
CPU time 69.52 seconds
Started Feb 04 01:33:48 PM PST 24
Finished Feb 04 01:35:01 PM PST 24
Peak memory 198956 kb
Host smart-96c75654-c3eb-4449-aa65-013adceb6cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127127006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.127127006
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2819204391
Short name T281
Test name
Test status
Simulation time 15433844 ps
CPU time 0.57 seconds
Started Feb 04 01:33:40 PM PST 24
Finished Feb 04 01:33:43 PM PST 24
Peak memory 193272 kb
Host smart-2bb33f56-b05b-40eb-bfc2-d998165dc49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819204391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2819204391
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.6119488
Short name T868
Test name
Test status
Simulation time 2957677343 ps
CPU time 70.99 seconds
Started Feb 04 01:33:33 PM PST 24
Finished Feb 04 01:34:49 PM PST 24
Peak memory 199124 kb
Host smart-438df66c-1009-4869-802d-8255287e7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6119488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.6119488
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3859032794
Short name T563
Test name
Test status
Simulation time 1487993263 ps
CPU time 4.17 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:33:44 PM PST 24
Peak memory 198880 kb
Host smart-16aa6e44-5d82-454d-85b1-031eb9fca3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859032794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3859032794
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2372085911
Short name T634
Test name
Test status
Simulation time 186405864291 ps
CPU time 521.47 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:42:21 PM PST 24
Peak memory 199168 kb
Host smart-b3375640-8784-4dcd-b00e-7c76de3dff7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372085911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2372085911
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.3116054631
Short name T464
Test name
Test status
Simulation time 125978167095 ps
CPU time 1114.46 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:52:14 PM PST 24
Peak memory 215596 kb
Host smart-a529a57f-4675-4b09-b848-a8510dbc8903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116054631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.3116054631
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1301648074
Short name T835
Test name
Test status
Simulation time 43315838 ps
CPU time 0.9 seconds
Started Feb 04 01:33:39 PM PST 24
Finished Feb 04 01:33:42 PM PST 24
Peak memory 196188 kb
Host smart-cb90add3-c57f-4ff2-aefb-590f0e96eff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301648074 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1301648074
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3705325773
Short name T647
Test name
Test status
Simulation time 15041520156 ps
CPU time 378.24 seconds
Started Feb 04 01:33:40 PM PST 24
Finished Feb 04 01:40:00 PM PST 24
Peak memory 199044 kb
Host smart-ba2d12e2-8f26-4c3c-99e0-e4b0c7768ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705325773 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.3705325773
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1629799401
Short name T35
Test name
Test status
Simulation time 1180831862 ps
CPU time 49.91 seconds
Started Feb 04 01:33:48 PM PST 24
Finished Feb 04 01:34:41 PM PST 24
Peak memory 199000 kb
Host smart-90c638a0-f553-40e8-a26d-bc5930da20d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629799401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1629799401
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.766945165
Short name T669
Test name
Test status
Simulation time 12261938 ps
CPU time 0.57 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 01:34:04 PM PST 24
Peak memory 193464 kb
Host smart-982ab5f8-96fe-43ab-b70f-bad95202f36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766945165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.766945165
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.278650173
Short name T865
Test name
Test status
Simulation time 4198605571 ps
CPU time 32.45 seconds
Started Feb 04 01:33:36 PM PST 24
Finished Feb 04 01:34:12 PM PST 24
Peak memory 207332 kb
Host smart-18e9ab44-ab0c-4476-ae28-dc6f0cacb349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278650173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.278650173
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3094788302
Short name T422
Test name
Test status
Simulation time 1991463850 ps
CPU time 44.87 seconds
Started Feb 04 01:33:35 PM PST 24
Finished Feb 04 01:34:24 PM PST 24
Peak memory 199080 kb
Host smart-a0dcced9-86e1-455f-9abe-5c9fe28fd391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094788302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3094788302
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1201966211
Short name T841
Test name
Test status
Simulation time 3638873261 ps
CPU time 90.74 seconds
Started Feb 04 01:33:37 PM PST 24
Finished Feb 04 01:35:11 PM PST 24
Peak memory 199124 kb
Host smart-ffe85d54-7f31-406b-84e8-f9b921f7d34f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201966211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1201966211
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1504532277
Short name T667
Test name
Test status
Simulation time 19850042067 ps
CPU time 228.39 seconds
Started Feb 04 01:33:40 PM PST 24
Finished Feb 04 01:37:31 PM PST 24
Peak memory 198996 kb
Host smart-fcad616e-eb2a-452b-ba41-285ef653041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504532277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1504532277
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.466772504
Short name T629
Test name
Test status
Simulation time 51894414 ps
CPU time 0.6 seconds
Started Feb 04 01:33:40 PM PST 24
Finished Feb 04 01:33:43 PM PST 24
Peak memory 193944 kb
Host smart-89c85a42-602c-4b89-b6d1-5baf0d9c413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466772504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.466772504
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3529956416
Short name T10
Test name
Test status
Simulation time 347375288 ps
CPU time 3.67 seconds
Started Feb 04 01:33:37 PM PST 24
Finished Feb 04 01:33:44 PM PST 24
Peak memory 198248 kb
Host smart-6cb9005f-3d32-47d2-9fc5-01613c88a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529956416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3529956416
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4029105994
Short name T623
Test name
Test status
Simulation time 45787261487 ps
CPU time 291.75 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 01:38:56 PM PST 24
Peak memory 237632 kb
Host smart-0c8fcef6-f1e0-47b7-9ae8-853409284bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029105994 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4029105994
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1323813887
Short name T121
Test name
Test status
Simulation time 537093983913 ps
CPU time 4641.17 seconds
Started Feb 04 01:34:00 PM PST 24
Finished Feb 04 02:51:23 PM PST 24
Peak memory 272840 kb
Host smart-80c382a3-9b87-412e-901c-a08b3a51cac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323813887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.1323813887
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1441003137
Short name T626
Test name
Test status
Simulation time 334354386 ps
CPU time 1.11 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:34:01 PM PST 24
Peak memory 197120 kb
Host smart-41f84a02-ec88-460e-a3b0-b19af62d008a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441003137 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1441003137
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1177698108
Short name T234
Test name
Test status
Simulation time 17684235234 ps
CPU time 434.58 seconds
Started Feb 04 01:34:01 PM PST 24
Finished Feb 04 01:41:18 PM PST 24
Peak memory 199112 kb
Host smart-d917bb57-4701-4f55-a2bd-83d4fd083bbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177698108 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1177698108
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.625284774
Short name T370
Test name
Test status
Simulation time 17198917647 ps
CPU time 77.5 seconds
Started Feb 04 01:33:37 PM PST 24
Finished Feb 04 01:34:58 PM PST 24
Peak memory 199132 kb
Host smart-3d4666e1-0a00-4841-b07a-05e0697a94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625284774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.625284774
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3720589762
Short name T627
Test name
Test status
Simulation time 47182788 ps
CPU time 0.57 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:34:00 PM PST 24
Peak memory 193456 kb
Host smart-e883304b-b683-4538-b164-3c3d16a8513a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720589762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3720589762
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1601423103
Short name T516
Test name
Test status
Simulation time 279206612 ps
CPU time 8.43 seconds
Started Feb 04 01:34:03 PM PST 24
Finished Feb 04 01:34:13 PM PST 24
Peak memory 199052 kb
Host smart-7e88ebe3-5f4b-42e4-8890-5ddaf84ca92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601423103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1601423103
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1502826809
Short name T732
Test name
Test status
Simulation time 774189612 ps
CPU time 33.84 seconds
Started Feb 04 01:33:58 PM PST 24
Finished Feb 04 01:34:34 PM PST 24
Peak memory 199052 kb
Host smart-47cad46e-3083-43c5-a8b5-adc4d7dccdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502826809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1502826809
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3975760766
Short name T840
Test name
Test status
Simulation time 2434636722 ps
CPU time 107.5 seconds
Started Feb 04 01:34:04 PM PST 24
Finished Feb 04 01:35:53 PM PST 24
Peak memory 199072 kb
Host smart-17ac6681-8c74-4e3f-a636-4f70046fbb66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975760766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3975760766
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.365321139
Short name T598
Test name
Test status
Simulation time 4756185531 ps
CPU time 72.18 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:35:12 PM PST 24
Peak memory 199044 kb
Host smart-c75593c9-35f3-4754-ad49-d310ca662111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365321139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.365321139
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3233887986
Short name T338
Test name
Test status
Simulation time 3258001051 ps
CPU time 13.1 seconds
Started Feb 04 01:34:01 PM PST 24
Finished Feb 04 01:34:16 PM PST 24
Peak memory 199072 kb
Host smart-d5f3e3c5-11e7-4381-aa66-f2602fb817c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233887986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3233887986
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.251869539
Short name T490
Test name
Test status
Simulation time 449267053 ps
CPU time 2.49 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 01:34:06 PM PST 24
Peak memory 199032 kb
Host smart-fe321863-4473-4c8c-b58f-f364612facde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251869539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.251869539
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1247002451
Short name T578
Test name
Test status
Simulation time 197173990095 ps
CPU time 1641.62 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 02:01:25 PM PST 24
Peak memory 199104 kb
Host smart-9d107986-2598-4b9c-be7a-3761ae73f6e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247002451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1247002451
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.2272110950
Short name T666
Test name
Test status
Simulation time 118130073365 ps
CPU time 573.87 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:43:34 PM PST 24
Peak memory 241464 kb
Host smart-3c49df74-d259-4128-93db-8f3ad796beba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272110950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.2272110950
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2752194296
Short name T309
Test name
Test status
Simulation time 119261494 ps
CPU time 1.13 seconds
Started Feb 04 01:34:00 PM PST 24
Finished Feb 04 01:34:03 PM PST 24
Peak memory 197316 kb
Host smart-bb595b83-2257-4c9b-8d00-9e7391d790dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752194296 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2752194296
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.233534557
Short name T452
Test name
Test status
Simulation time 25588150890 ps
CPU time 363.15 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 01:40:06 PM PST 24
Peak memory 199136 kb
Host smart-2590a0c9-9215-451a-84ac-2be9915fc574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233534557 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.hmac_test_sha_vectors.233534557
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1627608154
Short name T712
Test name
Test status
Simulation time 7404933393 ps
CPU time 63.24 seconds
Started Feb 04 01:34:04 PM PST 24
Finished Feb 04 01:35:08 PM PST 24
Peak memory 199116 kb
Host smart-89179546-b8cb-4225-b135-9ceee1908d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627608154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1627608154
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3771594831
Short name T496
Test name
Test status
Simulation time 13541712 ps
CPU time 0.56 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 193424 kb
Host smart-f1246742-ca92-4aa1-851f-b8e056ee715f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771594831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3771594831
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2473683714
Short name T605
Test name
Test status
Simulation time 702151937 ps
CPU time 22.16 seconds
Started Feb 04 01:32:17 PM PST 24
Finished Feb 04 01:32:42 PM PST 24
Peak memory 217412 kb
Host smart-cbc74131-318d-4e85-8675-8e36503db508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473683714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2473683714
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1345436197
Short name T805
Test name
Test status
Simulation time 3163798644 ps
CPU time 29.23 seconds
Started Feb 04 01:32:24 PM PST 24
Finished Feb 04 01:33:01 PM PST 24
Peak memory 199044 kb
Host smart-dd151d95-d68b-4a52-a858-e86ef1951544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345436197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1345436197
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1087273520
Short name T60
Test name
Test status
Simulation time 2301498911 ps
CPU time 59.25 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:33:35 PM PST 24
Peak memory 199060 kb
Host smart-f7d81712-1f09-4bb1-90cc-532786214516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087273520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1087273520
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1068901601
Short name T703
Test name
Test status
Simulation time 11975572505 ps
CPU time 34.63 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:33:11 PM PST 24
Peak memory 199044 kb
Host smart-7e6637c8-af6f-4f13-b917-5d7e2e52c265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068901601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1068901601
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.337305702
Short name T848
Test name
Test status
Simulation time 5028455690 ps
CPU time 83.11 seconds
Started Feb 04 01:32:24 PM PST 24
Finished Feb 04 01:33:55 PM PST 24
Peak memory 199060 kb
Host smart-c65848e1-ae86-4700-9f77-087ffbf01eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337305702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.337305702
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4163686157
Short name T54
Test name
Test status
Simulation time 67921647 ps
CPU time 0.86 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:30 PM PST 24
Peak memory 216116 kb
Host smart-11562c82-8c86-4512-94fe-703906caffa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163686157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4163686157
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3712944680
Short name T546
Test name
Test status
Simulation time 137867540 ps
CPU time 1.98 seconds
Started Feb 04 01:32:24 PM PST 24
Finished Feb 04 01:32:34 PM PST 24
Peak memory 197912 kb
Host smart-1efb94d2-abe1-4356-b40c-53a6ad2031ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712944680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3712944680
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3808121698
Short name T740
Test name
Test status
Simulation time 11304821986 ps
CPU time 540.45 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:41:22 PM PST 24
Peak memory 207308 kb
Host smart-01f9fa59-df2d-46ed-91b8-4b243b871291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808121698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3808121698
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2521030366
Short name T509
Test name
Test status
Simulation time 333957515680 ps
CPU time 1563.62 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:58:26 PM PST 24
Peak memory 226644 kb
Host smart-1a11d50b-c84c-466b-a618-60954664c2cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521030366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2521030366
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3884566583
Short name T463
Test name
Test status
Simulation time 109146497 ps
CPU time 1.11 seconds
Started Feb 04 01:32:17 PM PST 24
Finished Feb 04 01:32:20 PM PST 24
Peak memory 197236 kb
Host smart-8be89127-35d1-4d94-bc2f-7dcaf7a1dfb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884566583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3884566583
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1497986418
Short name T512
Test name
Test status
Simulation time 27616668153 ps
CPU time 425.66 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:39:42 PM PST 24
Peak memory 199092 kb
Host smart-5c2a2a41-4c5f-4d73-8ea1-77318e2233e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497986418 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1497986418
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.394931708
Short name T418
Test name
Test status
Simulation time 1091676124 ps
CPU time 44.15 seconds
Started Feb 04 01:32:25 PM PST 24
Finished Feb 04 01:33:16 PM PST 24
Peak memory 199056 kb
Host smart-21d450b2-1539-46aa-9611-19d4580c62ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394931708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.394931708
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2663774189
Short name T470
Test name
Test status
Simulation time 13787895 ps
CPU time 0.59 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 194484 kb
Host smart-aa1f42ad-18a3-4bb1-a04a-e823c5436332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663774189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2663774189
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1033952693
Short name T417
Test name
Test status
Simulation time 55389237 ps
CPU time 1.93 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:34:02 PM PST 24
Peak memory 199008 kb
Host smart-e3f1a725-2a30-4280-b716-5b34935c65b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033952693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1033952693
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3952252015
Short name T722
Test name
Test status
Simulation time 17830195255 ps
CPU time 14.19 seconds
Started Feb 04 01:34:01 PM PST 24
Finished Feb 04 01:34:17 PM PST 24
Peak memory 199052 kb
Host smart-36af6be1-ac37-4b6d-95e2-d10bad49862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952252015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3952252015
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.100120437
Short name T561
Test name
Test status
Simulation time 4769748269 ps
CPU time 124.67 seconds
Started Feb 04 01:34:01 PM PST 24
Finished Feb 04 01:36:07 PM PST 24
Peak memory 199128 kb
Host smart-5b184149-6957-45be-bc5e-8fe0b467f64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100120437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.100120437
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1512236042
Short name T298
Test name
Test status
Simulation time 32318261003 ps
CPU time 79.44 seconds
Started Feb 04 01:34:03 PM PST 24
Finished Feb 04 01:35:24 PM PST 24
Peak memory 199116 kb
Host smart-9e13485d-5d6e-49b8-84b5-42699d8ace35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512236042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1512236042
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2248031960
Short name T368
Test name
Test status
Simulation time 56954010129 ps
CPU time 97.52 seconds
Started Feb 04 01:34:03 PM PST 24
Finished Feb 04 01:35:42 PM PST 24
Peak memory 199080 kb
Host smart-76d54762-35ac-4ff0-82b1-730c9a460b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248031960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2248031960
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.4208780279
Short name T860
Test name
Test status
Simulation time 228611321 ps
CPU time 1.71 seconds
Started Feb 04 01:34:00 PM PST 24
Finished Feb 04 01:34:04 PM PST 24
Peak memory 198808 kb
Host smart-4513a9c4-a09b-466a-be42-7650fedf7214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208780279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.4208780279
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3132395298
Short name T855
Test name
Test status
Simulation time 55358745320 ps
CPU time 529.44 seconds
Started Feb 04 01:34:01 PM PST 24
Finished Feb 04 01:42:52 PM PST 24
Peak memory 223728 kb
Host smart-1929a379-236c-4705-a712-8f33a0dc8109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132395298 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3132395298
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.842582849
Short name T737
Test name
Test status
Simulation time 122905731362 ps
CPU time 1805.31 seconds
Started Feb 04 01:34:02 PM PST 24
Finished Feb 04 02:04:09 PM PST 24
Peak memory 262036 kb
Host smart-2e9f2eef-cd8c-4c54-ba83-ce2b9667f5f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842582849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.842582849
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4177804488
Short name T350
Test name
Test status
Simulation time 65955778 ps
CPU time 0.93 seconds
Started Feb 04 01:34:03 PM PST 24
Finished Feb 04 01:34:06 PM PST 24
Peak memory 195828 kb
Host smart-9ac8443b-00ac-448f-97cd-7270136d1840
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177804488 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4177804488
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2135941054
Short name T590
Test name
Test status
Simulation time 9013983212 ps
CPU time 466.82 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:41:47 PM PST 24
Peak memory 199144 kb
Host smart-44c09899-d711-475b-aaae-7fddf627f0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135941054 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.2135941054
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.800931792
Short name T776
Test name
Test status
Simulation time 19869646934 ps
CPU time 53.59 seconds
Started Feb 04 01:33:59 PM PST 24
Finished Feb 04 01:34:54 PM PST 24
Peak memory 199100 kb
Host smart-b451cae1-c9ff-4e67-9615-db39a1251fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800931792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.800931792
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3391488911
Short name T273
Test name
Test status
Simulation time 12553453 ps
CPU time 0.59 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:34:19 PM PST 24
Peak memory 193340 kb
Host smart-c0b6b576-64db-4cd7-9442-5f6905e85a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391488911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3391488911
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2770624802
Short name T455
Test name
Test status
Simulation time 2885717887 ps
CPU time 12.03 seconds
Started Feb 04 01:34:19 PM PST 24
Finished Feb 04 01:34:33 PM PST 24
Peak memory 199088 kb
Host smart-3adb4f85-5a20-4c34-8c04-663773894c18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770624802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2770624802
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2786101958
Short name T320
Test name
Test status
Simulation time 1465551656 ps
CPU time 20.69 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:40 PM PST 24
Peak memory 199028 kb
Host smart-0d5604a9-933c-4f16-8ece-16aae28130cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786101958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2786101958
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1969354166
Short name T218
Test name
Test status
Simulation time 2917167758 ps
CPU time 50.25 seconds
Started Feb 04 01:34:19 PM PST 24
Finished Feb 04 01:35:11 PM PST 24
Peak memory 198856 kb
Host smart-9f407b4b-2bee-44ec-ba37-50093da22e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969354166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1969354166
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1825877536
Short name T229
Test name
Test status
Simulation time 1000214594 ps
CPU time 49.96 seconds
Started Feb 04 01:34:19 PM PST 24
Finished Feb 04 01:35:11 PM PST 24
Peak memory 199032 kb
Host smart-d74ce435-9a8d-46ab-906b-3dd185d186fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825877536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1825877536
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3257639837
Short name T582
Test name
Test status
Simulation time 3760605256 ps
CPU time 45.02 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:35:03 PM PST 24
Peak memory 199024 kb
Host smart-720ffaa4-ccf3-4fd8-8c07-189685ad4386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257639837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3257639837
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2920064757
Short name T826
Test name
Test status
Simulation time 25429234 ps
CPU time 0.92 seconds
Started Feb 04 01:34:18 PM PST 24
Finished Feb 04 01:34:22 PM PST 24
Peak memory 195956 kb
Host smart-655e368c-3eac-414e-bada-aec3c5fdff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920064757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2920064757
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2865582423
Short name T384
Test name
Test status
Simulation time 587208763 ps
CPU time 8.57 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:28 PM PST 24
Peak memory 199124 kb
Host smart-034346f3-95f3-46af-ae5b-333a4aadfe55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865582423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2865582423
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2669891994
Short name T631
Test name
Test status
Simulation time 112906794 ps
CPU time 1.11 seconds
Started Feb 04 01:34:19 PM PST 24
Finished Feb 04 01:34:22 PM PST 24
Peak memory 197360 kb
Host smart-0ea7f767-0444-4340-9d34-68a9914e240d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669891994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2669891994
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4191098562
Short name T219
Test name
Test status
Simulation time 83776412636 ps
CPU time 433.25 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:41:33 PM PST 24
Peak memory 199092 kb
Host smart-f7dbf890-8f11-4d44-96e5-eb476a447c67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191098562 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.4191098562
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3681283968
Short name T451
Test name
Test status
Simulation time 1542285412 ps
CPU time 67.98 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:35:28 PM PST 24
Peak memory 198920 kb
Host smart-d38eb1b4-b517-49fe-b5d7-a2faeaf562d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681283968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3681283968
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3027555447
Short name T332
Test name
Test status
Simulation time 24402262 ps
CPU time 0.57 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 193540 kb
Host smart-cbe3a9ee-d735-4544-babc-107ef683d7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027555447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3027555447
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3021824250
Short name T466
Test name
Test status
Simulation time 2196010309 ps
CPU time 36.45 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:34:55 PM PST 24
Peak memory 199104 kb
Host smart-53689940-1a0d-4f47-a9c9-346c0da406c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021824250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3021824250
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3964559225
Short name T545
Test name
Test status
Simulation time 246530470 ps
CPU time 3.06 seconds
Started Feb 04 01:34:18 PM PST 24
Finished Feb 04 01:34:24 PM PST 24
Peak memory 199060 kb
Host smart-d32ab3bb-0ec7-4f97-8d95-2bb47e7b44a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964559225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3964559225
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3580982138
Short name T548
Test name
Test status
Simulation time 4561872817 ps
CPU time 62.62 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:35:22 PM PST 24
Peak memory 199164 kb
Host smart-c9a899c1-68c8-4261-a90e-23f1d2fb032d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580982138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3580982138
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1060804964
Short name T713
Test name
Test status
Simulation time 3031695412 ps
CPU time 155.69 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:36:56 PM PST 24
Peak memory 199100 kb
Host smart-3d1fa2c6-b34d-49fe-97e3-3fb89817e369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060804964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1060804964
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.346741065
Short name T467
Test name
Test status
Simulation time 55201537998 ps
CPU time 78.64 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:35:38 PM PST 24
Peak memory 199036 kb
Host smart-26648c5a-72b4-42f5-93e4-7dc1074be313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346741065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.346741065
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.991656156
Short name T553
Test name
Test status
Simulation time 594466617 ps
CPU time 3.83 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:34:22 PM PST 24
Peak memory 198844 kb
Host smart-f98caeaf-ad25-4ed0-92a4-f4a52af61afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991656156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.991656156
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.654443496
Short name T635
Test name
Test status
Simulation time 1349803063 ps
CPU time 35.25 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:34:54 PM PST 24
Peak memory 199104 kb
Host smart-44c521f8-545c-4014-9c73-0019b23b8d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654443496 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.654443496
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.1817731730
Short name T115
Test name
Test status
Simulation time 20332455682 ps
CPU time 251.25 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:38:30 PM PST 24
Peak memory 214660 kb
Host smart-50180eda-ed56-458b-9bdc-33b3ad011875
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817731730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.1817731730
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2577516422
Short name T64
Test name
Test status
Simulation time 57313853 ps
CPU time 1.18 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 197292 kb
Host smart-caaedb3e-bb74-48fa-a02f-0e39ef5f3627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577516422 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2577516422
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.311135419
Short name T560
Test name
Test status
Simulation time 41899639351 ps
CPU time 465.41 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:42:04 PM PST 24
Peak memory 199088 kb
Host smart-e5453313-fb75-441b-90f0-f3ee58075ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311135419 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_sha_vectors.311135419
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.903333901
Short name T701
Test name
Test status
Simulation time 1767596370 ps
CPU time 68.34 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:35:27 PM PST 24
Peak memory 199012 kb
Host smart-1def7627-aab7-451f-8b06-62a525ee3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903333901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.903333901
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.136877621
Short name T397
Test name
Test status
Simulation time 10387223 ps
CPU time 0.56 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 193352 kb
Host smart-96d80cef-dd38-40c4-b933-9567c67c9896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136877621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.136877621
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4013384303
Short name T363
Test name
Test status
Simulation time 1476536232 ps
CPU time 31.46 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:34:50 PM PST 24
Peak memory 231800 kb
Host smart-acec14cd-fec8-4a3f-9da0-e6665d3df2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013384303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4013384303
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2246401822
Short name T824
Test name
Test status
Simulation time 2698153572 ps
CPU time 13.58 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:34:32 PM PST 24
Peak memory 199080 kb
Host smart-ca2b7747-321e-4149-bc78-70f3458a2343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246401822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2246401822
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1642622502
Short name T568
Test name
Test status
Simulation time 716837401 ps
CPU time 8.91 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:34:29 PM PST 24
Peak memory 199016 kb
Host smart-fbc88e72-d3e9-44c2-a0c5-a465df2b8b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642622502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1642622502
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4042379534
Short name T274
Test name
Test status
Simulation time 5600320017 ps
CPU time 91.56 seconds
Started Feb 04 01:34:20 PM PST 24
Finished Feb 04 01:35:53 PM PST 24
Peak memory 199096 kb
Host smart-72722be8-389d-4636-8a18-4fe3b4f1cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042379534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4042379534
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.370262382
Short name T349
Test name
Test status
Simulation time 14556509791 ps
CPU time 11.51 seconds
Started Feb 04 01:34:14 PM PST 24
Finished Feb 04 01:34:30 PM PST 24
Peak memory 199080 kb
Host smart-7063c219-5fe2-4a0a-abe0-f5dfd230297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370262382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.370262382
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.300548384
Short name T823
Test name
Test status
Simulation time 783582874 ps
CPU time 2.97 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:22 PM PST 24
Peak memory 199028 kb
Host smart-93e15342-a4ba-40eb-a8a7-9ebc4e97ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300548384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.300548384
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.377966928
Short name T513
Test name
Test status
Simulation time 69043027788 ps
CPU time 296.23 seconds
Started Feb 04 01:34:15 PM PST 24
Finished Feb 04 01:39:15 PM PST 24
Peak memory 224584 kb
Host smart-aaaaf12e-ef66-4c97-9b07-5c02293c1e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377966928 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.377966928
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.2851489170
Short name T431
Test name
Test status
Simulation time 180929059365 ps
CPU time 1053.92 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:51:54 PM PST 24
Peak memory 215592 kb
Host smart-8a659217-1191-49aa-bb2a-588392238bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851489170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.2851489170
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1085383760
Short name T267
Test name
Test status
Simulation time 239104800 ps
CPU time 1.12 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 196988 kb
Host smart-5958e8da-27b7-4295-9ede-c87344e008b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085383760 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1085383760
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1999832752
Short name T402
Test name
Test status
Simulation time 34238232599 ps
CPU time 415.68 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:41:16 PM PST 24
Peak memory 199116 kb
Host smart-bf0889cb-7ea9-412c-b73c-16a44438b78a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999832752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.1999832752
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4025150743
Short name T816
Test name
Test status
Simulation time 1636835213 ps
CPU time 55.65 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:35:15 PM PST 24
Peak memory 199036 kb
Host smart-cf4f546a-aa3a-4998-99e8-792a51ccf459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025150743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4025150743
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2441761969
Short name T468
Test name
Test status
Simulation time 31985472 ps
CPU time 0.57 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:34:35 PM PST 24
Peak memory 193408 kb
Host smart-f46423d5-8aab-4408-907e-0b84a5f89c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441761969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2441761969
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3526006966
Short name T575
Test name
Test status
Simulation time 6711931081 ps
CPU time 47.08 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:35:21 PM PST 24
Peak memory 213500 kb
Host smart-be5be031-9b99-4354-bbec-e00aa3234db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526006966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3526006966
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1825878477
Short name T401
Test name
Test status
Simulation time 2335408079 ps
CPU time 11.4 seconds
Started Feb 04 01:34:29 PM PST 24
Finished Feb 04 01:34:41 PM PST 24
Peak memory 199072 kb
Host smart-c3f14e6a-4a78-40c7-a5be-dfe6f8198091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825878477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1825878477
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2291453284
Short name T387
Test name
Test status
Simulation time 4775667269 ps
CPU time 112.42 seconds
Started Feb 04 01:34:29 PM PST 24
Finished Feb 04 01:36:22 PM PST 24
Peak memory 199136 kb
Host smart-ac1c4f9d-5e46-4c9f-91c3-0b2376cb75a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291453284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2291453284
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2908387696
Short name T589
Test name
Test status
Simulation time 2183537221 ps
CPU time 104.86 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:36:18 PM PST 24
Peak memory 198964 kb
Host smart-899eed05-9d8d-40dc-8d59-d09fcbdaf22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908387696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2908387696
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2318606382
Short name T493
Test name
Test status
Simulation time 7304022989 ps
CPU time 79.88 seconds
Started Feb 04 01:34:16 PM PST 24
Finished Feb 04 01:35:40 PM PST 24
Peak memory 199108 kb
Host smart-7d735fd5-6597-49d3-ae44-264bad1590b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318606382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2318606382
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1592767662
Short name T314
Test name
Test status
Simulation time 389552975 ps
CPU time 4.39 seconds
Started Feb 04 01:34:17 PM PST 24
Finished Feb 04 01:34:24 PM PST 24
Peak memory 198896 kb
Host smart-61421f32-76c3-4d81-bda4-40e5a32890e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592767662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1592767662
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.443106527
Short name T436
Test name
Test status
Simulation time 95455090542 ps
CPU time 1217.52 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:54:49 PM PST 24
Peak memory 198964 kb
Host smart-0c32f94c-e51f-4f4e-967d-146b86215eac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443106527 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.443106527
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.4247349078
Short name T223
Test name
Test status
Simulation time 53655970 ps
CPU time 0.93 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 01:34:29 PM PST 24
Peak memory 196060 kb
Host smart-e9a68c68-a164-4886-8863-fbc1649cfd5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247349078 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.4247349078
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2013386138
Short name T866
Test name
Test status
Simulation time 161744158731 ps
CPU time 431.2 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 01:41:40 PM PST 24
Peak memory 199088 kb
Host smart-8d6d3027-6285-480d-9ebd-17039ee8db4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013386138 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.2013386138
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3098257013
Short name T552
Test name
Test status
Simulation time 2819416020 ps
CPU time 36.87 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:35:10 PM PST 24
Peak memory 199080 kb
Host smart-e3debe39-00e4-4ef8-bf9d-e48c3d9f89b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098257013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3098257013
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4010302275
Short name T536
Test name
Test status
Simulation time 41524941 ps
CPU time 0.55 seconds
Started Feb 04 01:34:29 PM PST 24
Finished Feb 04 01:34:30 PM PST 24
Peak memory 193468 kb
Host smart-d4154ead-25c6-47f9-925b-0b867ec02217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010302275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4010302275
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2669148610
Short name T491
Test name
Test status
Simulation time 1651555275 ps
CPU time 47.9 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:35:22 PM PST 24
Peak memory 231632 kb
Host smart-3d2269cd-9f6f-4d56-801e-c08dd19e8742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669148610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2669148610
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3154137630
Short name T296
Test name
Test status
Simulation time 1367787482 ps
CPU time 24.05 seconds
Started Feb 04 01:34:26 PM PST 24
Finished Feb 04 01:34:51 PM PST 24
Peak memory 198960 kb
Host smart-bfa37263-7793-49aa-910a-4bfe6c4717ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154137630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3154137630
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2745419065
Short name T579
Test name
Test status
Simulation time 4061886802 ps
CPU time 97.45 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 01:36:06 PM PST 24
Peak memory 199140 kb
Host smart-7bf02fb8-a568-498c-8cbe-8b1946554401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745419065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2745419065
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.295208119
Short name T257
Test name
Test status
Simulation time 4863558246 ps
CPU time 10.9 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:34:43 PM PST 24
Peak memory 199056 kb
Host smart-cf0dbe56-5990-441f-be45-c716791549f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295208119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.295208119
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.87149900
Short name T352
Test name
Test status
Simulation time 7339071930 ps
CPU time 79.36 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:35:52 PM PST 24
Peak memory 198956 kb
Host smart-2a039a9d-8a6a-4330-bbf2-211d16826c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87149900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.87149900
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2943443872
Short name T276
Test name
Test status
Simulation time 255174077 ps
CPU time 2.87 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:34:36 PM PST 24
Peak memory 199072 kb
Host smart-fb4f9781-a99a-470f-9b64-9f704c2791d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943443872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2943443872
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.2814085373
Short name T251
Test name
Test status
Simulation time 638788170236 ps
CPU time 783.16 seconds
Started Feb 04 01:34:35 PM PST 24
Finished Feb 04 01:47:40 PM PST 24
Peak memory 248156 kb
Host smart-7dda30d9-8ef9-434e-ae58-b9d65a2e6b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814085373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.2814085373
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.386108204
Short name T217
Test name
Test status
Simulation time 34766007 ps
CPU time 1.12 seconds
Started Feb 04 01:34:30 PM PST 24
Finished Feb 04 01:34:32 PM PST 24
Peak memory 196312 kb
Host smart-1e1e10e7-1569-486c-8bb9-4297cdece8cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386108204 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.386108204
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.34161282
Short name T6
Test name
Test status
Simulation time 33018980704 ps
CPU time 413.45 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:41:26 PM PST 24
Peak memory 198864 kb
Host smart-828d97d2-cd6b-4192-9f2d-c4f8a11e1c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34161282 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.hmac_test_sha_vectors.34161282
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1602416179
Short name T409
Test name
Test status
Simulation time 1965684412 ps
CPU time 24.56 seconds
Started Feb 04 01:34:27 PM PST 24
Finished Feb 04 01:34:53 PM PST 24
Peak memory 199112 kb
Host smart-887b63db-ec63-4f26-a002-fab16be50803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602416179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1602416179
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1858508927
Short name T501
Test name
Test status
Simulation time 47371982 ps
CPU time 0.56 seconds
Started Feb 04 01:34:29 PM PST 24
Finished Feb 04 01:34:31 PM PST 24
Peak memory 193428 kb
Host smart-5424dd94-9a42-4c75-9fd9-3fef6c660c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858508927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1858508927
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1119816242
Short name T645
Test name
Test status
Simulation time 1339311510 ps
CPU time 9.15 seconds
Started Feb 04 01:34:27 PM PST 24
Finished Feb 04 01:34:37 PM PST 24
Peak memory 215420 kb
Host smart-556d64cd-3b63-49c2-acfc-77abb8395780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119816242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1119816242
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3935314377
Short name T618
Test name
Test status
Simulation time 11021246451 ps
CPU time 40.41 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:35:13 PM PST 24
Peak memory 198956 kb
Host smart-a30e17b2-416c-4066-b37d-aa56c088a3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935314377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3935314377
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2281804712
Short name T806
Test name
Test status
Simulation time 656125019 ps
CPU time 31.13 seconds
Started Feb 04 01:34:26 PM PST 24
Finished Feb 04 01:34:59 PM PST 24
Peak memory 199016 kb
Host smart-3de17850-fc28-4f99-9cbb-d4cbff368896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281804712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2281804712
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1482412870
Short name T744
Test name
Test status
Simulation time 57279059818 ps
CPU time 182.91 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:37:37 PM PST 24
Peak memory 199076 kb
Host smart-1643360e-732e-4b32-9fa1-77f1f79f9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482412870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1482412870
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2253883591
Short name T595
Test name
Test status
Simulation time 10292578184 ps
CPU time 21.65 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:34:55 PM PST 24
Peak memory 199056 kb
Host smart-a49fcb32-20d3-46c8-a45a-ea2a86b986fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253883591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2253883591
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2913736914
Short name T231
Test name
Test status
Simulation time 564852828 ps
CPU time 3.72 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:34:37 PM PST 24
Peak memory 198992 kb
Host smart-4b615edf-5838-454f-aab3-ebb25fa96c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913736914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2913736914
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3366640838
Short name T446
Test name
Test status
Simulation time 39448064411 ps
CPU time 619.26 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:44:52 PM PST 24
Peak memory 199148 kb
Host smart-88013608-9474-4569-b50d-59158fe3ce22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366640838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3366640838
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.408335320
Short name T405
Test name
Test status
Simulation time 267492607762 ps
CPU time 2143.34 seconds
Started Feb 04 01:34:30 PM PST 24
Finished Feb 04 02:10:14 PM PST 24
Peak memory 248176 kb
Host smart-8700b8d7-e6e3-4d86-b421-cbced9d7ac3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408335320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.408335320
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3157300275
Short name T447
Test name
Test status
Simulation time 54548160 ps
CPU time 1.01 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:34:33 PM PST 24
Peak memory 196024 kb
Host smart-0d3ca115-dafd-48c7-a251-429887d1442c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157300275 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3157300275
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.870291661
Short name T458
Test name
Test status
Simulation time 30522336374 ps
CPU time 495.13 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:42:47 PM PST 24
Peak memory 199000 kb
Host smart-06f9e1a0-d6f8-4b9f-bdac-4c9e1141b6e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870291661 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.870291661
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2246789072
Short name T421
Test name
Test status
Simulation time 2261562789 ps
CPU time 27.1 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:35:01 PM PST 24
Peak memory 199120 kb
Host smart-115213b3-a602-4fdb-abaa-71d77399d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246789072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2246789072
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3471771
Short name T739
Test name
Test status
Simulation time 14857505 ps
CPU time 0.57 seconds
Started Feb 04 01:34:57 PM PST 24
Finished Feb 04 01:34:58 PM PST 24
Peak memory 193452 kb
Host smart-24cf9c7e-9ded-49b0-8159-e7550e0c0460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3471771
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1548488215
Short name T403
Test name
Test status
Simulation time 865692937 ps
CPU time 27.99 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:35:02 PM PST 24
Peak memory 231676 kb
Host smart-a4fdad36-4af6-4568-ba47-911a5411483b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548488215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1548488215
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4108691959
Short name T260
Test name
Test status
Simulation time 1491053834 ps
CPU time 19.55 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:34:52 PM PST 24
Peak memory 199020 kb
Host smart-1b42871d-3465-470e-b3ab-2f94e9b0ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108691959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4108691959
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2359165170
Short name T330
Test name
Test status
Simulation time 1456366287 ps
CPU time 76.08 seconds
Started Feb 04 01:34:32 PM PST 24
Finished Feb 04 01:35:49 PM PST 24
Peak memory 198984 kb
Host smart-ed4e7ab2-0aca-49fd-8ca1-ea49e78b86ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359165170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2359165170
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3725242944
Short name T683
Test name
Test status
Simulation time 33659317134 ps
CPU time 218.5 seconds
Started Feb 04 01:34:33 PM PST 24
Finished Feb 04 01:38:13 PM PST 24
Peak memory 199076 kb
Host smart-9dc2ea69-32c3-495a-9831-29f66c3237d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725242944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3725242944
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.767506520
Short name T637
Test name
Test status
Simulation time 498067357 ps
CPU time 2.82 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:34:35 PM PST 24
Peak memory 199036 kb
Host smart-682f85e0-cd57-4b29-9c11-5c7997edd959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767506520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.767506520
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.946000939
Short name T374
Test name
Test status
Simulation time 622638846 ps
CPU time 3.56 seconds
Started Feb 04 01:34:31 PM PST 24
Finished Feb 04 01:34:35 PM PST 24
Peak memory 199036 kb
Host smart-f02a27a7-9b7c-437d-8478-8d29740d14c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946000939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.946000939
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.56242467
Short name T146
Test name
Test status
Simulation time 400770808181 ps
CPU time 1185.39 seconds
Started Feb 04 01:34:51 PM PST 24
Finished Feb 04 01:54:41 PM PST 24
Peak memory 231852 kb
Host smart-6ba10048-1ad9-41ca-8ddb-934ba6220a95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56242467 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.56242467
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.258169259
Short name T135
Test name
Test status
Simulation time 38530337208 ps
CPU time 623.12 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:45:23 PM PST 24
Peak memory 214576 kb
Host smart-08df824e-1c96-4233-b120-8d2ee9673968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258169259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.258169259
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3082401156
Short name T319
Test name
Test status
Simulation time 198947250 ps
CPU time 1.04 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:35:00 PM PST 24
Peak memory 197188 kb
Host smart-76775903-b098-4285-a12c-35992aa58eee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082401156 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3082401156
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.950153612
Short name T250
Test name
Test status
Simulation time 68168258593 ps
CPU time 380.6 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 01:40:50 PM PST 24
Peak memory 199108 kb
Host smart-b232f764-74eb-47d1-9da5-9073775033df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950153612 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.hmac_test_sha_vectors.950153612
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2302052624
Short name T438
Test name
Test status
Simulation time 1576524412 ps
CPU time 18.9 seconds
Started Feb 04 01:34:28 PM PST 24
Finished Feb 04 01:34:48 PM PST 24
Peak memory 199092 kb
Host smart-00f30f58-9d57-47f5-8d65-1dfa780e8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302052624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2302052624
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2980861637
Short name T426
Test name
Test status
Simulation time 21885547 ps
CPU time 0.54 seconds
Started Feb 04 01:34:51 PM PST 24
Finished Feb 04 01:34:56 PM PST 24
Peak memory 193396 kb
Host smart-0cf90cd7-ec7e-4cca-b8ec-f33dc2032113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980861637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2980861637
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2925243955
Short name T261
Test name
Test status
Simulation time 581365475 ps
CPU time 18.33 seconds
Started Feb 04 01:35:03 PM PST 24
Finished Feb 04 01:35:24 PM PST 24
Peak memory 198984 kb
Host smart-41b72c7d-47a1-46d9-ac75-645de2ce131f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925243955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2925243955
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2993918341
Short name T766
Test name
Test status
Simulation time 4955865332 ps
CPU time 24.13 seconds
Started Feb 04 01:34:55 PM PST 24
Finished Feb 04 01:35:21 PM PST 24
Peak memory 199096 kb
Host smart-43d084d4-d8d1-4162-a83b-7de6b5b1643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993918341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2993918341
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4063687147
Short name T457
Test name
Test status
Simulation time 2543151414 ps
CPU time 62.91 seconds
Started Feb 04 01:34:56 PM PST 24
Finished Feb 04 01:36:00 PM PST 24
Peak memory 199112 kb
Host smart-c22fa70f-3cbf-42f7-8cb5-394cab818df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063687147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4063687147
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.271413784
Short name T699
Test name
Test status
Simulation time 15671148885 ps
CPU time 10.55 seconds
Started Feb 04 01:34:52 PM PST 24
Finished Feb 04 01:35:06 PM PST 24
Peak memory 199056 kb
Host smart-076651ba-b572-4add-a238-3d787618d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271413784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.271413784
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3659491577
Short name T707
Test name
Test status
Simulation time 24591917019 ps
CPU time 79.32 seconds
Started Feb 04 01:34:57 PM PST 24
Finished Feb 04 01:36:18 PM PST 24
Peak memory 199076 kb
Host smart-903d93d7-02a0-4f88-82ec-5cde4366b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659491577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3659491577
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1649607928
Short name T613
Test name
Test status
Simulation time 657458286 ps
CPU time 4.72 seconds
Started Feb 04 01:34:51 PM PST 24
Finished Feb 04 01:35:00 PM PST 24
Peak memory 198980 kb
Host smart-5dbccdf0-9ec8-4f6f-8e24-337cebc8eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649607928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1649607928
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1868561531
Short name T305
Test name
Test status
Simulation time 3101834790140 ps
CPU time 3332.69 seconds
Started Feb 04 01:34:52 PM PST 24
Finished Feb 04 02:30:29 PM PST 24
Peak memory 199096 kb
Host smart-f44b372f-7322-4d71-aff4-dee2c350f770
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868561531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1868561531
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.2517562513
Short name T360
Test name
Test status
Simulation time 67854589061 ps
CPU time 3430.66 seconds
Started Feb 04 01:34:56 PM PST 24
Finished Feb 04 02:32:08 PM PST 24
Peak memory 248268 kb
Host smart-f80dc786-0c82-4c9b-aeb1-c579d1134076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517562513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.2517562513
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.4183063008
Short name T11
Test name
Test status
Simulation time 43905481 ps
CPU time 0.96 seconds
Started Feb 04 01:34:54 PM PST 24
Finished Feb 04 01:34:57 PM PST 24
Peak memory 196840 kb
Host smart-ca9d63b3-a650-44c5-b383-ac2b2d0e6f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183063008 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.4183063008
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.651277689
Short name T769
Test name
Test status
Simulation time 158227330232 ps
CPU time 455.25 seconds
Started Feb 04 01:34:59 PM PST 24
Finished Feb 04 01:42:36 PM PST 24
Peak memory 198976 kb
Host smart-956dfb0e-793e-4311-a98b-b0ccda8b9b8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651277689 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_sha_vectors.651277689
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1655496936
Short name T672
Test name
Test status
Simulation time 16130119259 ps
CPU time 66.32 seconds
Started Feb 04 01:34:57 PM PST 24
Finished Feb 04 01:36:05 PM PST 24
Peak memory 199100 kb
Host smart-70a5da90-8c4a-47ca-a5e4-69bed70e434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655496936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1655496936
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.742131842
Short name T573
Test name
Test status
Simulation time 28534381 ps
CPU time 0.56 seconds
Started Feb 04 01:34:56 PM PST 24
Finished Feb 04 01:34:58 PM PST 24
Peak memory 193420 kb
Host smart-a6bf78b3-6c2e-4e18-a8f2-20b92fb27558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742131842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.742131842
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1030049372
Short name T628
Test name
Test status
Simulation time 1367368933 ps
CPU time 41.54 seconds
Started Feb 04 01:34:52 PM PST 24
Finished Feb 04 01:35:37 PM PST 24
Peak memory 227660 kb
Host smart-6c68bab4-3610-4b28-91f8-128b70c3a403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030049372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1030049372
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3659257705
Short name T293
Test name
Test status
Simulation time 5043072219 ps
CPU time 56.84 seconds
Started Feb 04 01:34:49 PM PST 24
Finished Feb 04 01:35:51 PM PST 24
Peak memory 199088 kb
Host smart-08dc74ec-4f3d-416a-950a-6842f6bdd211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659257705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3659257705
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.533485721
Short name T456
Test name
Test status
Simulation time 1263763313 ps
CPU time 16.35 seconds
Started Feb 04 01:34:57 PM PST 24
Finished Feb 04 01:35:14 PM PST 24
Peak memory 199048 kb
Host smart-9198d757-864a-4112-b2cc-9416809d37e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533485721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.533485721
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.107130087
Short name T518
Test name
Test status
Simulation time 2503920634 ps
CPU time 114.54 seconds
Started Feb 04 01:34:51 PM PST 24
Finished Feb 04 01:36:50 PM PST 24
Peak memory 199140 kb
Host smart-ec8016a0-5ed4-4c3a-93f1-4873b10afb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107130087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.107130087
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1134388868
Short name T761
Test name
Test status
Simulation time 31805221012 ps
CPU time 98.76 seconds
Started Feb 04 01:34:53 PM PST 24
Finished Feb 04 01:36:35 PM PST 24
Peak memory 199028 kb
Host smart-1802bb04-7654-4cc2-9e59-d8191b19d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134388868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1134388868
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3046717386
Short name T280
Test name
Test status
Simulation time 576856409 ps
CPU time 1.98 seconds
Started Feb 04 01:34:49 PM PST 24
Finished Feb 04 01:34:57 PM PST 24
Peak memory 198572 kb
Host smart-e540df67-dd71-4147-be5d-768317e6fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046717386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3046717386
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.378336090
Short name T107
Test name
Test status
Simulation time 10629730587 ps
CPU time 187.8 seconds
Started Feb 04 01:34:56 PM PST 24
Finished Feb 04 01:38:05 PM PST 24
Peak memory 199156 kb
Host smart-c883be46-fc0e-42d4-8828-39dd200b46a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378336090 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.378336090
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3766913218
Short name T676
Test name
Test status
Simulation time 596486906509 ps
CPU time 3906.86 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 02:40:06 PM PST 24
Peak memory 241504 kb
Host smart-a6484c5d-4f54-45a2-a8c1-4e9a5c7dd77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766913218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.3766913218
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1876555092
Short name T543
Test name
Test status
Simulation time 95071448 ps
CPU time 0.96 seconds
Started Feb 04 01:34:51 PM PST 24
Finished Feb 04 01:34:56 PM PST 24
Peak memory 196996 kb
Host smart-82fd1757-3073-4514-9f4a-61951743817b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876555092 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1876555092
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.970143455
Short name T329
Test name
Test status
Simulation time 136974622476 ps
CPU time 424.9 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:42:05 PM PST 24
Peak memory 199108 kb
Host smart-65602dbf-9a9a-4fc3-930c-5022337c4411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970143455 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_sha_vectors.970143455
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.389239753
Short name T677
Test name
Test status
Simulation time 12807614357 ps
CPU time 79.25 seconds
Started Feb 04 01:35:02 PM PST 24
Finished Feb 04 01:36:24 PM PST 24
Peak memory 199068 kb
Host smart-83f016c5-55f1-4e4b-9fd5-26b358c1f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389239753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.389239753
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1792167771
Short name T248
Test name
Test status
Simulation time 13800534 ps
CPU time 0.64 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:11 PM PST 24
Peak memory 193436 kb
Host smart-fd6e6e37-d72f-4c3f-909a-15014ea22919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792167771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1792167771
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.212451465
Short name T454
Test name
Test status
Simulation time 48601823 ps
CPU time 1.61 seconds
Started Feb 04 01:31:59 PM PST 24
Finished Feb 04 01:32:03 PM PST 24
Peak memory 199024 kb
Host smart-e4c055fd-6c53-4f95-89fa-d004fa846822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212451465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.212451465
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3435833687
Short name T562
Test name
Test status
Simulation time 24684036863 ps
CPU time 23.41 seconds
Started Feb 04 01:31:53 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 199120 kb
Host smart-61f6d5e3-8186-4ff8-b6dc-763999ce2bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435833687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3435833687
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3574790473
Short name T851
Test name
Test status
Simulation time 1940464459 ps
CPU time 93.63 seconds
Started Feb 04 01:31:54 PM PST 24
Finished Feb 04 01:33:33 PM PST 24
Peak memory 199032 kb
Host smart-c5e7da98-700d-4ca8-ab24-c7cd02cf49f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574790473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3574790473
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1325231996
Short name T836
Test name
Test status
Simulation time 11905323020 ps
CPU time 137.33 seconds
Started Feb 04 01:31:53 PM PST 24
Finished Feb 04 01:34:17 PM PST 24
Peak memory 199136 kb
Host smart-37869498-4646-45be-8836-0480e2541327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325231996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1325231996
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2634043624
Short name T381
Test name
Test status
Simulation time 6043427181 ps
CPU time 78.07 seconds
Started Feb 04 01:31:57 PM PST 24
Finished Feb 04 01:33:18 PM PST 24
Peak memory 199112 kb
Host smart-91a70f28-3199-46b7-a851-eb53e56637ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634043624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2634043624
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2961125704
Short name T52
Test name
Test status
Simulation time 812894752 ps
CPU time 0.84 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:10 PM PST 24
Peak memory 216080 kb
Host smart-f9c86fc9-70dc-4f58-b33b-d1602a118ef6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961125704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2961125704
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.272241617
Short name T323
Test name
Test status
Simulation time 251981480 ps
CPU time 3.18 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 01:32:25 PM PST 24
Peak memory 199040 kb
Host smart-ba81da44-1c2e-4925-ae5d-b75c78374018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272241617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.272241617
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3992438633
Short name T754
Test name
Test status
Simulation time 525345022126 ps
CPU time 1483.93 seconds
Started Feb 04 01:31:57 PM PST 24
Finished Feb 04 01:56:44 PM PST 24
Peak memory 199116 kb
Host smart-7ee2ed2c-cf14-40c4-bfe6-ea78ff4f02e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992438633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3992438633
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.415497721
Short name T767
Test name
Test status
Simulation time 83196745179 ps
CPU time 2323.1 seconds
Started Feb 04 01:32:10 PM PST 24
Finished Feb 04 02:10:55 PM PST 24
Peak memory 238548 kb
Host smart-0df2e781-2c8f-4fb9-b723-77c60bb9afc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415497721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.415497721
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2771747354
Short name T3
Test name
Test status
Simulation time 146937826 ps
CPU time 0.96 seconds
Started Feb 04 01:32:05 PM PST 24
Finished Feb 04 01:32:08 PM PST 24
Peak memory 196632 kb
Host smart-97ba6264-fd39-46f2-a33e-6e46404f22fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771747354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2771747354
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2083309119
Short name T749
Test name
Test status
Simulation time 29097010481 ps
CPU time 379.45 seconds
Started Feb 04 01:32:03 PM PST 24
Finished Feb 04 01:38:24 PM PST 24
Peak memory 199112 kb
Host smart-c5337ed9-8e64-4f2a-a704-79b1e556250f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083309119 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.2083309119
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1933590540
Short name T477
Test name
Test status
Simulation time 705200768 ps
CPU time 12.1 seconds
Started Feb 04 01:31:57 PM PST 24
Finished Feb 04 01:32:12 PM PST 24
Peak memory 198940 kb
Host smart-a178cf4b-28d6-4d69-b7d8-cbca5c2cc984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933590540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1933590540
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.920680023
Short name T236
Test name
Test status
Simulation time 17381564 ps
CPU time 0.54 seconds
Started Feb 04 01:35:00 PM PST 24
Finished Feb 04 01:35:02 PM PST 24
Peak memory 193464 kb
Host smart-9bed14aa-be6e-4438-abd0-9fdb81ee3552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920680023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.920680023
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1493425857
Short name T858
Test name
Test status
Simulation time 5954658786 ps
CPU time 42.79 seconds
Started Feb 04 01:34:59 PM PST 24
Finished Feb 04 01:35:43 PM PST 24
Peak memory 207288 kb
Host smart-deaa22c7-d92e-4358-88db-74e18a4895fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493425857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1493425857
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1763674315
Short name T572
Test name
Test status
Simulation time 1959864422 ps
CPU time 36.27 seconds
Started Feb 04 01:34:53 PM PST 24
Finished Feb 04 01:35:32 PM PST 24
Peak memory 198988 kb
Host smart-9053ce3a-758d-4d18-8137-5bf10d2ccc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763674315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1763674315
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2939072535
Short name T375
Test name
Test status
Simulation time 1676525757 ps
CPU time 85.87 seconds
Started Feb 04 01:34:54 PM PST 24
Finished Feb 04 01:36:22 PM PST 24
Peak memory 199048 kb
Host smart-ba7c90e4-b921-42c2-8dfd-5a72facf6bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939072535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2939072535
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.22122125
Short name T461
Test name
Test status
Simulation time 2331662750 ps
CPU time 37.05 seconds
Started Feb 04 01:35:01 PM PST 24
Finished Feb 04 01:35:42 PM PST 24
Peak memory 199104 kb
Host smart-881119ac-30fb-46d0-b533-a12f8acaee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22122125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.22122125
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1259791892
Short name T638
Test name
Test status
Simulation time 5808852158 ps
CPU time 79.63 seconds
Started Feb 04 01:34:49 PM PST 24
Finished Feb 04 01:36:14 PM PST 24
Peak memory 199260 kb
Host smart-015be5f5-c123-4072-aff9-f3ebb5b4366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259791892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1259791892
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1917183358
Short name T577
Test name
Test status
Simulation time 173548915 ps
CPU time 3.83 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:35:03 PM PST 24
Peak memory 198836 kb
Host smart-bab4fca2-c09b-40d2-9fa4-f34889bf1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917183358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1917183358
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1068353297
Short name T687
Test name
Test status
Simulation time 27977883759 ps
CPU time 1380.97 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:58:00 PM PST 24
Peak memory 239560 kb
Host smart-aa7527c9-aadd-4bb0-ad77-bcf5607de0de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068353297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1068353297
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.1090651189
Short name T494
Test name
Test status
Simulation time 41610866335 ps
CPU time 1449.96 seconds
Started Feb 04 01:34:53 PM PST 24
Finished Feb 04 01:59:06 PM PST 24
Peak memory 232784 kb
Host smart-8e7b3052-88be-4dfd-ab4c-11d7e47dfe1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090651189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.1090651189
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3894574303
Short name T500
Test name
Test status
Simulation time 106946567 ps
CPU time 1.22 seconds
Started Feb 04 01:34:55 PM PST 24
Finished Feb 04 01:34:58 PM PST 24
Peak memory 197304 kb
Host smart-6fe14402-7c4c-457c-9140-801746ff520c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894574303 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3894574303
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.4178542927
Short name T644
Test name
Test status
Simulation time 68697131639 ps
CPU time 443.19 seconds
Started Feb 04 01:34:50 PM PST 24
Finished Feb 04 01:42:18 PM PST 24
Peak memory 199164 kb
Host smart-3cad7b33-67dc-4506-b6e1-1aed75f521b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178542927 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.4178542927
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4292985335
Short name T642
Test name
Test status
Simulation time 1565368041 ps
CPU time 21.61 seconds
Started Feb 04 01:34:56 PM PST 24
Finished Feb 04 01:35:18 PM PST 24
Peak memory 199108 kb
Host smart-674f504d-da46-4b99-8dca-5237f8eb411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292985335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4292985335
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3510951069
Short name T306
Test name
Test status
Simulation time 12445961 ps
CPU time 0.58 seconds
Started Feb 04 01:35:04 PM PST 24
Finished Feb 04 01:35:07 PM PST 24
Peak memory 193488 kb
Host smart-13f1a0e4-b288-4665-906c-da9506546e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510951069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3510951069
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1591096853
Short name T301
Test name
Test status
Simulation time 838599316 ps
CPU time 36.6 seconds
Started Feb 04 01:34:48 PM PST 24
Finished Feb 04 01:35:29 PM PST 24
Peak memory 231804 kb
Host smart-90fa20bb-3859-496c-990a-41fa984aa24e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591096853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1591096853
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2263524011
Short name T48
Test name
Test status
Simulation time 7693695025 ps
CPU time 28.51 seconds
Started Feb 04 01:35:01 PM PST 24
Finished Feb 04 01:35:33 PM PST 24
Peak memory 199084 kb
Host smart-ad3c5ea6-0b0d-4486-8549-9a5e89d54c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263524011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2263524011
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.691932121
Short name T58
Test name
Test status
Simulation time 1483695082 ps
CPU time 78.52 seconds
Started Feb 04 01:34:53 PM PST 24
Finished Feb 04 01:36:14 PM PST 24
Peak memory 199036 kb
Host smart-ee599f9b-3de1-47c8-b41b-32eda959e3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691932121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.691932121
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1950182647
Short name T838
Test name
Test status
Simulation time 1772611534 ps
CPU time 93.24 seconds
Started Feb 04 01:34:57 PM PST 24
Finished Feb 04 01:36:31 PM PST 24
Peak memory 198996 kb
Host smart-643d0762-7aa8-435f-be62-be94bb46faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950182647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1950182647
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2488310979
Short name T679
Test name
Test status
Simulation time 9200612185 ps
CPU time 78.84 seconds
Started Feb 04 01:34:55 PM PST 24
Finished Feb 04 01:36:15 PM PST 24
Peak memory 199096 kb
Host smart-50154d1a-824e-4882-9cfa-9c42b470d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488310979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2488310979
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2773153303
Short name T345
Test name
Test status
Simulation time 134582670 ps
CPU time 2.13 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 01:35:02 PM PST 24
Peak memory 199076 kb
Host smart-529e03d1-876c-441f-98ea-ac851891b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773153303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2773153303
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1960273189
Short name T131
Test name
Test status
Simulation time 742080276952 ps
CPU time 2005.75 seconds
Started Feb 04 01:34:58 PM PST 24
Finished Feb 04 02:08:25 PM PST 24
Peak memory 233944 kb
Host smart-d1b22883-d711-4fc5-9eaa-d8d34cab848c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960273189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1960273189
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.951012063
Short name T266
Test name
Test status
Simulation time 111777269620 ps
CPU time 779.17 seconds
Started Feb 04 01:35:00 PM PST 24
Finished Feb 04 01:48:02 PM PST 24
Peak memory 230900 kb
Host smart-0578015f-4d6f-4b69-8008-f3d9371f10cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951012063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.951012063
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.410752624
Short name T367
Test name
Test status
Simulation time 38417458 ps
CPU time 0.92 seconds
Started Feb 04 01:35:00 PM PST 24
Finished Feb 04 01:35:03 PM PST 24
Peak memory 196724 kb
Host smart-42ced03f-06a5-45a0-89c9-60eb8aea348c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410752624 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.410752624
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1727351755
Short name T863
Test name
Test status
Simulation time 15221778130 ps
CPU time 382.48 seconds
Started Feb 04 01:35:00 PM PST 24
Finished Feb 04 01:41:24 PM PST 24
Peak memory 199156 kb
Host smart-d9ef8c18-97d9-463c-9334-153ddcda3b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727351755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1727351755
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2275561858
Short name T757
Test name
Test status
Simulation time 1491162977 ps
CPU time 51.19 seconds
Started Feb 04 01:35:00 PM PST 24
Finished Feb 04 01:35:53 PM PST 24
Peak memory 199076 kb
Host smart-d4a47735-a78a-4bf0-9516-724c2620c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275561858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2275561858
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3879046602
Short name T700
Test name
Test status
Simulation time 48378357 ps
CPU time 0.54 seconds
Started Feb 04 01:35:20 PM PST 24
Finished Feb 04 01:35:28 PM PST 24
Peak memory 193420 kb
Host smart-026b7a5b-b872-401c-95ce-74b504e1b4a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879046602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3879046602
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.214434360
Short name T428
Test name
Test status
Simulation time 716651426 ps
CPU time 20.88 seconds
Started Feb 04 01:35:09 PM PST 24
Finished Feb 04 01:35:34 PM PST 24
Peak memory 207280 kb
Host smart-0d32de99-4c99-4f1d-aab3-d71710558265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214434360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.214434360
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.460177070
Short name T801
Test name
Test status
Simulation time 1201802484 ps
CPU time 17.06 seconds
Started Feb 04 01:35:08 PM PST 24
Finished Feb 04 01:35:29 PM PST 24
Peak memory 199080 kb
Host smart-f516f89e-6f68-4931-822b-b934e376f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460177070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.460177070
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2307151666
Short name T671
Test name
Test status
Simulation time 9871469422 ps
CPU time 28.26 seconds
Started Feb 04 01:35:03 PM PST 24
Finished Feb 04 01:35:34 PM PST 24
Peak memory 199060 kb
Host smart-616003fe-5eda-45b2-967f-a33eb6e7afde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307151666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2307151666
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2469108330
Short name T630
Test name
Test status
Simulation time 14807166808 ps
CPU time 94.65 seconds
Started Feb 04 01:35:10 PM PST 24
Finished Feb 04 01:36:49 PM PST 24
Peak memory 198972 kb
Host smart-455c36cd-6e3c-42b5-a3cd-fc428f3838f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469108330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2469108330
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2899805487
Short name T648
Test name
Test status
Simulation time 33248220912 ps
CPU time 104.48 seconds
Started Feb 04 01:35:11 PM PST 24
Finished Feb 04 01:37:00 PM PST 24
Peak memory 199088 kb
Host smart-337f2d6f-2e1f-4523-86d0-4a8a6640e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899805487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2899805487
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1023910367
Short name T636
Test name
Test status
Simulation time 756770588 ps
CPU time 4.3 seconds
Started Feb 04 01:35:10 PM PST 24
Finished Feb 04 01:35:19 PM PST 24
Peak memory 199060 kb
Host smart-9b9bb585-eadf-4cdf-b428-98693383db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023910367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1023910367
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3863206513
Short name T825
Test name
Test status
Simulation time 19818126767 ps
CPU time 1006.22 seconds
Started Feb 04 01:35:08 PM PST 24
Finished Feb 04 01:51:58 PM PST 24
Peak memory 229556 kb
Host smart-9690c650-2706-474d-9363-2c7dc974b878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863206513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3863206513
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.122869327
Short name T41
Test name
Test status
Simulation time 436398045820 ps
CPU time 1987.85 seconds
Started Feb 04 01:35:12 PM PST 24
Finished Feb 04 02:08:24 PM PST 24
Peak memory 247284 kb
Host smart-da05f30e-2425-43de-a2e3-abe9bdede44a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122869327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.122869327
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3153869383
Short name T310
Test name
Test status
Simulation time 95641826 ps
CPU time 0.96 seconds
Started Feb 04 01:35:09 PM PST 24
Finished Feb 04 01:35:13 PM PST 24
Peak memory 196180 kb
Host smart-03c14539-ed04-4bd1-9bd2-a6ca9972f0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153869383 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3153869383
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3463412437
Short name T279
Test name
Test status
Simulation time 30970741504 ps
CPU time 371.5 seconds
Started Feb 04 01:35:02 PM PST 24
Finished Feb 04 01:41:17 PM PST 24
Peak memory 199072 kb
Host smart-b89ada93-155b-4965-8b5b-408807f0af48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463412437 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.3463412437
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3080768119
Short name T526
Test name
Test status
Simulation time 679934602 ps
CPU time 7.14 seconds
Started Feb 04 01:35:10 PM PST 24
Finished Feb 04 01:35:22 PM PST 24
Peak memory 199052 kb
Host smart-8a0034f6-6d39-4689-a434-3be30164fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080768119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3080768119
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2350260032
Short name T50
Test name
Test status
Simulation time 39847442 ps
CPU time 0.57 seconds
Started Feb 04 01:35:21 PM PST 24
Finished Feb 04 01:35:28 PM PST 24
Peak memory 193428 kb
Host smart-7594a5c4-16de-4452-ae9c-a829bd02de9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350260032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2350260032
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1582724530
Short name T639
Test name
Test status
Simulation time 12097957372 ps
CPU time 40.73 seconds
Started Feb 04 01:35:25 PM PST 24
Finished Feb 04 01:36:15 PM PST 24
Peak memory 230884 kb
Host smart-fbb224e4-457f-43e6-936d-258b33d72ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582724530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1582724530
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2840713741
Short name T760
Test name
Test status
Simulation time 18026423111 ps
CPU time 26.35 seconds
Started Feb 04 01:35:20 PM PST 24
Finished Feb 04 01:35:54 PM PST 24
Peak memory 198988 kb
Host smart-8b7186b5-60ea-4db4-828e-a47ea76d1587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840713741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2840713741
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1208783156
Short name T255
Test name
Test status
Simulation time 683081944 ps
CPU time 35.13 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:36:03 PM PST 24
Peak memory 199048 kb
Host smart-c4b1f2f3-a7da-4131-891c-f3defe7da6f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208783156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1208783156
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1749959083
Short name T357
Test name
Test status
Simulation time 16048055325 ps
CPU time 183.04 seconds
Started Feb 04 01:35:20 PM PST 24
Finished Feb 04 01:38:30 PM PST 24
Peak memory 199076 kb
Host smart-a4699083-689a-4c08-a7f6-7f75736fb061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749959083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1749959083
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2813790508
Short name T365
Test name
Test status
Simulation time 1196788755 ps
CPU time 58.67 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:36:35 PM PST 24
Peak memory 199060 kb
Host smart-e4dc1291-44cf-44e6-887a-7d548cd7054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813790508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2813790508
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2208590518
Short name T380
Test name
Test status
Simulation time 635650909 ps
CPU time 4.41 seconds
Started Feb 04 01:35:21 PM PST 24
Finished Feb 04 01:35:33 PM PST 24
Peak memory 199012 kb
Host smart-a8f4fae4-6fb0-4272-8fed-7b761138d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208590518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2208590518
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1288581457
Short name T727
Test name
Test status
Simulation time 297599175298 ps
CPU time 609.75 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:45:47 PM PST 24
Peak memory 222856 kb
Host smart-f5015117-6cb1-4939-a01f-e1145a08a48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288581457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1288581457
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.1401764564
Short name T664
Test name
Test status
Simulation time 567336923014 ps
CPU time 545.48 seconds
Started Feb 04 01:35:23 PM PST 24
Finished Feb 04 01:44:35 PM PST 24
Peak memory 208044 kb
Host smart-7dcfd3e7-0414-47a5-99ed-023a16f6377b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401764564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.1401764564
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.626662029
Short name T442
Test name
Test status
Simulation time 29768422 ps
CPU time 0.9 seconds
Started Feb 04 01:35:24 PM PST 24
Finished Feb 04 01:35:32 PM PST 24
Peak memory 196088 kb
Host smart-242d674a-3fb0-45ba-a032-cd35964e78de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626662029 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.626662029
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3522647567
Short name T736
Test name
Test status
Simulation time 8183353477 ps
CPU time 391.47 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:41:59 PM PST 24
Peak memory 199080 kb
Host smart-3f4bbfe1-780a-4742-a56c-2b4de30536d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522647567 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.3522647567
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1618033450
Short name T588
Test name
Test status
Simulation time 820551838 ps
CPU time 43.1 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:36:19 PM PST 24
Peak memory 199116 kb
Host smart-59d29298-b219-4744-8694-58c329e59b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618033450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1618033450
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1359286392
Short name T294
Test name
Test status
Simulation time 10820005 ps
CPU time 0.56 seconds
Started Feb 04 01:35:23 PM PST 24
Finished Feb 04 01:35:29 PM PST 24
Peak memory 193456 kb
Host smart-bd8ec11d-17a5-47d7-9832-f7d5c2ac2664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359286392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1359286392
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.334583536
Short name T244
Test name
Test status
Simulation time 437655577 ps
CPU time 14.23 seconds
Started Feb 04 01:35:25 PM PST 24
Finished Feb 04 01:35:46 PM PST 24
Peak memory 207240 kb
Host smart-404fb011-bfce-487a-90bc-e2fd3024334a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334583536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.334583536
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.278750349
Short name T685
Test name
Test status
Simulation time 1103491842 ps
CPU time 16.88 seconds
Started Feb 04 01:35:19 PM PST 24
Finished Feb 04 01:35:43 PM PST 24
Peak memory 198892 kb
Host smart-33430142-70c4-41cc-96fd-83098b4b04c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278750349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.278750349
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.400365968
Short name T832
Test name
Test status
Simulation time 7640790151 ps
CPU time 76.16 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:36:53 PM PST 24
Peak memory 199024 kb
Host smart-3ba60412-b5d6-4f6a-9f50-1efcd9049c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400365968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.400365968
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1219897565
Short name T847
Test name
Test status
Simulation time 1551913318 ps
CPU time 38.62 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:36:07 PM PST 24
Peak memory 199008 kb
Host smart-7809248c-b3e6-479f-a0b7-10a81fad1ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219897565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1219897565
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1622919172
Short name T240
Test name
Test status
Simulation time 1167102568 ps
CPU time 13.57 seconds
Started Feb 04 01:35:19 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 199020 kb
Host smart-ef39a0b3-e98a-4cf6-959b-3864a0d62e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622919172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1622919172
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.805234127
Short name T779
Test name
Test status
Simulation time 937076884 ps
CPU time 3.23 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:35:31 PM PST 24
Peak memory 199020 kb
Host smart-38965684-0248-47f3-a0f0-494c906a6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805234127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.805234127
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2566883538
Short name T571
Test name
Test status
Simulation time 42611147857 ps
CPU time 689.87 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:47:06 PM PST 24
Peak memory 231576 kb
Host smart-6f3cce07-c0ae-47bd-af7b-cdd4f10c243e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566883538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2566883538
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.2547201530
Short name T506
Test name
Test status
Simulation time 197065613538 ps
CPU time 561.73 seconds
Started Feb 04 01:35:21 PM PST 24
Finished Feb 04 01:44:50 PM PST 24
Peak memory 228872 kb
Host smart-aca0c837-77ae-4e04-925a-f7b680c128d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547201530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.2547201530
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3715072851
Short name T443
Test name
Test status
Simulation time 45943190 ps
CPU time 0.89 seconds
Started Feb 04 01:35:23 PM PST 24
Finished Feb 04 01:35:29 PM PST 24
Peak memory 196036 kb
Host smart-b18b21f1-4879-43a4-b09a-8050cd72b655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715072851 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3715072851
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2051483443
Short name T427
Test name
Test status
Simulation time 14784492985 ps
CPU time 350.2 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:41:27 PM PST 24
Peak memory 199076 kb
Host smart-64e5426d-7035-47cf-8d3d-cb6ba1f2e120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051483443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.2051483443
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.29427456
Short name T682
Test name
Test status
Simulation time 35054145187 ps
CPU time 52.51 seconds
Started Feb 04 01:35:19 PM PST 24
Finished Feb 04 01:36:20 PM PST 24
Peak memory 199172 kb
Host smart-b9dfa2b4-5331-4559-ab96-3130bd2093cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29427456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.29427456
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.244663508
Short name T507
Test name
Test status
Simulation time 52848246 ps
CPU time 0.6 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:35:29 PM PST 24
Peak memory 193408 kb
Host smart-3da75ce1-baae-422f-916b-7b6a8755d01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244663508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.244663508
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3366567583
Short name T774
Test name
Test status
Simulation time 942176003 ps
CPU time 30.88 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:35:59 PM PST 24
Peak memory 207412 kb
Host smart-0670f76d-2d53-458f-96fe-de6f924a1ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366567583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3366567583
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3713228017
Short name T649
Test name
Test status
Simulation time 3071276037 ps
CPU time 38.85 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:36:07 PM PST 24
Peak memory 199064 kb
Host smart-2054b49f-1058-4b33-a19f-57b990cc252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713228017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3713228017
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3037335304
Short name T662
Test name
Test status
Simulation time 3591490553 ps
CPU time 47.59 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:36:16 PM PST 24
Peak memory 199112 kb
Host smart-d4feaa76-164b-4461-a205-a51f75ef6921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037335304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3037335304
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1722618076
Short name T243
Test name
Test status
Simulation time 14585010567 ps
CPU time 171.16 seconds
Started Feb 04 01:35:22 PM PST 24
Finished Feb 04 01:38:19 PM PST 24
Peak memory 199044 kb
Host smart-53631141-1953-472b-a242-00aa25b9a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722618076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1722618076
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3121369184
Short name T399
Test name
Test status
Simulation time 19951251987 ps
CPU time 40.42 seconds
Started Feb 04 01:35:27 PM PST 24
Finished Feb 04 01:36:18 PM PST 24
Peak memory 198276 kb
Host smart-3f9ff951-07b9-40af-aefa-ef878408ba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121369184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3121369184
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2592935280
Short name T603
Test name
Test status
Simulation time 281704803 ps
CPU time 3.21 seconds
Started Feb 04 01:35:24 PM PST 24
Finished Feb 04 01:35:35 PM PST 24
Peak memory 198980 kb
Host smart-5480f0bf-81e5-44f1-b6e0-dba3fd30bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592935280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2592935280
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2149191650
Short name T140
Test name
Test status
Simulation time 63052513409 ps
CPU time 1452.21 seconds
Started Feb 04 01:35:21 PM PST 24
Finished Feb 04 01:59:40 PM PST 24
Peak memory 225856 kb
Host smart-5a237720-d677-4930-ba4e-25075e26862c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149191650 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2149191650
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1601900790
Short name T230
Test name
Test status
Simulation time 64156890 ps
CPU time 1.1 seconds
Started Feb 04 01:35:19 PM PST 24
Finished Feb 04 01:35:28 PM PST 24
Peak memory 197000 kb
Host smart-a98ab6db-6210-4811-8b92-f977bec58c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601900790 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1601900790
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3503112012
Short name T394
Test name
Test status
Simulation time 36528350833 ps
CPU time 342.01 seconds
Started Feb 04 01:35:26 PM PST 24
Finished Feb 04 01:41:18 PM PST 24
Peak memory 199148 kb
Host smart-b91e9778-e07b-4413-97c2-ad30228965d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503112012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.3503112012
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1079465037
Short name T220
Test name
Test status
Simulation time 4608822493 ps
CPU time 20.86 seconds
Started Feb 04 01:35:27 PM PST 24
Finished Feb 04 01:35:59 PM PST 24
Peak memory 198192 kb
Host smart-5147ee2f-3557-414c-a885-8c3de7b30b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079465037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1079465037
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4077923471
Short name T768
Test name
Test status
Simulation time 39033189 ps
CPU time 0.58 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:35:43 PM PST 24
Peak memory 193476 kb
Host smart-0b33eefc-5750-42ac-965c-666771511e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077923471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4077923471
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2398890863
Short name T420
Test name
Test status
Simulation time 1265092433 ps
CPU time 39.57 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:36:20 PM PST 24
Peak memory 215412 kb
Host smart-1e696979-7f47-422c-b497-bd9c2231bbc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398890863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2398890863
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2695453410
Short name T772
Test name
Test status
Simulation time 1777410564 ps
CPU time 42.7 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:36:23 PM PST 24
Peak memory 199040 kb
Host smart-8300620a-b4d6-4eb7-83cc-b911e403a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695453410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2695453410
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4166657876
Short name T278
Test name
Test status
Simulation time 7211147929 ps
CPU time 101.97 seconds
Started Feb 04 01:35:36 PM PST 24
Finished Feb 04 01:37:25 PM PST 24
Peak memory 199072 kb
Host smart-6253f729-2777-4a5f-8bd0-409499c82332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166657876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4166657876
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2488260014
Short name T382
Test name
Test status
Simulation time 16603081097 ps
CPU time 94.46 seconds
Started Feb 04 01:35:39 PM PST 24
Finished Feb 04 01:37:19 PM PST 24
Peak memory 199024 kb
Host smart-2a3435e6-7fe5-4331-b65d-e47bf321a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488260014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2488260014
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.357842207
Short name T569
Test name
Test status
Simulation time 111161860923 ps
CPU time 70.62 seconds
Started Feb 04 01:35:23 PM PST 24
Finished Feb 04 01:36:39 PM PST 24
Peak memory 199084 kb
Host smart-371d86f9-4bd0-4df4-a44d-2dcb0b4f1b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357842207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.357842207
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.859065083
Short name T795
Test name
Test status
Simulation time 49956723 ps
CPU time 0.98 seconds
Started Feb 04 01:35:23 PM PST 24
Finished Feb 04 01:35:31 PM PST 24
Peak memory 196252 kb
Host smart-baf41d70-9e54-464e-b093-cbf341096aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859065083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.859065083
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1892237577
Short name T241
Test name
Test status
Simulation time 19514349379 ps
CPU time 914.21 seconds
Started Feb 04 01:35:39 PM PST 24
Finished Feb 04 01:50:59 PM PST 24
Peak memory 199040 kb
Host smart-4b2af82d-ca64-4b55-b3b4-d71bc5db3f1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892237577 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1892237577
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.38077748
Short name T853
Test name
Test status
Simulation time 66995618192 ps
CPU time 954.77 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:51:39 PM PST 24
Peak memory 215488 kb
Host smart-f9f26c31-91d8-4c2c-b68b-f087710ee2c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38077748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.38077748
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.984255929
Short name T237
Test name
Test status
Simulation time 30442454 ps
CPU time 1.09 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:35:46 PM PST 24
Peak memory 197304 kb
Host smart-dd088724-6674-40f3-b2b3-8317d794f129
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984255929 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.984255929
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.741954253
Short name T444
Test name
Test status
Simulation time 26598987134 ps
CPU time 428.66 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:42:48 PM PST 24
Peak memory 199128 kb
Host smart-b5c07eeb-ca5e-4255-89b7-2af03d8c02b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741954253 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.hmac_test_sha_vectors.741954253
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1231001145
Short name T224
Test name
Test status
Simulation time 2342888950 ps
CPU time 27.15 seconds
Started Feb 04 01:35:31 PM PST 24
Finished Feb 04 01:36:06 PM PST 24
Peak memory 199104 kb
Host smart-4f21a84f-86d9-407e-92ee-4ed865d9ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231001145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1231001145
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4128287674
Short name T770
Test name
Test status
Simulation time 175242252 ps
CPU time 0.58 seconds
Started Feb 04 01:35:31 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 194496 kb
Host smart-e0707ea0-8485-46a2-aba8-51703c13d2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128287674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4128287674
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1841446437
Short name T657
Test name
Test status
Simulation time 1248163410 ps
CPU time 26.52 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:36:12 PM PST 24
Peak memory 222524 kb
Host smart-66d3e74e-833d-4cc7-b5fc-09d65132e2db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841446437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1841446437
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1954269586
Short name T404
Test name
Test status
Simulation time 358521032 ps
CPU time 17.13 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:35:58 PM PST 24
Peak memory 198980 kb
Host smart-b98733a4-19ad-4006-9a0c-7a183ca0d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954269586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1954269586
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1790279681
Short name T658
Test name
Test status
Simulation time 828739960 ps
CPU time 41.91 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:36:26 PM PST 24
Peak memory 199004 kb
Host smart-ec3429dd-5b93-4f0e-bdf4-9363ea54f84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790279681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1790279681
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.139488425
Short name T692
Test name
Test status
Simulation time 5941789339 ps
CPU time 76.84 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 01:36:59 PM PST 24
Peak memory 199120 kb
Host smart-38d6a529-fdc3-49f5-acbf-6d1d9efea028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139488425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.139488425
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1642863589
Short name T574
Test name
Test status
Simulation time 220544141 ps
CPU time 1.44 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 198516 kb
Host smart-e8e1edb8-3d37-4708-8402-d29acea21b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642863589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1642863589
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1902143631
Short name T514
Test name
Test status
Simulation time 20011169460 ps
CPU time 920.93 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:51:03 PM PST 24
Peak memory 199076 kb
Host smart-09e10e95-0c70-4644-ab16-a4e11982f3a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902143631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1902143631
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.1491716032
Short name T843
Test name
Test status
Simulation time 108169116030 ps
CPU time 1846.7 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 02:06:31 PM PST 24
Peak memory 240568 kb
Host smart-5ec2e13e-8355-42f1-a1cb-80070d3271eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491716032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.1491716032
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2342145960
Short name T5
Test name
Test status
Simulation time 60321867 ps
CPU time 1.16 seconds
Started Feb 04 01:35:41 PM PST 24
Finished Feb 04 01:35:47 PM PST 24
Peak memory 197552 kb
Host smart-dd9077b3-8aae-4a05-a082-08bdf8bb1cd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342145960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2342145960
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.955819778
Short name T615
Test name
Test status
Simulation time 28367891898 ps
CPU time 328.48 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:41:10 PM PST 24
Peak memory 199092 kb
Host smart-e7e448a7-fe43-47ba-9fd3-c421b6214698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955819778 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.hmac_test_sha_vectors.955819778
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2688168694
Short name T663
Test name
Test status
Simulation time 2750802228 ps
CPU time 45.04 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:36:24 PM PST 24
Peak memory 199056 kb
Host smart-41c9714c-cd1d-4384-a268-6b5240c92ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688168694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2688168694
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3608630106
Short name T587
Test name
Test status
Simulation time 64434682 ps
CPU time 0.58 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 193428 kb
Host smart-59dbc87e-3179-4f9a-a5f9-9c4e9f7e8a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608630106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3608630106
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.502892708
Short name T721
Test name
Test status
Simulation time 895420046 ps
CPU time 30.6 seconds
Started Feb 04 01:35:39 PM PST 24
Finished Feb 04 01:36:16 PM PST 24
Peak memory 232668 kb
Host smart-4dde3df5-d6c7-423a-bd2c-87364ce1cb18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502892708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.502892708
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4095142572
Short name T596
Test name
Test status
Simulation time 1812757200 ps
CPU time 31.84 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:36:17 PM PST 24
Peak memory 198948 kb
Host smart-6e2fa7d5-64a3-48ec-97ab-77523293348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095142572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4095142572
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3601933367
Short name T729
Test name
Test status
Simulation time 4835033635 ps
CPU time 62.23 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:36:41 PM PST 24
Peak memory 198976 kb
Host smart-32412bc3-88fa-44f3-a0ea-8d77455e661c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601933367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3601933367
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.473320584
Short name T750
Test name
Test status
Simulation time 10467104851 ps
CPU time 127.84 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:37:52 PM PST 24
Peak memory 199012 kb
Host smart-e6799101-ee14-4744-a840-013dd2949714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473320584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.473320584
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1226186938
Short name T775
Test name
Test status
Simulation time 1371117903 ps
CPU time 4.33 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:35:46 PM PST 24
Peak memory 199120 kb
Host smart-637189ca-f18e-46b3-8eb9-d453ce8e57a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226186938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1226186938
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3775355967
Short name T602
Test name
Test status
Simulation time 214851852 ps
CPU time 1.16 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 01:35:43 PM PST 24
Peak memory 198192 kb
Host smart-d15621bc-bbdf-4f6b-adba-8e0793552444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775355967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3775355967
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1249303079
Short name T113
Test name
Test status
Simulation time 211127415109 ps
CPU time 926.81 seconds
Started Feb 04 01:35:35 PM PST 24
Finished Feb 04 01:51:09 PM PST 24
Peak memory 245068 kb
Host smart-60c19d49-f88f-47b8-95d2-9e51e53f8469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249303079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1249303079
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.1251894692
Short name T377
Test name
Test status
Simulation time 8183046270 ps
CPU time 124.7 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:37:50 PM PST 24
Peak memory 231804 kb
Host smart-ce3d3344-3494-4d7d-9c7b-032838c8ef86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251894692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.1251894692
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1677217099
Short name T322
Test name
Test status
Simulation time 72202160 ps
CPU time 1.22 seconds
Started Feb 04 01:35:31 PM PST 24
Finished Feb 04 01:35:41 PM PST 24
Peak memory 196368 kb
Host smart-baae316b-ae53-4ddd-a6f8-3a18c6750f75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677217099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1677217099
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.733416766
Short name T295
Test name
Test status
Simulation time 42028033062 ps
CPU time 346.85 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:41:29 PM PST 24
Peak memory 199120 kb
Host smart-b16c671d-f6d3-4839-be2c-97a248ce4198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733416766 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_sha_vectors.733416766
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3596731549
Short name T814
Test name
Test status
Simulation time 557533490 ps
CPU time 6.72 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:35:51 PM PST 24
Peak memory 198988 kb
Host smart-c146a664-a926-481d-b0e1-e756fc12790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596731549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3596731549
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2346833967
Short name T534
Test name
Test status
Simulation time 14623274 ps
CPU time 0.59 seconds
Started Feb 04 01:35:28 PM PST 24
Finished Feb 04 01:35:39 PM PST 24
Peak memory 194492 kb
Host smart-a9b940f9-5363-4df6-b87f-d14e511b3c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346833967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2346833967
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3336784148
Short name T36
Test name
Test status
Simulation time 1277624194 ps
CPU time 44.78 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:36:30 PM PST 24
Peak memory 220460 kb
Host smart-9dfd2d59-a6d6-4b05-bc03-0ac7e4b22078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336784148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3336784148
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1322866781
Short name T686
Test name
Test status
Simulation time 515340341 ps
CPU time 6.31 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 01:35:48 PM PST 24
Peak memory 199080 kb
Host smart-787c9d3b-586b-4cbd-abfa-38fc37a3c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322866781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1322866781
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4074689063
Short name T437
Test name
Test status
Simulation time 552305851 ps
CPU time 14.51 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:35:54 PM PST 24
Peak memory 199012 kb
Host smart-8791c7f0-bd07-4e12-ba53-fc89686a07c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074689063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4074689063
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2495613057
Short name T362
Test name
Test status
Simulation time 2612607248 ps
CPU time 14.32 seconds
Started Feb 04 01:35:30 PM PST 24
Finished Feb 04 01:35:53 PM PST 24
Peak memory 199036 kb
Host smart-9396e06c-c83f-4524-97e9-93f84cd69052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495613057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2495613057
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.625075941
Short name T287
Test name
Test status
Simulation time 10176727672 ps
CPU time 71.77 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 01:36:54 PM PST 24
Peak memory 199072 kb
Host smart-a5559395-f353-402c-98f9-414ed681cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625075941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.625075941
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3435870374
Short name T856
Test name
Test status
Simulation time 134297160 ps
CPU time 1.8 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 01:35:44 PM PST 24
Peak memory 198852 kb
Host smart-bedce4c3-17e9-48ab-b3bc-06fbedeafff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435870374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3435870374
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.641618279
Short name T542
Test name
Test status
Simulation time 32381856743 ps
CPU time 202.76 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:39:07 PM PST 24
Peak memory 214796 kb
Host smart-74483fde-ee27-4d3b-be27-4b3549fa4326
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641618279 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.641618279
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2957530947
Short name T519
Test name
Test status
Simulation time 164955294 ps
CPU time 0.92 seconds
Started Feb 04 01:35:35 PM PST 24
Finished Feb 04 01:35:43 PM PST 24
Peak memory 196148 kb
Host smart-06dfc770-58f9-434a-aa40-7f8b77ab3db0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957530947 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2957530947
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1117434478
Short name T586
Test name
Test status
Simulation time 28562236059 ps
CPU time 436.34 seconds
Started Feb 04 01:35:39 PM PST 24
Finished Feb 04 01:43:01 PM PST 24
Peak memory 199028 kb
Host smart-359d8d70-0f93-47a7-8bb8-ca6a4919b3e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117434478 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.1117434478
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1365404756
Short name T478
Test name
Test status
Simulation time 272930365 ps
CPU time 12.42 seconds
Started Feb 04 01:35:38 PM PST 24
Finished Feb 04 01:35:56 PM PST 24
Peak memory 198960 kb
Host smart-d685d631-b09b-4807-8c9b-c2fa44afd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365404756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1365404756
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.460183449
Short name T510
Test name
Test status
Simulation time 19808843 ps
CPU time 0.57 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:11 PM PST 24
Peak memory 193456 kb
Host smart-ec7fb2a5-236f-47f4-8726-ba3751a93d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460183449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.460183449
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2293731252
Short name T612
Test name
Test status
Simulation time 6537303568 ps
CPU time 51.02 seconds
Started Feb 04 01:32:19 PM PST 24
Finished Feb 04 01:33:12 PM PST 24
Peak memory 215344 kb
Host smart-a4151c65-0d3b-4887-822a-58b43d6211b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293731252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2293731252
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4104846561
Short name T304
Test name
Test status
Simulation time 2103485251 ps
CPU time 39.05 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:49 PM PST 24
Peak memory 199044 kb
Host smart-a36916e1-d8d3-4e74-9f42-6be94c42de3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104846561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4104846561
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3005787075
Short name T12
Test name
Test status
Simulation time 1317609730 ps
CPU time 16.11 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:25 PM PST 24
Peak memory 198940 kb
Host smart-9476309c-106a-40a4-9741-a339f9f97d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005787075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3005787075
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.8509722
Short name T246
Test name
Test status
Simulation time 7422148046 ps
CPU time 97.07 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:33:47 PM PST 24
Peak memory 199060 kb
Host smart-d170da26-1321-4c5c-9250-bc52cf349919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8509722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.8509722
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3478645228
Short name T62
Test name
Test status
Simulation time 3742908846 ps
CPU time 23.51 seconds
Started Feb 04 01:32:09 PM PST 24
Finished Feb 04 01:32:34 PM PST 24
Peak memory 199032 kb
Host smart-9e99e226-a6ab-4c5c-8097-809c919ad30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478645228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3478645228
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1687526328
Short name T813
Test name
Test status
Simulation time 271085842 ps
CPU time 1.36 seconds
Started Feb 04 01:32:02 PM PST 24
Finished Feb 04 01:32:04 PM PST 24
Peak memory 198504 kb
Host smart-012dd532-74cc-4f0a-9744-1c91e2f1b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687526328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1687526328
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3763499445
Short name T411
Test name
Test status
Simulation time 273373348729 ps
CPU time 1497.93 seconds
Started Feb 04 01:32:19 PM PST 24
Finished Feb 04 01:57:20 PM PST 24
Peak memory 199128 kb
Host smart-b09c65df-3df1-4e33-bb65-fc7a43944d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763499445 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3763499445
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3417351987
Short name T694
Test name
Test status
Simulation time 21260711464 ps
CPU time 1058.61 seconds
Started Feb 04 01:32:00 PM PST 24
Finished Feb 04 01:49:40 PM PST 24
Peak memory 247880 kb
Host smart-aa327876-6fb8-4822-828c-14336094583b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417351987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3417351987
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3857371861
Short name T697
Test name
Test status
Simulation time 80067407 ps
CPU time 1 seconds
Started Feb 04 01:32:21 PM PST 24
Finished Feb 04 01:32:29 PM PST 24
Peak memory 196212 kb
Host smart-659f92dc-fbd9-4e62-9968-7187748e312c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857371861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3857371861
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.4034066651
Short name T745
Test name
Test status
Simulation time 27133956174 ps
CPU time 463.55 seconds
Started Feb 04 01:32:21 PM PST 24
Finished Feb 04 01:40:12 PM PST 24
Peak memory 199060 kb
Host smart-a8a9676a-3b7b-4878-892e-6f92d6c1398e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034066651 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.4034066651
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1354864965
Short name T725
Test name
Test status
Simulation time 4045669021 ps
CPU time 17.3 seconds
Started Feb 04 01:32:17 PM PST 24
Finished Feb 04 01:32:38 PM PST 24
Peak memory 199032 kb
Host smart-5db6f1b1-9358-4d71-b3cb-17ebb6f8aaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354864965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1354864965
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.4247840690
Short name T584
Test name
Test status
Simulation time 128032442815 ps
CPU time 790.13 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:48:52 PM PST 24
Peak memory 248472 kb
Host smart-c5ac8189-c62e-4038-ac6d-e75ac2bbeaa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247840690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.4247840690
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.1179593189
Short name T118
Test name
Test status
Simulation time 490054467490 ps
CPU time 1524.77 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 02:01:06 PM PST 24
Peak memory 248276 kb
Host smart-5673babc-c0aa-40e9-8254-07663b1d1d86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179593189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.1179593189
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.3363085667
Short name T788
Test name
Test status
Simulation time 304681926971 ps
CPU time 2263.47 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 02:13:25 PM PST 24
Peak memory 264716 kb
Host smart-bfd77795-3347-4a57-ac78-d7cab68d36c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363085667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.3363085667
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.826572722
Short name T108
Test name
Test status
Simulation time 80747019593 ps
CPU time 1466.75 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 02:00:09 PM PST 24
Peak memory 228516 kb
Host smart-87b2c389-d2e9-4368-a26e-c1bf25625c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826572722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.826572722
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.484977153
Short name T252
Test name
Test status
Simulation time 14351397194 ps
CPU time 226.39 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:39:32 PM PST 24
Peak memory 214344 kb
Host smart-ee7b9e77-4b36-41b6-b459-1fbee7f960e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484977153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.484977153
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.2250177122
Short name T511
Test name
Test status
Simulation time 316633721937 ps
CPU time 1306.77 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 01:57:29 PM PST 24
Peak memory 232016 kb
Host smart-226eeac5-00f1-481b-a0c5-da44f1f8a637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250177122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.2250177122
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.2259539043
Short name T4
Test name
Test status
Simulation time 101040054029 ps
CPU time 1415.17 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 01:59:23 PM PST 24
Peak memory 248332 kb
Host smart-d509485d-a674-4822-8b3e-7fadadf58762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259539043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.2259539043
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.2131406472
Short name T531
Test name
Test status
Simulation time 103113650770 ps
CPU time 3560.72 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 02:35:03 PM PST 24
Peak memory 265072 kb
Host smart-29f94d9e-33e0-4489-ab67-7781d1033050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131406472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.2131406472
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.3800709679
Short name T318
Test name
Test status
Simulation time 108980539166 ps
CPU time 1457.46 seconds
Started Feb 04 01:35:35 PM PST 24
Finished Feb 04 02:00:00 PM PST 24
Peak memory 246256 kb
Host smart-57c9b656-f6e7-48ba-a3c9-a7e9c8bc9053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800709679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.3800709679
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.2624108056
Short name T620
Test name
Test status
Simulation time 62894388966 ps
CPU time 3111.05 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 02:27:33 PM PST 24
Peak memory 256496 kb
Host smart-69a30c0e-efcb-4aba-8b4a-6ef858110eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624108056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.2624108056
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2757338912
Short name T535
Test name
Test status
Simulation time 30174797 ps
CPU time 0.56 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:11 PM PST 24
Peak memory 193348 kb
Host smart-b42490f0-8108-465f-bb1f-037284e34f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757338912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2757338912
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2099940486
Short name T619
Test name
Test status
Simulation time 6982355321 ps
CPU time 58.05 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:33:16 PM PST 24
Peak memory 240104 kb
Host smart-ec9d5b41-4ca1-4bae-b6c0-538c2b9b44dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099940486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2099940486
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.985292888
Short name T238
Test name
Test status
Simulation time 6278525735 ps
CPU time 29.04 seconds
Started Feb 04 01:32:06 PM PST 24
Finished Feb 04 01:32:36 PM PST 24
Peak memory 199068 kb
Host smart-f729f0e6-ed20-4005-b0fb-f5c7161e36d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985292888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.985292888
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.4059051666
Short name T827
Test name
Test status
Simulation time 11594878075 ps
CPU time 148.75 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:34:36 PM PST 24
Peak memory 199108 kb
Host smart-b6abd920-e351-4955-b922-c0c61757448b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059051666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4059051666
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1044377021
Short name T678
Test name
Test status
Simulation time 19037263875 ps
CPU time 213.12 seconds
Started Feb 04 01:32:21 PM PST 24
Finished Feb 04 01:36:02 PM PST 24
Peak memory 199208 kb
Host smart-9fea95ef-c7c4-4df9-bbb8-c373e65a2c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044377021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1044377021
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1399561440
Short name T728
Test name
Test status
Simulation time 1812412543 ps
CPU time 49.67 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:19 PM PST 24
Peak memory 199056 kb
Host smart-b5b74574-5ebb-42af-9afd-08fa5708c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399561440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1399561440
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.233012802
Short name T328
Test name
Test status
Simulation time 1851630792 ps
CPU time 4.79 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:14 PM PST 24
Peak memory 198988 kb
Host smart-02444a27-d4e7-4cbc-a3dc-6aa40ea9c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233012802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.233012802
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1525426425
Short name T607
Test name
Test status
Simulation time 1593775989329 ps
CPU time 1596.91 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:58:46 PM PST 24
Peak memory 215196 kb
Host smart-89554905-5d33-477a-a68c-122c1c407cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525426425 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1525426425
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4207966823
Short name T264
Test name
Test status
Simulation time 185377465182 ps
CPU time 2624.48 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 02:16:16 PM PST 24
Peak memory 226656 kb
Host smart-dc395273-70a9-40ca-99a1-f4a2025331c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207966823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4207966823
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4243914505
Short name T599
Test name
Test status
Simulation time 62332244 ps
CPU time 1.15 seconds
Started Feb 04 01:32:17 PM PST 24
Finished Feb 04 01:32:22 PM PST 24
Peak memory 196728 kb
Host smart-afdb401b-bc51-43f7-81eb-0a253e52a9dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243914505 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4243914505
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.676131054
Short name T259
Test name
Test status
Simulation time 27960007613 ps
CPU time 336.39 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:37:45 PM PST 24
Peak memory 199064 kb
Host smart-ee38ed63-e184-4a87-8750-c14f24fc4bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676131054 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.hmac_test_sha_vectors.676131054
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.850160043
Short name T354
Test name
Test status
Simulation time 12244981753 ps
CPU time 54.31 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:33:04 PM PST 24
Peak memory 199016 kb
Host smart-20271396-428b-4ebc-abbf-5b19df8a6adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850160043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.850160043
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.3842587460
Short name T529
Test name
Test status
Simulation time 136682631618 ps
CPU time 3122.32 seconds
Started Feb 04 01:35:31 PM PST 24
Finished Feb 04 02:27:42 PM PST 24
Peak memory 244424 kb
Host smart-0a3c049d-892f-4380-8ccd-a07347c16caf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842587460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.3842587460
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.626388810
Short name T624
Test name
Test status
Simulation time 232517010893 ps
CPU time 1039.24 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:53:05 PM PST 24
Peak memory 223744 kb
Host smart-ba7bfb26-f3bd-49d7-b47f-22b5668ee5f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626388810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.626388810
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.2712717700
Short name T469
Test name
Test status
Simulation time 520727782387 ps
CPU time 1882.55 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 02:07:04 PM PST 24
Peak memory 259520 kb
Host smart-a01e60b9-722f-455b-88b7-463d0d5b43a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712717700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.2712717700
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.410971464
Short name T673
Test name
Test status
Simulation time 343826506006 ps
CPU time 1471.08 seconds
Started Feb 04 01:35:39 PM PST 24
Finished Feb 04 02:00:16 PM PST 24
Peak memory 223640 kb
Host smart-4209e4cd-aec1-422a-a4cb-77d6e679a9af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410971464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.410971464
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.3959171923
Short name T419
Test name
Test status
Simulation time 36299200839 ps
CPU time 609.88 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 01:45:58 PM PST 24
Peak memory 215576 kb
Host smart-cd9ccc45-79a2-4e9a-bf99-7d80f9aa4a6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959171923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.3959171923
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.3849838301
Short name T465
Test name
Test status
Simulation time 204674305470 ps
CPU time 1036.88 seconds
Started Feb 04 01:35:40 PM PST 24
Finished Feb 04 01:53:03 PM PST 24
Peak memory 241172 kb
Host smart-fad8e30e-c667-4f59-aff1-12245f787ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849838301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.3849838301
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3501831865
Short name T132
Test name
Test status
Simulation time 25059211663 ps
CPU time 1251.38 seconds
Started Feb 04 01:35:35 PM PST 24
Finished Feb 04 01:56:34 PM PST 24
Peak memory 215608 kb
Host smart-d934b4f1-f0f3-4505-ae8e-26f499b33f9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501831865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3501831865
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.2238167512
Short name T594
Test name
Test status
Simulation time 153874617047 ps
CPU time 1730.88 seconds
Started Feb 04 01:35:32 PM PST 24
Finished Feb 04 02:04:31 PM PST 24
Peak memory 231900 kb
Host smart-f29cf7a3-1aa3-4e6a-aaac-495c67ba4948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238167512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.2238167512
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.2762603530
Short name T733
Test name
Test status
Simulation time 71816084918 ps
CPU time 243.66 seconds
Started Feb 04 01:35:36 PM PST 24
Finished Feb 04 01:39:46 PM PST 24
Peak memory 240160 kb
Host smart-4c1f850a-dac5-4591-b398-f9ca4d500aa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762603530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.2762603530
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.3819971054
Short name T784
Test name
Test status
Simulation time 82469083905 ps
CPU time 3369.66 seconds
Started Feb 04 01:35:35 PM PST 24
Finished Feb 04 02:31:52 PM PST 24
Peak memory 264540 kb
Host smart-ee460c10-7cd9-4c4f-9f70-e5321763b905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819971054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.3819971054
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3215348037
Short name T225
Test name
Test status
Simulation time 18673776 ps
CPU time 0.57 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:18 PM PST 24
Peak memory 193464 kb
Host smart-4b266e5f-cb2e-4757-a42a-9752d1b601ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215348037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3215348037
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2836496927
Short name T336
Test name
Test status
Simulation time 17636000600 ps
CPU time 28.51 seconds
Started Feb 04 01:32:05 PM PST 24
Finished Feb 04 01:32:35 PM PST 24
Peak memory 198984 kb
Host smart-4c779b56-2a3b-47e0-b3de-7f0c79162542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836496927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2836496927
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2936805036
Short name T719
Test name
Test status
Simulation time 7878634072 ps
CPU time 49.04 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:18 PM PST 24
Peak memory 199088 kb
Host smart-79c28e7d-66d5-447c-a930-fcd78f7b0dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936805036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2936805036
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3413157895
Short name T232
Test name
Test status
Simulation time 422224059 ps
CPU time 4.81 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:14 PM PST 24
Peak memory 199076 kb
Host smart-3da1485f-bd54-44e8-b1c6-9652d27958a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413157895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3413157895
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1250351295
Short name T643
Test name
Test status
Simulation time 10399893783 ps
CPU time 78 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:33:28 PM PST 24
Peak memory 199144 kb
Host smart-522cb731-0f27-4e1d-95dc-6545540314d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250351295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1250351295
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.66587048
Short name T786
Test name
Test status
Simulation time 7560651676 ps
CPU time 49.2 seconds
Started Feb 04 01:32:07 PM PST 24
Finished Feb 04 01:32:57 PM PST 24
Peak memory 199072 kb
Host smart-218fe9a0-60f2-486e-857e-00be9209cd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66587048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.66587048
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3976156447
Short name T331
Test name
Test status
Simulation time 659456671 ps
CPU time 3.96 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:13 PM PST 24
Peak memory 198936 kb
Host smart-46b6f0d8-b65d-43f7-a352-7d414af34369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976156447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3976156447
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1562378793
Short name T432
Test name
Test status
Simulation time 9667301870 ps
CPU time 160.82 seconds
Started Feb 04 01:32:03 PM PST 24
Finished Feb 04 01:34:44 PM PST 24
Peak memory 199116 kb
Host smart-17038b8d-17e3-4156-b7c2-6e384a2735f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562378793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1562378793
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2215104040
Short name T40
Test name
Test status
Simulation time 385083388861 ps
CPU time 1821.16 seconds
Started Feb 04 01:32:20 PM PST 24
Finished Feb 04 02:02:43 PM PST 24
Peak memory 244336 kb
Host smart-f16802ef-8883-49fb-bcc0-24c13b4a0d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215104040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2215104040
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2040217433
Short name T857
Test name
Test status
Simulation time 106123929 ps
CPU time 1.22 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:32:22 PM PST 24
Peak memory 196644 kb
Host smart-8136663f-326b-4f0b-a002-ec04ce5aa6ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040217433 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2040217433
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2585636489
Short name T289
Test name
Test status
Simulation time 37957366486 ps
CPU time 404.73 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:38:55 PM PST 24
Peak memory 199068 kb
Host smart-2f7d6054-5a50-4295-8134-6df72d502935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585636489 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.2585636489
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1538443009
Short name T849
Test name
Test status
Simulation time 474192067 ps
CPU time 19.16 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:32:28 PM PST 24
Peak memory 199052 kb
Host smart-12c8d422-aaca-4f48-b48a-6dfcea499d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538443009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1538443009
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2858132201
Short name T558
Test name
Test status
Simulation time 18403576480 ps
CPU time 937.6 seconds
Started Feb 04 01:35:33 PM PST 24
Finished Feb 04 01:51:19 PM PST 24
Peak memory 227756 kb
Host smart-2db52cb3-9b53-4564-9e75-c714be7694fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858132201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2858132201
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.802973215
Short name T239
Test name
Test status
Simulation time 32685203368 ps
CPU time 517.69 seconds
Started Feb 04 01:35:36 PM PST 24
Finished Feb 04 01:44:21 PM PST 24
Peak memory 207388 kb
Host smart-97d4f439-b2f2-4360-88bb-7d8034daa9cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802973215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.802973215
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.1310838073
Short name T731
Test name
Test status
Simulation time 446363810487 ps
CPU time 1719.93 seconds
Started Feb 04 01:35:34 PM PST 24
Finished Feb 04 02:04:22 PM PST 24
Peak memory 257516 kb
Host smart-f943b349-a98d-41c2-80c0-98dc9dffcd67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310838073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.1310838073
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2515140724
Short name T286
Test name
Test status
Simulation time 80313474182 ps
CPU time 291.36 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 01:40:40 PM PST 24
Peak memory 240152 kb
Host smart-1f84a66a-7183-40c4-9947-419218878c6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515140724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2515140724
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3200231589
Short name T123
Test name
Test status
Simulation time 57818001109 ps
CPU time 2483.28 seconds
Started Feb 04 01:35:49 PM PST 24
Finished Feb 04 02:17:16 PM PST 24
Peak memory 215540 kb
Host smart-62214b1b-d8d7-4b3a-b11c-9a54b8648e17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200231589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.3200231589
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.4016850134
Short name T777
Test name
Test status
Simulation time 122535111483 ps
CPU time 438.48 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 01:43:09 PM PST 24
Peak memory 215548 kb
Host smart-00b608f1-5f29-4348-bc77-4e0f3a856cce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016850134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.4016850134
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3089110587
Short name T112
Test name
Test status
Simulation time 97338224526 ps
CPU time 437.91 seconds
Started Feb 04 01:35:49 PM PST 24
Finished Feb 04 01:43:10 PM PST 24
Peak memory 207352 kb
Host smart-8d2b56af-be02-4c06-bf78-ab3a090a7e89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089110587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3089110587
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1947429885
Short name T800
Test name
Test status
Simulation time 175455139331 ps
CPU time 1709.08 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 02:04:19 PM PST 24
Peak memory 248320 kb
Host smart-34d69b8a-9105-4712-b3a2-212013629d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947429885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.1947429885
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.4262371710
Short name T485
Test name
Test status
Simulation time 52406365997 ps
CPU time 372.83 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 01:42:03 PM PST 24
Peak memory 214820 kb
Host smart-6cb82b97-cacf-4085-8a03-0945df0a949f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262371710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.4262371710
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3933961614
Short name T49
Test name
Test status
Simulation time 12847062 ps
CPU time 0.56 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:32 PM PST 24
Peak memory 193420 kb
Host smart-cd34fad2-6283-4c1c-aa90-a1f3659f6364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933961614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3933961614
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2095269776
Short name T262
Test name
Test status
Simulation time 279632834 ps
CPU time 2.86 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:21 PM PST 24
Peak memory 198972 kb
Host smart-682f9dbd-ab7a-448a-b58a-59576df6976a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095269776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2095269776
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3192052057
Short name T337
Test name
Test status
Simulation time 582293213 ps
CPU time 14.38 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:32:44 PM PST 24
Peak memory 199164 kb
Host smart-8bcc3d3a-144f-48a9-9169-27789b7cf150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192052057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3192052057
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.974730261
Short name T533
Test name
Test status
Simulation time 2075523767 ps
CPU time 112.25 seconds
Started Feb 04 01:32:08 PM PST 24
Finished Feb 04 01:34:02 PM PST 24
Peak memory 199052 kb
Host smart-eca9a54e-a1d9-42d0-abe7-9dc095fd85a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974730261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.974730261
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1906580010
Short name T448
Test name
Test status
Simulation time 2792194116 ps
CPU time 42.89 seconds
Started Feb 04 01:32:26 PM PST 24
Finished Feb 04 01:33:15 PM PST 24
Peak memory 198956 kb
Host smart-78bb2eaf-f60e-429e-b9fe-ac0295d053f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906580010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1906580010
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.539174834
Short name T787
Test name
Test status
Simulation time 2000755149 ps
CPU time 24.11 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:42 PM PST 24
Peak memory 199036 kb
Host smart-3e148457-1e85-4c90-9cf0-58b880f9f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539174834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.539174834
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.207917980
Short name T780
Test name
Test status
Simulation time 180219569 ps
CPU time 1.35 seconds
Started Feb 04 01:32:19 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 198660 kb
Host smart-329599be-0f93-4a52-858f-1c6ee554ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207917980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.207917980
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.147021848
Short name T445
Test name
Test status
Simulation time 205411835793 ps
CPU time 207.97 seconds
Started Feb 04 01:32:27 PM PST 24
Finished Feb 04 01:36:00 PM PST 24
Peak memory 215348 kb
Host smart-83bf9db8-60ed-4358-8443-30256e5a4fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147021848 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.147021848
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2432344953
Short name T815
Test name
Test status
Simulation time 151615409866 ps
CPU time 574.16 seconds
Started Feb 04 01:32:25 PM PST 24
Finished Feb 04 01:42:06 PM PST 24
Peak memory 215528 kb
Host smart-b1803493-8d5e-44cb-ae77-672b94229b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432344953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2432344953
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1227737146
Short name T450
Test name
Test status
Simulation time 209082686 ps
CPU time 1.25 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:19 PM PST 24
Peak memory 197332 kb
Host smart-4e9718ae-2c3d-4127-94a6-647c8f16eee6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227737146 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1227737146
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.28694422
Short name T706
Test name
Test status
Simulation time 7031201527 ps
CPU time 356.58 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:38:18 PM PST 24
Peak memory 199040 kb
Host smart-00a6ccc2-adc6-4da2-b81a-41450ea70d2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28694422 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.hmac_test_sha_vectors.28694422
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3734285852
Short name T269
Test name
Test status
Simulation time 3403104773 ps
CPU time 22.79 seconds
Started Feb 04 01:32:14 PM PST 24
Finished Feb 04 01:32:38 PM PST 24
Peak memory 198956 kb
Host smart-6d475dd6-4fc8-4cce-b0af-c67aeedcd68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734285852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3734285852
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1041952113
Short name T842
Test name
Test status
Simulation time 40568376279 ps
CPU time 521.15 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 01:44:30 PM PST 24
Peak memory 207276 kb
Host smart-564a7fa2-77c9-4cd0-b4f9-e7e18e15cb3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041952113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.1041952113
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.389984806
Short name T829
Test name
Test status
Simulation time 152178167891 ps
CPU time 1793.17 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 02:05:41 PM PST 24
Peak memory 243120 kb
Host smart-a36d129d-2fde-4b7b-a75d-d6965ad5d0c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389984806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.389984806
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.845640907
Short name T698
Test name
Test status
Simulation time 126893985229 ps
CPU time 1757.74 seconds
Started Feb 04 01:35:42 PM PST 24
Finished Feb 04 02:05:04 PM PST 24
Peak memory 244944 kb
Host smart-f21c064c-a90f-4596-a4dc-5f4551f783c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845640907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.845640907
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3257045399
Short name T837
Test name
Test status
Simulation time 22426073095 ps
CPU time 186.51 seconds
Started Feb 04 01:35:43 PM PST 24
Finished Feb 04 01:38:54 PM PST 24
Peak memory 215564 kb
Host smart-54e266e7-5949-45bb-ae79-43aaca0bac75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257045399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.3257045399
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.2946263921
Short name T759
Test name
Test status
Simulation time 79567458890 ps
CPU time 983.7 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 01:52:14 PM PST 24
Peak memory 248332 kb
Host smart-e7013e04-65c7-4686-8bdf-02aa61a3c7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946263921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.2946263921
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.448675541
Short name T693
Test name
Test status
Simulation time 335342828639 ps
CPU time 1183.1 seconds
Started Feb 04 01:35:42 PM PST 24
Finished Feb 04 01:55:30 PM PST 24
Peak memory 240372 kb
Host smart-5c08b1e5-045a-4205-90eb-b2be8ca3400b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448675541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.448675541
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.1358819920
Short name T348
Test name
Test status
Simulation time 9055138154 ps
CPU time 187.96 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 01:38:55 PM PST 24
Peak memory 199200 kb
Host smart-26857a00-333a-4264-afd7-665187282a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358819920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.1358819920
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3291168150
Short name T828
Test name
Test status
Simulation time 98258181224 ps
CPU time 3964.21 seconds
Started Feb 04 01:35:44 PM PST 24
Finished Feb 04 02:41:53 PM PST 24
Peak memory 264644 kb
Host smart-5de797b6-d9dc-4a6b-81e9-990e1a60d88b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291168150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.3291168150
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3786875020
Short name T670
Test name
Test status
Simulation time 12789417 ps
CPU time 0.57 seconds
Started Feb 04 01:32:18 PM PST 24
Finished Feb 04 01:32:21 PM PST 24
Peak memory 192796 kb
Host smart-517e3ffa-1faf-4776-94ec-35cc7dd20b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786875020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3786875020
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.624428836
Short name T313
Test name
Test status
Simulation time 1278735146 ps
CPU time 9.44 seconds
Started Feb 04 01:32:23 PM PST 24
Finished Feb 04 01:32:41 PM PST 24
Peak memory 207136 kb
Host smart-c671edf5-009d-4685-9db1-2e4d832036cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624428836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.624428836
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2534542893
Short name T621
Test name
Test status
Simulation time 4336827275 ps
CPU time 23.03 seconds
Started Feb 04 01:32:14 PM PST 24
Finished Feb 04 01:32:38 PM PST 24
Peak memory 199040 kb
Host smart-90f47a0e-f94f-4456-a0f7-001f057c4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534542893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2534542893
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.67996280
Short name T487
Test name
Test status
Simulation time 1376643582 ps
CPU time 69.74 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:39 PM PST 24
Peak memory 199004 kb
Host smart-99e9f01c-7741-4017-a79f-5f43a9e632ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67996280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.67996280
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4280280150
Short name T268
Test name
Test status
Simulation time 6488559379 ps
CPU time 82.32 seconds
Started Feb 04 01:32:26 PM PST 24
Finished Feb 04 01:33:54 PM PST 24
Peak memory 198980 kb
Host smart-3513f829-55dc-420f-8d2b-1b2cc4d8918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280280150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4280280150
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1508248298
Short name T503
Test name
Test status
Simulation time 2723288335 ps
CPU time 38.19 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:08 PM PST 24
Peak memory 199092 kb
Host smart-508e746e-1baf-43eb-925d-d13d0a35f79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508248298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1508248298
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3633757014
Short name T758
Test name
Test status
Simulation time 125380893 ps
CPU time 1.54 seconds
Started Feb 04 01:32:19 PM PST 24
Finished Feb 04 01:32:23 PM PST 24
Peak memory 198664 kb
Host smart-739cd202-3bf0-46ea-a137-417fbf5de2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633757014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3633757014
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1097846269
Short name T747
Test name
Test status
Simulation time 24602687604 ps
CPU time 113.22 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:34:29 PM PST 24
Peak memory 227804 kb
Host smart-a51c1a28-4498-4894-b211-aada66c4e783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097846269 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1097846269
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.4162313277
Short name T430
Test name
Test status
Simulation time 86399186330 ps
CPU time 751.65 seconds
Started Feb 04 01:32:31 PM PST 24
Finished Feb 04 01:45:08 PM PST 24
Peak memory 215548 kb
Host smart-2482cb6d-33e1-40b2-af11-1bab8cc62ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162313277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.4162313277
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1083417603
Short name T592
Test name
Test status
Simulation time 179944093 ps
CPU time 1.26 seconds
Started Feb 04 01:32:16 PM PST 24
Finished Feb 04 01:32:19 PM PST 24
Peak memory 196292 kb
Host smart-4c3df74b-c41a-4dc4-aabf-9086593c4a9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083417603 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1083417603
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2535259979
Short name T609
Test name
Test status
Simulation time 10311028654 ps
CPU time 35.96 seconds
Started Feb 04 01:32:22 PM PST 24
Finished Feb 04 01:33:05 PM PST 24
Peak memory 199080 kb
Host smart-8f80866e-b878-45f0-bde2-d400f7b481b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535259979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2535259979
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3683017214
Short name T710
Test name
Test status
Simulation time 33554287801 ps
CPU time 109.3 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 01:37:39 PM PST 24
Peak memory 215380 kb
Host smart-38c20347-b20d-4d9c-8614-7327ad1c20ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683017214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.3683017214
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1235097479
Short name T471
Test name
Test status
Simulation time 25099763068 ps
CPU time 97.12 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 01:37:32 PM PST 24
Peak memory 207328 kb
Host smart-7d589e94-2d55-4866-ba08-a8fb74827f35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235097479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.1235097479
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.595240798
Short name T617
Test name
Test status
Simulation time 108746050042 ps
CPU time 420.63 seconds
Started Feb 04 01:35:47 PM PST 24
Finished Feb 04 01:42:52 PM PST 24
Peak memory 234980 kb
Host smart-69809873-bc70-4959-b0bb-c5a23e467e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595240798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.595240798
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.731031671
Short name T796
Test name
Test status
Simulation time 580312020794 ps
CPU time 1287.02 seconds
Started Feb 04 01:35:52 PM PST 24
Finished Feb 04 01:57:22 PM PST 24
Peak memory 246440 kb
Host smart-f5af060e-ee93-49e0-95de-fb2dc43b5390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731031671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.731031671
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.2927005396
Short name T581
Test name
Test status
Simulation time 77002105970 ps
CPU time 300.23 seconds
Started Feb 04 01:35:45 PM PST 24
Finished Feb 04 01:40:50 PM PST 24
Peak memory 224924 kb
Host smart-8c15b58a-4e50-422e-b51c-a8ef18c039b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927005396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.2927005396
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2167880638
Short name T696
Test name
Test status
Simulation time 19011948821 ps
CPU time 310.72 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 01:41:01 PM PST 24
Peak memory 240152 kb
Host smart-5d6c0f72-0fec-4062-8891-a3bba8118378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167880638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.2167880638
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1616737249
Short name T756
Test name
Test status
Simulation time 63809884167 ps
CPU time 1661.61 seconds
Started Feb 04 01:35:46 PM PST 24
Finished Feb 04 02:03:32 PM PST 24
Peak memory 230788 kb
Host smart-be76633c-ca7e-450e-bf04-58a8b6593fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616737249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1616737249
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2474398628
Short name T834
Test name
Test status
Simulation time 151370547763 ps
CPU time 564.94 seconds
Started Feb 04 01:35:41 PM PST 24
Finished Feb 04 01:45:11 PM PST 24
Peak memory 244244 kb
Host smart-12caae9b-7048-478f-8c2b-dce2891a23c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474398628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.2474398628
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1951616500
Short name T139
Test name
Test status
Simulation time 375459800967 ps
CPU time 1790.28 seconds
Started Feb 04 01:35:47 PM PST 24
Finished Feb 04 02:05:42 PM PST 24
Peak memory 264632 kb
Host smart-7da8b3e6-c1d6-4f4f-b74d-6667bfc159ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951616500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.1951616500
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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